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drm/i915: Replace the array of pages with a scatterlist
[deliverable/linux.git] / drivers / char / agp / intel-gtt.c
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <linux/delay.h>
25 #include <asm/smp.h>
26 #include "agp.h"
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 struct intel_gtt_driver {
43 unsigned int gen : 8;
44 unsigned int is_g33 : 1;
45 unsigned int is_pineview : 1;
46 unsigned int is_ironlake : 1;
47 unsigned int has_pgtbl_enable : 1;
48 unsigned int dma_mask_size : 8;
49 /* Chipset specific GTT setup */
50 int (*setup)(void);
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup)(void);
54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags)(unsigned int flags);
59 void (*chipset_flush)(void);
60 };
61
62 static struct _intel_private {
63 struct intel_gtt base;
64 const struct intel_gtt_driver *driver;
65 struct pci_dev *pcidev; /* device one */
66 struct pci_dev *bridge_dev;
67 u8 __iomem *registers;
68 phys_addr_t gtt_bus_addr;
69 u32 PGETBL_save;
70 u32 __iomem *gtt; /* I915G */
71 bool clear_fake_agp; /* on first access via agp, fill with scratch */
72 int num_dcache_entries;
73 void __iomem *i9xx_flush_page;
74 char *i81x_gtt_table;
75 struct resource ifp_resource;
76 int resource_valid;
77 struct page *scratch_page;
78 int refcount;
79 } intel_private;
80
81 #define INTEL_GTT_GEN intel_private.driver->gen
82 #define IS_G33 intel_private.driver->is_g33
83 #define IS_PINEVIEW intel_private.driver->is_pineview
84 #define IS_IRONLAKE intel_private.driver->is_ironlake
85 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
86
87 static int intel_gtt_map_memory(struct page **pages,
88 unsigned int num_entries,
89 struct sg_table *st)
90 {
91 struct scatterlist *sg;
92 int i;
93
94 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
95
96 if (sg_alloc_table(st, num_entries, GFP_KERNEL))
97 goto err;
98
99 for_each_sg(st->sgl, sg, num_entries, i)
100 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
101
102 if (!pci_map_sg(intel_private.pcidev,
103 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
104 goto err;
105
106 return 0;
107
108 err:
109 sg_free_table(st);
110 return -ENOMEM;
111 }
112
113 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
114 {
115 struct sg_table st;
116 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
117
118 pci_unmap_sg(intel_private.pcidev, sg_list,
119 num_sg, PCI_DMA_BIDIRECTIONAL);
120
121 st.sgl = sg_list;
122 st.orig_nents = st.nents = num_sg;
123
124 sg_free_table(&st);
125 }
126
127 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
128 {
129 return;
130 }
131
132 /* Exists to support ARGB cursors */
133 static struct page *i8xx_alloc_pages(void)
134 {
135 struct page *page;
136
137 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
138 if (page == NULL)
139 return NULL;
140
141 if (set_pages_uc(page, 4) < 0) {
142 set_pages_wb(page, 4);
143 __free_pages(page, 2);
144 return NULL;
145 }
146 get_page(page);
147 atomic_inc(&agp_bridge->current_memory_agp);
148 return page;
149 }
150
151 static void i8xx_destroy_pages(struct page *page)
152 {
153 if (page == NULL)
154 return;
155
156 set_pages_wb(page, 4);
157 put_page(page);
158 __free_pages(page, 2);
159 atomic_dec(&agp_bridge->current_memory_agp);
160 }
161
162 #define I810_GTT_ORDER 4
163 static int i810_setup(void)
164 {
165 u32 reg_addr;
166 char *gtt_table;
167
168 /* i81x does not preallocate the gtt. It's always 64kb in size. */
169 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
170 if (gtt_table == NULL)
171 return -ENOMEM;
172 intel_private.i81x_gtt_table = gtt_table;
173
174 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
175 reg_addr &= 0xfff80000;
176
177 intel_private.registers = ioremap(reg_addr, KB(64));
178 if (!intel_private.registers)
179 return -ENOMEM;
180
181 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
182 intel_private.registers+I810_PGETBL_CTL);
183
184 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
185
186 if ((readl(intel_private.registers+I810_DRAM_CTL)
187 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
188 dev_info(&intel_private.pcidev->dev,
189 "detected 4MB dedicated video ram\n");
190 intel_private.num_dcache_entries = 1024;
191 }
192
193 return 0;
194 }
195
196 static void i810_cleanup(void)
197 {
198 writel(0, intel_private.registers+I810_PGETBL_CTL);
199 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
200 }
201
202 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
203 int type)
204 {
205 int i;
206
207 if ((pg_start + mem->page_count)
208 > intel_private.num_dcache_entries)
209 return -EINVAL;
210
211 if (!mem->is_flushed)
212 global_cache_flush();
213
214 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
215 dma_addr_t addr = i << PAGE_SHIFT;
216 intel_private.driver->write_entry(addr,
217 i, type);
218 }
219 readl(intel_private.gtt+i-1);
220
221 return 0;
222 }
223
224 /*
225 * The i810/i830 requires a physical address to program its mouse
226 * pointer into hardware.
227 * However the Xserver still writes to it through the agp aperture.
228 */
229 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
230 {
231 struct agp_memory *new;
232 struct page *page;
233
234 switch (pg_count) {
235 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
236 break;
237 case 4:
238 /* kludge to get 4 physical pages for ARGB cursor */
239 page = i8xx_alloc_pages();
240 break;
241 default:
242 return NULL;
243 }
244
245 if (page == NULL)
246 return NULL;
247
248 new = agp_create_memory(pg_count);
249 if (new == NULL)
250 return NULL;
251
252 new->pages[0] = page;
253 if (pg_count == 4) {
254 /* kludge to get 4 physical pages for ARGB cursor */
255 new->pages[1] = new->pages[0] + 1;
256 new->pages[2] = new->pages[1] + 1;
257 new->pages[3] = new->pages[2] + 1;
258 }
259 new->page_count = pg_count;
260 new->num_scratch_pages = pg_count;
261 new->type = AGP_PHYS_MEMORY;
262 new->physical = page_to_phys(new->pages[0]);
263 return new;
264 }
265
266 static void intel_i810_free_by_type(struct agp_memory *curr)
267 {
268 agp_free_key(curr->key);
269 if (curr->type == AGP_PHYS_MEMORY) {
270 if (curr->page_count == 4)
271 i8xx_destroy_pages(curr->pages[0]);
272 else {
273 agp_bridge->driver->agp_destroy_page(curr->pages[0],
274 AGP_PAGE_DESTROY_UNMAP);
275 agp_bridge->driver->agp_destroy_page(curr->pages[0],
276 AGP_PAGE_DESTROY_FREE);
277 }
278 agp_free_page_array(curr);
279 }
280 kfree(curr);
281 }
282
283 static int intel_gtt_setup_scratch_page(void)
284 {
285 struct page *page;
286 dma_addr_t dma_addr;
287
288 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
289 if (page == NULL)
290 return -ENOMEM;
291 get_page(page);
292 set_pages_uc(page, 1);
293
294 if (intel_private.base.needs_dmar) {
295 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
296 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
297 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
298 return -EINVAL;
299
300 intel_private.base.scratch_page_dma = dma_addr;
301 } else
302 intel_private.base.scratch_page_dma = page_to_phys(page);
303
304 intel_private.scratch_page = page;
305
306 return 0;
307 }
308
309 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
310 unsigned int flags)
311 {
312 u32 pte_flags = I810_PTE_VALID;
313
314 switch (flags) {
315 case AGP_DCACHE_MEMORY:
316 pte_flags |= I810_PTE_LOCAL;
317 break;
318 case AGP_USER_CACHED_MEMORY:
319 pte_flags |= I830_PTE_SYSTEM_CACHED;
320 break;
321 }
322
323 writel(addr | pte_flags, intel_private.gtt + entry);
324 }
325
326 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
327 {32, 8192, 3},
328 {64, 16384, 4},
329 {128, 32768, 5},
330 {256, 65536, 6},
331 {512, 131072, 7},
332 };
333
334 static unsigned int intel_gtt_stolen_size(void)
335 {
336 u16 gmch_ctrl;
337 u8 rdct;
338 int local = 0;
339 static const int ddt[4] = { 0, 16, 32, 64 };
340 unsigned int stolen_size = 0;
341
342 if (INTEL_GTT_GEN == 1)
343 return 0; /* no stolen mem on i81x */
344
345 pci_read_config_word(intel_private.bridge_dev,
346 I830_GMCH_CTRL, &gmch_ctrl);
347
348 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
349 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
350 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
351 case I830_GMCH_GMS_STOLEN_512:
352 stolen_size = KB(512);
353 break;
354 case I830_GMCH_GMS_STOLEN_1024:
355 stolen_size = MB(1);
356 break;
357 case I830_GMCH_GMS_STOLEN_8192:
358 stolen_size = MB(8);
359 break;
360 case I830_GMCH_GMS_LOCAL:
361 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
362 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
363 MB(ddt[I830_RDRAM_DDT(rdct)]);
364 local = 1;
365 break;
366 default:
367 stolen_size = 0;
368 break;
369 }
370 } else if (INTEL_GTT_GEN == 6) {
371 /*
372 * SandyBridge has new memory control reg at 0x50.w
373 */
374 u16 snb_gmch_ctl;
375 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
376 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
377 case SNB_GMCH_GMS_STOLEN_32M:
378 stolen_size = MB(32);
379 break;
380 case SNB_GMCH_GMS_STOLEN_64M:
381 stolen_size = MB(64);
382 break;
383 case SNB_GMCH_GMS_STOLEN_96M:
384 stolen_size = MB(96);
385 break;
386 case SNB_GMCH_GMS_STOLEN_128M:
387 stolen_size = MB(128);
388 break;
389 case SNB_GMCH_GMS_STOLEN_160M:
390 stolen_size = MB(160);
391 break;
392 case SNB_GMCH_GMS_STOLEN_192M:
393 stolen_size = MB(192);
394 break;
395 case SNB_GMCH_GMS_STOLEN_224M:
396 stolen_size = MB(224);
397 break;
398 case SNB_GMCH_GMS_STOLEN_256M:
399 stolen_size = MB(256);
400 break;
401 case SNB_GMCH_GMS_STOLEN_288M:
402 stolen_size = MB(288);
403 break;
404 case SNB_GMCH_GMS_STOLEN_320M:
405 stolen_size = MB(320);
406 break;
407 case SNB_GMCH_GMS_STOLEN_352M:
408 stolen_size = MB(352);
409 break;
410 case SNB_GMCH_GMS_STOLEN_384M:
411 stolen_size = MB(384);
412 break;
413 case SNB_GMCH_GMS_STOLEN_416M:
414 stolen_size = MB(416);
415 break;
416 case SNB_GMCH_GMS_STOLEN_448M:
417 stolen_size = MB(448);
418 break;
419 case SNB_GMCH_GMS_STOLEN_480M:
420 stolen_size = MB(480);
421 break;
422 case SNB_GMCH_GMS_STOLEN_512M:
423 stolen_size = MB(512);
424 break;
425 }
426 } else {
427 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
428 case I855_GMCH_GMS_STOLEN_1M:
429 stolen_size = MB(1);
430 break;
431 case I855_GMCH_GMS_STOLEN_4M:
432 stolen_size = MB(4);
433 break;
434 case I855_GMCH_GMS_STOLEN_8M:
435 stolen_size = MB(8);
436 break;
437 case I855_GMCH_GMS_STOLEN_16M:
438 stolen_size = MB(16);
439 break;
440 case I855_GMCH_GMS_STOLEN_32M:
441 stolen_size = MB(32);
442 break;
443 case I915_GMCH_GMS_STOLEN_48M:
444 stolen_size = MB(48);
445 break;
446 case I915_GMCH_GMS_STOLEN_64M:
447 stolen_size = MB(64);
448 break;
449 case G33_GMCH_GMS_STOLEN_128M:
450 stolen_size = MB(128);
451 break;
452 case G33_GMCH_GMS_STOLEN_256M:
453 stolen_size = MB(256);
454 break;
455 case INTEL_GMCH_GMS_STOLEN_96M:
456 stolen_size = MB(96);
457 break;
458 case INTEL_GMCH_GMS_STOLEN_160M:
459 stolen_size = MB(160);
460 break;
461 case INTEL_GMCH_GMS_STOLEN_224M:
462 stolen_size = MB(224);
463 break;
464 case INTEL_GMCH_GMS_STOLEN_352M:
465 stolen_size = MB(352);
466 break;
467 default:
468 stolen_size = 0;
469 break;
470 }
471 }
472
473 if (stolen_size > 0) {
474 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
475 stolen_size / KB(1), local ? "local" : "stolen");
476 } else {
477 dev_info(&intel_private.bridge_dev->dev,
478 "no pre-allocated video memory detected\n");
479 stolen_size = 0;
480 }
481
482 return stolen_size;
483 }
484
485 static void i965_adjust_pgetbl_size(unsigned int size_flag)
486 {
487 u32 pgetbl_ctl, pgetbl_ctl2;
488
489 /* ensure that ppgtt is disabled */
490 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
491 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
492 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
493
494 /* write the new ggtt size */
495 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
496 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
497 pgetbl_ctl |= size_flag;
498 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
499 }
500
501 static unsigned int i965_gtt_total_entries(void)
502 {
503 int size;
504 u32 pgetbl_ctl;
505 u16 gmch_ctl;
506
507 pci_read_config_word(intel_private.bridge_dev,
508 I830_GMCH_CTRL, &gmch_ctl);
509
510 if (INTEL_GTT_GEN == 5) {
511 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
512 case G4x_GMCH_SIZE_1M:
513 case G4x_GMCH_SIZE_VT_1M:
514 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
515 break;
516 case G4x_GMCH_SIZE_VT_1_5M:
517 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
518 break;
519 case G4x_GMCH_SIZE_2M:
520 case G4x_GMCH_SIZE_VT_2M:
521 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
522 break;
523 }
524 }
525
526 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
527
528 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
529 case I965_PGETBL_SIZE_128KB:
530 size = KB(128);
531 break;
532 case I965_PGETBL_SIZE_256KB:
533 size = KB(256);
534 break;
535 case I965_PGETBL_SIZE_512KB:
536 size = KB(512);
537 break;
538 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
539 case I965_PGETBL_SIZE_1MB:
540 size = KB(1024);
541 break;
542 case I965_PGETBL_SIZE_2MB:
543 size = KB(2048);
544 break;
545 case I965_PGETBL_SIZE_1_5MB:
546 size = KB(1024 + 512);
547 break;
548 default:
549 dev_info(&intel_private.pcidev->dev,
550 "unknown page table size, assuming 512KB\n");
551 size = KB(512);
552 }
553
554 return size/4;
555 }
556
557 static unsigned int intel_gtt_total_entries(void)
558 {
559 int size;
560
561 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
562 return i965_gtt_total_entries();
563 else if (INTEL_GTT_GEN == 6) {
564 u16 snb_gmch_ctl;
565
566 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
567 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
568 default:
569 case SNB_GTT_SIZE_0M:
570 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
571 size = MB(0);
572 break;
573 case SNB_GTT_SIZE_1M:
574 size = MB(1);
575 break;
576 case SNB_GTT_SIZE_2M:
577 size = MB(2);
578 break;
579 }
580 return size/4;
581 } else {
582 /* On previous hardware, the GTT size was just what was
583 * required to map the aperture.
584 */
585 return intel_private.base.gtt_mappable_entries;
586 }
587 }
588
589 static unsigned int intel_gtt_mappable_entries(void)
590 {
591 unsigned int aperture_size;
592
593 if (INTEL_GTT_GEN == 1) {
594 u32 smram_miscc;
595
596 pci_read_config_dword(intel_private.bridge_dev,
597 I810_SMRAM_MISCC, &smram_miscc);
598
599 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
600 == I810_GFX_MEM_WIN_32M)
601 aperture_size = MB(32);
602 else
603 aperture_size = MB(64);
604 } else if (INTEL_GTT_GEN == 2) {
605 u16 gmch_ctrl;
606
607 pci_read_config_word(intel_private.bridge_dev,
608 I830_GMCH_CTRL, &gmch_ctrl);
609
610 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
611 aperture_size = MB(64);
612 else
613 aperture_size = MB(128);
614 } else {
615 /* 9xx supports large sizes, just look at the length */
616 aperture_size = pci_resource_len(intel_private.pcidev, 2);
617 }
618
619 return aperture_size >> PAGE_SHIFT;
620 }
621
622 static void intel_gtt_teardown_scratch_page(void)
623 {
624 set_pages_wb(intel_private.scratch_page, 1);
625 pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
626 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
627 put_page(intel_private.scratch_page);
628 __free_page(intel_private.scratch_page);
629 }
630
631 static void intel_gtt_cleanup(void)
632 {
633 intel_private.driver->cleanup();
634
635 iounmap(intel_private.gtt);
636 iounmap(intel_private.registers);
637
638 intel_gtt_teardown_scratch_page();
639 }
640
641 static int intel_gtt_init(void)
642 {
643 u32 gma_addr;
644 u32 gtt_map_size;
645 int ret;
646
647 ret = intel_private.driver->setup();
648 if (ret != 0)
649 return ret;
650
651 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
652 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
653
654 /* save the PGETBL reg for resume */
655 intel_private.PGETBL_save =
656 readl(intel_private.registers+I810_PGETBL_CTL)
657 & ~I810_PGETBL_ENABLED;
658 /* we only ever restore the register when enabling the PGTBL... */
659 if (HAS_PGTBL_EN)
660 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
661
662 dev_info(&intel_private.bridge_dev->dev,
663 "detected gtt size: %dK total, %dK mappable\n",
664 intel_private.base.gtt_total_entries * 4,
665 intel_private.base.gtt_mappable_entries * 4);
666
667 gtt_map_size = intel_private.base.gtt_total_entries * 4;
668
669 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
670 gtt_map_size);
671 if (!intel_private.gtt) {
672 intel_private.driver->cleanup();
673 iounmap(intel_private.registers);
674 return -ENOMEM;
675 }
676 intel_private.base.gtt = intel_private.gtt;
677
678 global_cache_flush(); /* FIXME: ? */
679
680 intel_private.base.stolen_size = intel_gtt_stolen_size();
681
682 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
683
684 ret = intel_gtt_setup_scratch_page();
685 if (ret != 0) {
686 intel_gtt_cleanup();
687 return ret;
688 }
689
690 if (INTEL_GTT_GEN <= 2)
691 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
692 &gma_addr);
693 else
694 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
695 &gma_addr);
696
697 intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
698
699 return 0;
700 }
701
702 static int intel_fake_agp_fetch_size(void)
703 {
704 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
705 unsigned int aper_size;
706 int i;
707
708 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
709 / MB(1);
710
711 for (i = 0; i < num_sizes; i++) {
712 if (aper_size == intel_fake_agp_sizes[i].size) {
713 agp_bridge->current_size =
714 (void *) (intel_fake_agp_sizes + i);
715 return aper_size;
716 }
717 }
718
719 return 0;
720 }
721
722 static void i830_cleanup(void)
723 {
724 }
725
726 /* The chipset_flush interface needs to get data that has already been
727 * flushed out of the CPU all the way out to main memory, because the GPU
728 * doesn't snoop those buffers.
729 *
730 * The 8xx series doesn't have the same lovely interface for flushing the
731 * chipset write buffers that the later chips do. According to the 865
732 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
733 * that buffer out, we just fill 1KB and clflush it out, on the assumption
734 * that it'll push whatever was in there out. It appears to work.
735 */
736 static void i830_chipset_flush(void)
737 {
738 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
739
740 /* Forcibly evict everything from the CPU write buffers.
741 * clflush appears to be insufficient.
742 */
743 wbinvd_on_all_cpus();
744
745 /* Now we've only seen documents for this magic bit on 855GM,
746 * we hope it exists for the other gen2 chipsets...
747 *
748 * Also works as advertised on my 845G.
749 */
750 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
751 intel_private.registers+I830_HIC);
752
753 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
754 if (time_after(jiffies, timeout))
755 break;
756
757 udelay(50);
758 }
759 }
760
761 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
762 unsigned int flags)
763 {
764 u32 pte_flags = I810_PTE_VALID;
765
766 if (flags == AGP_USER_CACHED_MEMORY)
767 pte_flags |= I830_PTE_SYSTEM_CACHED;
768
769 writel(addr | pte_flags, intel_private.gtt + entry);
770 }
771
772 bool intel_enable_gtt(void)
773 {
774 u8 __iomem *reg;
775
776 if (INTEL_GTT_GEN >= 6)
777 return true;
778
779 if (INTEL_GTT_GEN == 2) {
780 u16 gmch_ctrl;
781
782 pci_read_config_word(intel_private.bridge_dev,
783 I830_GMCH_CTRL, &gmch_ctrl);
784 gmch_ctrl |= I830_GMCH_ENABLED;
785 pci_write_config_word(intel_private.bridge_dev,
786 I830_GMCH_CTRL, gmch_ctrl);
787
788 pci_read_config_word(intel_private.bridge_dev,
789 I830_GMCH_CTRL, &gmch_ctrl);
790 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
791 dev_err(&intel_private.pcidev->dev,
792 "failed to enable the GTT: GMCH_CTRL=%x\n",
793 gmch_ctrl);
794 return false;
795 }
796 }
797
798 /* On the resume path we may be adjusting the PGTBL value, so
799 * be paranoid and flush all chipset write buffers...
800 */
801 if (INTEL_GTT_GEN >= 3)
802 writel(0, intel_private.registers+GFX_FLSH_CNTL);
803
804 reg = intel_private.registers+I810_PGETBL_CTL;
805 writel(intel_private.PGETBL_save, reg);
806 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
807 dev_err(&intel_private.pcidev->dev,
808 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
809 readl(reg), intel_private.PGETBL_save);
810 return false;
811 }
812
813 if (INTEL_GTT_GEN >= 3)
814 writel(0, intel_private.registers+GFX_FLSH_CNTL);
815
816 return true;
817 }
818 EXPORT_SYMBOL(intel_enable_gtt);
819
820 static int i830_setup(void)
821 {
822 u32 reg_addr;
823
824 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
825 reg_addr &= 0xfff80000;
826
827 intel_private.registers = ioremap(reg_addr, KB(64));
828 if (!intel_private.registers)
829 return -ENOMEM;
830
831 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
832
833 return 0;
834 }
835
836 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
837 {
838 agp_bridge->gatt_table_real = NULL;
839 agp_bridge->gatt_table = NULL;
840 agp_bridge->gatt_bus_addr = 0;
841
842 return 0;
843 }
844
845 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
846 {
847 return 0;
848 }
849
850 static int intel_fake_agp_configure(void)
851 {
852 if (!intel_enable_gtt())
853 return -EIO;
854
855 intel_private.clear_fake_agp = true;
856 agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr;
857
858 return 0;
859 }
860
861 static bool i830_check_flags(unsigned int flags)
862 {
863 switch (flags) {
864 case 0:
865 case AGP_PHYS_MEMORY:
866 case AGP_USER_CACHED_MEMORY:
867 case AGP_USER_MEMORY:
868 return true;
869 }
870
871 return false;
872 }
873
874 void intel_gtt_insert_sg_entries(struct sg_table *st,
875 unsigned int pg_start,
876 unsigned int flags)
877 {
878 struct scatterlist *sg;
879 unsigned int len, m;
880 int i, j;
881
882 j = pg_start;
883
884 /* sg may merge pages, but we have to separate
885 * per-page addr for GTT */
886 for_each_sg(st->sgl, sg, st->nents, i) {
887 len = sg_dma_len(sg) >> PAGE_SHIFT;
888 for (m = 0; m < len; m++) {
889 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
890 intel_private.driver->write_entry(addr, j, flags);
891 j++;
892 }
893 }
894 readl(intel_private.gtt+j-1);
895 }
896 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
897
898 static void intel_gtt_insert_pages(unsigned int first_entry,
899 unsigned int num_entries,
900 struct page **pages,
901 unsigned int flags)
902 {
903 int i, j;
904
905 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
906 dma_addr_t addr = page_to_phys(pages[i]);
907 intel_private.driver->write_entry(addr,
908 j, flags);
909 }
910 readl(intel_private.gtt+j-1);
911 }
912
913 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
914 off_t pg_start, int type)
915 {
916 int ret = -EINVAL;
917
918 if (intel_private.base.do_idle_maps)
919 return -ENODEV;
920
921 if (intel_private.clear_fake_agp) {
922 int start = intel_private.base.stolen_size / PAGE_SIZE;
923 int end = intel_private.base.gtt_mappable_entries;
924 intel_gtt_clear_range(start, end - start);
925 intel_private.clear_fake_agp = false;
926 }
927
928 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
929 return i810_insert_dcache_entries(mem, pg_start, type);
930
931 if (mem->page_count == 0)
932 goto out;
933
934 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
935 goto out_err;
936
937 if (type != mem->type)
938 goto out_err;
939
940 if (!intel_private.driver->check_flags(type))
941 goto out_err;
942
943 if (!mem->is_flushed)
944 global_cache_flush();
945
946 if (intel_private.base.needs_dmar) {
947 struct sg_table st;
948
949 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
950 if (ret != 0)
951 return ret;
952
953 intel_gtt_insert_sg_entries(&st, pg_start, type);
954 mem->sg_list = st.sgl;
955 mem->num_sg = st.nents;
956 } else
957 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
958 type);
959
960 out:
961 ret = 0;
962 out_err:
963 mem->is_flushed = true;
964 return ret;
965 }
966
967 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
968 {
969 unsigned int i;
970
971 for (i = first_entry; i < (first_entry + num_entries); i++) {
972 intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
973 i, 0);
974 }
975 readl(intel_private.gtt+i-1);
976 }
977 EXPORT_SYMBOL(intel_gtt_clear_range);
978
979 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
980 off_t pg_start, int type)
981 {
982 if (mem->page_count == 0)
983 return 0;
984
985 if (intel_private.base.do_idle_maps)
986 return -ENODEV;
987
988 intel_gtt_clear_range(pg_start, mem->page_count);
989
990 if (intel_private.base.needs_dmar) {
991 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
992 mem->sg_list = NULL;
993 mem->num_sg = 0;
994 }
995
996 return 0;
997 }
998
999 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1000 int type)
1001 {
1002 struct agp_memory *new;
1003
1004 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1005 if (pg_count != intel_private.num_dcache_entries)
1006 return NULL;
1007
1008 new = agp_create_memory(1);
1009 if (new == NULL)
1010 return NULL;
1011
1012 new->type = AGP_DCACHE_MEMORY;
1013 new->page_count = pg_count;
1014 new->num_scratch_pages = 0;
1015 agp_free_page_array(new);
1016 return new;
1017 }
1018 if (type == AGP_PHYS_MEMORY)
1019 return alloc_agpphysmem_i8xx(pg_count, type);
1020 /* always return NULL for other allocation types for now */
1021 return NULL;
1022 }
1023
1024 static int intel_alloc_chipset_flush_resource(void)
1025 {
1026 int ret;
1027 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1028 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1029 pcibios_align_resource, intel_private.bridge_dev);
1030
1031 return ret;
1032 }
1033
1034 static void intel_i915_setup_chipset_flush(void)
1035 {
1036 int ret;
1037 u32 temp;
1038
1039 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1040 if (!(temp & 0x1)) {
1041 intel_alloc_chipset_flush_resource();
1042 intel_private.resource_valid = 1;
1043 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1044 } else {
1045 temp &= ~1;
1046
1047 intel_private.resource_valid = 1;
1048 intel_private.ifp_resource.start = temp;
1049 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1050 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1051 /* some BIOSes reserve this area in a pnp some don't */
1052 if (ret)
1053 intel_private.resource_valid = 0;
1054 }
1055 }
1056
1057 static void intel_i965_g33_setup_chipset_flush(void)
1058 {
1059 u32 temp_hi, temp_lo;
1060 int ret;
1061
1062 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1063 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1064
1065 if (!(temp_lo & 0x1)) {
1066
1067 intel_alloc_chipset_flush_resource();
1068
1069 intel_private.resource_valid = 1;
1070 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1071 upper_32_bits(intel_private.ifp_resource.start));
1072 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1073 } else {
1074 u64 l64;
1075
1076 temp_lo &= ~0x1;
1077 l64 = ((u64)temp_hi << 32) | temp_lo;
1078
1079 intel_private.resource_valid = 1;
1080 intel_private.ifp_resource.start = l64;
1081 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1082 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1083 /* some BIOSes reserve this area in a pnp some don't */
1084 if (ret)
1085 intel_private.resource_valid = 0;
1086 }
1087 }
1088
1089 static void intel_i9xx_setup_flush(void)
1090 {
1091 /* return if already configured */
1092 if (intel_private.ifp_resource.start)
1093 return;
1094
1095 if (INTEL_GTT_GEN == 6)
1096 return;
1097
1098 /* setup a resource for this object */
1099 intel_private.ifp_resource.name = "Intel Flush Page";
1100 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1101
1102 /* Setup chipset flush for 915 */
1103 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1104 intel_i965_g33_setup_chipset_flush();
1105 } else {
1106 intel_i915_setup_chipset_flush();
1107 }
1108
1109 if (intel_private.ifp_resource.start)
1110 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1111 if (!intel_private.i9xx_flush_page)
1112 dev_err(&intel_private.pcidev->dev,
1113 "can't ioremap flush page - no chipset flushing\n");
1114 }
1115
1116 static void i9xx_cleanup(void)
1117 {
1118 if (intel_private.i9xx_flush_page)
1119 iounmap(intel_private.i9xx_flush_page);
1120 if (intel_private.resource_valid)
1121 release_resource(&intel_private.ifp_resource);
1122 intel_private.ifp_resource.start = 0;
1123 intel_private.resource_valid = 0;
1124 }
1125
1126 static void i9xx_chipset_flush(void)
1127 {
1128 if (intel_private.i9xx_flush_page)
1129 writel(1, intel_private.i9xx_flush_page);
1130 }
1131
1132 static void i965_write_entry(dma_addr_t addr,
1133 unsigned int entry,
1134 unsigned int flags)
1135 {
1136 u32 pte_flags;
1137
1138 pte_flags = I810_PTE_VALID;
1139 if (flags == AGP_USER_CACHED_MEMORY)
1140 pte_flags |= I830_PTE_SYSTEM_CACHED;
1141
1142 /* Shift high bits down */
1143 addr |= (addr >> 28) & 0xf0;
1144 writel(addr | pte_flags, intel_private.gtt + entry);
1145 }
1146
1147 static bool gen6_check_flags(unsigned int flags)
1148 {
1149 return true;
1150 }
1151
1152 static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
1153 unsigned int flags)
1154 {
1155 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1156 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1157 u32 pte_flags;
1158
1159 if (type_mask == AGP_USER_MEMORY)
1160 pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
1161 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1162 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1163 if (gfdt)
1164 pte_flags |= GEN6_PTE_GFDT;
1165 } else { /* set 'normal'/'cached' to LLC by default */
1166 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1167 if (gfdt)
1168 pte_flags |= GEN6_PTE_GFDT;
1169 }
1170
1171 /* gen6 has bit11-4 for physical addr bit39-32 */
1172 addr |= (addr >> 28) & 0xff0;
1173 writel(addr | pte_flags, intel_private.gtt + entry);
1174 }
1175
1176 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1177 unsigned int flags)
1178 {
1179 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1180 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1181 u32 pte_flags;
1182
1183 if (type_mask == AGP_USER_MEMORY)
1184 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1185 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1186 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1187 if (gfdt)
1188 pte_flags |= GEN6_PTE_GFDT;
1189 } else { /* set 'normal'/'cached' to LLC by default */
1190 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1191 if (gfdt)
1192 pte_flags |= GEN6_PTE_GFDT;
1193 }
1194
1195 /* gen6 has bit11-4 for physical addr bit39-32 */
1196 addr |= (addr >> 28) & 0xff0;
1197 writel(addr | pte_flags, intel_private.gtt + entry);
1198 }
1199
1200 static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
1201 unsigned int flags)
1202 {
1203 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1204 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1205 u32 pte_flags;
1206
1207 if (type_mask == AGP_USER_MEMORY)
1208 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1209 else {
1210 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1211 if (gfdt)
1212 pte_flags |= GEN6_PTE_GFDT;
1213 }
1214
1215 /* gen6 has bit11-4 for physical addr bit39-32 */
1216 addr |= (addr >> 28) & 0xff0;
1217 writel(addr | pte_flags, intel_private.gtt + entry);
1218
1219 writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);
1220 }
1221
1222 static void gen6_cleanup(void)
1223 {
1224 }
1225
1226 /* Certain Gen5 chipsets require require idling the GPU before
1227 * unmapping anything from the GTT when VT-d is enabled.
1228 */
1229 static inline int needs_idle_maps(void)
1230 {
1231 #ifdef CONFIG_INTEL_IOMMU
1232 const unsigned short gpu_devid = intel_private.pcidev->device;
1233
1234 /* Query intel_iommu to see if we need the workaround. Presumably that
1235 * was loaded first.
1236 */
1237 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1238 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1239 intel_iommu_gfx_mapped)
1240 return 1;
1241 #endif
1242 return 0;
1243 }
1244
1245 static int i9xx_setup(void)
1246 {
1247 u32 reg_addr;
1248 int size = KB(512);
1249
1250 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1251
1252 reg_addr &= 0xfff80000;
1253
1254 if (INTEL_GTT_GEN >= 7)
1255 size = MB(2);
1256
1257 intel_private.registers = ioremap(reg_addr, size);
1258 if (!intel_private.registers)
1259 return -ENOMEM;
1260
1261 if (INTEL_GTT_GEN == 3) {
1262 u32 gtt_addr;
1263
1264 pci_read_config_dword(intel_private.pcidev,
1265 I915_PTEADDR, &gtt_addr);
1266 intel_private.gtt_bus_addr = gtt_addr;
1267 } else {
1268 u32 gtt_offset;
1269
1270 switch (INTEL_GTT_GEN) {
1271 case 5:
1272 case 6:
1273 case 7:
1274 gtt_offset = MB(2);
1275 break;
1276 case 4:
1277 default:
1278 gtt_offset = KB(512);
1279 break;
1280 }
1281 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1282 }
1283
1284 if (needs_idle_maps())
1285 intel_private.base.do_idle_maps = 1;
1286
1287 intel_i9xx_setup_flush();
1288
1289 return 0;
1290 }
1291
1292 static const struct agp_bridge_driver intel_fake_agp_driver = {
1293 .owner = THIS_MODULE,
1294 .size_type = FIXED_APER_SIZE,
1295 .aperture_sizes = intel_fake_agp_sizes,
1296 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1297 .configure = intel_fake_agp_configure,
1298 .fetch_size = intel_fake_agp_fetch_size,
1299 .cleanup = intel_gtt_cleanup,
1300 .agp_enable = intel_fake_agp_enable,
1301 .cache_flush = global_cache_flush,
1302 .create_gatt_table = intel_fake_agp_create_gatt_table,
1303 .free_gatt_table = intel_fake_agp_free_gatt_table,
1304 .insert_memory = intel_fake_agp_insert_entries,
1305 .remove_memory = intel_fake_agp_remove_entries,
1306 .alloc_by_type = intel_fake_agp_alloc_by_type,
1307 .free_by_type = intel_i810_free_by_type,
1308 .agp_alloc_page = agp_generic_alloc_page,
1309 .agp_alloc_pages = agp_generic_alloc_pages,
1310 .agp_destroy_page = agp_generic_destroy_page,
1311 .agp_destroy_pages = agp_generic_destroy_pages,
1312 };
1313
1314 static const struct intel_gtt_driver i81x_gtt_driver = {
1315 .gen = 1,
1316 .has_pgtbl_enable = 1,
1317 .dma_mask_size = 32,
1318 .setup = i810_setup,
1319 .cleanup = i810_cleanup,
1320 .check_flags = i830_check_flags,
1321 .write_entry = i810_write_entry,
1322 };
1323 static const struct intel_gtt_driver i8xx_gtt_driver = {
1324 .gen = 2,
1325 .has_pgtbl_enable = 1,
1326 .setup = i830_setup,
1327 .cleanup = i830_cleanup,
1328 .write_entry = i830_write_entry,
1329 .dma_mask_size = 32,
1330 .check_flags = i830_check_flags,
1331 .chipset_flush = i830_chipset_flush,
1332 };
1333 static const struct intel_gtt_driver i915_gtt_driver = {
1334 .gen = 3,
1335 .has_pgtbl_enable = 1,
1336 .setup = i9xx_setup,
1337 .cleanup = i9xx_cleanup,
1338 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1339 .write_entry = i830_write_entry,
1340 .dma_mask_size = 32,
1341 .check_flags = i830_check_flags,
1342 .chipset_flush = i9xx_chipset_flush,
1343 };
1344 static const struct intel_gtt_driver g33_gtt_driver = {
1345 .gen = 3,
1346 .is_g33 = 1,
1347 .setup = i9xx_setup,
1348 .cleanup = i9xx_cleanup,
1349 .write_entry = i965_write_entry,
1350 .dma_mask_size = 36,
1351 .check_flags = i830_check_flags,
1352 .chipset_flush = i9xx_chipset_flush,
1353 };
1354 static const struct intel_gtt_driver pineview_gtt_driver = {
1355 .gen = 3,
1356 .is_pineview = 1, .is_g33 = 1,
1357 .setup = i9xx_setup,
1358 .cleanup = i9xx_cleanup,
1359 .write_entry = i965_write_entry,
1360 .dma_mask_size = 36,
1361 .check_flags = i830_check_flags,
1362 .chipset_flush = i9xx_chipset_flush,
1363 };
1364 static const struct intel_gtt_driver i965_gtt_driver = {
1365 .gen = 4,
1366 .has_pgtbl_enable = 1,
1367 .setup = i9xx_setup,
1368 .cleanup = i9xx_cleanup,
1369 .write_entry = i965_write_entry,
1370 .dma_mask_size = 36,
1371 .check_flags = i830_check_flags,
1372 .chipset_flush = i9xx_chipset_flush,
1373 };
1374 static const struct intel_gtt_driver g4x_gtt_driver = {
1375 .gen = 5,
1376 .setup = i9xx_setup,
1377 .cleanup = i9xx_cleanup,
1378 .write_entry = i965_write_entry,
1379 .dma_mask_size = 36,
1380 .check_flags = i830_check_flags,
1381 .chipset_flush = i9xx_chipset_flush,
1382 };
1383 static const struct intel_gtt_driver ironlake_gtt_driver = {
1384 .gen = 5,
1385 .is_ironlake = 1,
1386 .setup = i9xx_setup,
1387 .cleanup = i9xx_cleanup,
1388 .write_entry = i965_write_entry,
1389 .dma_mask_size = 36,
1390 .check_flags = i830_check_flags,
1391 .chipset_flush = i9xx_chipset_flush,
1392 };
1393 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1394 .gen = 6,
1395 .setup = i9xx_setup,
1396 .cleanup = gen6_cleanup,
1397 .write_entry = gen6_write_entry,
1398 .dma_mask_size = 40,
1399 .check_flags = gen6_check_flags,
1400 .chipset_flush = i9xx_chipset_flush,
1401 };
1402 static const struct intel_gtt_driver haswell_gtt_driver = {
1403 .gen = 6,
1404 .setup = i9xx_setup,
1405 .cleanup = gen6_cleanup,
1406 .write_entry = haswell_write_entry,
1407 .dma_mask_size = 40,
1408 .check_flags = gen6_check_flags,
1409 .chipset_flush = i9xx_chipset_flush,
1410 };
1411 static const struct intel_gtt_driver valleyview_gtt_driver = {
1412 .gen = 7,
1413 .setup = i9xx_setup,
1414 .cleanup = gen6_cleanup,
1415 .write_entry = valleyview_write_entry,
1416 .dma_mask_size = 40,
1417 .check_flags = gen6_check_flags,
1418 };
1419
1420 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1421 * driver and gmch_driver must be non-null, and find_gmch will determine
1422 * which one should be used if a gmch_chip_id is present.
1423 */
1424 static const struct intel_gtt_driver_description {
1425 unsigned int gmch_chip_id;
1426 char *name;
1427 const struct intel_gtt_driver *gtt_driver;
1428 } intel_gtt_chipsets[] = {
1429 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1430 &i81x_gtt_driver},
1431 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1432 &i81x_gtt_driver},
1433 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1434 &i81x_gtt_driver},
1435 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1436 &i81x_gtt_driver},
1437 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1438 &i8xx_gtt_driver},
1439 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1440 &i8xx_gtt_driver},
1441 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1442 &i8xx_gtt_driver},
1443 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1444 &i8xx_gtt_driver},
1445 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1446 &i8xx_gtt_driver},
1447 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1448 &i915_gtt_driver },
1449 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1450 &i915_gtt_driver },
1451 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1452 &i915_gtt_driver },
1453 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1454 &i915_gtt_driver },
1455 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1456 &i915_gtt_driver },
1457 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1458 &i915_gtt_driver },
1459 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1460 &i965_gtt_driver },
1461 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1462 &i965_gtt_driver },
1463 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1464 &i965_gtt_driver },
1465 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1466 &i965_gtt_driver },
1467 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1468 &i965_gtt_driver },
1469 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1470 &i965_gtt_driver },
1471 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1472 &g33_gtt_driver },
1473 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1474 &g33_gtt_driver },
1475 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1476 &g33_gtt_driver },
1477 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1478 &pineview_gtt_driver },
1479 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1480 &pineview_gtt_driver },
1481 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1482 &g4x_gtt_driver },
1483 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1484 &g4x_gtt_driver },
1485 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1486 &g4x_gtt_driver },
1487 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1488 &g4x_gtt_driver },
1489 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1490 &g4x_gtt_driver },
1491 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1492 &g4x_gtt_driver },
1493 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1494 &g4x_gtt_driver },
1495 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1496 "HD Graphics", &ironlake_gtt_driver },
1497 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1498 "HD Graphics", &ironlake_gtt_driver },
1499 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1500 "Sandybridge", &sandybridge_gtt_driver },
1501 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1502 "Sandybridge", &sandybridge_gtt_driver },
1503 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1504 "Sandybridge", &sandybridge_gtt_driver },
1505 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1506 "Sandybridge", &sandybridge_gtt_driver },
1507 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1508 "Sandybridge", &sandybridge_gtt_driver },
1509 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1510 "Sandybridge", &sandybridge_gtt_driver },
1511 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1512 "Sandybridge", &sandybridge_gtt_driver },
1513 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
1514 "Ivybridge", &sandybridge_gtt_driver },
1515 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
1516 "Ivybridge", &sandybridge_gtt_driver },
1517 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
1518 "Ivybridge", &sandybridge_gtt_driver },
1519 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
1520 "Ivybridge", &sandybridge_gtt_driver },
1521 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
1522 "Ivybridge", &sandybridge_gtt_driver },
1523 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
1524 "Ivybridge", &sandybridge_gtt_driver },
1525 { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
1526 "ValleyView", &valleyview_gtt_driver },
1527 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
1528 "Haswell", &haswell_gtt_driver },
1529 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
1530 "Haswell", &haswell_gtt_driver },
1531 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
1532 "Haswell", &haswell_gtt_driver },
1533 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
1534 "Haswell", &haswell_gtt_driver },
1535 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
1536 "Haswell", &haswell_gtt_driver },
1537 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
1538 "Haswell", &haswell_gtt_driver },
1539 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
1540 "Haswell", &haswell_gtt_driver },
1541 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
1542 "Haswell", &haswell_gtt_driver },
1543 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
1544 "Haswell", &haswell_gtt_driver },
1545 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
1546 "Haswell", &haswell_gtt_driver },
1547 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
1548 "Haswell", &haswell_gtt_driver },
1549 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
1550 "Haswell", &haswell_gtt_driver },
1551 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
1552 "Haswell", &haswell_gtt_driver },
1553 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
1554 "Haswell", &haswell_gtt_driver },
1555 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
1556 "Haswell", &haswell_gtt_driver },
1557 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
1558 "Haswell", &haswell_gtt_driver },
1559 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
1560 "Haswell", &haswell_gtt_driver },
1561 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
1562 "Haswell", &haswell_gtt_driver },
1563 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
1564 "Haswell", &haswell_gtt_driver },
1565 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
1566 "Haswell", &haswell_gtt_driver },
1567 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
1568 "Haswell", &haswell_gtt_driver },
1569 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
1570 "Haswell", &haswell_gtt_driver },
1571 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
1572 "Haswell", &haswell_gtt_driver },
1573 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
1574 "Haswell", &haswell_gtt_driver },
1575 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
1576 "Haswell", &haswell_gtt_driver },
1577 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
1578 "Haswell", &haswell_gtt_driver },
1579 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
1580 "Haswell", &haswell_gtt_driver },
1581 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
1582 "Haswell", &haswell_gtt_driver },
1583 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
1584 "Haswell", &haswell_gtt_driver },
1585 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
1586 "Haswell", &haswell_gtt_driver },
1587 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
1588 "Haswell", &haswell_gtt_driver },
1589 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
1590 "Haswell", &haswell_gtt_driver },
1591 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
1592 "Haswell", &haswell_gtt_driver },
1593 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
1594 "Haswell", &haswell_gtt_driver },
1595 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
1596 "Haswell", &haswell_gtt_driver },
1597 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
1598 "Haswell", &haswell_gtt_driver },
1599 { 0, NULL, NULL }
1600 };
1601
1602 static int find_gmch(u16 device)
1603 {
1604 struct pci_dev *gmch_device;
1605
1606 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1607 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1608 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1609 device, gmch_device);
1610 }
1611
1612 if (!gmch_device)
1613 return 0;
1614
1615 intel_private.pcidev = gmch_device;
1616 return 1;
1617 }
1618
1619 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1620 struct agp_bridge_data *bridge)
1621 {
1622 int i, mask;
1623
1624 /*
1625 * Can be called from the fake agp driver but also directly from
1626 * drm/i915.ko. Hence we need to check whether everything is set up
1627 * already.
1628 */
1629 if (intel_private.driver) {
1630 intel_private.refcount++;
1631 return 1;
1632 }
1633
1634 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1635 if (gpu_pdev) {
1636 if (gpu_pdev->device ==
1637 intel_gtt_chipsets[i].gmch_chip_id) {
1638 intel_private.pcidev = pci_dev_get(gpu_pdev);
1639 intel_private.driver =
1640 intel_gtt_chipsets[i].gtt_driver;
1641
1642 break;
1643 }
1644 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1645 intel_private.driver =
1646 intel_gtt_chipsets[i].gtt_driver;
1647 break;
1648 }
1649 }
1650
1651 if (!intel_private.driver)
1652 return 0;
1653
1654 intel_private.refcount++;
1655
1656 if (bridge) {
1657 bridge->driver = &intel_fake_agp_driver;
1658 bridge->dev_private_data = &intel_private;
1659 bridge->dev = bridge_pdev;
1660 }
1661
1662 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1663
1664 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1665
1666 mask = intel_private.driver->dma_mask_size;
1667 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1668 dev_err(&intel_private.pcidev->dev,
1669 "set gfx device dma mask %d-bit failed!\n", mask);
1670 else
1671 pci_set_consistent_dma_mask(intel_private.pcidev,
1672 DMA_BIT_MASK(mask));
1673
1674 if (intel_gtt_init() != 0) {
1675 intel_gmch_remove();
1676
1677 return 0;
1678 }
1679
1680 return 1;
1681 }
1682 EXPORT_SYMBOL(intel_gmch_probe);
1683
1684 const struct intel_gtt *intel_gtt_get(void)
1685 {
1686 return &intel_private.base;
1687 }
1688 EXPORT_SYMBOL(intel_gtt_get);
1689
1690 void intel_gtt_chipset_flush(void)
1691 {
1692 if (intel_private.driver->chipset_flush)
1693 intel_private.driver->chipset_flush();
1694 }
1695 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1696
1697 void intel_gmch_remove(void)
1698 {
1699 if (--intel_private.refcount)
1700 return;
1701
1702 if (intel_private.pcidev)
1703 pci_dev_put(intel_private.pcidev);
1704 if (intel_private.bridge_dev)
1705 pci_dev_put(intel_private.bridge_dev);
1706 intel_private.driver = NULL;
1707 }
1708 EXPORT_SYMBOL(intel_gmch_remove);
1709
1710 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1711 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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