1 /* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Abraham vd Merwe <abraham@2d3d.co.za>
38 #include <linux/interrupt.h> /* For task queue support */
39 #include <linux/pagemap.h> /* For FASTCALL on unlock_page() */
40 #include <linux/delay.h>
41 #include <asm/uaccess.h>
43 #define I830_BUF_FREE 2
44 #define I830_BUF_CLIENT 1
45 #define I830_BUF_HARDWARE 0
47 #define I830_BUF_UNMAPPED 0
48 #define I830_BUF_MAPPED 1
50 static drm_buf_t
*i830_freelist_get(drm_device_t
* dev
)
52 drm_device_dma_t
*dma
= dev
->dma
;
56 /* Linear search might not be the best solution */
58 for (i
= 0; i
< dma
->buf_count
; i
++) {
59 drm_buf_t
*buf
= dma
->buflist
[i
];
60 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
61 /* In use is already a pointer */
62 used
= cmpxchg(buf_priv
->in_use
, I830_BUF_FREE
,
64 if (used
== I830_BUF_FREE
) {
71 /* This should only be called if the buffer is not sent to the hardware
72 * yet, the hardware updates in use for us once its on the ring buffer.
75 static int i830_freelist_put(drm_device_t
* dev
, drm_buf_t
* buf
)
77 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
80 /* In use is already a pointer */
81 used
= cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
, I830_BUF_FREE
);
82 if (used
!= I830_BUF_CLIENT
) {
83 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf
->idx
);
90 static int i830_mmap_buffers(struct file
*filp
, struct vm_area_struct
*vma
)
92 drm_file_t
*priv
= filp
->private_data
;
94 drm_i830_private_t
*dev_priv
;
96 drm_i830_buf_priv_t
*buf_priv
;
99 dev
= priv
->head
->dev
;
100 dev_priv
= dev
->dev_private
;
101 buf
= dev_priv
->mmap_buffer
;
102 buf_priv
= buf
->dev_private
;
104 vma
->vm_flags
|= (VM_IO
| VM_DONTCOPY
);
107 buf_priv
->currently_mapped
= I830_BUF_MAPPED
;
110 if (io_remap_pfn_range(vma
, vma
->vm_start
,
111 VM_OFFSET(vma
) >> PAGE_SHIFT
,
112 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
117 static struct file_operations i830_buffer_fops
= {
120 .release
= drm_release
,
122 .mmap
= i830_mmap_buffers
,
123 .fasync
= drm_fasync
,
126 static int i830_map_buffer(drm_buf_t
* buf
, struct file
*filp
)
128 drm_file_t
*priv
= filp
->private_data
;
129 drm_device_t
*dev
= priv
->head
->dev
;
130 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
131 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
132 struct file_operations
*old_fops
;
133 unsigned long virtual;
136 if (buf_priv
->currently_mapped
== I830_BUF_MAPPED
)
139 down_write(¤t
->mm
->mmap_sem
);
140 old_fops
= filp
->f_op
;
141 filp
->f_op
= &i830_buffer_fops
;
142 dev_priv
->mmap_buffer
= buf
;
143 virtual = do_mmap(filp
, 0, buf
->total
, PROT_READ
| PROT_WRITE
,
144 MAP_SHARED
, buf
->bus_address
);
145 dev_priv
->mmap_buffer
= NULL
;
146 filp
->f_op
= old_fops
;
147 if (IS_ERR((void *)virtual)) { /* ugh */
149 DRM_ERROR("mmap error\n");
151 buf_priv
->virtual = NULL
;
153 buf_priv
->virtual = (void __user
*)virtual;
155 up_write(¤t
->mm
->mmap_sem
);
160 static int i830_unmap_buffer(drm_buf_t
* buf
)
162 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
165 if (buf_priv
->currently_mapped
!= I830_BUF_MAPPED
)
168 down_write(¤t
->mm
->mmap_sem
);
169 retcode
= do_munmap(current
->mm
,
170 (unsigned long)buf_priv
->virtual,
171 (size_t) buf
->total
);
172 up_write(¤t
->mm
->mmap_sem
);
174 buf_priv
->currently_mapped
= I830_BUF_UNMAPPED
;
175 buf_priv
->virtual = NULL
;
180 static int i830_dma_get_buffer(drm_device_t
* dev
, drm_i830_dma_t
* d
,
184 drm_i830_buf_priv_t
*buf_priv
;
187 buf
= i830_freelist_get(dev
);
190 DRM_DEBUG("retcode=%d\n", retcode
);
194 retcode
= i830_map_buffer(buf
, filp
);
196 i830_freelist_put(dev
, buf
);
197 DRM_ERROR("mapbuf failed, retcode %d\n", retcode
);
201 buf_priv
= buf
->dev_private
;
203 d
->request_idx
= buf
->idx
;
204 d
->request_size
= buf
->total
;
205 d
->virtual = buf_priv
->virtual;
210 static int i830_dma_cleanup(drm_device_t
* dev
)
212 drm_device_dma_t
*dma
= dev
->dma
;
214 /* Make sure interrupts are disabled here because the uninstall ioctl
215 * may not have been called from userspace and after dev_private
216 * is freed, it's too late.
218 if (dev
->irq_enabled
)
219 drm_irq_uninstall(dev
);
221 if (dev
->dev_private
) {
223 drm_i830_private_t
*dev_priv
=
224 (drm_i830_private_t
*) dev
->dev_private
;
226 if (dev_priv
->ring
.virtual_start
) {
227 drm_ioremapfree((void *)dev_priv
->ring
.virtual_start
,
228 dev_priv
->ring
.Size
, dev
);
230 if (dev_priv
->hw_status_page
) {
231 pci_free_consistent(dev
->pdev
, PAGE_SIZE
,
232 dev_priv
->hw_status_page
,
233 dev_priv
->dma_status_page
);
234 /* Need to rewrite hardware status page */
235 I830_WRITE(0x02080, 0x1ffff000);
238 drm_free(dev
->dev_private
, sizeof(drm_i830_private_t
),
240 dev
->dev_private
= NULL
;
242 for (i
= 0; i
< dma
->buf_count
; i
++) {
243 drm_buf_t
*buf
= dma
->buflist
[i
];
244 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
245 if (buf_priv
->kernel_virtual
&& buf
->total
)
246 drm_ioremapfree(buf_priv
->kernel_virtual
,
253 int i830_wait_ring(drm_device_t
* dev
, int n
, const char *caller
)
255 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
256 drm_i830_ring_buffer_t
*ring
= &(dev_priv
->ring
);
259 unsigned int last_head
= I830_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
261 end
= jiffies
+ (HZ
* 3);
262 while (ring
->space
< n
) {
263 ring
->head
= I830_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
264 ring
->space
= ring
->head
- (ring
->tail
+ 8);
266 ring
->space
+= ring
->Size
;
268 if (ring
->head
!= last_head
) {
269 end
= jiffies
+ (HZ
* 3);
270 last_head
= ring
->head
;
274 if (time_before(end
, jiffies
)) {
275 DRM_ERROR("space: %d wanted %d\n", ring
->space
, n
);
276 DRM_ERROR("lockup\n");
280 dev_priv
->sarea_priv
->perf_boxes
|= I830_BOX_WAIT
;
287 static void i830_kernel_lost_context(drm_device_t
* dev
)
289 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
290 drm_i830_ring_buffer_t
*ring
= &(dev_priv
->ring
);
292 ring
->head
= I830_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
293 ring
->tail
= I830_READ(LP_RING
+ RING_TAIL
) & TAIL_ADDR
;
294 ring
->space
= ring
->head
- (ring
->tail
+ 8);
296 ring
->space
+= ring
->Size
;
298 if (ring
->head
== ring
->tail
)
299 dev_priv
->sarea_priv
->perf_boxes
|= I830_BOX_RING_EMPTY
;
302 static int i830_freelist_init(drm_device_t
* dev
, drm_i830_private_t
* dev_priv
)
304 drm_device_dma_t
*dma
= dev
->dma
;
306 u32
*hw_status
= (u32
*) (dev_priv
->hw_status_page
+ my_idx
);
309 if (dma
->buf_count
> 1019) {
310 /* Not enough space in the status page for the freelist */
314 for (i
= 0; i
< dma
->buf_count
; i
++) {
315 drm_buf_t
*buf
= dma
->buflist
[i
];
316 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
318 buf_priv
->in_use
= hw_status
++;
319 buf_priv
->my_use_idx
= my_idx
;
322 *buf_priv
->in_use
= I830_BUF_FREE
;
324 buf_priv
->kernel_virtual
= drm_ioremap(buf
->bus_address
,
330 static int i830_dma_initialize(drm_device_t
* dev
,
331 drm_i830_private_t
* dev_priv
,
332 drm_i830_init_t
* init
)
334 struct list_head
*list
;
336 memset(dev_priv
, 0, sizeof(drm_i830_private_t
));
338 list_for_each(list
, &dev
->maplist
->head
) {
339 drm_map_list_t
*r_list
= list_entry(list
, drm_map_list_t
, head
);
341 r_list
->map
->type
== _DRM_SHM
&&
342 r_list
->map
->flags
& _DRM_CONTAINS_LOCK
) {
343 dev_priv
->sarea_map
= r_list
->map
;
348 if (!dev_priv
->sarea_map
) {
349 dev
->dev_private
= (void *)dev_priv
;
350 i830_dma_cleanup(dev
);
351 DRM_ERROR("can not find sarea!\n");
354 dev_priv
->mmio_map
= drm_core_findmap(dev
, init
->mmio_offset
);
355 if (!dev_priv
->mmio_map
) {
356 dev
->dev_private
= (void *)dev_priv
;
357 i830_dma_cleanup(dev
);
358 DRM_ERROR("can not find mmio map!\n");
361 dev
->agp_buffer_token
= init
->buffers_offset
;
362 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
363 if (!dev
->agp_buffer_map
) {
364 dev
->dev_private
= (void *)dev_priv
;
365 i830_dma_cleanup(dev
);
366 DRM_ERROR("can not find dma buffer map!\n");
370 dev_priv
->sarea_priv
= (drm_i830_sarea_t
*)
371 ((u8
*) dev_priv
->sarea_map
->handle
+ init
->sarea_priv_offset
);
373 dev_priv
->ring
.Start
= init
->ring_start
;
374 dev_priv
->ring
.End
= init
->ring_end
;
375 dev_priv
->ring
.Size
= init
->ring_size
;
377 dev_priv
->ring
.virtual_start
= drm_ioremap(dev
->agp
->base
+
379 init
->ring_size
, dev
);
381 if (dev_priv
->ring
.virtual_start
== NULL
) {
382 dev
->dev_private
= (void *)dev_priv
;
383 i830_dma_cleanup(dev
);
384 DRM_ERROR("can not ioremap virtual address for"
389 dev_priv
->ring
.tail_mask
= dev_priv
->ring
.Size
- 1;
391 dev_priv
->w
= init
->w
;
392 dev_priv
->h
= init
->h
;
393 dev_priv
->pitch
= init
->pitch
;
394 dev_priv
->back_offset
= init
->back_offset
;
395 dev_priv
->depth_offset
= init
->depth_offset
;
396 dev_priv
->front_offset
= init
->front_offset
;
398 dev_priv
->front_di1
= init
->front_offset
| init
->pitch_bits
;
399 dev_priv
->back_di1
= init
->back_offset
| init
->pitch_bits
;
400 dev_priv
->zi1
= init
->depth_offset
| init
->pitch_bits
;
402 DRM_DEBUG("front_di1 %x\n", dev_priv
->front_di1
);
403 DRM_DEBUG("back_offset %x\n", dev_priv
->back_offset
);
404 DRM_DEBUG("back_di1 %x\n", dev_priv
->back_di1
);
405 DRM_DEBUG("pitch_bits %x\n", init
->pitch_bits
);
407 dev_priv
->cpp
= init
->cpp
;
408 /* We are using separate values as placeholders for mechanisms for
409 * private backbuffer/depthbuffer usage.
412 dev_priv
->back_pitch
= init
->back_pitch
;
413 dev_priv
->depth_pitch
= init
->depth_pitch
;
414 dev_priv
->do_boxes
= 0;
415 dev_priv
->use_mi_batchbuffer_start
= 0;
417 /* Program Hardware Status Page */
418 dev_priv
->hw_status_page
=
419 pci_alloc_consistent(dev
->pdev
, PAGE_SIZE
,
420 &dev_priv
->dma_status_page
);
421 if (!dev_priv
->hw_status_page
) {
422 dev
->dev_private
= (void *)dev_priv
;
423 i830_dma_cleanup(dev
);
424 DRM_ERROR("Can not allocate hardware status page\n");
427 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
428 DRM_DEBUG("hw status page @ %p\n", dev_priv
->hw_status_page
);
430 I830_WRITE(0x02080, dev_priv
->dma_status_page
);
431 DRM_DEBUG("Enabled hardware status page\n");
433 /* Now we need to init our freelist */
434 if (i830_freelist_init(dev
, dev_priv
) != 0) {
435 dev
->dev_private
= (void *)dev_priv
;
436 i830_dma_cleanup(dev
);
437 DRM_ERROR("Not enough space in the status page for"
441 dev
->dev_private
= (void *)dev_priv
;
446 static int i830_dma_init(struct inode
*inode
, struct file
*filp
,
447 unsigned int cmd
, unsigned long arg
)
449 drm_file_t
*priv
= filp
->private_data
;
450 drm_device_t
*dev
= priv
->head
->dev
;
451 drm_i830_private_t
*dev_priv
;
452 drm_i830_init_t init
;
455 if (copy_from_user(&init
, (void *__user
)arg
, sizeof(init
)))
460 dev_priv
= drm_alloc(sizeof(drm_i830_private_t
),
462 if (dev_priv
== NULL
)
464 retcode
= i830_dma_initialize(dev
, dev_priv
, &init
);
466 case I830_CLEANUP_DMA
:
467 retcode
= i830_dma_cleanup(dev
);
477 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
478 #define ST1_ENABLE (1<<16)
479 #define ST1_MASK (0xffff)
481 /* Most efficient way to verify state for the i830 is as it is
482 * emitted. Non-conformant state is silently dropped.
484 static void i830EmitContextVerified(drm_device_t
* dev
, unsigned int *code
)
486 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
491 BEGIN_LP_RING(I830_CTX_SETUP_SIZE
+ 4);
493 for (i
= 0; i
< I830_CTXREG_BLENDCOLR0
; i
++) {
495 if ((tmp
& (7 << 29)) == CMD_3D
&&
496 (tmp
& (0x1f << 24)) < (0x1d << 24)) {
500 DRM_ERROR("Skipping %d\n", i
);
504 OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD
);
505 OUT_RING(code
[I830_CTXREG_BLENDCOLR
]);
508 for (i
= I830_CTXREG_VF
; i
< I830_CTXREG_MCSB0
; i
++) {
510 if ((tmp
& (7 << 29)) == CMD_3D
&&
511 (tmp
& (0x1f << 24)) < (0x1d << 24)) {
515 DRM_ERROR("Skipping %d\n", i
);
519 OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD
);
520 OUT_RING(code
[I830_CTXREG_MCSB1
]);
529 static void i830EmitTexVerified(drm_device_t
* dev
, unsigned int *code
)
531 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
536 if (code
[I830_TEXREG_MI0
] == GFX_OP_MAP_INFO
||
537 (code
[I830_TEXREG_MI0
] & ~(0xf * LOAD_TEXTURE_MAP0
)) ==
538 (STATE3D_LOAD_STATE_IMMEDIATE_2
| 4)) {
540 BEGIN_LP_RING(I830_TEX_SETUP_SIZE
);
542 OUT_RING(code
[I830_TEXREG_MI0
]); /* TM0LI */
543 OUT_RING(code
[I830_TEXREG_MI1
]); /* TM0S0 */
544 OUT_RING(code
[I830_TEXREG_MI2
]); /* TM0S1 */
545 OUT_RING(code
[I830_TEXREG_MI3
]); /* TM0S2 */
546 OUT_RING(code
[I830_TEXREG_MI4
]); /* TM0S3 */
547 OUT_RING(code
[I830_TEXREG_MI5
]); /* TM0S4 */
549 for (i
= 6; i
< I830_TEX_SETUP_SIZE
; i
++) {
560 printk("rejected packet %x\n", code
[0]);
563 static void i830EmitTexBlendVerified(drm_device_t
* dev
,
564 unsigned int *code
, unsigned int num
)
566 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
574 BEGIN_LP_RING(num
+ 1);
576 for (i
= 0; i
< num
; i
++) {
588 static void i830EmitTexPalette(drm_device_t
* dev
,
589 unsigned int *palette
, int number
, int is_shared
)
591 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
599 if (is_shared
== 1) {
600 OUT_RING(CMD_OP_MAP_PALETTE_LOAD
|
601 MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH
);
603 OUT_RING(CMD_OP_MAP_PALETTE_LOAD
| MAP_PALETTE_NUM(number
));
605 for (i
= 0; i
< 256; i
++) {
606 OUT_RING(palette
[i
]);
609 /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop!
613 /* Need to do some additional checking when setting the dest buffer.
615 static void i830EmitDestVerified(drm_device_t
* dev
, unsigned int *code
)
617 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
621 BEGIN_LP_RING(I830_DEST_SETUP_SIZE
+ 10);
623 tmp
= code
[I830_DESTREG_CBUFADDR
];
624 if (tmp
== dev_priv
->front_di1
|| tmp
== dev_priv
->back_di1
) {
625 if (((int)outring
) & 8) {
630 OUT_RING(CMD_OP_DESTBUFFER_INFO
);
631 OUT_RING(BUF_3D_ID_COLOR_BACK
|
632 BUF_3D_PITCH(dev_priv
->back_pitch
* dev_priv
->cpp
) |
637 OUT_RING(CMD_OP_DESTBUFFER_INFO
);
638 OUT_RING(BUF_3D_ID_DEPTH
| BUF_3D_USE_FENCE
|
639 BUF_3D_PITCH(dev_priv
->depth_pitch
* dev_priv
->cpp
));
640 OUT_RING(dev_priv
->zi1
);
643 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
644 tmp
, dev_priv
->front_di1
, dev_priv
->back_di1
);
650 OUT_RING(GFX_OP_DESTBUFFER_VARS
);
651 OUT_RING(code
[I830_DESTREG_DV1
]);
653 OUT_RING(GFX_OP_DRAWRECT_INFO
);
654 OUT_RING(code
[I830_DESTREG_DR1
]);
655 OUT_RING(code
[I830_DESTREG_DR2
]);
656 OUT_RING(code
[I830_DESTREG_DR3
]);
657 OUT_RING(code
[I830_DESTREG_DR4
]);
659 /* Need to verify this */
660 tmp
= code
[I830_DESTREG_SENABLE
];
661 if ((tmp
& ~0x3) == GFX_OP_SCISSOR_ENABLE
) {
664 DRM_ERROR("bad scissor enable\n");
668 OUT_RING(GFX_OP_SCISSOR_RECT
);
669 OUT_RING(code
[I830_DESTREG_SR1
]);
670 OUT_RING(code
[I830_DESTREG_SR2
]);
676 static void i830EmitStippleVerified(drm_device_t
* dev
, unsigned int *code
)
678 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
682 OUT_RING(GFX_OP_STIPPLE
);
687 static void i830EmitState(drm_device_t
* dev
)
689 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
690 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
691 unsigned int dirty
= sarea_priv
->dirty
;
693 DRM_DEBUG("%s %x\n", __FUNCTION__
, dirty
);
695 if (dirty
& I830_UPLOAD_BUFFERS
) {
696 i830EmitDestVerified(dev
, sarea_priv
->BufferState
);
697 sarea_priv
->dirty
&= ~I830_UPLOAD_BUFFERS
;
700 if (dirty
& I830_UPLOAD_CTX
) {
701 i830EmitContextVerified(dev
, sarea_priv
->ContextState
);
702 sarea_priv
->dirty
&= ~I830_UPLOAD_CTX
;
705 if (dirty
& I830_UPLOAD_TEX0
) {
706 i830EmitTexVerified(dev
, sarea_priv
->TexState
[0]);
707 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX0
;
710 if (dirty
& I830_UPLOAD_TEX1
) {
711 i830EmitTexVerified(dev
, sarea_priv
->TexState
[1]);
712 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX1
;
715 if (dirty
& I830_UPLOAD_TEXBLEND0
) {
716 i830EmitTexBlendVerified(dev
, sarea_priv
->TexBlendState
[0],
717 sarea_priv
->TexBlendStateWordsUsed
[0]);
718 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND0
;
721 if (dirty
& I830_UPLOAD_TEXBLEND1
) {
722 i830EmitTexBlendVerified(dev
, sarea_priv
->TexBlendState
[1],
723 sarea_priv
->TexBlendStateWordsUsed
[1]);
724 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND1
;
727 if (dirty
& I830_UPLOAD_TEX_PALETTE_SHARED
) {
728 i830EmitTexPalette(dev
, sarea_priv
->Palette
[0], 0, 1);
730 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(0)) {
731 i830EmitTexPalette(dev
, sarea_priv
->Palette
[0], 0, 0);
732 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(0);
734 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(1)) {
735 i830EmitTexPalette(dev
, sarea_priv
->Palette
[1], 1, 0);
736 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(1);
742 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(2)) {
743 i830EmitTexPalette(dev
, sarea_priv
->Palette2
[0], 0, 0);
744 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(2);
746 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(3)) {
747 i830EmitTexPalette(dev
, sarea_priv
->Palette2
[1], 1, 0);
748 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(2);
755 if (dirty
& I830_UPLOAD_STIPPLE
) {
756 i830EmitStippleVerified(dev
, sarea_priv
->StippleState
);
757 sarea_priv
->dirty
&= ~I830_UPLOAD_STIPPLE
;
760 if (dirty
& I830_UPLOAD_TEX2
) {
761 i830EmitTexVerified(dev
, sarea_priv
->TexState2
);
762 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX2
;
765 if (dirty
& I830_UPLOAD_TEX3
) {
766 i830EmitTexVerified(dev
, sarea_priv
->TexState3
);
767 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX3
;
770 if (dirty
& I830_UPLOAD_TEXBLEND2
) {
771 i830EmitTexBlendVerified(dev
,
772 sarea_priv
->TexBlendState2
,
773 sarea_priv
->TexBlendStateWordsUsed2
);
775 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND2
;
778 if (dirty
& I830_UPLOAD_TEXBLEND3
) {
779 i830EmitTexBlendVerified(dev
,
780 sarea_priv
->TexBlendState3
,
781 sarea_priv
->TexBlendStateWordsUsed3
);
782 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND3
;
786 /* ================================================================
787 * Performance monitoring functions
790 static void i830_fill_box(drm_device_t
* dev
,
791 int x
, int y
, int w
, int h
, int r
, int g
, int b
)
793 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
795 unsigned int BR13
, CMD
;
798 BR13
= (0xF0 << 16) | (dev_priv
->pitch
* dev_priv
->cpp
) | (1 << 24);
799 CMD
= XY_COLOR_BLT_CMD
;
800 x
+= dev_priv
->sarea_priv
->boxes
[0].x1
;
801 y
+= dev_priv
->sarea_priv
->boxes
[0].y1
;
803 if (dev_priv
->cpp
== 4) {
805 CMD
|= (XY_COLOR_BLT_WRITE_ALPHA
| XY_COLOR_BLT_WRITE_RGB
);
806 color
= (((0xff) << 24) | (r
<< 16) | (g
<< 8) | b
);
808 color
= (((r
& 0xf8) << 8) |
809 ((g
& 0xfc) << 3) | ((b
& 0xf8) >> 3));
815 OUT_RING((y
<< 16) | x
);
816 OUT_RING(((y
+ h
) << 16) | (x
+ w
));
818 if (dev_priv
->current_page
== 1) {
819 OUT_RING(dev_priv
->front_offset
);
821 OUT_RING(dev_priv
->back_offset
);
828 static void i830_cp_performance_boxes(drm_device_t
* dev
)
830 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
832 /* Purple box for page flipping
834 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_FLIP
)
835 i830_fill_box(dev
, 4, 4, 8, 8, 255, 0, 255);
837 /* Red box if we have to wait for idle at any point
839 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_WAIT
)
840 i830_fill_box(dev
, 16, 4, 8, 8, 255, 0, 0);
842 /* Blue box: lost context?
844 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_LOST_CONTEXT
)
845 i830_fill_box(dev
, 28, 4, 8, 8, 0, 0, 255);
847 /* Yellow box for texture swaps
849 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_TEXTURE_LOAD
)
850 i830_fill_box(dev
, 40, 4, 8, 8, 255, 255, 0);
852 /* Green box if hardware never idles (as far as we can tell)
854 if (!(dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_RING_EMPTY
))
855 i830_fill_box(dev
, 64, 4, 8, 8, 0, 255, 0);
857 /* Draw bars indicating number of buffers allocated
858 * (not a great measure, easily confused)
860 if (dev_priv
->dma_used
) {
861 int bar
= dev_priv
->dma_used
/ 10240;
866 i830_fill_box(dev
, 4, 16, bar
, 4, 196, 128, 128);
867 dev_priv
->dma_used
= 0;
870 dev_priv
->sarea_priv
->perf_boxes
= 0;
873 static void i830_dma_dispatch_clear(drm_device_t
* dev
, int flags
,
874 unsigned int clear_color
,
875 unsigned int clear_zval
,
876 unsigned int clear_depthmask
)
878 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
879 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
880 int nbox
= sarea_priv
->nbox
;
881 drm_clip_rect_t
*pbox
= sarea_priv
->boxes
;
882 int pitch
= dev_priv
->pitch
;
883 int cpp
= dev_priv
->cpp
;
885 unsigned int BR13
, CMD
, D_CMD
;
888 if (dev_priv
->current_page
== 1) {
889 unsigned int tmp
= flags
;
891 flags
&= ~(I830_FRONT
| I830_BACK
);
892 if (tmp
& I830_FRONT
)
898 i830_kernel_lost_context(dev
);
902 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24);
903 D_CMD
= CMD
= XY_COLOR_BLT_CMD
;
906 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24) | (1 << 25);
907 CMD
= (XY_COLOR_BLT_CMD
| XY_COLOR_BLT_WRITE_ALPHA
|
908 XY_COLOR_BLT_WRITE_RGB
);
909 D_CMD
= XY_COLOR_BLT_CMD
;
910 if (clear_depthmask
& 0x00ffffff)
911 D_CMD
|= XY_COLOR_BLT_WRITE_RGB
;
912 if (clear_depthmask
& 0xff000000)
913 D_CMD
|= XY_COLOR_BLT_WRITE_ALPHA
;
916 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24);
917 D_CMD
= CMD
= XY_COLOR_BLT_CMD
;
921 if (nbox
> I830_NR_SAREA_CLIPRECTS
)
922 nbox
= I830_NR_SAREA_CLIPRECTS
;
924 for (i
= 0; i
< nbox
; i
++, pbox
++) {
925 if (pbox
->x1
> pbox
->x2
||
926 pbox
->y1
> pbox
->y2
||
927 pbox
->x2
> dev_priv
->w
|| pbox
->y2
> dev_priv
->h
)
930 if (flags
& I830_FRONT
) {
931 DRM_DEBUG("clear front\n");
935 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
936 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
937 OUT_RING(dev_priv
->front_offset
);
938 OUT_RING(clear_color
);
942 if (flags
& I830_BACK
) {
943 DRM_DEBUG("clear back\n");
947 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
948 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
949 OUT_RING(dev_priv
->back_offset
);
950 OUT_RING(clear_color
);
954 if (flags
& I830_DEPTH
) {
955 DRM_DEBUG("clear depth\n");
959 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
960 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
961 OUT_RING(dev_priv
->depth_offset
);
962 OUT_RING(clear_zval
);
968 static void i830_dma_dispatch_swap(drm_device_t
* dev
)
970 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
971 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
972 int nbox
= sarea_priv
->nbox
;
973 drm_clip_rect_t
*pbox
= sarea_priv
->boxes
;
974 int pitch
= dev_priv
->pitch
;
975 int cpp
= dev_priv
->cpp
;
977 unsigned int CMD
, BR13
;
980 DRM_DEBUG("swapbuffers\n");
982 i830_kernel_lost_context(dev
);
984 if (dev_priv
->do_boxes
)
985 i830_cp_performance_boxes(dev
);
989 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24);
990 CMD
= XY_SRC_COPY_BLT_CMD
;
993 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24) | (1 << 25);
994 CMD
= (XY_SRC_COPY_BLT_CMD
| XY_SRC_COPY_BLT_WRITE_ALPHA
|
995 XY_SRC_COPY_BLT_WRITE_RGB
);
998 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24);
999 CMD
= XY_SRC_COPY_BLT_CMD
;
1003 if (nbox
> I830_NR_SAREA_CLIPRECTS
)
1004 nbox
= I830_NR_SAREA_CLIPRECTS
;
1006 for (i
= 0; i
< nbox
; i
++, pbox
++) {
1007 if (pbox
->x1
> pbox
->x2
||
1008 pbox
->y1
> pbox
->y2
||
1009 pbox
->x2
> dev_priv
->w
|| pbox
->y2
> dev_priv
->h
)
1012 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1013 pbox
->x1
, pbox
->y1
, pbox
->x2
, pbox
->y2
);
1018 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
1019 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
1021 if (dev_priv
->current_page
== 0)
1022 OUT_RING(dev_priv
->front_offset
);
1024 OUT_RING(dev_priv
->back_offset
);
1026 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
1027 OUT_RING(BR13
& 0xffff);
1029 if (dev_priv
->current_page
== 0)
1030 OUT_RING(dev_priv
->back_offset
);
1032 OUT_RING(dev_priv
->front_offset
);
1038 static void i830_dma_dispatch_flip(drm_device_t
* dev
)
1040 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1043 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1045 dev_priv
->current_page
,
1046 dev_priv
->sarea_priv
->pf_current_page
);
1048 i830_kernel_lost_context(dev
);
1050 if (dev_priv
->do_boxes
) {
1051 dev_priv
->sarea_priv
->perf_boxes
|= I830_BOX_FLIP
;
1052 i830_cp_performance_boxes(dev
);
1056 OUT_RING(INST_PARSER_CLIENT
| INST_OP_FLUSH
| INST_FLUSH_MAP_CACHE
);
1061 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
1063 if (dev_priv
->current_page
== 0) {
1064 OUT_RING(dev_priv
->back_offset
);
1065 dev_priv
->current_page
= 1;
1067 OUT_RING(dev_priv
->front_offset
);
1068 dev_priv
->current_page
= 0;
1074 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
1078 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
1081 static void i830_dma_dispatch_vertex(drm_device_t
* dev
,
1082 drm_buf_t
* buf
, int discard
, int used
)
1084 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1085 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
1086 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
1087 drm_clip_rect_t
*box
= sarea_priv
->boxes
;
1088 int nbox
= sarea_priv
->nbox
;
1089 unsigned long address
= (unsigned long)buf
->bus_address
;
1090 unsigned long start
= address
- dev
->agp
->base
;
1094 i830_kernel_lost_context(dev
);
1096 if (nbox
> I830_NR_SAREA_CLIPRECTS
)
1097 nbox
= I830_NR_SAREA_CLIPRECTS
;
1100 u
= cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
,
1102 if (u
!= I830_BUF_CLIENT
) {
1103 DRM_DEBUG("xxxx 2\n");
1107 if (used
> 4 * 1023)
1110 if (sarea_priv
->dirty
)
1113 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1114 address
, used
, nbox
);
1116 dev_priv
->counter
++;
1117 DRM_DEBUG("dispatch counter : %ld\n", dev_priv
->counter
);
1118 DRM_DEBUG("i830_dma_dispatch\n");
1119 DRM_DEBUG("start : %lx\n", start
);
1120 DRM_DEBUG("used : %d\n", used
);
1121 DRM_DEBUG("start + used - 4 : %ld\n", start
+ used
- 4);
1123 if (buf_priv
->currently_mapped
== I830_BUF_MAPPED
) {
1124 u32
*vp
= buf_priv
->kernel_virtual
;
1126 vp
[0] = (GFX_OP_PRIMITIVE
|
1127 sarea_priv
->vertex_prim
| ((used
/ 4) - 2));
1129 if (dev_priv
->use_mi_batchbuffer_start
) {
1130 vp
[used
/ 4] = MI_BATCH_BUFFER_END
;
1139 i830_unmap_buffer(buf
);
1146 OUT_RING(GFX_OP_DRAWRECT_INFO
);
1147 OUT_RING(sarea_priv
->
1148 BufferState
[I830_DESTREG_DR1
]);
1149 OUT_RING(box
[i
].x1
| (box
[i
].y1
<< 16));
1150 OUT_RING(box
[i
].x2
| (box
[i
].y2
<< 16));
1151 OUT_RING(sarea_priv
->
1152 BufferState
[I830_DESTREG_DR4
]);
1157 if (dev_priv
->use_mi_batchbuffer_start
) {
1159 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
1160 OUT_RING(start
| MI_BATCH_NON_SECURE
);
1164 OUT_RING(MI_BATCH_BUFFER
);
1165 OUT_RING(start
| MI_BATCH_NON_SECURE
);
1166 OUT_RING(start
+ used
- 4);
1171 } while (++i
< nbox
);
1175 dev_priv
->counter
++;
1177 (void)cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
,
1181 OUT_RING(CMD_STORE_DWORD_IDX
);
1183 OUT_RING(dev_priv
->counter
);
1184 OUT_RING(CMD_STORE_DWORD_IDX
);
1185 OUT_RING(buf_priv
->my_use_idx
);
1186 OUT_RING(I830_BUF_FREE
);
1187 OUT_RING(CMD_REPORT_HEAD
);
1193 static void i830_dma_quiescent(drm_device_t
* dev
)
1195 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1198 i830_kernel_lost_context(dev
);
1201 OUT_RING(INST_PARSER_CLIENT
| INST_OP_FLUSH
| INST_FLUSH_MAP_CACHE
);
1202 OUT_RING(CMD_REPORT_HEAD
);
1207 i830_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __FUNCTION__
);
1210 static int i830_flush_queue(drm_device_t
* dev
)
1212 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1213 drm_device_dma_t
*dma
= dev
->dma
;
1217 i830_kernel_lost_context(dev
);
1220 OUT_RING(CMD_REPORT_HEAD
);
1224 i830_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __FUNCTION__
);
1226 for (i
= 0; i
< dma
->buf_count
; i
++) {
1227 drm_buf_t
*buf
= dma
->buflist
[i
];
1228 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
1230 int used
= cmpxchg(buf_priv
->in_use
, I830_BUF_HARDWARE
,
1233 if (used
== I830_BUF_HARDWARE
)
1234 DRM_DEBUG("reclaimed from HARDWARE\n");
1235 if (used
== I830_BUF_CLIENT
)
1236 DRM_DEBUG("still on client\n");
1242 /* Must be called with the lock held */
1243 void i830_reclaim_buffers(drm_device_t
* dev
, struct file
*filp
)
1245 drm_device_dma_t
*dma
= dev
->dma
;
1250 if (!dev
->dev_private
)
1255 i830_flush_queue(dev
);
1257 for (i
= 0; i
< dma
->buf_count
; i
++) {
1258 drm_buf_t
*buf
= dma
->buflist
[i
];
1259 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
1261 if (buf
->filp
== filp
&& buf_priv
) {
1262 int used
= cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
,
1265 if (used
== I830_BUF_CLIENT
)
1266 DRM_DEBUG("reclaimed from client\n");
1267 if (buf_priv
->currently_mapped
== I830_BUF_MAPPED
)
1268 buf_priv
->currently_mapped
= I830_BUF_UNMAPPED
;
1273 static int i830_flush_ioctl(struct inode
*inode
, struct file
*filp
,
1274 unsigned int cmd
, unsigned long arg
)
1276 drm_file_t
*priv
= filp
->private_data
;
1277 drm_device_t
*dev
= priv
->head
->dev
;
1279 LOCK_TEST_WITH_RETURN(dev
, filp
);
1281 i830_flush_queue(dev
);
1285 static int i830_dma_vertex(struct inode
*inode
, struct file
*filp
,
1286 unsigned int cmd
, unsigned long arg
)
1288 drm_file_t
*priv
= filp
->private_data
;
1289 drm_device_t
*dev
= priv
->head
->dev
;
1290 drm_device_dma_t
*dma
= dev
->dma
;
1291 drm_i830_private_t
*dev_priv
= (drm_i830_private_t
*) dev
->dev_private
;
1292 u32
*hw_status
= dev_priv
->hw_status_page
;
1293 drm_i830_sarea_t
*sarea_priv
= (drm_i830_sarea_t
*)
1294 dev_priv
->sarea_priv
;
1295 drm_i830_vertex_t vertex
;
1298 (&vertex
, (drm_i830_vertex_t __user
*) arg
, sizeof(vertex
)))
1301 LOCK_TEST_WITH_RETURN(dev
, filp
);
1303 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1304 vertex
.idx
, vertex
.used
, vertex
.discard
);
1306 if (vertex
.idx
< 0 || vertex
.idx
> dma
->buf_count
)
1309 i830_dma_dispatch_vertex(dev
,
1310 dma
->buflist
[vertex
.idx
],
1311 vertex
.discard
, vertex
.used
);
1313 sarea_priv
->last_enqueue
= dev_priv
->counter
- 1;
1314 sarea_priv
->last_dispatch
= (int)hw_status
[5];
1319 static int i830_clear_bufs(struct inode
*inode
, struct file
*filp
,
1320 unsigned int cmd
, unsigned long arg
)
1322 drm_file_t
*priv
= filp
->private_data
;
1323 drm_device_t
*dev
= priv
->head
->dev
;
1324 drm_i830_clear_t clear
;
1327 (&clear
, (drm_i830_clear_t __user
*) arg
, sizeof(clear
)))
1330 LOCK_TEST_WITH_RETURN(dev
, filp
);
1332 /* GH: Someone's doing nasty things... */
1333 if (!dev
->dev_private
) {
1337 i830_dma_dispatch_clear(dev
, clear
.flags
,
1339 clear
.clear_depth
, clear
.clear_depthmask
);
1343 static int i830_swap_bufs(struct inode
*inode
, struct file
*filp
,
1344 unsigned int cmd
, unsigned long arg
)
1346 drm_file_t
*priv
= filp
->private_data
;
1347 drm_device_t
*dev
= priv
->head
->dev
;
1349 DRM_DEBUG("i830_swap_bufs\n");
1351 LOCK_TEST_WITH_RETURN(dev
, filp
);
1353 i830_dma_dispatch_swap(dev
);
1357 /* Not sure why this isn't set all the time:
1359 static void i830_do_init_pageflip(drm_device_t
* dev
)
1361 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1363 DRM_DEBUG("%s\n", __FUNCTION__
);
1364 dev_priv
->page_flipping
= 1;
1365 dev_priv
->current_page
= 0;
1366 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
1369 static int i830_do_cleanup_pageflip(drm_device_t
* dev
)
1371 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1373 DRM_DEBUG("%s\n", __FUNCTION__
);
1374 if (dev_priv
->current_page
!= 0)
1375 i830_dma_dispatch_flip(dev
);
1377 dev_priv
->page_flipping
= 0;
1381 static int i830_flip_bufs(struct inode
*inode
, struct file
*filp
,
1382 unsigned int cmd
, unsigned long arg
)
1384 drm_file_t
*priv
= filp
->private_data
;
1385 drm_device_t
*dev
= priv
->head
->dev
;
1386 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1388 DRM_DEBUG("%s\n", __FUNCTION__
);
1390 LOCK_TEST_WITH_RETURN(dev
, filp
);
1392 if (!dev_priv
->page_flipping
)
1393 i830_do_init_pageflip(dev
);
1395 i830_dma_dispatch_flip(dev
);
1399 static int i830_getage(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
1402 drm_file_t
*priv
= filp
->private_data
;
1403 drm_device_t
*dev
= priv
->head
->dev
;
1404 drm_i830_private_t
*dev_priv
= (drm_i830_private_t
*) dev
->dev_private
;
1405 u32
*hw_status
= dev_priv
->hw_status_page
;
1406 drm_i830_sarea_t
*sarea_priv
= (drm_i830_sarea_t
*)
1407 dev_priv
->sarea_priv
;
1409 sarea_priv
->last_dispatch
= (int)hw_status
[5];
1413 static int i830_getbuf(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
1416 drm_file_t
*priv
= filp
->private_data
;
1417 drm_device_t
*dev
= priv
->head
->dev
;
1420 drm_i830_private_t
*dev_priv
= (drm_i830_private_t
*) dev
->dev_private
;
1421 u32
*hw_status
= dev_priv
->hw_status_page
;
1422 drm_i830_sarea_t
*sarea_priv
= (drm_i830_sarea_t
*)
1423 dev_priv
->sarea_priv
;
1425 DRM_DEBUG("getbuf\n");
1426 if (copy_from_user(&d
, (drm_i830_dma_t __user
*) arg
, sizeof(d
)))
1429 LOCK_TEST_WITH_RETURN(dev
, filp
);
1433 retcode
= i830_dma_get_buffer(dev
, &d
, filp
);
1435 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1436 current
->pid
, retcode
, d
.granted
);
1438 if (copy_to_user((drm_dma_t __user
*) arg
, &d
, sizeof(d
)))
1440 sarea_priv
->last_dispatch
= (int)hw_status
[5];
1445 static int i830_copybuf(struct inode
*inode
,
1446 struct file
*filp
, unsigned int cmd
, unsigned long arg
)
1448 /* Never copy - 2.4.x doesn't need it */
1452 static int i830_docopy(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
1458 static int i830_getparam(struct inode
*inode
, struct file
*filp
,
1459 unsigned int cmd
, unsigned long arg
)
1461 drm_file_t
*priv
= filp
->private_data
;
1462 drm_device_t
*dev
= priv
->head
->dev
;
1463 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1464 drm_i830_getparam_t param
;
1468 DRM_ERROR("%s called with no initialization\n", __FUNCTION__
);
1473 (¶m
, (drm_i830_getparam_t __user
*) arg
, sizeof(param
)))
1476 switch (param
.param
) {
1477 case I830_PARAM_IRQ_ACTIVE
:
1478 value
= dev
->irq_enabled
;
1484 if (copy_to_user(param
.value
, &value
, sizeof(int))) {
1485 DRM_ERROR("copy_to_user\n");
1492 static int i830_setparam(struct inode
*inode
, struct file
*filp
,
1493 unsigned int cmd
, unsigned long arg
)
1495 drm_file_t
*priv
= filp
->private_data
;
1496 drm_device_t
*dev
= priv
->head
->dev
;
1497 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1498 drm_i830_setparam_t param
;
1501 DRM_ERROR("%s called with no initialization\n", __FUNCTION__
);
1506 (¶m
, (drm_i830_setparam_t __user
*) arg
, sizeof(param
)))
1509 switch (param
.param
) {
1510 case I830_SETPARAM_USE_MI_BATCHBUFFER_START
:
1511 dev_priv
->use_mi_batchbuffer_start
= param
.value
;
1520 void i830_driver_pretakedown(drm_device_t
* dev
)
1522 i830_dma_cleanup(dev
);
1525 void i830_driver_prerelease(drm_device_t
* dev
, DRMFILE filp
)
1527 if (dev
->dev_private
) {
1528 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1529 if (dev_priv
->page_flipping
) {
1530 i830_do_cleanup_pageflip(dev
);
1535 void i830_driver_release(drm_device_t
* dev
, struct file
*filp
)
1537 i830_reclaim_buffers(dev
, filp
);
1540 int i830_driver_dma_quiescent(drm_device_t
* dev
)
1542 i830_dma_quiescent(dev
);
1546 drm_ioctl_desc_t i830_ioctls
[] = {
1547 [DRM_IOCTL_NR(DRM_I830_INIT
)] = {i830_dma_init
, 1, 1}
1549 [DRM_IOCTL_NR(DRM_I830_VERTEX
)] = {i830_dma_vertex
, 1, 0}
1551 [DRM_IOCTL_NR(DRM_I830_CLEAR
)] = {i830_clear_bufs
, 1, 0}
1553 [DRM_IOCTL_NR(DRM_I830_FLUSH
)] = {i830_flush_ioctl
, 1, 0}
1555 [DRM_IOCTL_NR(DRM_I830_GETAGE
)] = {i830_getage
, 1, 0}
1557 [DRM_IOCTL_NR(DRM_I830_GETBUF
)] = {i830_getbuf
, 1, 0}
1559 [DRM_IOCTL_NR(DRM_I830_SWAP
)] = {i830_swap_bufs
, 1, 0}
1561 [DRM_IOCTL_NR(DRM_I830_COPY
)] = {i830_copybuf
, 1, 0}
1563 [DRM_IOCTL_NR(DRM_I830_DOCOPY
)] = {i830_docopy
, 1, 0}
1565 [DRM_IOCTL_NR(DRM_I830_FLIP
)] = {i830_flip_bufs
, 1, 0}
1567 [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT
)] = {i830_irq_emit
, 1, 0}
1569 [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT
)] = {i830_irq_wait
, 1, 0}
1571 [DRM_IOCTL_NR(DRM_I830_GETPARAM
)] = {i830_getparam
, 1, 0}
1573 [DRM_IOCTL_NR(DRM_I830_SETPARAM
)] = {i830_setparam
, 1, 0}
1576 int i830_max_ioctl
= DRM_ARRAY_SIZE(i830_ioctls
);
1579 * Determine if the device really is AGP or not.
1581 * All Intel graphics chipsets are treated as AGP, even if they are really
1584 * \param dev The device to be tested.
1587 * A value of 1 is always retured to indictate every i8xx is AGP.
1589 int i830_driver_device_is_agp(drm_device_t
* dev
)