2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 /* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
36 /* Each region is a minimum of 16k, and there are at most 255 of them.
38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
42 typedef struct _drm_i915_init
{
45 I915_CLEANUP_DMA
= 0x02,
46 I915_RESUME_DMA
= 0x03
48 unsigned int mmio_offset
;
49 int sarea_priv_offset
;
50 unsigned int ring_start
;
51 unsigned int ring_end
;
52 unsigned int ring_size
;
53 unsigned int front_offset
;
54 unsigned int back_offset
;
55 unsigned int depth_offset
;
59 unsigned int pitch_bits
;
60 unsigned int back_pitch
;
61 unsigned int depth_pitch
;
66 typedef struct _drm_i915_sarea
{
67 drm_tex_region_t texList
[I915_NR_TEX_REGIONS
+ 1];
68 int last_upload
; /* last time texture was uploaded */
69 int last_enqueue
; /* last time a buffer was enqueued */
70 int last_dispatch
; /* age of the most recently dispatched buffer */
71 int ctxOwner
; /* last context to upload state */
73 int pf_enabled
; /* is pageflipping allowed? */
75 int pf_current_page
; /* which buffer is being displayed? */
76 int perf_boxes
; /* performance boxes to be displayed */
77 int width
, height
; /* screen size in pixels */
79 drm_handle_t front_handle
;
83 drm_handle_t back_handle
;
87 drm_handle_t depth_handle
;
91 drm_handle_t tex_handle
;
94 int log_tex_granularity
;
96 int rotation
; /* 0, 90, 180 or 270 */
100 int virtualX
, virtualY
;
102 unsigned int front_tiled
;
103 unsigned int back_tiled
;
104 unsigned int depth_tiled
;
105 unsigned int rotated_tiled
;
106 unsigned int rotated2_tiled
;
109 /* Flags for perf_boxes
111 #define I915_BOX_RING_EMPTY 0x1
112 #define I915_BOX_FLIP 0x2
113 #define I915_BOX_WAIT 0x4
114 #define I915_BOX_TEXTURE_LOAD 0x8
115 #define I915_BOX_LOST_CONTEXT 0x10
117 /* I915 specific ioctls
118 * The device specific ioctl range is 0x40 to 0x79.
120 #define DRM_I915_INIT 0x00
121 #define DRM_I915_FLUSH 0x01
122 #define DRM_I915_FLIP 0x02
123 #define DRM_I915_BATCHBUFFER 0x03
124 #define DRM_I915_IRQ_EMIT 0x04
125 #define DRM_I915_IRQ_WAIT 0x05
126 #define DRM_I915_GETPARAM 0x06
127 #define DRM_I915_SETPARAM 0x07
128 #define DRM_I915_ALLOC 0x08
129 #define DRM_I915_FREE 0x09
130 #define DRM_I915_INIT_HEAP 0x0a
131 #define DRM_I915_CMDBUFFER 0x0b
132 #define DRM_I915_DESTROY_HEAP 0x0c
133 #define DRM_I915_SET_VBLANK_PIPE 0x0d
134 #define DRM_I915_GET_VBLANK_PIPE 0x0e
135 #define DRM_I915_VBLANK_SWAP 0x0f
137 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
138 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
139 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
140 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
141 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
142 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
143 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
144 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
145 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
146 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
147 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
148 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
149 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
150 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
151 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
153 /* Allow drivers to submit batchbuffers directly to hardware, relying
154 * on the security mechanisms provided by hardware.
156 typedef struct _drm_i915_batchbuffer
{
157 int start
; /* agp offset */
158 int used
; /* nr bytes in use */
159 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
160 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
161 int num_cliprects
; /* mulitpass with multiple cliprects? */
162 drm_clip_rect_t __user
*cliprects
; /* pointer to userspace cliprects */
163 } drm_i915_batchbuffer_t
;
165 /* As above, but pass a pointer to userspace buffer which can be
166 * validated by the kernel prior to sending to hardware.
168 typedef struct _drm_i915_cmdbuffer
{
169 char __user
*buf
; /* pointer to userspace command buffer */
170 int sz
; /* nr bytes in buf */
171 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
172 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
173 int num_cliprects
; /* mulitpass with multiple cliprects? */
174 drm_clip_rect_t __user
*cliprects
; /* pointer to userspace cliprects */
175 } drm_i915_cmdbuffer_t
;
177 /* Userspace can request & wait on irq's:
179 typedef struct drm_i915_irq_emit
{
181 } drm_i915_irq_emit_t
;
183 typedef struct drm_i915_irq_wait
{
185 } drm_i915_irq_wait_t
;
187 /* Ioctl to query kernel params:
189 #define I915_PARAM_IRQ_ACTIVE 1
190 #define I915_PARAM_ALLOW_BATCHBUFFER 2
191 #define I915_PARAM_LAST_DISPATCH 3
193 typedef struct drm_i915_getparam
{
196 } drm_i915_getparam_t
;
198 /* Ioctl to set kernel params:
200 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
201 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
202 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
204 typedef struct drm_i915_setparam
{
207 } drm_i915_setparam_t
;
209 /* A memory manager for regions of shared memory:
211 #define I915_MEM_REGION_AGP 1
213 typedef struct drm_i915_mem_alloc
{
217 int __user
*region_offset
; /* offset from start of fb or agp */
218 } drm_i915_mem_alloc_t
;
220 typedef struct drm_i915_mem_free
{
223 } drm_i915_mem_free_t
;
225 typedef struct drm_i915_mem_init_heap
{
229 } drm_i915_mem_init_heap_t
;
231 /* Allow memory manager to be torn down and re-initialized (eg on
234 typedef struct drm_i915_mem_destroy_heap
{
236 } drm_i915_mem_destroy_heap_t
;
238 /* Allow X server to configure which pipes to monitor for vblank signals
240 #define DRM_I915_VBLANK_PIPE_A 1
241 #define DRM_I915_VBLANK_PIPE_B 2
243 typedef struct drm_i915_vblank_pipe
{
245 } drm_i915_vblank_pipe_t
;
247 /* Schedule buffer swap at given vertical blank:
249 typedef struct drm_i915_vblank_swap
{
250 drm_drawable_t drawable
;
252 unsigned int sequence
;
253 } drm_i915_vblank_swap_t
;
255 #endif /* _I915_DRM_H_ */