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Merge branch 'xen-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen
[deliverable/linux.git] / drivers / char / drm / r128_state.c
1 /* r128_state.c -- State support for r128 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
3 */
4 /*
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "r128_drm.h"
34 #include "r128_drv.h"
35
36 /* ================================================================
37 * CCE hardware state programming functions
38 */
39
40 static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
41 struct drm_clip_rect * boxes, int count)
42 {
43 u32 aux_sc_cntl = 0x00000000;
44 RING_LOCALS;
45 DRM_DEBUG(" %s\n", __FUNCTION__);
46
47 BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
48
49 if (count >= 1) {
50 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
51 OUT_RING(boxes[0].x1);
52 OUT_RING(boxes[0].x2 - 1);
53 OUT_RING(boxes[0].y1);
54 OUT_RING(boxes[0].y2 - 1);
55
56 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
57 }
58 if (count >= 2) {
59 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
60 OUT_RING(boxes[1].x1);
61 OUT_RING(boxes[1].x2 - 1);
62 OUT_RING(boxes[1].y1);
63 OUT_RING(boxes[1].y2 - 1);
64
65 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
66 }
67 if (count >= 3) {
68 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
69 OUT_RING(boxes[2].x1);
70 OUT_RING(boxes[2].x2 - 1);
71 OUT_RING(boxes[2].y1);
72 OUT_RING(boxes[2].y2 - 1);
73
74 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
75 }
76
77 OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
78 OUT_RING(aux_sc_cntl);
79
80 ADVANCE_RING();
81 }
82
83 static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
84 {
85 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
86 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
87 RING_LOCALS;
88 DRM_DEBUG(" %s\n", __FUNCTION__);
89
90 BEGIN_RING(2);
91
92 OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
93 OUT_RING(ctx->scale_3d_cntl);
94
95 ADVANCE_RING();
96 }
97
98 static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
99 {
100 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
101 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
102 RING_LOCALS;
103 DRM_DEBUG(" %s\n", __FUNCTION__);
104
105 BEGIN_RING(13);
106
107 OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
108 OUT_RING(ctx->dst_pitch_offset_c);
109 OUT_RING(ctx->dp_gui_master_cntl_c);
110 OUT_RING(ctx->sc_top_left_c);
111 OUT_RING(ctx->sc_bottom_right_c);
112 OUT_RING(ctx->z_offset_c);
113 OUT_RING(ctx->z_pitch_c);
114 OUT_RING(ctx->z_sten_cntl_c);
115 OUT_RING(ctx->tex_cntl_c);
116 OUT_RING(ctx->misc_3d_state_cntl_reg);
117 OUT_RING(ctx->texture_clr_cmp_clr_c);
118 OUT_RING(ctx->texture_clr_cmp_msk_c);
119 OUT_RING(ctx->fog_color_c);
120
121 ADVANCE_RING();
122 }
123
124 static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
125 {
126 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
127 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
128 RING_LOCALS;
129 DRM_DEBUG(" %s\n", __FUNCTION__);
130
131 BEGIN_RING(3);
132
133 OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
134 OUT_RING(ctx->setup_cntl);
135 OUT_RING(ctx->pm4_vc_fpu_setup);
136
137 ADVANCE_RING();
138 }
139
140 static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
141 {
142 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
143 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
144 RING_LOCALS;
145 DRM_DEBUG(" %s\n", __FUNCTION__);
146
147 BEGIN_RING(5);
148
149 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
150 OUT_RING(ctx->dp_write_mask);
151
152 OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
153 OUT_RING(ctx->sten_ref_mask_c);
154 OUT_RING(ctx->plane_3d_mask_c);
155
156 ADVANCE_RING();
157 }
158
159 static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
160 {
161 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
162 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
163 RING_LOCALS;
164 DRM_DEBUG(" %s\n", __FUNCTION__);
165
166 BEGIN_RING(2);
167
168 OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
169 OUT_RING(ctx->window_xy_offset);
170
171 ADVANCE_RING();
172 }
173
174 static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
175 {
176 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
177 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
178 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
179 int i;
180 RING_LOCALS;
181 DRM_DEBUG(" %s\n", __FUNCTION__);
182
183 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
184
185 OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
186 2 + R128_MAX_TEXTURE_LEVELS));
187 OUT_RING(tex->tex_cntl);
188 OUT_RING(tex->tex_combine_cntl);
189 OUT_RING(ctx->tex_size_pitch_c);
190 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
191 OUT_RING(tex->tex_offset[i]);
192 }
193
194 OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
195 OUT_RING(ctx->constant_color_c);
196 OUT_RING(tex->tex_border_color);
197
198 ADVANCE_RING();
199 }
200
201 static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
202 {
203 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
204 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
205 int i;
206 RING_LOCALS;
207 DRM_DEBUG(" %s\n", __FUNCTION__);
208
209 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
210
211 OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
212 OUT_RING(tex->tex_cntl);
213 OUT_RING(tex->tex_combine_cntl);
214 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
215 OUT_RING(tex->tex_offset[i]);
216 }
217
218 OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
219 OUT_RING(tex->tex_border_color);
220
221 ADVANCE_RING();
222 }
223
224 static void r128_emit_state(drm_r128_private_t * dev_priv)
225 {
226 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
227 unsigned int dirty = sarea_priv->dirty;
228
229 DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
230
231 if (dirty & R128_UPLOAD_CORE) {
232 r128_emit_core(dev_priv);
233 sarea_priv->dirty &= ~R128_UPLOAD_CORE;
234 }
235
236 if (dirty & R128_UPLOAD_CONTEXT) {
237 r128_emit_context(dev_priv);
238 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
239 }
240
241 if (dirty & R128_UPLOAD_SETUP) {
242 r128_emit_setup(dev_priv);
243 sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
244 }
245
246 if (dirty & R128_UPLOAD_MASKS) {
247 r128_emit_masks(dev_priv);
248 sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
249 }
250
251 if (dirty & R128_UPLOAD_WINDOW) {
252 r128_emit_window(dev_priv);
253 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
254 }
255
256 if (dirty & R128_UPLOAD_TEX0) {
257 r128_emit_tex0(dev_priv);
258 sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
259 }
260
261 if (dirty & R128_UPLOAD_TEX1) {
262 r128_emit_tex1(dev_priv);
263 sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
264 }
265
266 /* Turn off the texture cache flushing */
267 sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
268
269 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
270 }
271
272 #if R128_PERFORMANCE_BOXES
273 /* ================================================================
274 * Performance monitoring functions
275 */
276
277 static void r128_clear_box(drm_r128_private_t * dev_priv,
278 int x, int y, int w, int h, int r, int g, int b)
279 {
280 u32 pitch, offset;
281 u32 fb_bpp, color;
282 RING_LOCALS;
283
284 switch (dev_priv->fb_bpp) {
285 case 16:
286 fb_bpp = R128_GMC_DST_16BPP;
287 color = (((r & 0xf8) << 8) |
288 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
289 break;
290 case 24:
291 fb_bpp = R128_GMC_DST_24BPP;
292 color = ((r << 16) | (g << 8) | b);
293 break;
294 case 32:
295 fb_bpp = R128_GMC_DST_32BPP;
296 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
297 break;
298 default:
299 return;
300 }
301
302 offset = dev_priv->back_offset;
303 pitch = dev_priv->back_pitch >> 3;
304
305 BEGIN_RING(6);
306
307 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
308 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
309 R128_GMC_BRUSH_SOLID_COLOR |
310 fb_bpp |
311 R128_GMC_SRC_DATATYPE_COLOR |
312 R128_ROP3_P |
313 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
314
315 OUT_RING((pitch << 21) | (offset >> 5));
316 OUT_RING(color);
317
318 OUT_RING((x << 16) | y);
319 OUT_RING((w << 16) | h);
320
321 ADVANCE_RING();
322 }
323
324 static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
325 {
326 if (atomic_read(&dev_priv->idle_count) == 0) {
327 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
328 } else {
329 atomic_set(&dev_priv->idle_count, 0);
330 }
331 }
332
333 #endif
334
335 /* ================================================================
336 * CCE command dispatch functions
337 */
338
339 static void r128_print_dirty(const char *msg, unsigned int flags)
340 {
341 DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
342 msg,
343 flags,
344 (flags & R128_UPLOAD_CORE) ? "core, " : "",
345 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
346 (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
347 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
348 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
349 (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
350 (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
351 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
352 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
353 }
354
355 static void r128_cce_dispatch_clear(struct drm_device * dev,
356 drm_r128_clear_t * clear)
357 {
358 drm_r128_private_t *dev_priv = dev->dev_private;
359 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
360 int nbox = sarea_priv->nbox;
361 struct drm_clip_rect *pbox = sarea_priv->boxes;
362 unsigned int flags = clear->flags;
363 int i;
364 RING_LOCALS;
365 DRM_DEBUG("%s\n", __FUNCTION__);
366
367 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
368 unsigned int tmp = flags;
369
370 flags &= ~(R128_FRONT | R128_BACK);
371 if (tmp & R128_FRONT)
372 flags |= R128_BACK;
373 if (tmp & R128_BACK)
374 flags |= R128_FRONT;
375 }
376
377 for (i = 0; i < nbox; i++) {
378 int x = pbox[i].x1;
379 int y = pbox[i].y1;
380 int w = pbox[i].x2 - x;
381 int h = pbox[i].y2 - y;
382
383 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
384 pbox[i].x1, pbox[i].y1, pbox[i].x2,
385 pbox[i].y2, flags);
386
387 if (flags & (R128_FRONT | R128_BACK)) {
388 BEGIN_RING(2);
389
390 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
391 OUT_RING(clear->color_mask);
392
393 ADVANCE_RING();
394 }
395
396 if (flags & R128_FRONT) {
397 BEGIN_RING(6);
398
399 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
400 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
401 R128_GMC_BRUSH_SOLID_COLOR |
402 (dev_priv->color_fmt << 8) |
403 R128_GMC_SRC_DATATYPE_COLOR |
404 R128_ROP3_P |
405 R128_GMC_CLR_CMP_CNTL_DIS |
406 R128_GMC_AUX_CLIP_DIS);
407
408 OUT_RING(dev_priv->front_pitch_offset_c);
409 OUT_RING(clear->clear_color);
410
411 OUT_RING((x << 16) | y);
412 OUT_RING((w << 16) | h);
413
414 ADVANCE_RING();
415 }
416
417 if (flags & R128_BACK) {
418 BEGIN_RING(6);
419
420 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
421 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
422 R128_GMC_BRUSH_SOLID_COLOR |
423 (dev_priv->color_fmt << 8) |
424 R128_GMC_SRC_DATATYPE_COLOR |
425 R128_ROP3_P |
426 R128_GMC_CLR_CMP_CNTL_DIS |
427 R128_GMC_AUX_CLIP_DIS);
428
429 OUT_RING(dev_priv->back_pitch_offset_c);
430 OUT_RING(clear->clear_color);
431
432 OUT_RING((x << 16) | y);
433 OUT_RING((w << 16) | h);
434
435 ADVANCE_RING();
436 }
437
438 if (flags & R128_DEPTH) {
439 BEGIN_RING(6);
440
441 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
442 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
443 R128_GMC_BRUSH_SOLID_COLOR |
444 (dev_priv->depth_fmt << 8) |
445 R128_GMC_SRC_DATATYPE_COLOR |
446 R128_ROP3_P |
447 R128_GMC_CLR_CMP_CNTL_DIS |
448 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
449
450 OUT_RING(dev_priv->depth_pitch_offset_c);
451 OUT_RING(clear->clear_depth);
452
453 OUT_RING((x << 16) | y);
454 OUT_RING((w << 16) | h);
455
456 ADVANCE_RING();
457 }
458 }
459 }
460
461 static void r128_cce_dispatch_swap(struct drm_device * dev)
462 {
463 drm_r128_private_t *dev_priv = dev->dev_private;
464 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
465 int nbox = sarea_priv->nbox;
466 struct drm_clip_rect *pbox = sarea_priv->boxes;
467 int i;
468 RING_LOCALS;
469 DRM_DEBUG("%s\n", __FUNCTION__);
470
471 #if R128_PERFORMANCE_BOXES
472 /* Do some trivial performance monitoring...
473 */
474 r128_cce_performance_boxes(dev_priv);
475 #endif
476
477 for (i = 0; i < nbox; i++) {
478 int x = pbox[i].x1;
479 int y = pbox[i].y1;
480 int w = pbox[i].x2 - x;
481 int h = pbox[i].y2 - y;
482
483 BEGIN_RING(7);
484
485 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
486 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
487 R128_GMC_DST_PITCH_OFFSET_CNTL |
488 R128_GMC_BRUSH_NONE |
489 (dev_priv->color_fmt << 8) |
490 R128_GMC_SRC_DATATYPE_COLOR |
491 R128_ROP3_S |
492 R128_DP_SRC_SOURCE_MEMORY |
493 R128_GMC_CLR_CMP_CNTL_DIS |
494 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
495
496 /* Make this work even if front & back are flipped:
497 */
498 if (dev_priv->current_page == 0) {
499 OUT_RING(dev_priv->back_pitch_offset_c);
500 OUT_RING(dev_priv->front_pitch_offset_c);
501 } else {
502 OUT_RING(dev_priv->front_pitch_offset_c);
503 OUT_RING(dev_priv->back_pitch_offset_c);
504 }
505
506 OUT_RING((x << 16) | y);
507 OUT_RING((x << 16) | y);
508 OUT_RING((w << 16) | h);
509
510 ADVANCE_RING();
511 }
512
513 /* Increment the frame counter. The client-side 3D driver must
514 * throttle the framerate by waiting for this value before
515 * performing the swapbuffer ioctl.
516 */
517 dev_priv->sarea_priv->last_frame++;
518
519 BEGIN_RING(2);
520
521 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
522 OUT_RING(dev_priv->sarea_priv->last_frame);
523
524 ADVANCE_RING();
525 }
526
527 static void r128_cce_dispatch_flip(struct drm_device * dev)
528 {
529 drm_r128_private_t *dev_priv = dev->dev_private;
530 RING_LOCALS;
531 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
532 __FUNCTION__,
533 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
534
535 #if R128_PERFORMANCE_BOXES
536 /* Do some trivial performance monitoring...
537 */
538 r128_cce_performance_boxes(dev_priv);
539 #endif
540
541 BEGIN_RING(4);
542
543 R128_WAIT_UNTIL_PAGE_FLIPPED();
544 OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
545
546 if (dev_priv->current_page == 0) {
547 OUT_RING(dev_priv->back_offset);
548 } else {
549 OUT_RING(dev_priv->front_offset);
550 }
551
552 ADVANCE_RING();
553
554 /* Increment the frame counter. The client-side 3D driver must
555 * throttle the framerate by waiting for this value before
556 * performing the swapbuffer ioctl.
557 */
558 dev_priv->sarea_priv->last_frame++;
559 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
560 1 - dev_priv->current_page;
561
562 BEGIN_RING(2);
563
564 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
565 OUT_RING(dev_priv->sarea_priv->last_frame);
566
567 ADVANCE_RING();
568 }
569
570 static void r128_cce_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
571 {
572 drm_r128_private_t *dev_priv = dev->dev_private;
573 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
574 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
575 int format = sarea_priv->vc_format;
576 int offset = buf->bus_address;
577 int size = buf->used;
578 int prim = buf_priv->prim;
579 int i = 0;
580 RING_LOCALS;
581 DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
582
583 if (0)
584 r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
585
586 if (buf->used) {
587 buf_priv->dispatched = 1;
588
589 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
590 r128_emit_state(dev_priv);
591 }
592
593 do {
594 /* Emit the next set of up to three cliprects */
595 if (i < sarea_priv->nbox) {
596 r128_emit_clip_rects(dev_priv,
597 &sarea_priv->boxes[i],
598 sarea_priv->nbox - i);
599 }
600
601 /* Emit the vertex buffer rendering commands */
602 BEGIN_RING(5);
603
604 OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
605 OUT_RING(offset);
606 OUT_RING(size);
607 OUT_RING(format);
608 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
609 (size << R128_CCE_VC_CNTL_NUM_SHIFT));
610
611 ADVANCE_RING();
612
613 i += 3;
614 } while (i < sarea_priv->nbox);
615 }
616
617 if (buf_priv->discard) {
618 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
619
620 /* Emit the vertex buffer age */
621 BEGIN_RING(2);
622
623 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
624 OUT_RING(buf_priv->age);
625
626 ADVANCE_RING();
627
628 buf->pending = 1;
629 buf->used = 0;
630 /* FIXME: Check dispatched field */
631 buf_priv->dispatched = 0;
632 }
633
634 dev_priv->sarea_priv->last_dispatch++;
635
636 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
637 sarea_priv->nbox = 0;
638 }
639
640 static void r128_cce_dispatch_indirect(struct drm_device * dev,
641 struct drm_buf * buf, int start, int end)
642 {
643 drm_r128_private_t *dev_priv = dev->dev_private;
644 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
645 RING_LOCALS;
646 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
647
648 if (start != end) {
649 int offset = buf->bus_address + start;
650 int dwords = (end - start + 3) / sizeof(u32);
651
652 /* Indirect buffer data must be an even number of
653 * dwords, so if we've been given an odd number we must
654 * pad the data with a Type-2 CCE packet.
655 */
656 if (dwords & 1) {
657 u32 *data = (u32 *)
658 ((char *)dev->agp_buffer_map->handle
659 + buf->offset + start);
660 data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
661 }
662
663 buf_priv->dispatched = 1;
664
665 /* Fire off the indirect buffer */
666 BEGIN_RING(3);
667
668 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
669 OUT_RING(offset);
670 OUT_RING(dwords);
671
672 ADVANCE_RING();
673 }
674
675 if (buf_priv->discard) {
676 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
677
678 /* Emit the indirect buffer age */
679 BEGIN_RING(2);
680
681 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
682 OUT_RING(buf_priv->age);
683
684 ADVANCE_RING();
685
686 buf->pending = 1;
687 buf->used = 0;
688 /* FIXME: Check dispatched field */
689 buf_priv->dispatched = 0;
690 }
691
692 dev_priv->sarea_priv->last_dispatch++;
693 }
694
695 static void r128_cce_dispatch_indices(struct drm_device * dev,
696 struct drm_buf * buf,
697 int start, int end, int count)
698 {
699 drm_r128_private_t *dev_priv = dev->dev_private;
700 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
701 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
702 int format = sarea_priv->vc_format;
703 int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset;
704 int prim = buf_priv->prim;
705 u32 *data;
706 int dwords;
707 int i = 0;
708 RING_LOCALS;
709 DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
710
711 if (0)
712 r128_print_dirty("dispatch_indices", sarea_priv->dirty);
713
714 if (start != end) {
715 buf_priv->dispatched = 1;
716
717 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
718 r128_emit_state(dev_priv);
719 }
720
721 dwords = (end - start + 3) / sizeof(u32);
722
723 data = (u32 *) ((char *)dev->agp_buffer_map->handle
724 + buf->offset + start);
725
726 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
727 dwords - 2));
728
729 data[1] = cpu_to_le32(offset);
730 data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
731 data[3] = cpu_to_le32(format);
732 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
733 (count << 16)));
734
735 if (count & 0x1) {
736 #ifdef __LITTLE_ENDIAN
737 data[dwords - 1] &= 0x0000ffff;
738 #else
739 data[dwords - 1] &= 0xffff0000;
740 #endif
741 }
742
743 do {
744 /* Emit the next set of up to three cliprects */
745 if (i < sarea_priv->nbox) {
746 r128_emit_clip_rects(dev_priv,
747 &sarea_priv->boxes[i],
748 sarea_priv->nbox - i);
749 }
750
751 r128_cce_dispatch_indirect(dev, buf, start, end);
752
753 i += 3;
754 } while (i < sarea_priv->nbox);
755 }
756
757 if (buf_priv->discard) {
758 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
759
760 /* Emit the vertex buffer age */
761 BEGIN_RING(2);
762
763 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
764 OUT_RING(buf_priv->age);
765
766 ADVANCE_RING();
767
768 buf->pending = 1;
769 /* FIXME: Check dispatched field */
770 buf_priv->dispatched = 0;
771 }
772
773 dev_priv->sarea_priv->last_dispatch++;
774
775 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
776 sarea_priv->nbox = 0;
777 }
778
779 static int r128_cce_dispatch_blit(struct drm_device * dev,
780 struct drm_file *file_priv,
781 drm_r128_blit_t * blit)
782 {
783 drm_r128_private_t *dev_priv = dev->dev_private;
784 struct drm_device_dma *dma = dev->dma;
785 struct drm_buf *buf;
786 drm_r128_buf_priv_t *buf_priv;
787 u32 *data;
788 int dword_shift, dwords;
789 RING_LOCALS;
790 DRM_DEBUG("\n");
791
792 /* The compiler won't optimize away a division by a variable,
793 * even if the only legal values are powers of two. Thus, we'll
794 * use a shift instead.
795 */
796 switch (blit->format) {
797 case R128_DATATYPE_ARGB8888:
798 dword_shift = 0;
799 break;
800 case R128_DATATYPE_ARGB1555:
801 case R128_DATATYPE_RGB565:
802 case R128_DATATYPE_ARGB4444:
803 case R128_DATATYPE_YVYU422:
804 case R128_DATATYPE_VYUY422:
805 dword_shift = 1;
806 break;
807 case R128_DATATYPE_CI8:
808 case R128_DATATYPE_RGB8:
809 dword_shift = 2;
810 break;
811 default:
812 DRM_ERROR("invalid blit format %d\n", blit->format);
813 return -EINVAL;
814 }
815
816 /* Flush the pixel cache, and mark the contents as Read Invalid.
817 * This ensures no pixel data gets mixed up with the texture
818 * data from the host data blit, otherwise part of the texture
819 * image may be corrupted.
820 */
821 BEGIN_RING(2);
822
823 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
824 OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
825
826 ADVANCE_RING();
827
828 /* Dispatch the indirect buffer.
829 */
830 buf = dma->buflist[blit->idx];
831 buf_priv = buf->dev_private;
832
833 if (buf->file_priv != file_priv) {
834 DRM_ERROR("process %d using buffer owned by %p\n",
835 DRM_CURRENTPID, buf->file_priv);
836 return -EINVAL;
837 }
838 if (buf->pending) {
839 DRM_ERROR("sending pending buffer %d\n", blit->idx);
840 return -EINVAL;
841 }
842
843 buf_priv->discard = 1;
844
845 dwords = (blit->width * blit->height) >> dword_shift;
846
847 data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
848
849 data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
850 data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
851 R128_GMC_BRUSH_NONE |
852 (blit->format << 8) |
853 R128_GMC_SRC_DATATYPE_COLOR |
854 R128_ROP3_S |
855 R128_DP_SRC_SOURCE_HOST_DATA |
856 R128_GMC_CLR_CMP_CNTL_DIS |
857 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
858
859 data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
860 data[3] = cpu_to_le32(0xffffffff);
861 data[4] = cpu_to_le32(0xffffffff);
862 data[5] = cpu_to_le32((blit->y << 16) | blit->x);
863 data[6] = cpu_to_le32((blit->height << 16) | blit->width);
864 data[7] = cpu_to_le32(dwords);
865
866 buf->used = (dwords + 8) * sizeof(u32);
867
868 r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
869
870 /* Flush the pixel cache after the blit completes. This ensures
871 * the texture data is written out to memory before rendering
872 * continues.
873 */
874 BEGIN_RING(2);
875
876 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
877 OUT_RING(R128_PC_FLUSH_GUI);
878
879 ADVANCE_RING();
880
881 return 0;
882 }
883
884 /* ================================================================
885 * Tiled depth buffer management
886 *
887 * FIXME: These should all set the destination write mask for when we
888 * have hardware stencil support.
889 */
890
891 static int r128_cce_dispatch_write_span(struct drm_device * dev,
892 drm_r128_depth_t * depth)
893 {
894 drm_r128_private_t *dev_priv = dev->dev_private;
895 int count, x, y;
896 u32 *buffer;
897 u8 *mask;
898 int i, buffer_size, mask_size;
899 RING_LOCALS;
900 DRM_DEBUG("\n");
901
902 count = depth->n;
903 if (count > 4096 || count <= 0)
904 return -EMSGSIZE;
905
906 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
907 return -EFAULT;
908 }
909 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
910 return -EFAULT;
911 }
912
913 buffer_size = depth->n * sizeof(u32);
914 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
915 if (buffer == NULL)
916 return -ENOMEM;
917 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
918 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
919 return -EFAULT;
920 }
921
922 mask_size = depth->n * sizeof(u8);
923 if (depth->mask) {
924 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
925 if (mask == NULL) {
926 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
927 return -ENOMEM;
928 }
929 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
930 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
931 drm_free(mask, mask_size, DRM_MEM_BUFS);
932 return -EFAULT;
933 }
934
935 for (i = 0; i < count; i++, x++) {
936 if (mask[i]) {
937 BEGIN_RING(6);
938
939 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
940 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
941 R128_GMC_BRUSH_SOLID_COLOR |
942 (dev_priv->depth_fmt << 8) |
943 R128_GMC_SRC_DATATYPE_COLOR |
944 R128_ROP3_P |
945 R128_GMC_CLR_CMP_CNTL_DIS |
946 R128_GMC_WR_MSK_DIS);
947
948 OUT_RING(dev_priv->depth_pitch_offset_c);
949 OUT_RING(buffer[i]);
950
951 OUT_RING((x << 16) | y);
952 OUT_RING((1 << 16) | 1);
953
954 ADVANCE_RING();
955 }
956 }
957
958 drm_free(mask, mask_size, DRM_MEM_BUFS);
959 } else {
960 for (i = 0; i < count; i++, x++) {
961 BEGIN_RING(6);
962
963 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
964 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
965 R128_GMC_BRUSH_SOLID_COLOR |
966 (dev_priv->depth_fmt << 8) |
967 R128_GMC_SRC_DATATYPE_COLOR |
968 R128_ROP3_P |
969 R128_GMC_CLR_CMP_CNTL_DIS |
970 R128_GMC_WR_MSK_DIS);
971
972 OUT_RING(dev_priv->depth_pitch_offset_c);
973 OUT_RING(buffer[i]);
974
975 OUT_RING((x << 16) | y);
976 OUT_RING((1 << 16) | 1);
977
978 ADVANCE_RING();
979 }
980 }
981
982 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
983
984 return 0;
985 }
986
987 static int r128_cce_dispatch_write_pixels(struct drm_device * dev,
988 drm_r128_depth_t * depth)
989 {
990 drm_r128_private_t *dev_priv = dev->dev_private;
991 int count, *x, *y;
992 u32 *buffer;
993 u8 *mask;
994 int i, xbuf_size, ybuf_size, buffer_size, mask_size;
995 RING_LOCALS;
996 DRM_DEBUG("\n");
997
998 count = depth->n;
999 if (count > 4096 || count <= 0)
1000 return -EMSGSIZE;
1001
1002 xbuf_size = count * sizeof(*x);
1003 ybuf_size = count * sizeof(*y);
1004 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1005 if (x == NULL) {
1006 return -ENOMEM;
1007 }
1008 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1009 if (y == NULL) {
1010 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1011 return -ENOMEM;
1012 }
1013 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1014 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1015 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1016 return -EFAULT;
1017 }
1018 if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
1019 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1020 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1021 return -EFAULT;
1022 }
1023
1024 buffer_size = depth->n * sizeof(u32);
1025 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
1026 if (buffer == NULL) {
1027 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1028 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1029 return -ENOMEM;
1030 }
1031 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
1032 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1033 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1034 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1035 return -EFAULT;
1036 }
1037
1038 if (depth->mask) {
1039 mask_size = depth->n * sizeof(u8);
1040 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
1041 if (mask == NULL) {
1042 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1043 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1044 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1045 return -ENOMEM;
1046 }
1047 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
1048 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1049 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1050 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1051 drm_free(mask, mask_size, DRM_MEM_BUFS);
1052 return -EFAULT;
1053 }
1054
1055 for (i = 0; i < count; i++) {
1056 if (mask[i]) {
1057 BEGIN_RING(6);
1058
1059 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1060 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1061 R128_GMC_BRUSH_SOLID_COLOR |
1062 (dev_priv->depth_fmt << 8) |
1063 R128_GMC_SRC_DATATYPE_COLOR |
1064 R128_ROP3_P |
1065 R128_GMC_CLR_CMP_CNTL_DIS |
1066 R128_GMC_WR_MSK_DIS);
1067
1068 OUT_RING(dev_priv->depth_pitch_offset_c);
1069 OUT_RING(buffer[i]);
1070
1071 OUT_RING((x[i] << 16) | y[i]);
1072 OUT_RING((1 << 16) | 1);
1073
1074 ADVANCE_RING();
1075 }
1076 }
1077
1078 drm_free(mask, mask_size, DRM_MEM_BUFS);
1079 } else {
1080 for (i = 0; i < count; i++) {
1081 BEGIN_RING(6);
1082
1083 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1084 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1085 R128_GMC_BRUSH_SOLID_COLOR |
1086 (dev_priv->depth_fmt << 8) |
1087 R128_GMC_SRC_DATATYPE_COLOR |
1088 R128_ROP3_P |
1089 R128_GMC_CLR_CMP_CNTL_DIS |
1090 R128_GMC_WR_MSK_DIS);
1091
1092 OUT_RING(dev_priv->depth_pitch_offset_c);
1093 OUT_RING(buffer[i]);
1094
1095 OUT_RING((x[i] << 16) | y[i]);
1096 OUT_RING((1 << 16) | 1);
1097
1098 ADVANCE_RING();
1099 }
1100 }
1101
1102 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1103 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1104 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1105
1106 return 0;
1107 }
1108
1109 static int r128_cce_dispatch_read_span(struct drm_device * dev,
1110 drm_r128_depth_t * depth)
1111 {
1112 drm_r128_private_t *dev_priv = dev->dev_private;
1113 int count, x, y;
1114 RING_LOCALS;
1115 DRM_DEBUG("\n");
1116
1117 count = depth->n;
1118 if (count > 4096 || count <= 0)
1119 return -EMSGSIZE;
1120
1121 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
1122 return -EFAULT;
1123 }
1124 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
1125 return -EFAULT;
1126 }
1127
1128 BEGIN_RING(7);
1129
1130 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1131 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1132 R128_GMC_DST_PITCH_OFFSET_CNTL |
1133 R128_GMC_BRUSH_NONE |
1134 (dev_priv->depth_fmt << 8) |
1135 R128_GMC_SRC_DATATYPE_COLOR |
1136 R128_ROP3_S |
1137 R128_DP_SRC_SOURCE_MEMORY |
1138 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1139
1140 OUT_RING(dev_priv->depth_pitch_offset_c);
1141 OUT_RING(dev_priv->span_pitch_offset_c);
1142
1143 OUT_RING((x << 16) | y);
1144 OUT_RING((0 << 16) | 0);
1145 OUT_RING((count << 16) | 1);
1146
1147 ADVANCE_RING();
1148
1149 return 0;
1150 }
1151
1152 static int r128_cce_dispatch_read_pixels(struct drm_device * dev,
1153 drm_r128_depth_t * depth)
1154 {
1155 drm_r128_private_t *dev_priv = dev->dev_private;
1156 int count, *x, *y;
1157 int i, xbuf_size, ybuf_size;
1158 RING_LOCALS;
1159 DRM_DEBUG("%s\n", __FUNCTION__);
1160
1161 count = depth->n;
1162 if (count > 4096 || count <= 0)
1163 return -EMSGSIZE;
1164
1165 if (count > dev_priv->depth_pitch) {
1166 count = dev_priv->depth_pitch;
1167 }
1168
1169 xbuf_size = count * sizeof(*x);
1170 ybuf_size = count * sizeof(*y);
1171 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1172 if (x == NULL) {
1173 return -ENOMEM;
1174 }
1175 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1176 if (y == NULL) {
1177 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1178 return -ENOMEM;
1179 }
1180 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1181 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1182 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1183 return -EFAULT;
1184 }
1185 if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
1186 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1187 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1188 return -EFAULT;
1189 }
1190
1191 for (i = 0; i < count; i++) {
1192 BEGIN_RING(7);
1193
1194 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1195 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1196 R128_GMC_DST_PITCH_OFFSET_CNTL |
1197 R128_GMC_BRUSH_NONE |
1198 (dev_priv->depth_fmt << 8) |
1199 R128_GMC_SRC_DATATYPE_COLOR |
1200 R128_ROP3_S |
1201 R128_DP_SRC_SOURCE_MEMORY |
1202 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1203
1204 OUT_RING(dev_priv->depth_pitch_offset_c);
1205 OUT_RING(dev_priv->span_pitch_offset_c);
1206
1207 OUT_RING((x[i] << 16) | y[i]);
1208 OUT_RING((i << 16) | 0);
1209 OUT_RING((1 << 16) | 1);
1210
1211 ADVANCE_RING();
1212 }
1213
1214 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1215 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1216
1217 return 0;
1218 }
1219
1220 /* ================================================================
1221 * Polygon stipple
1222 */
1223
1224 static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple)
1225 {
1226 drm_r128_private_t *dev_priv = dev->dev_private;
1227 int i;
1228 RING_LOCALS;
1229 DRM_DEBUG("%s\n", __FUNCTION__);
1230
1231 BEGIN_RING(33);
1232
1233 OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
1234 for (i = 0; i < 32; i++) {
1235 OUT_RING(stipple[i]);
1236 }
1237
1238 ADVANCE_RING();
1239 }
1240
1241 /* ================================================================
1242 * IOCTL functions
1243 */
1244
1245 static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
1246 {
1247 drm_r128_private_t *dev_priv = dev->dev_private;
1248 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1249 drm_r128_clear_t *clear = data;
1250 DRM_DEBUG("\n");
1251
1252 LOCK_TEST_WITH_RETURN(dev, file_priv);
1253
1254 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1255
1256 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1257 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1258
1259 r128_cce_dispatch_clear(dev, clear);
1260 COMMIT_RING();
1261
1262 /* Make sure we restore the 3D state next time.
1263 */
1264 dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
1265
1266 return 0;
1267 }
1268
1269 static int r128_do_init_pageflip(struct drm_device * dev)
1270 {
1271 drm_r128_private_t *dev_priv = dev->dev_private;
1272 DRM_DEBUG("\n");
1273
1274 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1275 dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
1276
1277 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1278 R128_WRITE(R128_CRTC_OFFSET_CNTL,
1279 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
1280
1281 dev_priv->page_flipping = 1;
1282 dev_priv->current_page = 0;
1283 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1284
1285 return 0;
1286 }
1287
1288 static int r128_do_cleanup_pageflip(struct drm_device * dev)
1289 {
1290 drm_r128_private_t *dev_priv = dev->dev_private;
1291 DRM_DEBUG("\n");
1292
1293 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1294 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
1295
1296 if (dev_priv->current_page != 0) {
1297 r128_cce_dispatch_flip(dev);
1298 COMMIT_RING();
1299 }
1300
1301 dev_priv->page_flipping = 0;
1302 return 0;
1303 }
1304
1305 /* Swapping and flipping are different operations, need different ioctls.
1306 * They can & should be intermixed to support multiple 3d windows.
1307 */
1308
1309 static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
1310 {
1311 drm_r128_private_t *dev_priv = dev->dev_private;
1312 DRM_DEBUG("%s\n", __FUNCTION__);
1313
1314 LOCK_TEST_WITH_RETURN(dev, file_priv);
1315
1316 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1317
1318 if (!dev_priv->page_flipping)
1319 r128_do_init_pageflip(dev);
1320
1321 r128_cce_dispatch_flip(dev);
1322
1323 COMMIT_RING();
1324 return 0;
1325 }
1326
1327 static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
1328 {
1329 drm_r128_private_t *dev_priv = dev->dev_private;
1330 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1331 DRM_DEBUG("%s\n", __FUNCTION__);
1332
1333 LOCK_TEST_WITH_RETURN(dev, file_priv);
1334
1335 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1336
1337 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1338 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1339
1340 r128_cce_dispatch_swap(dev);
1341 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
1342 R128_UPLOAD_MASKS);
1343
1344 COMMIT_RING();
1345 return 0;
1346 }
1347
1348 static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
1349 {
1350 drm_r128_private_t *dev_priv = dev->dev_private;
1351 struct drm_device_dma *dma = dev->dma;
1352 struct drm_buf *buf;
1353 drm_r128_buf_priv_t *buf_priv;
1354 drm_r128_vertex_t *vertex = data;
1355
1356 LOCK_TEST_WITH_RETURN(dev, file_priv);
1357
1358 if (!dev_priv) {
1359 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1360 return -EINVAL;
1361 }
1362
1363 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1364 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
1365
1366 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
1367 DRM_ERROR("buffer index %d (of %d max)\n",
1368 vertex->idx, dma->buf_count - 1);
1369 return -EINVAL;
1370 }
1371 if (vertex->prim < 0 ||
1372 vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1373 DRM_ERROR("buffer prim %d\n", vertex->prim);
1374 return -EINVAL;
1375 }
1376
1377 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1378 VB_AGE_TEST_WITH_RETURN(dev_priv);
1379
1380 buf = dma->buflist[vertex->idx];
1381 buf_priv = buf->dev_private;
1382
1383 if (buf->file_priv != file_priv) {
1384 DRM_ERROR("process %d using buffer owned by %p\n",
1385 DRM_CURRENTPID, buf->file_priv);
1386 return -EINVAL;
1387 }
1388 if (buf->pending) {
1389 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
1390 return -EINVAL;
1391 }
1392
1393 buf->used = vertex->count;
1394 buf_priv->prim = vertex->prim;
1395 buf_priv->discard = vertex->discard;
1396
1397 r128_cce_dispatch_vertex(dev, buf);
1398
1399 COMMIT_RING();
1400 return 0;
1401 }
1402
1403 static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
1404 {
1405 drm_r128_private_t *dev_priv = dev->dev_private;
1406 struct drm_device_dma *dma = dev->dma;
1407 struct drm_buf *buf;
1408 drm_r128_buf_priv_t *buf_priv;
1409 drm_r128_indices_t *elts = data;
1410 int count;
1411
1412 LOCK_TEST_WITH_RETURN(dev, file_priv);
1413
1414 if (!dev_priv) {
1415 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1416 return -EINVAL;
1417 }
1418
1419 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1420 elts->idx, elts->start, elts->end, elts->discard);
1421
1422 if (elts->idx < 0 || elts->idx >= dma->buf_count) {
1423 DRM_ERROR("buffer index %d (of %d max)\n",
1424 elts->idx, dma->buf_count - 1);
1425 return -EINVAL;
1426 }
1427 if (elts->prim < 0 ||
1428 elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1429 DRM_ERROR("buffer prim %d\n", elts->prim);
1430 return -EINVAL;
1431 }
1432
1433 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1434 VB_AGE_TEST_WITH_RETURN(dev_priv);
1435
1436 buf = dma->buflist[elts->idx];
1437 buf_priv = buf->dev_private;
1438
1439 if (buf->file_priv != file_priv) {
1440 DRM_ERROR("process %d using buffer owned by %p\n",
1441 DRM_CURRENTPID, buf->file_priv);
1442 return -EINVAL;
1443 }
1444 if (buf->pending) {
1445 DRM_ERROR("sending pending buffer %d\n", elts->idx);
1446 return -EINVAL;
1447 }
1448
1449 count = (elts->end - elts->start) / sizeof(u16);
1450 elts->start -= R128_INDEX_PRIM_OFFSET;
1451
1452 if (elts->start & 0x7) {
1453 DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
1454 return -EINVAL;
1455 }
1456 if (elts->start < buf->used) {
1457 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
1458 return -EINVAL;
1459 }
1460
1461 buf->used = elts->end;
1462 buf_priv->prim = elts->prim;
1463 buf_priv->discard = elts->discard;
1464
1465 r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count);
1466
1467 COMMIT_RING();
1468 return 0;
1469 }
1470
1471 static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1472 {
1473 struct drm_device_dma *dma = dev->dma;
1474 drm_r128_private_t *dev_priv = dev->dev_private;
1475 drm_r128_blit_t *blit = data;
1476 int ret;
1477
1478 LOCK_TEST_WITH_RETURN(dev, file_priv);
1479
1480 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx);
1481
1482 if (blit->idx < 0 || blit->idx >= dma->buf_count) {
1483 DRM_ERROR("buffer index %d (of %d max)\n",
1484 blit->idx, dma->buf_count - 1);
1485 return -EINVAL;
1486 }
1487
1488 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1489 VB_AGE_TEST_WITH_RETURN(dev_priv);
1490
1491 ret = r128_cce_dispatch_blit(dev, file_priv, blit);
1492
1493 COMMIT_RING();
1494 return ret;
1495 }
1496
1497 static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv)
1498 {
1499 drm_r128_private_t *dev_priv = dev->dev_private;
1500 drm_r128_depth_t *depth = data;
1501 int ret;
1502
1503 LOCK_TEST_WITH_RETURN(dev, file_priv);
1504
1505 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1506
1507 ret = -EINVAL;
1508 switch (depth->func) {
1509 case R128_WRITE_SPAN:
1510 ret = r128_cce_dispatch_write_span(dev, depth);
1511 break;
1512 case R128_WRITE_PIXELS:
1513 ret = r128_cce_dispatch_write_pixels(dev, depth);
1514 break;
1515 case R128_READ_SPAN:
1516 ret = r128_cce_dispatch_read_span(dev, depth);
1517 break;
1518 case R128_READ_PIXELS:
1519 ret = r128_cce_dispatch_read_pixels(dev, depth);
1520 break;
1521 }
1522
1523 COMMIT_RING();
1524 return ret;
1525 }
1526
1527 static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
1528 {
1529 drm_r128_private_t *dev_priv = dev->dev_private;
1530 drm_r128_stipple_t *stipple = data;
1531 u32 mask[32];
1532
1533 LOCK_TEST_WITH_RETURN(dev, file_priv);
1534
1535 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
1536 return -EFAULT;
1537
1538 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1539
1540 r128_cce_dispatch_stipple(dev, mask);
1541
1542 COMMIT_RING();
1543 return 0;
1544 }
1545
1546 static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
1547 {
1548 drm_r128_private_t *dev_priv = dev->dev_private;
1549 struct drm_device_dma *dma = dev->dma;
1550 struct drm_buf *buf;
1551 drm_r128_buf_priv_t *buf_priv;
1552 drm_r128_indirect_t *indirect = data;
1553 #if 0
1554 RING_LOCALS;
1555 #endif
1556
1557 LOCK_TEST_WITH_RETURN(dev, file_priv);
1558
1559 if (!dev_priv) {
1560 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1561 return -EINVAL;
1562 }
1563
1564 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
1565 indirect->idx, indirect->start, indirect->end,
1566 indirect->discard);
1567
1568 if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
1569 DRM_ERROR("buffer index %d (of %d max)\n",
1570 indirect->idx, dma->buf_count - 1);
1571 return -EINVAL;
1572 }
1573
1574 buf = dma->buflist[indirect->idx];
1575 buf_priv = buf->dev_private;
1576
1577 if (buf->file_priv != file_priv) {
1578 DRM_ERROR("process %d using buffer owned by %p\n",
1579 DRM_CURRENTPID, buf->file_priv);
1580 return -EINVAL;
1581 }
1582 if (buf->pending) {
1583 DRM_ERROR("sending pending buffer %d\n", indirect->idx);
1584 return -EINVAL;
1585 }
1586
1587 if (indirect->start < buf->used) {
1588 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
1589 indirect->start, buf->used);
1590 return -EINVAL;
1591 }
1592
1593 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1594 VB_AGE_TEST_WITH_RETURN(dev_priv);
1595
1596 buf->used = indirect->end;
1597 buf_priv->discard = indirect->discard;
1598
1599 #if 0
1600 /* Wait for the 3D stream to idle before the indirect buffer
1601 * containing 2D acceleration commands is processed.
1602 */
1603 BEGIN_RING(2);
1604 RADEON_WAIT_UNTIL_3D_IDLE();
1605 ADVANCE_RING();
1606 #endif
1607
1608 /* Dispatch the indirect buffer full of commands from the
1609 * X server. This is insecure and is thus only available to
1610 * privileged clients.
1611 */
1612 r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end);
1613
1614 COMMIT_RING();
1615 return 0;
1616 }
1617
1618 static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1619 {
1620 drm_r128_private_t *dev_priv = dev->dev_private;
1621 drm_r128_getparam_t *param = data;
1622 int value;
1623
1624 if (!dev_priv) {
1625 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1626 return -EINVAL;
1627 }
1628
1629 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1630
1631 switch (param->param) {
1632 case R128_PARAM_IRQ_NR:
1633 value = dev->irq;
1634 break;
1635 default:
1636 return -EINVAL;
1637 }
1638
1639 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1640 DRM_ERROR("copy_to_user\n");
1641 return -EFAULT;
1642 }
1643
1644 return 0;
1645 }
1646
1647 void r128_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1648 {
1649 if (dev->dev_private) {
1650 drm_r128_private_t *dev_priv = dev->dev_private;
1651 if (dev_priv->page_flipping) {
1652 r128_do_cleanup_pageflip(dev);
1653 }
1654 }
1655 }
1656
1657 void r128_driver_lastclose(struct drm_device * dev)
1658 {
1659 r128_do_cleanup_cce(dev);
1660 }
1661
1662 struct drm_ioctl_desc r128_ioctls[] = {
1663 DRM_IOCTL_DEF(DRM_R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1664 DRM_IOCTL_DEF(DRM_R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1665 DRM_IOCTL_DEF(DRM_R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1666 DRM_IOCTL_DEF(DRM_R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1667 DRM_IOCTL_DEF(DRM_R128_CCE_IDLE, r128_cce_idle, DRM_AUTH),
1668 DRM_IOCTL_DEF(DRM_R128_RESET, r128_engine_reset, DRM_AUTH),
1669 DRM_IOCTL_DEF(DRM_R128_FULLSCREEN, r128_fullscreen, DRM_AUTH),
1670 DRM_IOCTL_DEF(DRM_R128_SWAP, r128_cce_swap, DRM_AUTH),
1671 DRM_IOCTL_DEF(DRM_R128_FLIP, r128_cce_flip, DRM_AUTH),
1672 DRM_IOCTL_DEF(DRM_R128_CLEAR, r128_cce_clear, DRM_AUTH),
1673 DRM_IOCTL_DEF(DRM_R128_VERTEX, r128_cce_vertex, DRM_AUTH),
1674 DRM_IOCTL_DEF(DRM_R128_INDICES, r128_cce_indices, DRM_AUTH),
1675 DRM_IOCTL_DEF(DRM_R128_BLIT, r128_cce_blit, DRM_AUTH),
1676 DRM_IOCTL_DEF(DRM_R128_DEPTH, r128_cce_depth, DRM_AUTH),
1677 DRM_IOCTL_DEF(DRM_R128_STIPPLE, r128_cce_stipple, DRM_AUTH),
1678 DRM_IOCTL_DEF(DRM_R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1679 DRM_IOCTL_DEF(DRM_R128_GETPARAM, r128_getparam, DRM_AUTH),
1680 };
1681
1682 int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
Linux kernel - Deliverables
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