drivers/char/drm/via_drm.h

   1 /*
   2  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 #ifndef _VIA_DRM_H_
  25 #define _VIA_DRM_H_
  26
  27 /* WARNING: These defines must be the same as what the Xserver uses.
  28  * if you change them, you must change the defines in the Xserver.
  29  */
  30
  31 #ifndef _VIA_DEFINES_
  32 #define _VIA_DEFINES_
  33
  34 #ifndef __KERNEL__
  35 #include "via_drmclient.h"
  36 #endif
  37
  38 #define VIA_NR_SAREA_CLIPRECTS          8
  39 #define VIA_NR_XVMC_PORTS               10
  40 #define VIA_NR_XVMC_LOCKS               5
  41 #define VIA_MAX_CACHELINE_SIZE          64
  42 #define XVMCLOCKPTR(saPriv,lockNo)                                      \
  43         ((volatile drm_hw_lock_t *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
  44                                       (VIA_MAX_CACHELINE_SIZE - 1)) &   \
  45                                      ~(VIA_MAX_CACHELINE_SIZE - 1)) +   \
  46                                     VIA_MAX_CACHELINE_SIZE*(lockNo)))
  47
  48 /* Each region is a minimum of 64k, and there are at most 64 of them.
  49  */
  50 #define VIA_NR_TEX_REGIONS 64
  51 #define VIA_LOG_MIN_TEX_REGION_SIZE 16
  52 #endif
  53
  54 #define VIA_UPLOAD_TEX0IMAGE  0x1       /* handled clientside */
  55 #define VIA_UPLOAD_TEX1IMAGE  0x2       /* handled clientside */
  56 #define VIA_UPLOAD_CTX        0x4
  57 #define VIA_UPLOAD_BUFFERS    0x8
  58 #define VIA_UPLOAD_TEX0       0x10
  59 #define VIA_UPLOAD_TEX1       0x20
  60 #define VIA_UPLOAD_CLIPRECTS  0x40
  61 #define VIA_UPLOAD_ALL        0xff
  62
  63 /* VIA specific ioctls */
  64 #define DRM_VIA_ALLOCMEM        0x00
  65 #define DRM_VIA_FREEMEM         0x01
  66 #define DRM_VIA_AGP_INIT        0x02
  67 #define DRM_VIA_FB_INIT         0x03
  68 #define DRM_VIA_MAP_INIT        0x04
  69 #define DRM_VIA_DEC_FUTEX       0x05
  70 #define NOT_USED
  71 #define DRM_VIA_DMA_INIT        0x07
  72 #define DRM_VIA_CMDBUFFER       0x08
  73 #define DRM_VIA_FLUSH           0x09
  74 #define DRM_VIA_PCICMD          0x0a
  75 #define DRM_VIA_CMDBUF_SIZE     0x0b
  76 #define NOT_USED
  77 #define DRM_VIA_WAIT_IRQ        0x0d
  78
  79 #define DRM_IOCTL_VIA_ALLOCMEM    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
  80 #define DRM_IOCTL_VIA_FREEMEM     DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
  81 #define DRM_IOCTL_VIA_AGP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
  82 #define DRM_IOCTL_VIA_FB_INIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
  83 #define DRM_IOCTL_VIA_MAP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
  84 #define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
  85 #define DRM_IOCTL_VIA_DMA_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
  86 #define DRM_IOCTL_VIA_CMDBUFFER   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
  87 #define DRM_IOCTL_VIA_FLUSH       DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
  88 #define DRM_IOCTL_VIA_PCICMD      DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
  89 #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
  90                                             drm_via_cmdbuf_size_t)
  91 #define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
  92
  93 /* Indices into buf.Setup where various bits of state are mirrored per
  94  * context and per buffer.  These can be fired at the card as a unit,
  95  * or in a piecewise fashion as required.
  96  */
  97
  98 #define VIA_TEX_SETUP_SIZE 8
  99
 100 /* Flags for clear ioctl
 101  */
 102 #define VIA_FRONT   0x1
 103 #define VIA_BACK    0x2
 104 #define VIA_DEPTH   0x4
 105 #define VIA_STENCIL 0x8
 106 #define VIDEO 0
 107 #define AGP 1
 108 typedef struct {
 109         uint32_t offset;
 110         uint32_t size;
 111 } drm_via_agp_t;
 112
 113 typedef struct {
 114         uint32_t offset;
 115         uint32_t size;
 116 } drm_via_fb_t;
 117
 118 typedef struct {
 119         uint32_t context;
 120         uint32_t type;
 121         uint32_t size;
 122         unsigned long index;
 123         unsigned long offset;
 124 } drm_via_mem_t;
 125
 126 typedef struct _drm_via_init {
 127         enum {
 128                 VIA_INIT_MAP = 0x01,
 129                 VIA_CLEANUP_MAP = 0x02
 130         } func;
 131
 132         unsigned long sarea_priv_offset;
 133         unsigned long fb_offset;
 134         unsigned long mmio_offset;
 135         unsigned long agpAddr;
 136 } drm_via_init_t;
 137
 138 typedef struct _drm_via_futex {
 139         enum {
 140                 VIA_FUTEX_WAIT = 0x00,
 141                 VIA_FUTEX_WAKE = 0X01
 142         } func;
 143         uint32_t ms;
 144         uint32_t lock;
 145         uint32_t val;
 146 } drm_via_futex_t;
 147
 148 typedef struct _drm_via_dma_init {
 149         enum {
 150                 VIA_INIT_DMA = 0x01,
 151                 VIA_CLEANUP_DMA = 0x02,
 152                 VIA_DMA_INITIALIZED = 0x03
 153         } func;
 154
 155         unsigned long offset;
 156         unsigned long size;
 157         unsigned long reg_pause_addr;
 158 } drm_via_dma_init_t;
 159
 160 typedef struct _drm_via_cmdbuffer {
 161         char __user *buf;
 162         unsigned long size;
 163 } drm_via_cmdbuffer_t;
 164
 165 /* Warning: If you change the SAREA structure you must change the Xserver
 166  * structure as well */
 167
 168 typedef struct _drm_via_tex_region {
 169         unsigned char next, prev;       /* indices to form a circular LRU  */
 170         unsigned char inUse;    /* owned by a client, or free? */
 171         int age;                /* tracked by clients to update local LRU's */
 172 } drm_via_tex_region_t;
 173
 174 typedef struct _drm_via_sarea {
 175         unsigned int dirty;
 176         unsigned int nbox;
 177         drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
 178         drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
 179         int texAge;             /* last time texture was uploaded */
 180         int ctxOwner;           /* last context to upload state */
 181         int vertexPrim;
 182
 183         /*
 184          * Below is for XvMC.
 185          * We want the lock integers alone on, and aligned to, a cache line.
 186          * Therefore this somewhat strange construct.
 187          */
 188
 189         char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
 190
 191         unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
 192         unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
 193         unsigned int XvMCCtxNoGrabbed;  /* Last context to hold decoder */
 194
 195 } drm_via_sarea_t;
 196
 197 typedef struct _drm_via_cmdbuf_size {
 198         enum {
 199                 VIA_CMDBUF_SPACE = 0x01,
 200                 VIA_CMDBUF_LAG = 0x02
 201         } func;
 202         int wait;
 203         uint32_t size;
 204 } drm_via_cmdbuf_size_t;
 205
 206 typedef enum {
 207         VIA_IRQ_ABSOLUTE = 0x0,
 208         VIA_IRQ_RELATIVE = 0x1,
 209         VIA_IRQ_SIGNAL = 0x10000000,
 210         VIA_IRQ_FORCE_SEQUENCE = 0x20000000
 211 } via_irq_seq_type_t;
 212
 213 #define VIA_IRQ_FLAGS_MASK 0xF0000000
 214
 215 struct drm_via_wait_irq_request {
 216         unsigned irq;
 217         via_irq_seq_type_t type;
 218         uint32_t sequence;
 219         uint32_t signal;
 220 };
 221
 222 typedef union drm_via_irqwait {
 223         struct drm_via_wait_irq_request request;
 224         struct drm_wait_vblank_reply reply;
 225 } drm_via_irqwait_t;
 226
 227 #ifdef __KERNEL__
 228
 229 int via_fb_init(DRM_IOCTL_ARGS);
 230 int via_mem_alloc(DRM_IOCTL_ARGS);
 231 int via_mem_free(DRM_IOCTL_ARGS);
 232 int via_agp_init(DRM_IOCTL_ARGS);
 233 int via_map_init(DRM_IOCTL_ARGS);
 234 int via_decoder_futex(DRM_IOCTL_ARGS);
 235 int via_dma_init(DRM_IOCTL_ARGS);
 236 int via_cmdbuffer(DRM_IOCTL_ARGS);
 237 int via_flush_ioctl(DRM_IOCTL_ARGS);
 238 int via_pci_cmdbuffer(DRM_IOCTL_ARGS);
 239 int via_cmdbuf_size(DRM_IOCTL_ARGS);
 240 int via_wait_irq(DRM_IOCTL_ARGS);
 241
 242 #endif
 243 #endif                          /* _VIA_DRM_H_ */