projects / deliverable / linux.git / blob
? search:


0606586e76abf04f56e47589d6e08afdc78582ab
[deliverable/linux.git] / drivers / char / pcmcia / synclink_cs.c
1 /*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 #if defined(__i386__)
31 # define BREAKPOINT() asm(" int $3");
32 #else
33 # define BREAKPOINT() { }
34 #endif
35
36 #define MAX_DEVICE_COUNT 4
37
38 #include <linux/module.h>
39 #include <linux/errno.h>
40 #include <linux/signal.h>
41 #include <linux/sched.h>
42 #include <linux/timer.h>
43 #include <linux/time.h>
44 #include <linux/interrupt.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial.h>
48 #include <linux/major.h>
49 #include <linux/string.h>
50 #include <linux/fcntl.h>
51 #include <linux/ptrace.h>
52 #include <linux/ioport.h>
53 #include <linux/mm.h>
54 #include <linux/seq_file.h>
55 #include <linux/slab.h>
56 #include <linux/netdevice.h>
57 #include <linux/vmalloc.h>
58 #include <linux/init.h>
59 #include <linux/delay.h>
60 #include <linux/ioctl.h>
61 #include <linux/synclink.h>
62
63 #include <asm/io.h>
64 #include <asm/irq.h>
65 #include <asm/dma.h>
66 #include <linux/bitops.h>
67 #include <asm/types.h>
68 #include <linux/termios.h>
69 #include <linux/workqueue.h>
70 #include <linux/hdlc.h>
71
72 #include <pcmcia/cistpl.h>
73 #include <pcmcia/cisreg.h>
74 #include <pcmcia/ds.h>
75
76 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
77 #define SYNCLINK_GENERIC_HDLC 1
78 #else
79 #define SYNCLINK_GENERIC_HDLC 0
80 #endif
81
82 #define GET_USER(error,value,addr) error = get_user(value,addr)
83 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
84 #define PUT_USER(error,value,addr) error = put_user(value,addr)
85 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
86
87 #include <asm/uaccess.h>
88
89 static MGSL_PARAMS default_params = {
90 MGSL_MODE_HDLC, /* unsigned long mode */
91 0, /* unsigned char loopback; */
92 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
93 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
94 0, /* unsigned long clock_speed; */
95 0xff, /* unsigned char addr_filter; */
96 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
97 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
98 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
99 9600, /* unsigned long data_rate; */
100 8, /* unsigned char data_bits; */
101 1, /* unsigned char stop_bits; */
102 ASYNC_PARITY_NONE /* unsigned char parity; */
103 };
104
105 typedef struct
106 {
107 int count;
108 unsigned char status;
109 char data[1];
110 } RXBUF;
111
112 /* The queue of BH actions to be performed */
113
114 #define BH_RECEIVE 1
115 #define BH_TRANSMIT 2
116 #define BH_STATUS 4
117
118 #define IO_PIN_SHUTDOWN_LIMIT 100
119
120 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
121
122 struct _input_signal_events {
123 int ri_up;
124 int ri_down;
125 int dsr_up;
126 int dsr_down;
127 int dcd_up;
128 int dcd_down;
129 int cts_up;
130 int cts_down;
131 };
132
133
134 /*
135 * Device instance data structure
136 */
137
138 typedef struct _mgslpc_info {
139 struct tty_port port;
140 void *if_ptr; /* General purpose pointer (used by SPPP) */
141 int magic;
142 int line;
143
144 struct mgsl_icount icount;
145
146 int timeout;
147 int x_char; /* xon/xoff character */
148 unsigned char read_status_mask;
149 unsigned char ignore_status_mask;
150
151 unsigned char *tx_buf;
152 int tx_put;
153 int tx_get;
154 int tx_count;
155
156 /* circular list of fixed length rx buffers */
157
158 unsigned char *rx_buf; /* memory allocated for all rx buffers */
159 int rx_buf_total_size; /* size of memory allocated for rx buffers */
160 int rx_put; /* index of next empty rx buffer */
161 int rx_get; /* index of next full rx buffer */
162 int rx_buf_size; /* size in bytes of single rx buffer */
163 int rx_buf_count; /* total number of rx buffers */
164 int rx_frame_count; /* number of full rx buffers */
165
166 wait_queue_head_t status_event_wait_q;
167 wait_queue_head_t event_wait_q;
168 struct timer_list tx_timer; /* HDLC transmit timeout timer */
169 struct _mgslpc_info *next_device; /* device list link */
170
171 unsigned short imra_value;
172 unsigned short imrb_value;
173 unsigned char pim_value;
174
175 spinlock_t lock;
176 struct work_struct task; /* task structure for scheduling bh */
177
178 u32 max_frame_size;
179
180 u32 pending_bh;
181
182 bool bh_running;
183 bool bh_requested;
184
185 int dcd_chkcount; /* check counts to prevent */
186 int cts_chkcount; /* too many IRQs if a signal */
187 int dsr_chkcount; /* is floating */
188 int ri_chkcount;
189
190 bool rx_enabled;
191 bool rx_overflow;
192
193 bool tx_enabled;
194 bool tx_active;
195 bool tx_aborting;
196 u32 idle_mode;
197
198 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
199
200 char device_name[25]; /* device instance name */
201
202 unsigned int io_base; /* base I/O address of adapter */
203 unsigned int irq_level;
204
205 MGSL_PARAMS params; /* communications parameters */
206
207 unsigned char serial_signals; /* current serial signal states */
208
209 bool irq_occurred; /* for diagnostics use */
210 char testing_irq;
211 unsigned int init_error; /* startup error (DIAGS) */
212
213 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
214 bool drop_rts_on_tx_done;
215
216 struct _input_signal_events input_signal_events;
217
218 /* PCMCIA support */
219 struct pcmcia_device *p_dev;
220 int stop;
221
222 /* SPPP/Cisco HDLC device parts */
223 int netcount;
224 spinlock_t netlock;
225
226 #if SYNCLINK_GENERIC_HDLC
227 struct net_device *netdev;
228 #endif
229
230 } MGSLPC_INFO;
231
232 #define MGSLPC_MAGIC 0x5402
233
234 /*
235 * The size of the serial xmit buffer is 1 page, or 4096 bytes
236 */
237 #define TXBUFSIZE 4096
238
239
240 #define CHA 0x00 /* channel A offset */
241 #define CHB 0x40 /* channel B offset */
242
243 /*
244 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
245 */
246 #undef PVR
247
248 #define RXFIFO 0
249 #define TXFIFO 0
250 #define STAR 0x20
251 #define CMDR 0x20
252 #define RSTA 0x21
253 #define PRE 0x21
254 #define MODE 0x22
255 #define TIMR 0x23
256 #define XAD1 0x24
257 #define XAD2 0x25
258 #define RAH1 0x26
259 #define RAH2 0x27
260 #define DAFO 0x27
261 #define RAL1 0x28
262 #define RFC 0x28
263 #define RHCR 0x29
264 #define RAL2 0x29
265 #define RBCL 0x2a
266 #define XBCL 0x2a
267 #define RBCH 0x2b
268 #define XBCH 0x2b
269 #define CCR0 0x2c
270 #define CCR1 0x2d
271 #define CCR2 0x2e
272 #define CCR3 0x2f
273 #define VSTR 0x34
274 #define BGR 0x34
275 #define RLCR 0x35
276 #define AML 0x36
277 #define AMH 0x37
278 #define GIS 0x38
279 #define IVA 0x38
280 #define IPC 0x39
281 #define ISR 0x3a
282 #define IMR 0x3a
283 #define PVR 0x3c
284 #define PIS 0x3d
285 #define PIM 0x3d
286 #define PCR 0x3e
287 #define CCR4 0x3f
288
289 // IMR/ISR
290
291 #define IRQ_BREAK_ON BIT15 // rx break detected
292 #define IRQ_DATAOVERRUN BIT14 // receive data overflow
293 #define IRQ_ALLSENT BIT13 // all sent
294 #define IRQ_UNDERRUN BIT12 // transmit data underrun
295 #define IRQ_TIMER BIT11 // timer interrupt
296 #define IRQ_CTS BIT10 // CTS status change
297 #define IRQ_TXREPEAT BIT9 // tx message repeat
298 #define IRQ_TXFIFO BIT8 // transmit pool ready
299 #define IRQ_RXEOM BIT7 // receive message end
300 #define IRQ_EXITHUNT BIT6 // receive frame start
301 #define IRQ_RXTIME BIT6 // rx char timeout
302 #define IRQ_DCD BIT2 // carrier detect status change
303 #define IRQ_OVERRUN BIT1 // receive frame overflow
304 #define IRQ_RXFIFO BIT0 // receive pool full
305
306 // STAR
307
308 #define XFW BIT6 // transmit FIFO write enable
309 #define CEC BIT2 // command executing
310 #define CTS BIT1 // CTS state
311
312 #define PVR_DTR BIT0
313 #define PVR_DSR BIT1
314 #define PVR_RI BIT2
315 #define PVR_AUTOCTS BIT3
316 #define PVR_RS232 0x20 /* 0010b */
317 #define PVR_V35 0xe0 /* 1110b */
318 #define PVR_RS422 0x40 /* 0100b */
319
320 /* Register access functions */
321
322 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
323 #define read_reg(info, reg) inb((info)->io_base + (reg))
324
325 #define read_reg16(info, reg) inw((info)->io_base + (reg))
326 #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
327
328 #define set_reg_bits(info, reg, mask) \
329 write_reg(info, (reg), \
330 (unsigned char) (read_reg(info, (reg)) | (mask)))
331 #define clear_reg_bits(info, reg, mask) \
332 write_reg(info, (reg), \
333 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
334 /*
335 * interrupt enable/disable routines
336 */
337 static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
338 {
339 if (channel == CHA) {
340 info->imra_value |= mask;
341 write_reg16(info, CHA + IMR, info->imra_value);
342 } else {
343 info->imrb_value |= mask;
344 write_reg16(info, CHB + IMR, info->imrb_value);
345 }
346 }
347 static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
348 {
349 if (channel == CHA) {
350 info->imra_value &= ~mask;
351 write_reg16(info, CHA + IMR, info->imra_value);
352 } else {
353 info->imrb_value &= ~mask;
354 write_reg16(info, CHB + IMR, info->imrb_value);
355 }
356 }
357
358 #define port_irq_disable(info, mask) \
359 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
360
361 #define port_irq_enable(info, mask) \
362 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
363
364 static void rx_start(MGSLPC_INFO *info);
365 static void rx_stop(MGSLPC_INFO *info);
366
367 static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
368 static void tx_stop(MGSLPC_INFO *info);
369 static void tx_set_idle(MGSLPC_INFO *info);
370
371 static void get_signals(MGSLPC_INFO *info);
372 static void set_signals(MGSLPC_INFO *info);
373
374 static void reset_device(MGSLPC_INFO *info);
375
376 static void hdlc_mode(MGSLPC_INFO *info);
377 static void async_mode(MGSLPC_INFO *info);
378
379 static void tx_timeout(unsigned long context);
380
381 static int carrier_raised(struct tty_port *port);
382 static void dtr_rts(struct tty_port *port, int onoff);
383
384 #if SYNCLINK_GENERIC_HDLC
385 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
386 static void hdlcdev_tx_done(MGSLPC_INFO *info);
387 static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
388 static int hdlcdev_init(MGSLPC_INFO *info);
389 static void hdlcdev_exit(MGSLPC_INFO *info);
390 #endif
391
392 static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
393
394 static bool register_test(MGSLPC_INFO *info);
395 static bool irq_test(MGSLPC_INFO *info);
396 static int adapter_test(MGSLPC_INFO *info);
397
398 static int claim_resources(MGSLPC_INFO *info);
399 static void release_resources(MGSLPC_INFO *info);
400 static void mgslpc_add_device(MGSLPC_INFO *info);
401 static void mgslpc_remove_device(MGSLPC_INFO *info);
402
403 static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
404 static void rx_reset_buffers(MGSLPC_INFO *info);
405 static int rx_alloc_buffers(MGSLPC_INFO *info);
406 static void rx_free_buffers(MGSLPC_INFO *info);
407
408 static irqreturn_t mgslpc_isr(int irq, void *dev_id);
409
410 /*
411 * Bottom half interrupt handlers
412 */
413 static void bh_handler(struct work_struct *work);
414 static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
415 static void bh_status(MGSLPC_INFO *info);
416
417 /*
418 * ioctl handlers
419 */
420 static int tiocmget(struct tty_struct *tty);
421 static int tiocmset(struct tty_struct *tty,
422 unsigned int set, unsigned int clear);
423 static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
424 static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
425 static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
426 static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
427 static int set_txidle(MGSLPC_INFO *info, int idle_mode);
428 static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
429 static int tx_abort(MGSLPC_INFO *info);
430 static int set_rxenable(MGSLPC_INFO *info, int enable);
431 static int wait_events(MGSLPC_INFO *info, int __user *mask);
432
433 static MGSLPC_INFO *mgslpc_device_list = NULL;
434 static int mgslpc_device_count = 0;
435
436 /*
437 * Set this param to non-zero to load eax with the
438 * .text section address and breakpoint on module load.
439 * This is useful for use with gdb and add-symbol-file command.
440 */
441 static bool break_on_load=0;
442
443 /*
444 * Driver major number, defaults to zero to get auto
445 * assigned major number. May be forced as module parameter.
446 */
447 static int ttymajor=0;
448
449 static int debug_level = 0;
450 static int maxframe[MAX_DEVICE_COUNT] = {0,};
451
452 module_param(break_on_load, bool, 0);
453 module_param(ttymajor, int, 0);
454 module_param(debug_level, int, 0);
455 module_param_array(maxframe, int, NULL, 0);
456
457 MODULE_LICENSE("GPL");
458
459 static char *driver_name = "SyncLink PC Card driver";
460 static char *driver_version = "$Revision: 4.34 $";
461
462 static struct tty_driver *serial_driver;
463
464 /* number of characters left in xmit buffer before we ask for more */
465 #define WAKEUP_CHARS 256
466
467 static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
468 static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
469
470 /* PCMCIA prototypes */
471
472 static int mgslpc_config(struct pcmcia_device *link);
473 static void mgslpc_release(u_long arg);
474 static void mgslpc_detach(struct pcmcia_device *p_dev);
475
476 /*
477 * 1st function defined in .text section. Calling this function in
478 * init_module() followed by a breakpoint allows a remote debugger
479 * (gdb) to get the .text address for the add-symbol-file command.
480 * This allows remote debugging of dynamically loadable modules.
481 */
482 static void* mgslpc_get_text_ptr(void)
483 {
484 return mgslpc_get_text_ptr;
485 }
486
487 /**
488 * line discipline callback wrappers
489 *
490 * The wrappers maintain line discipline references
491 * while calling into the line discipline.
492 *
493 * ldisc_receive_buf - pass receive data to line discipline
494 */
495
496 static void ldisc_receive_buf(struct tty_struct *tty,
497 const __u8 *data, char *flags, int count)
498 {
499 struct tty_ldisc *ld;
500 if (!tty)
501 return;
502 ld = tty_ldisc_ref(tty);
503 if (ld) {
504 if (ld->ops->receive_buf)
505 ld->ops->receive_buf(tty, data, flags, count);
506 tty_ldisc_deref(ld);
507 }
508 }
509
510 static const struct tty_port_operations mgslpc_port_ops = {
511 .carrier_raised = carrier_raised,
512 .dtr_rts = dtr_rts
513 };
514
515 static int mgslpc_probe(struct pcmcia_device *link)
516 {
517 MGSLPC_INFO *info;
518 int ret;
519
520 if (debug_level >= DEBUG_LEVEL_INFO)
521 printk("mgslpc_attach\n");
522
523 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
524 if (!info) {
525 printk("Error can't allocate device instance data\n");
526 return -ENOMEM;
527 }
528
529 info->magic = MGSLPC_MAGIC;
530 tty_port_init(&info->port);
531 info->port.ops = &mgslpc_port_ops;
532 INIT_WORK(&info->task, bh_handler);
533 info->max_frame_size = 4096;
534 info->port.close_delay = 5*HZ/10;
535 info->port.closing_wait = 30*HZ;
536 init_waitqueue_head(&info->status_event_wait_q);
537 init_waitqueue_head(&info->event_wait_q);
538 spin_lock_init(&info->lock);
539 spin_lock_init(&info->netlock);
540 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
541 info->idle_mode = HDLC_TXIDLE_FLAGS;
542 info->imra_value = 0xffff;
543 info->imrb_value = 0xffff;
544 info->pim_value = 0xff;
545
546 info->p_dev = link;
547 link->priv = info;
548
549 /* Initialize the struct pcmcia_device structure */
550
551 ret = mgslpc_config(link);
552 if (ret)
553 return ret;
554
555 mgslpc_add_device(info);
556
557 return 0;
558 }
559
560 /* Card has been inserted.
561 */
562
563 static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
564 {
565 return pcmcia_request_io(p_dev);
566 }
567
568 static int mgslpc_config(struct pcmcia_device *link)
569 {
570 MGSLPC_INFO *info = link->priv;
571 int ret;
572
573 if (debug_level >= DEBUG_LEVEL_INFO)
574 printk("mgslpc_config(0x%p)\n", link);
575
576 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
577
578 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
579 if (ret != 0)
580 goto failed;
581
582 link->config_index = 8;
583 link->config_regs = PRESENT_OPTION;
584
585 ret = pcmcia_request_irq(link, mgslpc_isr);
586 if (ret)
587 goto failed;
588 ret = pcmcia_enable_device(link);
589 if (ret)
590 goto failed;
591
592 info->io_base = link->resource[0]->start;
593 info->irq_level = link->irq;
594 return 0;
595
596 failed:
597 mgslpc_release((u_long)link);
598 return -ENODEV;
599 }
600
601 /* Card has been removed.
602 * Unregister device and release PCMCIA configuration.
603 * If device is open, postpone until it is closed.
604 */
605 static void mgslpc_release(u_long arg)
606 {
607 struct pcmcia_device *link = (struct pcmcia_device *)arg;
608
609 if (debug_level >= DEBUG_LEVEL_INFO)
610 printk("mgslpc_release(0x%p)\n", link);
611
612 pcmcia_disable_device(link);
613 }
614
615 static void mgslpc_detach(struct pcmcia_device *link)
616 {
617 if (debug_level >= DEBUG_LEVEL_INFO)
618 printk("mgslpc_detach(0x%p)\n", link);
619
620 ((MGSLPC_INFO *)link->priv)->stop = 1;
621 mgslpc_release((u_long)link);
622
623 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
624 }
625
626 static int mgslpc_suspend(struct pcmcia_device *link)
627 {
628 MGSLPC_INFO *info = link->priv;
629
630 info->stop = 1;
631
632 return 0;
633 }
634
635 static int mgslpc_resume(struct pcmcia_device *link)
636 {
637 MGSLPC_INFO *info = link->priv;
638
639 info->stop = 0;
640
641 return 0;
642 }
643
644
645 static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
646 char *name, const char *routine)
647 {
648 #ifdef MGSLPC_PARANOIA_CHECK
649 static const char *badmagic =
650 "Warning: bad magic number for mgsl struct (%s) in %s\n";
651 static const char *badinfo =
652 "Warning: null mgslpc_info for (%s) in %s\n";
653
654 if (!info) {
655 printk(badinfo, name, routine);
656 return true;
657 }
658 if (info->magic != MGSLPC_MAGIC) {
659 printk(badmagic, name, routine);
660 return true;
661 }
662 #else
663 if (!info)
664 return true;
665 #endif
666 return false;
667 }
668
669
670 #define CMD_RXFIFO BIT7 // release current rx FIFO
671 #define CMD_RXRESET BIT6 // receiver reset
672 #define CMD_RXFIFO_READ BIT5
673 #define CMD_START_TIMER BIT4
674 #define CMD_TXFIFO BIT3 // release current tx FIFO
675 #define CMD_TXEOM BIT1 // transmit end message
676 #define CMD_TXRESET BIT0 // transmit reset
677
678 static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
679 {
680 int i = 0;
681 /* wait for command completion */
682 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
683 udelay(1);
684 if (i++ == 1000)
685 return false;
686 }
687 return true;
688 }
689
690 static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
691 {
692 wait_command_complete(info, channel);
693 write_reg(info, (unsigned char) (channel + CMDR), cmd);
694 }
695
696 static void tx_pause(struct tty_struct *tty)
697 {
698 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
699 unsigned long flags;
700
701 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
702 return;
703 if (debug_level >= DEBUG_LEVEL_INFO)
704 printk("tx_pause(%s)\n",info->device_name);
705
706 spin_lock_irqsave(&info->lock,flags);
707 if (info->tx_enabled)
708 tx_stop(info);
709 spin_unlock_irqrestore(&info->lock,flags);
710 }
711
712 static void tx_release(struct tty_struct *tty)
713 {
714 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
715 unsigned long flags;
716
717 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
718 return;
719 if (debug_level >= DEBUG_LEVEL_INFO)
720 printk("tx_release(%s)\n",info->device_name);
721
722 spin_lock_irqsave(&info->lock,flags);
723 if (!info->tx_enabled)
724 tx_start(info, tty);
725 spin_unlock_irqrestore(&info->lock,flags);
726 }
727
728 /* Return next bottom half action to perform.
729 * or 0 if nothing to do.
730 */
731 static int bh_action(MGSLPC_INFO *info)
732 {
733 unsigned long flags;
734 int rc = 0;
735
736 spin_lock_irqsave(&info->lock,flags);
737
738 if (info->pending_bh & BH_RECEIVE) {
739 info->pending_bh &= ~BH_RECEIVE;
740 rc = BH_RECEIVE;
741 } else if (info->pending_bh & BH_TRANSMIT) {
742 info->pending_bh &= ~BH_TRANSMIT;
743 rc = BH_TRANSMIT;
744 } else if (info->pending_bh & BH_STATUS) {
745 info->pending_bh &= ~BH_STATUS;
746 rc = BH_STATUS;
747 }
748
749 if (!rc) {
750 /* Mark BH routine as complete */
751 info->bh_running = false;
752 info->bh_requested = false;
753 }
754
755 spin_unlock_irqrestore(&info->lock,flags);
756
757 return rc;
758 }
759
760 static void bh_handler(struct work_struct *work)
761 {
762 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
763 struct tty_struct *tty;
764 int action;
765
766 if (!info)
767 return;
768
769 if (debug_level >= DEBUG_LEVEL_BH)
770 printk( "%s(%d):bh_handler(%s) entry\n",
771 __FILE__,__LINE__,info->device_name);
772
773 info->bh_running = true;
774 tty = tty_port_tty_get(&info->port);
775
776 while((action = bh_action(info)) != 0) {
777
778 /* Process work item */
779 if ( debug_level >= DEBUG_LEVEL_BH )
780 printk( "%s(%d):bh_handler() work item action=%d\n",
781 __FILE__,__LINE__,action);
782
783 switch (action) {
784
785 case BH_RECEIVE:
786 while(rx_get_frame(info, tty));
787 break;
788 case BH_TRANSMIT:
789 bh_transmit(info, tty);
790 break;
791 case BH_STATUS:
792 bh_status(info);
793 break;
794 default:
795 /* unknown work item ID */
796 printk("Unknown work item ID=%08X!\n", action);
797 break;
798 }
799 }
800
801 tty_kref_put(tty);
802 if (debug_level >= DEBUG_LEVEL_BH)
803 printk( "%s(%d):bh_handler(%s) exit\n",
804 __FILE__,__LINE__,info->device_name);
805 }
806
807 static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
808 {
809 if (debug_level >= DEBUG_LEVEL_BH)
810 printk("bh_transmit() entry on %s\n", info->device_name);
811
812 if (tty)
813 tty_wakeup(tty);
814 }
815
816 static void bh_status(MGSLPC_INFO *info)
817 {
818 info->ri_chkcount = 0;
819 info->dsr_chkcount = 0;
820 info->dcd_chkcount = 0;
821 info->cts_chkcount = 0;
822 }
823
824 /* eom: non-zero = end of frame */
825 static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
826 {
827 unsigned char data[2];
828 unsigned char fifo_count, read_count, i;
829 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
830
831 if (debug_level >= DEBUG_LEVEL_ISR)
832 printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
833
834 if (!info->rx_enabled)
835 return;
836
837 if (info->rx_frame_count >= info->rx_buf_count) {
838 /* no more free buffers */
839 issue_command(info, CHA, CMD_RXRESET);
840 info->pending_bh |= BH_RECEIVE;
841 info->rx_overflow = true;
842 info->icount.buf_overrun++;
843 return;
844 }
845
846 if (eom) {
847 /* end of frame, get FIFO count from RBCL register */
848 if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
849 fifo_count = 32;
850 } else
851 fifo_count = 32;
852
853 do {
854 if (fifo_count == 1) {
855 read_count = 1;
856 data[0] = read_reg(info, CHA + RXFIFO);
857 } else {
858 read_count = 2;
859 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
860 }
861 fifo_count -= read_count;
862 if (!fifo_count && eom)
863 buf->status = data[--read_count];
864
865 for (i = 0; i < read_count; i++) {
866 if (buf->count >= info->max_frame_size) {
867 /* frame too large, reset receiver and reset current buffer */
868 issue_command(info, CHA, CMD_RXRESET);
869 buf->count = 0;
870 return;
871 }
872 *(buf->data + buf->count) = data[i];
873 buf->count++;
874 }
875 } while (fifo_count);
876
877 if (eom) {
878 info->pending_bh |= BH_RECEIVE;
879 info->rx_frame_count++;
880 info->rx_put++;
881 if (info->rx_put >= info->rx_buf_count)
882 info->rx_put = 0;
883 }
884 issue_command(info, CHA, CMD_RXFIFO);
885 }
886
887 static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
888 {
889 unsigned char data, status, flag;
890 int fifo_count;
891 int work = 0;
892 struct mgsl_icount *icount = &info->icount;
893
894 if (tcd) {
895 /* early termination, get FIFO count from RBCL register */
896 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
897
898 /* Zero fifo count could mean 0 or 32 bytes available.
899 * If BIT5 of STAR is set then at least 1 byte is available.
900 */
901 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
902 fifo_count = 32;
903 } else
904 fifo_count = 32;
905
906 tty_buffer_request_room(tty, fifo_count);
907 /* Flush received async data to receive data buffer. */
908 while (fifo_count) {
909 data = read_reg(info, CHA + RXFIFO);
910 status = read_reg(info, CHA + RXFIFO);
911 fifo_count -= 2;
912
913 icount->rx++;
914 flag = TTY_NORMAL;
915
916 // if no frameing/crc error then save data
917 // BIT7:parity error
918 // BIT6:framing error
919
920 if (status & (BIT7 + BIT6)) {
921 if (status & BIT7)
922 icount->parity++;
923 else
924 icount->frame++;
925
926 /* discard char if tty control flags say so */
927 if (status & info->ignore_status_mask)
928 continue;
929
930 status &= info->read_status_mask;
931
932 if (status & BIT7)
933 flag = TTY_PARITY;
934 else if (status & BIT6)
935 flag = TTY_FRAME;
936 }
937 work += tty_insert_flip_char(tty, data, flag);
938 }
939 issue_command(info, CHA, CMD_RXFIFO);
940
941 if (debug_level >= DEBUG_LEVEL_ISR) {
942 printk("%s(%d):rx_ready_async",
943 __FILE__,__LINE__);
944 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
945 __FILE__,__LINE__,icount->rx,icount->brk,
946 icount->parity,icount->frame,icount->overrun);
947 }
948
949 if (work)
950 tty_flip_buffer_push(tty);
951 }
952
953
954 static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
955 {
956 if (!info->tx_active)
957 return;
958
959 info->tx_active = false;
960 info->tx_aborting = false;
961
962 if (info->params.mode == MGSL_MODE_ASYNC)
963 return;
964
965 info->tx_count = info->tx_put = info->tx_get = 0;
966 del_timer(&info->tx_timer);
967
968 if (info->drop_rts_on_tx_done) {
969 get_signals(info);
970 if (info->serial_signals & SerialSignal_RTS) {
971 info->serial_signals &= ~SerialSignal_RTS;
972 set_signals(info);
973 }
974 info->drop_rts_on_tx_done = false;
975 }
976
977 #if SYNCLINK_GENERIC_HDLC
978 if (info->netcount)
979 hdlcdev_tx_done(info);
980 else
981 #endif
982 {
983 if (tty->stopped || tty->hw_stopped) {
984 tx_stop(info);
985 return;
986 }
987 info->pending_bh |= BH_TRANSMIT;
988 }
989 }
990
991 static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
992 {
993 unsigned char fifo_count = 32;
994 int c;
995
996 if (debug_level >= DEBUG_LEVEL_ISR)
997 printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
998
999 if (info->params.mode == MGSL_MODE_HDLC) {
1000 if (!info->tx_active)
1001 return;
1002 } else {
1003 if (tty->stopped || tty->hw_stopped) {
1004 tx_stop(info);
1005 return;
1006 }
1007 if (!info->tx_count)
1008 info->tx_active = false;
1009 }
1010
1011 if (!info->tx_count)
1012 return;
1013
1014 while (info->tx_count && fifo_count) {
1015 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
1016
1017 if (c == 1) {
1018 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1019 } else {
1020 write_reg16(info, CHA + TXFIFO,
1021 *((unsigned short*)(info->tx_buf + info->tx_get)));
1022 }
1023 info->tx_count -= c;
1024 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1025 fifo_count -= c;
1026 }
1027
1028 if (info->params.mode == MGSL_MODE_ASYNC) {
1029 if (info->tx_count < WAKEUP_CHARS)
1030 info->pending_bh |= BH_TRANSMIT;
1031 issue_command(info, CHA, CMD_TXFIFO);
1032 } else {
1033 if (info->tx_count)
1034 issue_command(info, CHA, CMD_TXFIFO);
1035 else
1036 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1037 }
1038 }
1039
1040 static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
1041 {
1042 get_signals(info);
1043 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1044 irq_disable(info, CHB, IRQ_CTS);
1045 info->icount.cts++;
1046 if (info->serial_signals & SerialSignal_CTS)
1047 info->input_signal_events.cts_up++;
1048 else
1049 info->input_signal_events.cts_down++;
1050 wake_up_interruptible(&info->status_event_wait_q);
1051 wake_up_interruptible(&info->event_wait_q);
1052
1053 if (info->port.flags & ASYNC_CTS_FLOW) {
1054 if (tty->hw_stopped) {
1055 if (info->serial_signals & SerialSignal_CTS) {
1056 if (debug_level >= DEBUG_LEVEL_ISR)
1057 printk("CTS tx start...");
1058 if (tty)
1059 tty->hw_stopped = 0;
1060 tx_start(info, tty);
1061 info->pending_bh |= BH_TRANSMIT;
1062 return;
1063 }
1064 } else {
1065 if (!(info->serial_signals & SerialSignal_CTS)) {
1066 if (debug_level >= DEBUG_LEVEL_ISR)
1067 printk("CTS tx stop...");
1068 if (tty)
1069 tty->hw_stopped = 1;
1070 tx_stop(info);
1071 }
1072 }
1073 }
1074 info->pending_bh |= BH_STATUS;
1075 }
1076
1077 static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
1078 {
1079 get_signals(info);
1080 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1081 irq_disable(info, CHB, IRQ_DCD);
1082 info->icount.dcd++;
1083 if (info->serial_signals & SerialSignal_DCD) {
1084 info->input_signal_events.dcd_up++;
1085 }
1086 else
1087 info->input_signal_events.dcd_down++;
1088 #if SYNCLINK_GENERIC_HDLC
1089 if (info->netcount) {
1090 if (info->serial_signals & SerialSignal_DCD)
1091 netif_carrier_on(info->netdev);
1092 else
1093 netif_carrier_off(info->netdev);
1094 }
1095 #endif
1096 wake_up_interruptible(&info->status_event_wait_q);
1097 wake_up_interruptible(&info->event_wait_q);
1098
1099 if (info->port.flags & ASYNC_CHECK_CD) {
1100 if (debug_level >= DEBUG_LEVEL_ISR)
1101 printk("%s CD now %s...", info->device_name,
1102 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1103 if (info->serial_signals & SerialSignal_DCD)
1104 wake_up_interruptible(&info->port.open_wait);
1105 else {
1106 if (debug_level >= DEBUG_LEVEL_ISR)
1107 printk("doing serial hangup...");
1108 if (tty)
1109 tty_hangup(tty);
1110 }
1111 }
1112 info->pending_bh |= BH_STATUS;
1113 }
1114
1115 static void dsr_change(MGSLPC_INFO *info)
1116 {
1117 get_signals(info);
1118 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1119 port_irq_disable(info, PVR_DSR);
1120 info->icount.dsr++;
1121 if (info->serial_signals & SerialSignal_DSR)
1122 info->input_signal_events.dsr_up++;
1123 else
1124 info->input_signal_events.dsr_down++;
1125 wake_up_interruptible(&info->status_event_wait_q);
1126 wake_up_interruptible(&info->event_wait_q);
1127 info->pending_bh |= BH_STATUS;
1128 }
1129
1130 static void ri_change(MGSLPC_INFO *info)
1131 {
1132 get_signals(info);
1133 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1134 port_irq_disable(info, PVR_RI);
1135 info->icount.rng++;
1136 if (info->serial_signals & SerialSignal_RI)
1137 info->input_signal_events.ri_up++;
1138 else
1139 info->input_signal_events.ri_down++;
1140 wake_up_interruptible(&info->status_event_wait_q);
1141 wake_up_interruptible(&info->event_wait_q);
1142 info->pending_bh |= BH_STATUS;
1143 }
1144
1145 /* Interrupt service routine entry point.
1146 *
1147 * Arguments:
1148 *
1149 * irq interrupt number that caused interrupt
1150 * dev_id device ID supplied during interrupt registration
1151 */
1152 static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
1153 {
1154 MGSLPC_INFO *info = dev_id;
1155 struct tty_struct *tty;
1156 unsigned short isr;
1157 unsigned char gis, pis;
1158 int count=0;
1159
1160 if (debug_level >= DEBUG_LEVEL_ISR)
1161 printk("mgslpc_isr(%d) entry.\n", info->irq_level);
1162
1163 if (!(info->p_dev->_locked))
1164 return IRQ_HANDLED;
1165
1166 tty = tty_port_tty_get(&info->port);
1167
1168 spin_lock(&info->lock);
1169
1170 while ((gis = read_reg(info, CHA + GIS))) {
1171 if (debug_level >= DEBUG_LEVEL_ISR)
1172 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1173
1174 if ((gis & 0x70) || count > 1000) {
1175 printk("synclink_cs:hardware failed or ejected\n");
1176 break;
1177 }
1178 count++;
1179
1180 if (gis & (BIT1 + BIT0)) {
1181 isr = read_reg16(info, CHB + ISR);
1182 if (isr & IRQ_DCD)
1183 dcd_change(info, tty);
1184 if (isr & IRQ_CTS)
1185 cts_change(info, tty);
1186 }
1187 if (gis & (BIT3 + BIT2))
1188 {
1189 isr = read_reg16(info, CHA + ISR);
1190 if (isr & IRQ_TIMER) {
1191 info->irq_occurred = true;
1192 irq_disable(info, CHA, IRQ_TIMER);
1193 }
1194
1195 /* receive IRQs */
1196 if (isr & IRQ_EXITHUNT) {
1197 info->icount.exithunt++;
1198 wake_up_interruptible(&info->event_wait_q);
1199 }
1200 if (isr & IRQ_BREAK_ON) {
1201 info->icount.brk++;
1202 if (info->port.flags & ASYNC_SAK)
1203 do_SAK(tty);
1204 }
1205 if (isr & IRQ_RXTIME) {
1206 issue_command(info, CHA, CMD_RXFIFO_READ);
1207 }
1208 if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
1209 if (info->params.mode == MGSL_MODE_HDLC)
1210 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1211 else
1212 rx_ready_async(info, isr & IRQ_RXEOM, tty);
1213 }
1214
1215 /* transmit IRQs */
1216 if (isr & IRQ_UNDERRUN) {
1217 if (info->tx_aborting)
1218 info->icount.txabort++;
1219 else
1220 info->icount.txunder++;
1221 tx_done(info, tty);
1222 }
1223 else if (isr & IRQ_ALLSENT) {
1224 info->icount.txok++;
1225 tx_done(info, tty);
1226 }
1227 else if (isr & IRQ_TXFIFO)
1228 tx_ready(info, tty);
1229 }
1230 if (gis & BIT7) {
1231 pis = read_reg(info, CHA + PIS);
1232 if (pis & BIT1)
1233 dsr_change(info);
1234 if (pis & BIT2)
1235 ri_change(info);
1236 }
1237 }
1238
1239 /* Request bottom half processing if there's something
1240 * for it to do and the bh is not already running
1241 */
1242
1243 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
1244 if ( debug_level >= DEBUG_LEVEL_ISR )
1245 printk("%s(%d):%s queueing bh task.\n",
1246 __FILE__,__LINE__,info->device_name);
1247 schedule_work(&info->task);
1248 info->bh_requested = true;
1249 }
1250
1251 spin_unlock(&info->lock);
1252 tty_kref_put(tty);
1253
1254 if (debug_level >= DEBUG_LEVEL_ISR)
1255 printk("%s(%d):mgslpc_isr(%d)exit.\n",
1256 __FILE__, __LINE__, info->irq_level);
1257
1258 return IRQ_HANDLED;
1259 }
1260
1261 /* Initialize and start device.
1262 */
1263 static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
1264 {
1265 int retval = 0;
1266
1267 if (debug_level >= DEBUG_LEVEL_INFO)
1268 printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
1269
1270 if (info->port.flags & ASYNC_INITIALIZED)
1271 return 0;
1272
1273 if (!info->tx_buf) {
1274 /* allocate a page of memory for a transmit buffer */
1275 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1276 if (!info->tx_buf) {
1277 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1278 __FILE__,__LINE__,info->device_name);
1279 return -ENOMEM;
1280 }
1281 }
1282
1283 info->pending_bh = 0;
1284
1285 memset(&info->icount, 0, sizeof(info->icount));
1286
1287 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
1288
1289 /* Allocate and claim adapter resources */
1290 retval = claim_resources(info);
1291
1292 /* perform existence check and diagnostics */
1293 if ( !retval )
1294 retval = adapter_test(info);
1295
1296 if ( retval ) {
1297 if (capable(CAP_SYS_ADMIN) && tty)
1298 set_bit(TTY_IO_ERROR, &tty->flags);
1299 release_resources(info);
1300 return retval;
1301 }
1302
1303 /* program hardware for current parameters */
1304 mgslpc_change_params(info, tty);
1305
1306 if (tty)
1307 clear_bit(TTY_IO_ERROR, &tty->flags);
1308
1309 info->port.flags |= ASYNC_INITIALIZED;
1310
1311 return 0;
1312 }
1313
1314 /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1315 */
1316 static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
1317 {
1318 unsigned long flags;
1319
1320 if (!(info->port.flags & ASYNC_INITIALIZED))
1321 return;
1322
1323 if (debug_level >= DEBUG_LEVEL_INFO)
1324 printk("%s(%d):mgslpc_shutdown(%s)\n",
1325 __FILE__,__LINE__, info->device_name );
1326
1327 /* clear status wait queue because status changes */
1328 /* can't happen after shutting down the hardware */
1329 wake_up_interruptible(&info->status_event_wait_q);
1330 wake_up_interruptible(&info->event_wait_q);
1331
1332 del_timer_sync(&info->tx_timer);
1333
1334 if (info->tx_buf) {
1335 free_page((unsigned long) info->tx_buf);
1336 info->tx_buf = NULL;
1337 }
1338
1339 spin_lock_irqsave(&info->lock,flags);
1340
1341 rx_stop(info);
1342 tx_stop(info);
1343
1344 /* TODO:disable interrupts instead of reset to preserve signal states */
1345 reset_device(info);
1346
1347 if (!tty || tty->termios.c_cflag & HUPCL) {
1348 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1349 set_signals(info);
1350 }
1351
1352 spin_unlock_irqrestore(&info->lock,flags);
1353
1354 release_resources(info);
1355
1356 if (tty)
1357 set_bit(TTY_IO_ERROR, &tty->flags);
1358
1359 info->port.flags &= ~ASYNC_INITIALIZED;
1360 }
1361
1362 static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
1363 {
1364 unsigned long flags;
1365
1366 spin_lock_irqsave(&info->lock,flags);
1367
1368 rx_stop(info);
1369 tx_stop(info);
1370 info->tx_count = info->tx_put = info->tx_get = 0;
1371
1372 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1373 hdlc_mode(info);
1374 else
1375 async_mode(info);
1376
1377 set_signals(info);
1378
1379 info->dcd_chkcount = 0;
1380 info->cts_chkcount = 0;
1381 info->ri_chkcount = 0;
1382 info->dsr_chkcount = 0;
1383
1384 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1385 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1386 get_signals(info);
1387
1388 if (info->netcount || (tty && (tty->termios.c_cflag & CREAD)))
1389 rx_start(info);
1390
1391 spin_unlock_irqrestore(&info->lock,flags);
1392 }
1393
1394 /* Reconfigure adapter based on new parameters
1395 */
1396 static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
1397 {
1398 unsigned cflag;
1399 int bits_per_char;
1400
1401 if (!tty)
1402 return;
1403
1404 if (debug_level >= DEBUG_LEVEL_INFO)
1405 printk("%s(%d):mgslpc_change_params(%s)\n",
1406 __FILE__,__LINE__, info->device_name );
1407
1408 cflag = tty->termios.c_cflag;
1409
1410 /* if B0 rate (hangup) specified then negate DTR and RTS */
1411 /* otherwise assert DTR and RTS */
1412 if (cflag & CBAUD)
1413 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1414 else
1415 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1416
1417 /* byte size and parity */
1418
1419 switch (cflag & CSIZE) {
1420 case CS5: info->params.data_bits = 5; break;
1421 case CS6: info->params.data_bits = 6; break;
1422 case CS7: info->params.data_bits = 7; break;
1423 case CS8: info->params.data_bits = 8; break;
1424 default: info->params.data_bits = 7; break;
1425 }
1426
1427 if (cflag & CSTOPB)
1428 info->params.stop_bits = 2;
1429 else
1430 info->params.stop_bits = 1;
1431
1432 info->params.parity = ASYNC_PARITY_NONE;
1433 if (cflag & PARENB) {
1434 if (cflag & PARODD)
1435 info->params.parity = ASYNC_PARITY_ODD;
1436 else
1437 info->params.parity = ASYNC_PARITY_EVEN;
1438 #ifdef CMSPAR
1439 if (cflag & CMSPAR)
1440 info->params.parity = ASYNC_PARITY_SPACE;
1441 #endif
1442 }
1443
1444 /* calculate number of jiffies to transmit a full
1445 * FIFO (32 bytes) at specified data rate
1446 */
1447 bits_per_char = info->params.data_bits +
1448 info->params.stop_bits + 1;
1449
1450 /* if port data rate is set to 460800 or less then
1451 * allow tty settings to override, otherwise keep the
1452 * current data rate.
1453 */
1454 if (info->params.data_rate <= 460800) {
1455 info->params.data_rate = tty_get_baud_rate(tty);
1456 }
1457
1458 if ( info->params.data_rate ) {
1459 info->timeout = (32*HZ*bits_per_char) /
1460 info->params.data_rate;
1461 }
1462 info->timeout += HZ/50; /* Add .02 seconds of slop */
1463
1464 if (cflag & CRTSCTS)
1465 info->port.flags |= ASYNC_CTS_FLOW;
1466 else
1467 info->port.flags &= ~ASYNC_CTS_FLOW;
1468
1469 if (cflag & CLOCAL)
1470 info->port.flags &= ~ASYNC_CHECK_CD;
1471 else
1472 info->port.flags |= ASYNC_CHECK_CD;
1473
1474 /* process tty input control flags */
1475
1476 info->read_status_mask = 0;
1477 if (I_INPCK(tty))
1478 info->read_status_mask |= BIT7 | BIT6;
1479 if (I_IGNPAR(tty))
1480 info->ignore_status_mask |= BIT7 | BIT6;
1481
1482 mgslpc_program_hw(info, tty);
1483 }
1484
1485 /* Add a character to the transmit buffer
1486 */
1487 static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1488 {
1489 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1490 unsigned long flags;
1491
1492 if (debug_level >= DEBUG_LEVEL_INFO) {
1493 printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
1494 __FILE__,__LINE__,ch,info->device_name);
1495 }
1496
1497 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
1498 return 0;
1499
1500 if (!info->tx_buf)
1501 return 0;
1502
1503 spin_lock_irqsave(&info->lock,flags);
1504
1505 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1506 if (info->tx_count < TXBUFSIZE - 1) {
1507 info->tx_buf[info->tx_put++] = ch;
1508 info->tx_put &= TXBUFSIZE-1;
1509 info->tx_count++;
1510 }
1511 }
1512
1513 spin_unlock_irqrestore(&info->lock,flags);
1514 return 1;
1515 }
1516
1517 /* Enable transmitter so remaining characters in the
1518 * transmit buffer are sent.
1519 */
1520 static void mgslpc_flush_chars(struct tty_struct *tty)
1521 {
1522 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1523 unsigned long flags;
1524
1525 if (debug_level >= DEBUG_LEVEL_INFO)
1526 printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1527 __FILE__,__LINE__,info->device_name,info->tx_count);
1528
1529 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1530 return;
1531
1532 if (info->tx_count <= 0 || tty->stopped ||
1533 tty->hw_stopped || !info->tx_buf)
1534 return;
1535
1536 if (debug_level >= DEBUG_LEVEL_INFO)
1537 printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1538 __FILE__,__LINE__,info->device_name);
1539
1540 spin_lock_irqsave(&info->lock,flags);
1541 if (!info->tx_active)
1542 tx_start(info, tty);
1543 spin_unlock_irqrestore(&info->lock,flags);
1544 }
1545
1546 /* Send a block of data
1547 *
1548 * Arguments:
1549 *
1550 * tty pointer to tty information structure
1551 * buf pointer to buffer containing send data
1552 * count size of send data in bytes
1553 *
1554 * Returns: number of characters written
1555 */
1556 static int mgslpc_write(struct tty_struct * tty,
1557 const unsigned char *buf, int count)
1558 {
1559 int c, ret = 0;
1560 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1561 unsigned long flags;
1562
1563 if (debug_level >= DEBUG_LEVEL_INFO)
1564 printk( "%s(%d):mgslpc_write(%s) count=%d\n",
1565 __FILE__,__LINE__,info->device_name,count);
1566
1567 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
1568 !info->tx_buf)
1569 goto cleanup;
1570
1571 if (info->params.mode == MGSL_MODE_HDLC) {
1572 if (count > TXBUFSIZE) {
1573 ret = -EIO;
1574 goto cleanup;
1575 }
1576 if (info->tx_active)
1577 goto cleanup;
1578 else if (info->tx_count)
1579 goto start;
1580 }
1581
1582 for (;;) {
1583 c = min(count,
1584 min(TXBUFSIZE - info->tx_count - 1,
1585 TXBUFSIZE - info->tx_put));
1586 if (c <= 0)
1587 break;
1588
1589 memcpy(info->tx_buf + info->tx_put, buf, c);
1590
1591 spin_lock_irqsave(&info->lock,flags);
1592 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1593 info->tx_count += c;
1594 spin_unlock_irqrestore(&info->lock,flags);
1595
1596 buf += c;
1597 count -= c;
1598 ret += c;
1599 }
1600 start:
1601 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1602 spin_lock_irqsave(&info->lock,flags);
1603 if (!info->tx_active)
1604 tx_start(info, tty);
1605 spin_unlock_irqrestore(&info->lock,flags);
1606 }
1607 cleanup:
1608 if (debug_level >= DEBUG_LEVEL_INFO)
1609 printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
1610 __FILE__,__LINE__,info->device_name,ret);
1611 return ret;
1612 }
1613
1614 /* Return the count of free bytes in transmit buffer
1615 */
1616 static int mgslpc_write_room(struct tty_struct *tty)
1617 {
1618 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1619 int ret;
1620
1621 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1622 return 0;
1623
1624 if (info->params.mode == MGSL_MODE_HDLC) {
1625 /* HDLC (frame oriented) mode */
1626 if (info->tx_active)
1627 return 0;
1628 else
1629 return HDLC_MAX_FRAME_SIZE;
1630 } else {
1631 ret = TXBUFSIZE - info->tx_count - 1;
1632 if (ret < 0)
1633 ret = 0;
1634 }
1635
1636 if (debug_level >= DEBUG_LEVEL_INFO)
1637 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
1638 __FILE__,__LINE__, info->device_name, ret);
1639 return ret;
1640 }
1641
1642 /* Return the count of bytes in transmit buffer
1643 */
1644 static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1645 {
1646 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1647 int rc;
1648
1649 if (debug_level >= DEBUG_LEVEL_INFO)
1650 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
1651 __FILE__,__LINE__, info->device_name );
1652
1653 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1654 return 0;
1655
1656 if (info->params.mode == MGSL_MODE_HDLC)
1657 rc = info->tx_active ? info->max_frame_size : 0;
1658 else
1659 rc = info->tx_count;
1660
1661 if (debug_level >= DEBUG_LEVEL_INFO)
1662 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
1663 __FILE__,__LINE__, info->device_name, rc);
1664
1665 return rc;
1666 }
1667
1668 /* Discard all data in the send buffer
1669 */
1670 static void mgslpc_flush_buffer(struct tty_struct *tty)
1671 {
1672 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1673 unsigned long flags;
1674
1675 if (debug_level >= DEBUG_LEVEL_INFO)
1676 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
1677 __FILE__,__LINE__, info->device_name );
1678
1679 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1680 return;
1681
1682 spin_lock_irqsave(&info->lock,flags);
1683 info->tx_count = info->tx_put = info->tx_get = 0;
1684 del_timer(&info->tx_timer);
1685 spin_unlock_irqrestore(&info->lock,flags);
1686
1687 wake_up_interruptible(&tty->write_wait);
1688 tty_wakeup(tty);
1689 }
1690
1691 /* Send a high-priority XON/XOFF character
1692 */
1693 static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1694 {
1695 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1696 unsigned long flags;
1697
1698 if (debug_level >= DEBUG_LEVEL_INFO)
1699 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
1700 __FILE__,__LINE__, info->device_name, ch );
1701
1702 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1703 return;
1704
1705 info->x_char = ch;
1706 if (ch) {
1707 spin_lock_irqsave(&info->lock,flags);
1708 if (!info->tx_enabled)
1709 tx_start(info, tty);
1710 spin_unlock_irqrestore(&info->lock,flags);
1711 }
1712 }
1713
1714 /* Signal remote device to throttle send data (our receive data)
1715 */
1716 static void mgslpc_throttle(struct tty_struct * tty)
1717 {
1718 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1719 unsigned long flags;
1720
1721 if (debug_level >= DEBUG_LEVEL_INFO)
1722 printk("%s(%d):mgslpc_throttle(%s) entry\n",
1723 __FILE__,__LINE__, info->device_name );
1724
1725 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1726 return;
1727
1728 if (I_IXOFF(tty))
1729 mgslpc_send_xchar(tty, STOP_CHAR(tty));
1730
1731 if (tty->termios.c_cflag & CRTSCTS) {
1732 spin_lock_irqsave(&info->lock,flags);
1733 info->serial_signals &= ~SerialSignal_RTS;
1734 set_signals(info);
1735 spin_unlock_irqrestore(&info->lock,flags);
1736 }
1737 }
1738
1739 /* Signal remote device to stop throttling send data (our receive data)
1740 */
1741 static void mgslpc_unthrottle(struct tty_struct * tty)
1742 {
1743 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1744 unsigned long flags;
1745
1746 if (debug_level >= DEBUG_LEVEL_INFO)
1747 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
1748 __FILE__,__LINE__, info->device_name );
1749
1750 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1751 return;
1752
1753 if (I_IXOFF(tty)) {
1754 if (info->x_char)
1755 info->x_char = 0;
1756 else
1757 mgslpc_send_xchar(tty, START_CHAR(tty));
1758 }
1759
1760 if (tty->termios.c_cflag & CRTSCTS) {
1761 spin_lock_irqsave(&info->lock,flags);
1762 info->serial_signals |= SerialSignal_RTS;
1763 set_signals(info);
1764 spin_unlock_irqrestore(&info->lock,flags);
1765 }
1766 }
1767
1768 /* get the current serial statistics
1769 */
1770 static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1771 {
1772 int err;
1773 if (debug_level >= DEBUG_LEVEL_INFO)
1774 printk("get_params(%s)\n", info->device_name);
1775 if (!user_icount) {
1776 memset(&info->icount, 0, sizeof(info->icount));
1777 } else {
1778 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
1779 if (err)
1780 return -EFAULT;
1781 }
1782 return 0;
1783 }
1784
1785 /* get the current serial parameters
1786 */
1787 static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1788 {
1789 int err;
1790 if (debug_level >= DEBUG_LEVEL_INFO)
1791 printk("get_params(%s)\n", info->device_name);
1792 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1793 if (err)
1794 return -EFAULT;
1795 return 0;
1796 }
1797
1798 /* set the serial parameters
1799 *
1800 * Arguments:
1801 *
1802 * info pointer to device instance data
1803 * new_params user buffer containing new serial params
1804 *
1805 * Returns: 0 if success, otherwise error code
1806 */
1807 static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
1808 {
1809 unsigned long flags;
1810 MGSL_PARAMS tmp_params;
1811 int err;
1812
1813 if (debug_level >= DEBUG_LEVEL_INFO)
1814 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
1815 info->device_name );
1816 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1817 if (err) {
1818 if ( debug_level >= DEBUG_LEVEL_INFO )
1819 printk( "%s(%d):set_params(%s) user buffer copy failed\n",
1820 __FILE__,__LINE__,info->device_name);
1821 return -EFAULT;
1822 }
1823
1824 spin_lock_irqsave(&info->lock,flags);
1825 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
1826 spin_unlock_irqrestore(&info->lock,flags);
1827
1828 mgslpc_change_params(info, tty);
1829
1830 return 0;
1831 }
1832
1833 static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
1834 {
1835 int err;
1836 if (debug_level >= DEBUG_LEVEL_INFO)
1837 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
1838 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
1839 if (err)
1840 return -EFAULT;
1841 return 0;
1842 }
1843
1844 static int set_txidle(MGSLPC_INFO * info, int idle_mode)
1845 {
1846 unsigned long flags;
1847 if (debug_level >= DEBUG_LEVEL_INFO)
1848 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
1849 spin_lock_irqsave(&info->lock,flags);
1850 info->idle_mode = idle_mode;
1851 tx_set_idle(info);
1852 spin_unlock_irqrestore(&info->lock,flags);
1853 return 0;
1854 }
1855
1856 static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
1857 {
1858 int err;
1859 if (debug_level >= DEBUG_LEVEL_INFO)
1860 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
1861 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
1862 if (err)
1863 return -EFAULT;
1864 return 0;
1865 }
1866
1867 static int set_interface(MGSLPC_INFO * info, int if_mode)
1868 {
1869 unsigned long flags;
1870 unsigned char val;
1871 if (debug_level >= DEBUG_LEVEL_INFO)
1872 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
1873 spin_lock_irqsave(&info->lock,flags);
1874 info->if_mode = if_mode;
1875
1876 val = read_reg(info, PVR) & 0x0f;
1877 switch (info->if_mode)
1878 {
1879 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
1880 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
1881 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
1882 }
1883 write_reg(info, PVR, val);
1884
1885 spin_unlock_irqrestore(&info->lock,flags);
1886 return 0;
1887 }
1888
1889 static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
1890 {
1891 unsigned long flags;
1892
1893 if (debug_level >= DEBUG_LEVEL_INFO)
1894 printk("set_txenable(%s,%d)\n", info->device_name, enable);
1895
1896 spin_lock_irqsave(&info->lock,flags);
1897 if (enable) {
1898 if (!info->tx_enabled)
1899 tx_start(info, tty);
1900 } else {
1901 if (info->tx_enabled)
1902 tx_stop(info);
1903 }
1904 spin_unlock_irqrestore(&info->lock,flags);
1905 return 0;
1906 }
1907
1908 static int tx_abort(MGSLPC_INFO * info)
1909 {
1910 unsigned long flags;
1911
1912 if (debug_level >= DEBUG_LEVEL_INFO)
1913 printk("tx_abort(%s)\n", info->device_name);
1914
1915 spin_lock_irqsave(&info->lock,flags);
1916 if (info->tx_active && info->tx_count &&
1917 info->params.mode == MGSL_MODE_HDLC) {
1918 /* clear data count so FIFO is not filled on next IRQ.
1919 * This results in underrun and abort transmission.
1920 */
1921 info->tx_count = info->tx_put = info->tx_get = 0;
1922 info->tx_aborting = true;
1923 }
1924 spin_unlock_irqrestore(&info->lock,flags);
1925 return 0;
1926 }
1927
1928 static int set_rxenable(MGSLPC_INFO * info, int enable)
1929 {
1930 unsigned long flags;
1931
1932 if (debug_level >= DEBUG_LEVEL_INFO)
1933 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
1934
1935 spin_lock_irqsave(&info->lock,flags);
1936 if (enable) {
1937 if (!info->rx_enabled)
1938 rx_start(info);
1939 } else {
1940 if (info->rx_enabled)
1941 rx_stop(info);
1942 }
1943 spin_unlock_irqrestore(&info->lock,flags);
1944 return 0;
1945 }
1946
1947 /* wait for specified event to occur
1948 *
1949 * Arguments: info pointer to device instance data
1950 * mask pointer to bitmask of events to wait for
1951 * Return Value: 0 if successful and bit mask updated with
1952 * of events triggerred,
1953 * otherwise error code
1954 */
1955 static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
1956 {
1957 unsigned long flags;
1958 int s;
1959 int rc=0;
1960 struct mgsl_icount cprev, cnow;
1961 int events;
1962 int mask;
1963 struct _input_signal_events oldsigs, newsigs;
1964 DECLARE_WAITQUEUE(wait, current);
1965
1966 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
1967 if (rc)
1968 return -EFAULT;
1969
1970 if (debug_level >= DEBUG_LEVEL_INFO)
1971 printk("wait_events(%s,%d)\n", info->device_name, mask);
1972
1973 spin_lock_irqsave(&info->lock,flags);
1974
1975 /* return immediately if state matches requested events */
1976 get_signals(info);
1977 s = info->serial_signals;
1978 events = mask &
1979 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
1980 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
1981 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
1982 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
1983 if (events) {
1984 spin_unlock_irqrestore(&info->lock,flags);
1985 goto exit;
1986 }
1987
1988 /* save current irq counts */
1989 cprev = info->icount;
1990 oldsigs = info->input_signal_events;
1991
1992 if ((info->params.mode == MGSL_MODE_HDLC) &&
1993 (mask & MgslEvent_ExitHuntMode))
1994 irq_enable(info, CHA, IRQ_EXITHUNT);
1995
1996 set_current_state(TASK_INTERRUPTIBLE);
1997 add_wait_queue(&info->event_wait_q, &wait);
1998
1999 spin_unlock_irqrestore(&info->lock,flags);
2000
2001
2002 for(;;) {
2003 schedule();
2004 if (signal_pending(current)) {
2005 rc = -ERESTARTSYS;
2006 break;
2007 }
2008
2009 /* get current irq counts */
2010 spin_lock_irqsave(&info->lock,flags);
2011 cnow = info->icount;
2012 newsigs = info->input_signal_events;
2013 set_current_state(TASK_INTERRUPTIBLE);
2014 spin_unlock_irqrestore(&info->lock,flags);
2015
2016 /* if no change, wait aborted for some reason */
2017 if (newsigs.dsr_up == oldsigs.dsr_up &&
2018 newsigs.dsr_down == oldsigs.dsr_down &&
2019 newsigs.dcd_up == oldsigs.dcd_up &&
2020 newsigs.dcd_down == oldsigs.dcd_down &&
2021 newsigs.cts_up == oldsigs.cts_up &&
2022 newsigs.cts_down == oldsigs.cts_down &&
2023 newsigs.ri_up == oldsigs.ri_up &&
2024 newsigs.ri_down == oldsigs.ri_down &&
2025 cnow.exithunt == cprev.exithunt &&
2026 cnow.rxidle == cprev.rxidle) {
2027 rc = -EIO;
2028 break;
2029 }
2030
2031 events = mask &
2032 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2033 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2034 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2035 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2036 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2037 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2038 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2039 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2040 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2041 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2042 if (events)
2043 break;
2044
2045 cprev = cnow;
2046 oldsigs = newsigs;
2047 }
2048
2049 remove_wait_queue(&info->event_wait_q, &wait);
2050 set_current_state(TASK_RUNNING);
2051
2052 if (mask & MgslEvent_ExitHuntMode) {
2053 spin_lock_irqsave(&info->lock,flags);
2054 if (!waitqueue_active(&info->event_wait_q))
2055 irq_disable(info, CHA, IRQ_EXITHUNT);
2056 spin_unlock_irqrestore(&info->lock,flags);
2057 }
2058 exit:
2059 if (rc == 0)
2060 PUT_USER(rc, events, mask_ptr);
2061 return rc;
2062 }
2063
2064 static int modem_input_wait(MGSLPC_INFO *info,int arg)
2065 {
2066 unsigned long flags;
2067 int rc;
2068 struct mgsl_icount cprev, cnow;
2069 DECLARE_WAITQUEUE(wait, current);
2070
2071 /* save current irq counts */
2072 spin_lock_irqsave(&info->lock,flags);
2073 cprev = info->icount;
2074 add_wait_queue(&info->status_event_wait_q, &wait);
2075 set_current_state(TASK_INTERRUPTIBLE);
2076 spin_unlock_irqrestore(&info->lock,flags);
2077
2078 for(;;) {
2079 schedule();
2080 if (signal_pending(current)) {
2081 rc = -ERESTARTSYS;
2082 break;
2083 }
2084
2085 /* get new irq counts */
2086 spin_lock_irqsave(&info->lock,flags);
2087 cnow = info->icount;
2088 set_current_state(TASK_INTERRUPTIBLE);
2089 spin_unlock_irqrestore(&info->lock,flags);
2090
2091 /* if no change, wait aborted for some reason */
2092 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2093 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2094 rc = -EIO;
2095 break;
2096 }
2097
2098 /* check for change in caller specified modem input */
2099 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2100 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2101 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2102 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2103 rc = 0;
2104 break;
2105 }
2106
2107 cprev = cnow;
2108 }
2109 remove_wait_queue(&info->status_event_wait_q, &wait);
2110 set_current_state(TASK_RUNNING);
2111 return rc;
2112 }
2113
2114 /* return the state of the serial control and status signals
2115 */
2116 static int tiocmget(struct tty_struct *tty)
2117 {
2118 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2119 unsigned int result;
2120 unsigned long flags;
2121
2122 spin_lock_irqsave(&info->lock,flags);
2123 get_signals(info);
2124 spin_unlock_irqrestore(&info->lock,flags);
2125
2126 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2127 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2128 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2129 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2130 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2131 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2132
2133 if (debug_level >= DEBUG_LEVEL_INFO)
2134 printk("%s(%d):%s tiocmget() value=%08X\n",
2135 __FILE__,__LINE__, info->device_name, result );
2136 return result;
2137 }
2138
2139 /* set modem control signals (DTR/RTS)
2140 */
2141 static int tiocmset(struct tty_struct *tty,
2142 unsigned int set, unsigned int clear)
2143 {
2144 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2145 unsigned long flags;
2146
2147 if (debug_level >= DEBUG_LEVEL_INFO)
2148 printk("%s(%d):%s tiocmset(%x,%x)\n",
2149 __FILE__,__LINE__,info->device_name, set, clear);
2150
2151 if (set & TIOCM_RTS)
2152 info->serial_signals |= SerialSignal_RTS;
2153 if (set & TIOCM_DTR)
2154 info->serial_signals |= SerialSignal_DTR;
2155 if (clear & TIOCM_RTS)
2156 info->serial_signals &= ~SerialSignal_RTS;
2157 if (clear & TIOCM_DTR)
2158 info->serial_signals &= ~SerialSignal_DTR;
2159
2160 spin_lock_irqsave(&info->lock,flags);
2161 set_signals(info);
2162 spin_unlock_irqrestore(&info->lock,flags);
2163
2164 return 0;
2165 }
2166
2167 /* Set or clear transmit break condition
2168 *
2169 * Arguments: tty pointer to tty instance data
2170 * break_state -1=set break condition, 0=clear
2171 */
2172 static int mgslpc_break(struct tty_struct *tty, int break_state)
2173 {
2174 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2175 unsigned long flags;
2176
2177 if (debug_level >= DEBUG_LEVEL_INFO)
2178 printk("%s(%d):mgslpc_break(%s,%d)\n",
2179 __FILE__,__LINE__, info->device_name, break_state);
2180
2181 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
2182 return -EINVAL;
2183
2184 spin_lock_irqsave(&info->lock,flags);
2185 if (break_state == -1)
2186 set_reg_bits(info, CHA+DAFO, BIT6);
2187 else
2188 clear_reg_bits(info, CHA+DAFO, BIT6);
2189 spin_unlock_irqrestore(&info->lock,flags);
2190 return 0;
2191 }
2192
2193 static int mgslpc_get_icount(struct tty_struct *tty,
2194 struct serial_icounter_struct *icount)
2195 {
2196 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2197 struct mgsl_icount cnow; /* kernel counter temps */
2198 unsigned long flags;
2199
2200 spin_lock_irqsave(&info->lock,flags);
2201 cnow = info->icount;
2202 spin_unlock_irqrestore(&info->lock,flags);
2203
2204 icount->cts = cnow.cts;
2205 icount->dsr = cnow.dsr;
2206 icount->rng = cnow.rng;
2207 icount->dcd = cnow.dcd;
2208 icount->rx = cnow.rx;
2209 icount->tx = cnow.tx;
2210 icount->frame = cnow.frame;
2211 icount->overrun = cnow.overrun;
2212 icount->parity = cnow.parity;
2213 icount->brk = cnow.brk;
2214 icount->buf_overrun = cnow.buf_overrun;
2215
2216 return 0;
2217 }
2218
2219 /* Service an IOCTL request
2220 *
2221 * Arguments:
2222 *
2223 * tty pointer to tty instance data
2224 * cmd IOCTL command code
2225 * arg command argument/context
2226 *
2227 * Return Value: 0 if success, otherwise error code
2228 */
2229 static int mgslpc_ioctl(struct tty_struct *tty,
2230 unsigned int cmd, unsigned long arg)
2231 {
2232 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2233 void __user *argp = (void __user *)arg;
2234
2235 if (debug_level >= DEBUG_LEVEL_INFO)
2236 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2237 info->device_name, cmd );
2238
2239 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2240 return -ENODEV;
2241
2242 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2243 (cmd != TIOCMIWAIT)) {
2244 if (tty->flags & (1 << TTY_IO_ERROR))
2245 return -EIO;
2246 }
2247
2248 switch (cmd) {
2249 case MGSL_IOCGPARAMS:
2250 return get_params(info, argp);
2251 case MGSL_IOCSPARAMS:
2252 return set_params(info, argp, tty);
2253 case MGSL_IOCGTXIDLE:
2254 return get_txidle(info, argp);
2255 case MGSL_IOCSTXIDLE:
2256 return set_txidle(info, (int)arg);
2257 case MGSL_IOCGIF:
2258 return get_interface(info, argp);
2259 case MGSL_IOCSIF:
2260 return set_interface(info,(int)arg);
2261 case MGSL_IOCTXENABLE:
2262 return set_txenable(info,(int)arg, tty);
2263 case MGSL_IOCRXENABLE:
2264 return set_rxenable(info,(int)arg);
2265 case MGSL_IOCTXABORT:
2266 return tx_abort(info);
2267 case MGSL_IOCGSTATS:
2268 return get_stats(info, argp);
2269 case MGSL_IOCWAITEVENT:
2270 return wait_events(info, argp);
2271 case TIOCMIWAIT:
2272 return modem_input_wait(info,(int)arg);
2273 default:
2274 return -ENOIOCTLCMD;
2275 }
2276 return 0;
2277 }
2278
2279 /* Set new termios settings
2280 *
2281 * Arguments:
2282 *
2283 * tty pointer to tty structure
2284 * termios pointer to buffer to hold returned old termios
2285 */
2286 static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
2287 {
2288 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2289 unsigned long flags;
2290
2291 if (debug_level >= DEBUG_LEVEL_INFO)
2292 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
2293 tty->driver->name );
2294
2295 /* just return if nothing has changed */
2296 if ((tty->termios.c_cflag == old_termios->c_cflag)
2297 && (RELEVANT_IFLAG(tty->termios.c_iflag)
2298 == RELEVANT_IFLAG(old_termios->c_iflag)))
2299 return;
2300
2301 mgslpc_change_params(info, tty);
2302
2303 /* Handle transition to B0 status */
2304 if (old_termios->c_cflag & CBAUD &&
2305 !(tty->termios.c_cflag & CBAUD)) {
2306 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2307 spin_lock_irqsave(&info->lock,flags);
2308 set_signals(info);
2309 spin_unlock_irqrestore(&info->lock,flags);
2310 }
2311
2312 /* Handle transition away from B0 status */
2313 if (!(old_termios->c_cflag & CBAUD) &&
2314 tty->termios.c_cflag & CBAUD) {
2315 info->serial_signals |= SerialSignal_DTR;
2316 if (!(tty->termios.c_cflag & CRTSCTS) ||
2317 !test_bit(TTY_THROTTLED, &tty->flags)) {
2318 info->serial_signals |= SerialSignal_RTS;
2319 }
2320 spin_lock_irqsave(&info->lock,flags);
2321 set_signals(info);
2322 spin_unlock_irqrestore(&info->lock,flags);
2323 }
2324
2325 /* Handle turning off CRTSCTS */
2326 if (old_termios->c_cflag & CRTSCTS &&
2327 !(tty->termios.c_cflag & CRTSCTS)) {
2328 tty->hw_stopped = 0;
2329 tx_release(tty);
2330 }
2331 }
2332
2333 static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2334 {
2335 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2336 struct tty_port *port = &info->port;
2337
2338 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2339 return;
2340
2341 if (debug_level >= DEBUG_LEVEL_INFO)
2342 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
2343 __FILE__,__LINE__, info->device_name, port->count);
2344
2345 WARN_ON(!port->count);
2346
2347 if (tty_port_close_start(port, tty, filp) == 0)
2348 goto cleanup;
2349
2350 if (port->flags & ASYNC_INITIALIZED)
2351 mgslpc_wait_until_sent(tty, info->timeout);
2352
2353 mgslpc_flush_buffer(tty);
2354
2355 tty_ldisc_flush(tty);
2356 shutdown(info, tty);
2357
2358 tty_port_close_end(port, tty);
2359 tty_port_tty_set(port, NULL);
2360 cleanup:
2361 if (debug_level >= DEBUG_LEVEL_INFO)
2362 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
2363 tty->driver->name, port->count);
2364 }
2365
2366 /* Wait until the transmitter is empty.
2367 */
2368 static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2369 {
2370 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2371 unsigned long orig_jiffies, char_time;
2372
2373 if (!info )
2374 return;
2375
2376 if (debug_level >= DEBUG_LEVEL_INFO)
2377 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
2378 __FILE__,__LINE__, info->device_name );
2379
2380 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2381 return;
2382
2383 if (!(info->port.flags & ASYNC_INITIALIZED))
2384 goto exit;
2385
2386 orig_jiffies = jiffies;
2387
2388 /* Set check interval to 1/5 of estimated time to
2389 * send a character, and make it at least 1. The check
2390 * interval should also be less than the timeout.
2391 * Note: use tight timings here to satisfy the NIST-PCTS.
2392 */
2393
2394 if ( info->params.data_rate ) {
2395 char_time = info->timeout/(32 * 5);
2396 if (!char_time)
2397 char_time++;
2398 } else
2399 char_time = 1;
2400
2401 if (timeout)
2402 char_time = min_t(unsigned long, char_time, timeout);
2403
2404 if (info->params.mode == MGSL_MODE_HDLC) {
2405 while (info->tx_active) {
2406 msleep_interruptible(jiffies_to_msecs(char_time));
2407 if (signal_pending(current))
2408 break;
2409 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2410 break;
2411 }
2412 } else {
2413 while ((info->tx_count || info->tx_active) &&
2414 info->tx_enabled) {
2415 msleep_interruptible(jiffies_to_msecs(char_time));
2416 if (signal_pending(current))
2417 break;
2418 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2419 break;
2420 }
2421 }
2422
2423 exit:
2424 if (debug_level >= DEBUG_LEVEL_INFO)
2425 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
2426 __FILE__,__LINE__, info->device_name );
2427 }
2428
2429 /* Called by tty_hangup() when a hangup is signaled.
2430 * This is the same as closing all open files for the port.
2431 */
2432 static void mgslpc_hangup(struct tty_struct *tty)
2433 {
2434 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2435
2436 if (debug_level >= DEBUG_LEVEL_INFO)
2437 printk("%s(%d):mgslpc_hangup(%s)\n",
2438 __FILE__,__LINE__, info->device_name );
2439
2440 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2441 return;
2442
2443 mgslpc_flush_buffer(tty);
2444 shutdown(info, tty);
2445 tty_port_hangup(&info->port);
2446 }
2447
2448 static int carrier_raised(struct tty_port *port)
2449 {
2450 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2451 unsigned long flags;
2452
2453 spin_lock_irqsave(&info->lock,flags);
2454 get_signals(info);
2455 spin_unlock_irqrestore(&info->lock,flags);
2456
2457 if (info->serial_signals & SerialSignal_DCD)
2458 return 1;
2459 return 0;
2460 }
2461
2462 static void dtr_rts(struct tty_port *port, int onoff)
2463 {
2464 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2465 unsigned long flags;
2466
2467 spin_lock_irqsave(&info->lock,flags);
2468 if (onoff)
2469 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2470 else
2471 info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
2472 set_signals(info);
2473 spin_unlock_irqrestore(&info->lock,flags);
2474 }
2475
2476
2477 static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2478 {
2479 MGSLPC_INFO *info;
2480 struct tty_port *port;
2481 int retval, line;
2482 unsigned long flags;
2483
2484 /* verify range of specified line number */
2485 line = tty->index;
2486 if (line >= mgslpc_device_count) {
2487 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
2488 __FILE__,__LINE__,line);
2489 return -ENODEV;
2490 }
2491
2492 /* find the info structure for the specified line */
2493 info = mgslpc_device_list;
2494 while(info && info->line != line)
2495 info = info->next_device;
2496 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2497 return -ENODEV;
2498
2499 port = &info->port;
2500 tty->driver_data = info;
2501 tty_port_tty_set(port, tty);
2502
2503 if (debug_level >= DEBUG_LEVEL_INFO)
2504 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
2505 __FILE__,__LINE__,tty->driver->name, port->count);
2506
2507 /* If port is closing, signal caller to try again */
2508 if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
2509 if (port->flags & ASYNC_CLOSING)
2510 interruptible_sleep_on(&port->close_wait);
2511 retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
2512 -EAGAIN : -ERESTARTSYS);
2513 goto cleanup;
2514 }
2515
2516 tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
2517
2518 spin_lock_irqsave(&info->netlock, flags);
2519 if (info->netcount) {
2520 retval = -EBUSY;
2521 spin_unlock_irqrestore(&info->netlock, flags);
2522 goto cleanup;
2523 }
2524 spin_lock(&port->lock);
2525 port->count++;
2526 spin_unlock(&port->lock);
2527 spin_unlock_irqrestore(&info->netlock, flags);
2528
2529 if (port->count == 1) {
2530 /* 1st open on this device, init hardware */
2531 retval = startup(info, tty);
2532 if (retval < 0)
2533 goto cleanup;
2534 }
2535
2536 retval = tty_port_block_til_ready(&info->port, tty, filp);
2537 if (retval) {
2538 if (debug_level >= DEBUG_LEVEL_INFO)
2539 printk("%s(%d):block_til_ready(%s) returned %d\n",
2540 __FILE__,__LINE__, info->device_name, retval);
2541 goto cleanup;
2542 }
2543
2544 if (debug_level >= DEBUG_LEVEL_INFO)
2545 printk("%s(%d):mgslpc_open(%s) success\n",
2546 __FILE__,__LINE__, info->device_name);
2547 retval = 0;
2548
2549 cleanup:
2550 return retval;
2551 }
2552
2553 /*
2554 * /proc fs routines....
2555 */
2556
2557 static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
2558 {
2559 char stat_buf[30];
2560 unsigned long flags;
2561
2562 seq_printf(m, "%s:io:%04X irq:%d",
2563 info->device_name, info->io_base, info->irq_level);
2564
2565 /* output current serial signal states */
2566 spin_lock_irqsave(&info->lock,flags);
2567 get_signals(info);
2568 spin_unlock_irqrestore(&info->lock,flags);
2569
2570 stat_buf[0] = 0;
2571 stat_buf[1] = 0;
2572 if (info->serial_signals & SerialSignal_RTS)
2573 strcat(stat_buf, "|RTS");
2574 if (info->serial_signals & SerialSignal_CTS)
2575 strcat(stat_buf, "|CTS");
2576 if (info->serial_signals & SerialSignal_DTR)
2577 strcat(stat_buf, "|DTR");
2578 if (info->serial_signals & SerialSignal_DSR)
2579 strcat(stat_buf, "|DSR");
2580 if (info->serial_signals & SerialSignal_DCD)
2581 strcat(stat_buf, "|CD");
2582 if (info->serial_signals & SerialSignal_RI)
2583 strcat(stat_buf, "|RI");
2584
2585 if (info->params.mode == MGSL_MODE_HDLC) {
2586 seq_printf(m, " HDLC txok:%d rxok:%d",
2587 info->icount.txok, info->icount.rxok);
2588 if (info->icount.txunder)
2589 seq_printf(m, " txunder:%d", info->icount.txunder);
2590 if (info->icount.txabort)
2591 seq_printf(m, " txabort:%d", info->icount.txabort);
2592 if (info->icount.rxshort)
2593 seq_printf(m, " rxshort:%d", info->icount.rxshort);
2594 if (info->icount.rxlong)
2595 seq_printf(m, " rxlong:%d", info->icount.rxlong);
2596 if (info->icount.rxover)
2597 seq_printf(m, " rxover:%d", info->icount.rxover);
2598 if (info->icount.rxcrc)
2599 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
2600 } else {
2601 seq_printf(m, " ASYNC tx:%d rx:%d",
2602 info->icount.tx, info->icount.rx);
2603 if (info->icount.frame)
2604 seq_printf(m, " fe:%d", info->icount.frame);
2605 if (info->icount.parity)
2606 seq_printf(m, " pe:%d", info->icount.parity);
2607 if (info->icount.brk)
2608 seq_printf(m, " brk:%d", info->icount.brk);
2609 if (info->icount.overrun)
2610 seq_printf(m, " oe:%d", info->icount.overrun);
2611 }
2612
2613 /* Append serial signal status to end */
2614 seq_printf(m, " %s\n", stat_buf+1);
2615
2616 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
2617 info->tx_active,info->bh_requested,info->bh_running,
2618 info->pending_bh);
2619 }
2620
2621 /* Called to print information about devices
2622 */
2623 static int mgslpc_proc_show(struct seq_file *m, void *v)
2624 {
2625 MGSLPC_INFO *info;
2626
2627 seq_printf(m, "synclink driver:%s\n", driver_version);
2628
2629 info = mgslpc_device_list;
2630 while( info ) {
2631 line_info(m, info);
2632 info = info->next_device;
2633 }
2634 return 0;
2635 }
2636
2637 static int mgslpc_proc_open(struct inode *inode, struct file *file)
2638 {
2639 return single_open(file, mgslpc_proc_show, NULL);
2640 }
2641
2642 static const struct file_operations mgslpc_proc_fops = {
2643 .owner = THIS_MODULE,
2644 .open = mgslpc_proc_open,
2645 .read = seq_read,
2646 .llseek = seq_lseek,
2647 .release = single_release,
2648 };
2649
2650 static int rx_alloc_buffers(MGSLPC_INFO *info)
2651 {
2652 /* each buffer has header and data */
2653 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2654
2655 /* calculate total allocation size for 8 buffers */
2656 info->rx_buf_total_size = info->rx_buf_size * 8;
2657
2658 /* limit total allocated memory */
2659 if (info->rx_buf_total_size > 0x10000)
2660 info->rx_buf_total_size = 0x10000;
2661
2662 /* calculate number of buffers */
2663 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2664
2665 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2666 if (info->rx_buf == NULL)
2667 return -ENOMEM;
2668
2669 rx_reset_buffers(info);
2670 return 0;
2671 }
2672
2673 static void rx_free_buffers(MGSLPC_INFO *info)
2674 {
2675 kfree(info->rx_buf);
2676 info->rx_buf = NULL;
2677 }
2678
2679 static int claim_resources(MGSLPC_INFO *info)
2680 {
2681 if (rx_alloc_buffers(info) < 0 ) {
2682 printk( "Can't allocate rx buffer %s\n", info->device_name);
2683 release_resources(info);
2684 return -ENODEV;
2685 }
2686 return 0;
2687 }
2688
2689 static void release_resources(MGSLPC_INFO *info)
2690 {
2691 if (debug_level >= DEBUG_LEVEL_INFO)
2692 printk("release_resources(%s)\n", info->device_name);
2693 rx_free_buffers(info);
2694 }
2695
2696 /* Add the specified device instance data structure to the
2697 * global linked list of devices and increment the device count.
2698 *
2699 * Arguments: info pointer to device instance data
2700 */
2701 static void mgslpc_add_device(MGSLPC_INFO *info)
2702 {
2703 info->next_device = NULL;
2704 info->line = mgslpc_device_count;
2705 sprintf(info->device_name,"ttySLP%d",info->line);
2706
2707 if (info->line < MAX_DEVICE_COUNT) {
2708 if (maxframe[info->line])
2709 info->max_frame_size = maxframe[info->line];
2710 }
2711
2712 mgslpc_device_count++;
2713
2714 if (!mgslpc_device_list)
2715 mgslpc_device_list = info;
2716 else {
2717 MGSLPC_INFO *current_dev = mgslpc_device_list;
2718 while( current_dev->next_device )
2719 current_dev = current_dev->next_device;
2720 current_dev->next_device = info;
2721 }
2722
2723 if (info->max_frame_size < 4096)
2724 info->max_frame_size = 4096;
2725 else if (info->max_frame_size > 65535)
2726 info->max_frame_size = 65535;
2727
2728 printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
2729 info->device_name, info->io_base, info->irq_level);
2730
2731 #if SYNCLINK_GENERIC_HDLC
2732 hdlcdev_init(info);
2733 #endif
2734 }
2735
2736 static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
2737 {
2738 MGSLPC_INFO *info = mgslpc_device_list;
2739 MGSLPC_INFO *last = NULL;
2740
2741 while(info) {
2742 if (info == remove_info) {
2743 if (last)
2744 last->next_device = info->next_device;
2745 else
2746 mgslpc_device_list = info->next_device;
2747 #if SYNCLINK_GENERIC_HDLC
2748 hdlcdev_exit(info);
2749 #endif
2750 release_resources(info);
2751 kfree(info);
2752 mgslpc_device_count--;
2753 return;
2754 }
2755 last = info;
2756 info = info->next_device;
2757 }
2758 }
2759
2760 static const struct pcmcia_device_id mgslpc_ids[] = {
2761 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
2762 PCMCIA_DEVICE_NULL
2763 };
2764 MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
2765
2766 static struct pcmcia_driver mgslpc_driver = {
2767 .owner = THIS_MODULE,
2768 .name = "synclink_cs",
2769 .probe = mgslpc_probe,
2770 .remove = mgslpc_detach,
2771 .id_table = mgslpc_ids,
2772 .suspend = mgslpc_suspend,
2773 .resume = mgslpc_resume,
2774 };
2775
2776 static const struct tty_operations mgslpc_ops = {
2777 .open = mgslpc_open,
2778 .close = mgslpc_close,
2779 .write = mgslpc_write,
2780 .put_char = mgslpc_put_char,
2781 .flush_chars = mgslpc_flush_chars,
2782 .write_room = mgslpc_write_room,
2783 .chars_in_buffer = mgslpc_chars_in_buffer,
2784 .flush_buffer = mgslpc_flush_buffer,
2785 .ioctl = mgslpc_ioctl,
2786 .throttle = mgslpc_throttle,
2787 .unthrottle = mgslpc_unthrottle,
2788 .send_xchar = mgslpc_send_xchar,
2789 .break_ctl = mgslpc_break,
2790 .wait_until_sent = mgslpc_wait_until_sent,
2791 .set_termios = mgslpc_set_termios,
2792 .stop = tx_pause,
2793 .start = tx_release,
2794 .hangup = mgslpc_hangup,
2795 .tiocmget = tiocmget,
2796 .tiocmset = tiocmset,
2797 .get_icount = mgslpc_get_icount,
2798 .proc_fops = &mgslpc_proc_fops,
2799 };
2800
2801 static int __init synclink_cs_init(void)
2802 {
2803 int rc;
2804
2805 if (break_on_load) {
2806 mgslpc_get_text_ptr();
2807 BREAKPOINT();
2808 }
2809
2810 if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
2811 return rc;
2812
2813 serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
2814 if (!serial_driver) {
2815 rc = -ENOMEM;
2816 goto err_pcmcia_drv;
2817 }
2818
2819 /* Initialize the tty_driver structure */
2820
2821 serial_driver->driver_name = "synclink_cs";
2822 serial_driver->name = "ttySLP";
2823 serial_driver->major = ttymajor;
2824 serial_driver->minor_start = 64;
2825 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2826 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2827 serial_driver->init_termios = tty_std_termios;
2828 serial_driver->init_termios.c_cflag =
2829 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2830 serial_driver->flags = TTY_DRIVER_REAL_RAW;
2831 tty_set_operations(serial_driver, &mgslpc_ops);
2832
2833 if ((rc = tty_register_driver(serial_driver)) < 0) {
2834 printk("%s(%d):Couldn't register serial driver\n",
2835 __FILE__,__LINE__);
2836 goto err_put_tty;
2837 }
2838
2839 printk("%s %s, tty major#%d\n",
2840 driver_name, driver_version,
2841 serial_driver->major);
2842
2843 return 0;
2844 err_put_tty:
2845 put_tty_driver(serial_driver);
2846 err_pcmcia_drv:
2847 pcmcia_unregister_driver(&mgslpc_driver);
2848 return rc;
2849 }
2850
2851 static void __exit synclink_cs_exit(void)
2852 {
2853 while (mgslpc_device_list)
2854 mgslpc_remove_device(mgslpc_device_list);
2855
2856 tty_unregister_driver(serial_driver);
2857 put_tty_driver(serial_driver);
2858 pcmcia_unregister_driver(&mgslpc_driver);
2859 }
2860
2861 module_init(synclink_cs_init);
2862 module_exit(synclink_cs_exit);
2863
2864 static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2865 {
2866 unsigned int M, N;
2867 unsigned char val;
2868
2869 /* note:standard BRG mode is broken in V3.2 chip
2870 * so enhanced mode is always used
2871 */
2872
2873 if (rate) {
2874 N = 3686400 / rate;
2875 if (!N)
2876 N = 1;
2877 N >>= 1;
2878 for (M = 1; N > 64 && M < 16; M++)
2879 N >>= 1;
2880 N--;
2881
2882 /* BGR[5..0] = N
2883 * BGR[9..6] = M
2884 * BGR[7..0] contained in BGR register
2885 * BGR[9..8] contained in CCR2[7..6]
2886 * divisor = (N+1)*2^M
2887 *
2888 * Note: M *must* not be zero (causes asymetric duty cycle)
2889 */
2890 write_reg(info, (unsigned char) (channel + BGR),
2891 (unsigned char) ((M << 6) + N));
2892 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2893 val |= ((M << 4) & 0xc0);
2894 write_reg(info, (unsigned char) (channel + CCR2), val);
2895 }
2896 }
2897
2898 /* Enabled the AUX clock output at the specified frequency.
2899 */
2900 static void enable_auxclk(MGSLPC_INFO *info)
2901 {
2902 unsigned char val;
2903
2904 /* MODE
2905 *
2906 * 07..06 MDS[1..0] 10 = transparent HDLC mode
2907 * 05 ADM Address Mode, 0 = no addr recognition
2908 * 04 TMD Timer Mode, 0 = external
2909 * 03 RAC Receiver Active, 0 = inactive
2910 * 02 RTS 0=RTS active during xmit, 1=RTS always active
2911 * 01 TRS Timer Resolution, 1=512
2912 * 00 TLP Test Loop, 0 = no loop
2913 *
2914 * 1000 0010
2915 */
2916 val = 0x82;
2917
2918 /* channel B RTS is used to enable AUXCLK driver on SP505 */
2919 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2920 val |= BIT2;
2921 write_reg(info, CHB + MODE, val);
2922
2923 /* CCR0
2924 *
2925 * 07 PU Power Up, 1=active, 0=power down
2926 * 06 MCE Master Clock Enable, 1=enabled
2927 * 05 Reserved, 0
2928 * 04..02 SC[2..0] Encoding
2929 * 01..00 SM[1..0] Serial Mode, 00=HDLC
2930 *
2931 * 11000000
2932 */
2933 write_reg(info, CHB + CCR0, 0xc0);
2934
2935 /* CCR1
2936 *
2937 * 07 SFLG Shared Flag, 0 = disable shared flags
2938 * 06 GALP Go Active On Loop, 0 = not used
2939 * 05 GLP Go On Loop, 0 = not used
2940 * 04 ODS Output Driver Select, 1=TxD is push-pull output
2941 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
2942 * 02..00 CM[2..0] Clock Mode
2943 *
2944 * 0001 0111
2945 */
2946 write_reg(info, CHB + CCR1, 0x17);
2947
2948 /* CCR2 (Channel B)
2949 *
2950 * 07..06 BGR[9..8] Baud rate bits 9..8
2951 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
2952 * 04 SSEL Clock source select, 1=submode b
2953 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
2954 * 02 RWX Read/Write Exchange 0=disabled
2955 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
2956 * 00 DIV, data inversion 0=disabled, 1=enabled
2957 *
2958 * 0011 1000
2959 */
2960 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2961 write_reg(info, CHB + CCR2, 0x38);
2962 else
2963 write_reg(info, CHB + CCR2, 0x30);
2964
2965 /* CCR4
2966 *
2967 * 07 MCK4 Master Clock Divide by 4, 1=enabled
2968 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
2969 * 05 TST1 Test Pin, 0=normal operation
2970 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
2971 * 03..02 Reserved, must be 0
2972 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
2973 *
2974 * 0101 0000
2975 */
2976 write_reg(info, CHB + CCR4, 0x50);
2977
2978 /* if auxclk not enabled, set internal BRG so
2979 * CTS transitions can be detected (requires TxC)
2980 */
2981 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2982 mgslpc_set_rate(info, CHB, info->params.clock_speed);
2983 else
2984 mgslpc_set_rate(info, CHB, 921600);
2985 }
2986
2987 static void loopback_enable(MGSLPC_INFO *info)
2988 {
2989 unsigned char val;
2990
2991 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
2992 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
2993 write_reg(info, CHA + CCR1, val);
2994
2995 /* CCR2:04 SSEL Clock source select, 1=submode b */
2996 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
2997 write_reg(info, CHA + CCR2, val);
2998
2999 /* set LinkSpeed if available, otherwise default to 2Mbps */
3000 if (info->params.clock_speed)
3001 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3002 else
3003 mgslpc_set_rate(info, CHA, 1843200);
3004
3005 /* MODE:00 TLP Test Loop, 1=loopback enabled */
3006 val = read_reg(info, CHA + MODE) | BIT0;
3007 write_reg(info, CHA + MODE, val);
3008 }
3009
3010 static void hdlc_mode(MGSLPC_INFO *info)
3011 {
3012 unsigned char val;
3013 unsigned char clkmode, clksubmode;
3014
3015 /* disable all interrupts */
3016 irq_disable(info, CHA, 0xffff);
3017 irq_disable(info, CHB, 0xffff);
3018 port_irq_disable(info, 0xff);
3019
3020 /* assume clock mode 0a, rcv=RxC xmt=TxC */
3021 clkmode = clksubmode = 0;
3022 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3023 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
3024 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
3025 clkmode = 7;
3026 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3027 && info->params.flags & HDLC_FLAG_TXC_BRG) {
3028 /* clock mode 7b, rcv = BRG, xmt = BRG */
3029 clkmode = 7;
3030 clksubmode = 1;
3031 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3032 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
3033 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
3034 clkmode = 6;
3035 clksubmode = 1;
3036 } else {
3037 /* clock mode 6a, rcv = DPLL, xmt = TxC */
3038 clkmode = 6;
3039 }
3040 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
3041 /* clock mode 0b, rcv = RxC, xmt = BRG */
3042 clksubmode = 1;
3043 }
3044
3045 /* MODE
3046 *
3047 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3048 * 05 ADM Address Mode, 0 = no addr recognition
3049 * 04 TMD Timer Mode, 0 = external
3050 * 03 RAC Receiver Active, 0 = inactive
3051 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3052 * 01 TRS Timer Resolution, 1=512
3053 * 00 TLP Test Loop, 0 = no loop
3054 *
3055 * 1000 0010
3056 */
3057 val = 0x82;
3058 if (info->params.loopback)
3059 val |= BIT0;
3060
3061 /* preserve RTS state */
3062 if (info->serial_signals & SerialSignal_RTS)
3063 val |= BIT2;
3064 write_reg(info, CHA + MODE, val);
3065
3066 /* CCR0
3067 *
3068 * 07 PU Power Up, 1=active, 0=power down
3069 * 06 MCE Master Clock Enable, 1=enabled
3070 * 05 Reserved, 0
3071 * 04..02 SC[2..0] Encoding
3072 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3073 *
3074 * 11000000
3075 */
3076 val = 0xc0;
3077 switch (info->params.encoding)
3078 {
3079 case HDLC_ENCODING_NRZI:
3080 val |= BIT3;
3081 break;
3082 case HDLC_ENCODING_BIPHASE_SPACE:
3083 val |= BIT4;
3084 break; // FM0
3085 case HDLC_ENCODING_BIPHASE_MARK:
3086 val |= BIT4 + BIT2;
3087 break; // FM1
3088 case HDLC_ENCODING_BIPHASE_LEVEL:
3089 val |= BIT4 + BIT3;
3090 break; // Manchester
3091 }
3092 write_reg(info, CHA + CCR0, val);
3093
3094 /* CCR1
3095 *
3096 * 07 SFLG Shared Flag, 0 = disable shared flags
3097 * 06 GALP Go Active On Loop, 0 = not used
3098 * 05 GLP Go On Loop, 0 = not used
3099 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3100 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3101 * 02..00 CM[2..0] Clock Mode
3102 *
3103 * 0001 0000
3104 */
3105 val = 0x10 + clkmode;
3106 write_reg(info, CHA + CCR1, val);
3107
3108 /* CCR2
3109 *
3110 * 07..06 BGR[9..8] Baud rate bits 9..8
3111 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3112 * 04 SSEL Clock source select, 1=submode b
3113 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3114 * 02 RWX Read/Write Exchange 0=disabled
3115 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3116 * 00 DIV, data inversion 0=disabled, 1=enabled
3117 *
3118 * 0000 0000
3119 */
3120 val = 0x00;
3121 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3122 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3123 val |= BIT5;
3124 if (clksubmode)
3125 val |= BIT4;
3126 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3127 val |= BIT1;
3128 if (info->params.encoding == HDLC_ENCODING_NRZB)
3129 val |= BIT0;
3130 write_reg(info, CHA + CCR2, val);
3131
3132 /* CCR3
3133 *
3134 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3135 * 05 EPT Enable preamble transmission, 1=enabled
3136 * 04 RADD Receive address pushed to FIFO, 0=disabled
3137 * 03 CRL CRC Reset Level, 0=FFFF
3138 * 02 RCRC Rx CRC 0=On 1=Off
3139 * 01 TCRC Tx CRC 0=On 1=Off
3140 * 00 PSD DPLL Phase Shift Disable
3141 *
3142 * 0000 0000
3143 */
3144 val = 0x00;
3145 if (info->params.crc_type == HDLC_CRC_NONE)
3146 val |= BIT2 + BIT1;
3147 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3148 val |= BIT5;
3149 switch (info->params.preamble_length)
3150 {
3151 case HDLC_PREAMBLE_LENGTH_16BITS:
3152 val |= BIT6;
3153 break;
3154 case HDLC_PREAMBLE_LENGTH_32BITS:
3155 val |= BIT6;
3156 break;
3157 case HDLC_PREAMBLE_LENGTH_64BITS:
3158 val |= BIT7 + BIT6;
3159 break;
3160 }
3161 write_reg(info, CHA + CCR3, val);
3162
3163 /* PRE - Preamble pattern */
3164 val = 0;
3165 switch (info->params.preamble)
3166 {
3167 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3168 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3169 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3170 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3171 }
3172 write_reg(info, CHA + PRE, val);
3173
3174 /* CCR4
3175 *
3176 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3177 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3178 * 05 TST1 Test Pin, 0=normal operation
3179 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3180 * 03..02 Reserved, must be 0
3181 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3182 *
3183 * 0101 0000
3184 */
3185 val = 0x50;
3186 write_reg(info, CHA + CCR4, val);
3187 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3188 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3189 else
3190 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3191
3192 /* RLCR Receive length check register
3193 *
3194 * 7 1=enable receive length check
3195 * 6..0 Max frame length = (RL + 1) * 32
3196 */
3197 write_reg(info, CHA + RLCR, 0);
3198
3199 /* XBCH Transmit Byte Count High
3200 *
3201 * 07 DMA mode, 0 = interrupt driven
3202 * 06 NRM, 0=ABM (ignored)
3203 * 05 CAS Carrier Auto Start
3204 * 04 XC Transmit Continuously (ignored)
3205 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3206 *
3207 * 0000 0000
3208 */
3209 val = 0x00;
3210 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3211 val |= BIT5;
3212 write_reg(info, CHA + XBCH, val);
3213 enable_auxclk(info);
3214 if (info->params.loopback || info->testing_irq)
3215 loopback_enable(info);
3216 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3217 {
3218 irq_enable(info, CHB, IRQ_CTS);
3219 /* PVR[3] 1=AUTO CTS active */
3220 set_reg_bits(info, CHA + PVR, BIT3);
3221 } else
3222 clear_reg_bits(info, CHA + PVR, BIT3);
3223
3224 irq_enable(info, CHA,
3225 IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
3226 IRQ_UNDERRUN + IRQ_TXFIFO);
3227 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3228 wait_command_complete(info, CHA);
3229 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3230
3231 /* Master clock mode enabled above to allow reset commands
3232 * to complete even if no data clocks are present.
3233 *
3234 * Disable master clock mode for normal communications because
3235 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3236 * IRQ when in master clock mode.
3237 *
3238 * Leave master clock mode enabled for IRQ test because the
3239 * timer IRQ used by the test can only happen in master clock mode.
3240 */
3241 if (!info->testing_irq)
3242 clear_reg_bits(info, CHA + CCR0, BIT6);
3243
3244 tx_set_idle(info);
3245
3246 tx_stop(info);
3247 rx_stop(info);
3248 }
3249
3250 static void rx_stop(MGSLPC_INFO *info)
3251 {
3252 if (debug_level >= DEBUG_LEVEL_ISR)
3253 printk("%s(%d):rx_stop(%s)\n",
3254 __FILE__,__LINE__, info->device_name );
3255
3256 /* MODE:03 RAC Receiver Active, 0=inactive */
3257 clear_reg_bits(info, CHA + MODE, BIT3);
3258
3259 info->rx_enabled = false;
3260 info->rx_overflow = false;
3261 }
3262
3263 static void rx_start(MGSLPC_INFO *info)
3264 {
3265 if (debug_level >= DEBUG_LEVEL_ISR)
3266 printk("%s(%d):rx_start(%s)\n",
3267 __FILE__,__LINE__, info->device_name );
3268
3269 rx_reset_buffers(info);
3270 info->rx_enabled = false;
3271 info->rx_overflow = false;
3272
3273 /* MODE:03 RAC Receiver Active, 1=active */
3274 set_reg_bits(info, CHA + MODE, BIT3);
3275
3276 info->rx_enabled = true;
3277 }
3278
3279 static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
3280 {
3281 if (debug_level >= DEBUG_LEVEL_ISR)
3282 printk("%s(%d):tx_start(%s)\n",
3283 __FILE__,__LINE__, info->device_name );
3284
3285 if (info->tx_count) {
3286 /* If auto RTS enabled and RTS is inactive, then assert */
3287 /* RTS and set a flag indicating that the driver should */
3288 /* negate RTS when the transmission completes. */
3289 info->drop_rts_on_tx_done = false;
3290
3291 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3292 get_signals(info);
3293 if (!(info->serial_signals & SerialSignal_RTS)) {
3294 info->serial_signals |= SerialSignal_RTS;
3295 set_signals(info);
3296 info->drop_rts_on_tx_done = true;
3297 }
3298 }
3299
3300 if (info->params.mode == MGSL_MODE_ASYNC) {
3301 if (!info->tx_active) {
3302 info->tx_active = true;
3303 tx_ready(info, tty);
3304 }
3305 } else {
3306 info->tx_active = true;
3307 tx_ready(info, tty);
3308 mod_timer(&info->tx_timer, jiffies +
3309 msecs_to_jiffies(5000));
3310 }
3311 }
3312
3313 if (!info->tx_enabled)
3314 info->tx_enabled = true;
3315 }
3316
3317 static void tx_stop(MGSLPC_INFO *info)
3318 {
3319 if (debug_level >= DEBUG_LEVEL_ISR)
3320 printk("%s(%d):tx_stop(%s)\n",
3321 __FILE__,__LINE__, info->device_name );
3322
3323 del_timer(&info->tx_timer);
3324
3325 info->tx_enabled = false;
3326 info->tx_active = false;
3327 }
3328
3329 /* Reset the adapter to a known state and prepare it for further use.
3330 */
3331 static void reset_device(MGSLPC_INFO *info)
3332 {
3333 /* power up both channels (set BIT7) */
3334 write_reg(info, CHA + CCR0, 0x80);
3335 write_reg(info, CHB + CCR0, 0x80);
3336 write_reg(info, CHA + MODE, 0);
3337 write_reg(info, CHB + MODE, 0);
3338
3339 /* disable all interrupts */
3340 irq_disable(info, CHA, 0xffff);
3341 irq_disable(info, CHB, 0xffff);
3342 port_irq_disable(info, 0xff);
3343
3344 /* PCR Port Configuration Register
3345 *
3346 * 07..04 DEC[3..0] Serial I/F select outputs
3347 * 03 output, 1=AUTO CTS control enabled
3348 * 02 RI Ring Indicator input 0=active
3349 * 01 DSR input 0=active
3350 * 00 DTR output 0=active
3351 *
3352 * 0000 0110
3353 */
3354 write_reg(info, PCR, 0x06);
3355
3356 /* PVR Port Value Register
3357 *
3358 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3359 * 03 AUTO CTS output 1=enabled
3360 * 02 RI Ring Indicator input
3361 * 01 DSR input
3362 * 00 DTR output (1=inactive)
3363 *
3364 * 0000 0001
3365 */
3366 // write_reg(info, PVR, PVR_DTR);
3367
3368 /* IPC Interrupt Port Configuration
3369 *
3370 * 07 VIS 1=Masked interrupts visible
3371 * 06..05 Reserved, 0
3372 * 04..03 SLA Slave address, 00 ignored
3373 * 02 CASM Cascading Mode, 1=daisy chain
3374 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3375 *
3376 * 0000 0101
3377 */
3378 write_reg(info, IPC, 0x05);
3379 }
3380
3381 static void async_mode(MGSLPC_INFO *info)
3382 {
3383 unsigned char val;
3384
3385 /* disable all interrupts */
3386 irq_disable(info, CHA, 0xffff);
3387 irq_disable(info, CHB, 0xffff);
3388 port_irq_disable(info, 0xff);
3389
3390 /* MODE
3391 *
3392 * 07 Reserved, 0
3393 * 06 FRTS RTS State, 0=active
3394 * 05 FCTS Flow Control on CTS
3395 * 04 FLON Flow Control Enable
3396 * 03 RAC Receiver Active, 0 = inactive
3397 * 02 RTS 0=Auto RTS, 1=manual RTS
3398 * 01 TRS Timer Resolution, 1=512
3399 * 00 TLP Test Loop, 0 = no loop
3400 *
3401 * 0000 0110
3402 */
3403 val = 0x06;
3404 if (info->params.loopback)
3405 val |= BIT0;
3406
3407 /* preserve RTS state */
3408 if (!(info->serial_signals & SerialSignal_RTS))
3409 val |= BIT6;
3410 write_reg(info, CHA + MODE, val);
3411
3412 /* CCR0
3413 *
3414 * 07 PU Power Up, 1=active, 0=power down
3415 * 06 MCE Master Clock Enable, 1=enabled
3416 * 05 Reserved, 0
3417 * 04..02 SC[2..0] Encoding, 000=NRZ
3418 * 01..00 SM[1..0] Serial Mode, 11=Async
3419 *
3420 * 1000 0011
3421 */
3422 write_reg(info, CHA + CCR0, 0x83);
3423
3424 /* CCR1
3425 *
3426 * 07..05 Reserved, 0
3427 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3428 * 03 BCR Bit Clock Rate, 1=16x
3429 * 02..00 CM[2..0] Clock Mode, 111=BRG
3430 *
3431 * 0001 1111
3432 */
3433 write_reg(info, CHA + CCR1, 0x1f);
3434
3435 /* CCR2 (channel A)
3436 *
3437 * 07..06 BGR[9..8] Baud rate bits 9..8
3438 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3439 * 04 SSEL Clock source select, 1=submode b
3440 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3441 * 02 RWX Read/Write Exchange 0=disabled
3442 * 01 Reserved, 0
3443 * 00 DIV, data inversion 0=disabled, 1=enabled
3444 *
3445 * 0001 0000
3446 */
3447 write_reg(info, CHA + CCR2, 0x10);
3448
3449 /* CCR3
3450 *
3451 * 07..01 Reserved, 0
3452 * 00 PSD DPLL Phase Shift Disable
3453 *
3454 * 0000 0000
3455 */
3456 write_reg(info, CHA + CCR3, 0);
3457
3458 /* CCR4
3459 *
3460 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3461 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3462 * 05 TST1 Test Pin, 0=normal operation
3463 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3464 * 03..00 Reserved, must be 0
3465 *
3466 * 0101 0000
3467 */
3468 write_reg(info, CHA + CCR4, 0x50);
3469 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
3470
3471 /* DAFO Data Format
3472 *
3473 * 07 Reserved, 0
3474 * 06 XBRK transmit break, 0=normal operation
3475 * 05 Stop bits (0=1, 1=2)
3476 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3477 * 02 PAREN Parity Enable
3478 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3479 *
3480 */
3481 val = 0x00;
3482 if (info->params.data_bits != 8)
3483 val |= BIT0; /* 7 bits */
3484 if (info->params.stop_bits != 1)
3485 val |= BIT5;
3486 if (info->params.parity != ASYNC_PARITY_NONE)
3487 {
3488 val |= BIT2; /* Parity enable */
3489 if (info->params.parity == ASYNC_PARITY_ODD)
3490 val |= BIT3;
3491 else
3492 val |= BIT4;
3493 }
3494 write_reg(info, CHA + DAFO, val);
3495
3496 /* RFC Rx FIFO Control
3497 *
3498 * 07 Reserved, 0
3499 * 06 DPS, 1=parity bit not stored in data byte
3500 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3501 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3502 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3503 * 01 Reserved, 0
3504 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3505 *
3506 * 0101 1100
3507 */
3508 write_reg(info, CHA + RFC, 0x5c);
3509
3510 /* RLCR Receive length check register
3511 *
3512 * Max frame length = (RL + 1) * 32
3513 */
3514 write_reg(info, CHA + RLCR, 0);
3515
3516 /* XBCH Transmit Byte Count High
3517 *
3518 * 07 DMA mode, 0 = interrupt driven
3519 * 06 NRM, 0=ABM (ignored)
3520 * 05 CAS Carrier Auto Start
3521 * 04 XC Transmit Continuously (ignored)
3522 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3523 *
3524 * 0000 0000
3525 */
3526 val = 0x00;
3527 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3528 val |= BIT5;
3529 write_reg(info, CHA + XBCH, val);
3530 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3531 irq_enable(info, CHA, IRQ_CTS);
3532
3533 /* MODE:03 RAC Receiver Active, 1=active */
3534 set_reg_bits(info, CHA + MODE, BIT3);
3535 enable_auxclk(info);
3536 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3537 irq_enable(info, CHB, IRQ_CTS);
3538 /* PVR[3] 1=AUTO CTS active */
3539 set_reg_bits(info, CHA + PVR, BIT3);
3540 } else
3541 clear_reg_bits(info, CHA + PVR, BIT3);
3542 irq_enable(info, CHA,
3543 IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
3544 IRQ_ALLSENT + IRQ_TXFIFO);
3545 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3546 wait_command_complete(info, CHA);
3547 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3548 }
3549
3550 /* Set the HDLC idle mode for the transmitter.
3551 */
3552 static void tx_set_idle(MGSLPC_INFO *info)
3553 {
3554 /* Note: ESCC2 only supports flags and one idle modes */
3555 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3556 set_reg_bits(info, CHA + CCR1, BIT3);
3557 else
3558 clear_reg_bits(info, CHA + CCR1, BIT3);
3559 }
3560
3561 /* get state of the V24 status (input) signals.
3562 */
3563 static void get_signals(MGSLPC_INFO *info)
3564 {
3565 unsigned char status = 0;
3566
3567 /* preserve DTR and RTS */
3568 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
3569
3570 if (read_reg(info, CHB + VSTR) & BIT7)
3571 info->serial_signals |= SerialSignal_DCD;
3572 if (read_reg(info, CHB + STAR) & BIT1)
3573 info->serial_signals |= SerialSignal_CTS;
3574
3575 status = read_reg(info, CHA + PVR);
3576 if (!(status & PVR_RI))
3577 info->serial_signals |= SerialSignal_RI;
3578 if (!(status & PVR_DSR))
3579 info->serial_signals |= SerialSignal_DSR;
3580 }
3581
3582 /* Set the state of DTR and RTS based on contents of
3583 * serial_signals member of device extension.
3584 */
3585 static void set_signals(MGSLPC_INFO *info)
3586 {
3587 unsigned char val;
3588
3589 val = read_reg(info, CHA + MODE);
3590 if (info->params.mode == MGSL_MODE_ASYNC) {
3591 if (info->serial_signals & SerialSignal_RTS)
3592 val &= ~BIT6;
3593 else
3594 val |= BIT6;
3595 } else {
3596 if (info->serial_signals & SerialSignal_RTS)
3597 val |= BIT2;
3598 else
3599 val &= ~BIT2;
3600 }
3601 write_reg(info, CHA + MODE, val);
3602
3603 if (info->serial_signals & SerialSignal_DTR)
3604 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3605 else
3606 set_reg_bits(info, CHA + PVR, PVR_DTR);
3607 }
3608
3609 static void rx_reset_buffers(MGSLPC_INFO *info)
3610 {
3611 RXBUF *buf;
3612 int i;
3613
3614 info->rx_put = 0;
3615 info->rx_get = 0;
3616 info->rx_frame_count = 0;
3617 for (i=0 ; i < info->rx_buf_count ; i++) {
3618 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3619 buf->status = buf->count = 0;
3620 }
3621 }
3622
3623 /* Attempt to return a received HDLC frame
3624 * Only frames received without errors are returned.
3625 *
3626 * Returns true if frame returned, otherwise false
3627 */
3628 static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
3629 {
3630 unsigned short status;
3631 RXBUF *buf;
3632 unsigned int framesize = 0;
3633 unsigned long flags;
3634 bool return_frame = false;
3635
3636 if (info->rx_frame_count == 0)
3637 return false;
3638
3639 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3640
3641 status = buf->status;
3642
3643 /* 07 VFR 1=valid frame
3644 * 06 RDO 1=data overrun
3645 * 05 CRC 1=OK, 0=error
3646 * 04 RAB 1=frame aborted
3647 */
3648 if ((status & 0xf0) != 0xA0) {
3649 if (!(status & BIT7) || (status & BIT4))
3650 info->icount.rxabort++;
3651 else if (status & BIT6)
3652 info->icount.rxover++;
3653 else if (!(status & BIT5)) {
3654 info->icount.rxcrc++;
3655 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
3656 return_frame = true;
3657 }
3658 framesize = 0;
3659 #if SYNCLINK_GENERIC_HDLC
3660 {
3661 info->netdev->stats.rx_errors++;
3662 info->netdev->stats.rx_frame_errors++;
3663 }
3664 #endif
3665 } else
3666 return_frame = true;
3667
3668 if (return_frame)
3669 framesize = buf->count;
3670
3671 if (debug_level >= DEBUG_LEVEL_BH)
3672 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
3673 __FILE__,__LINE__,info->device_name,status,framesize);
3674
3675 if (debug_level >= DEBUG_LEVEL_DATA)
3676 trace_block(info, buf->data, framesize, 0);
3677
3678 if (framesize) {
3679 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
3680 framesize+1 > info->max_frame_size) ||
3681 framesize > info->max_frame_size)
3682 info->icount.rxlong++;
3683 else {
3684 if (status & BIT5)
3685 info->icount.rxok++;
3686
3687 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
3688 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
3689 ++framesize;
3690 }
3691
3692 #if SYNCLINK_GENERIC_HDLC
3693 if (info->netcount)
3694 hdlcdev_rx(info, buf->data, framesize);
3695 else
3696 #endif
3697 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
3698 }
3699 }
3700
3701 spin_lock_irqsave(&info->lock,flags);
3702 buf->status = buf->count = 0;
3703 info->rx_frame_count--;
3704 info->rx_get++;
3705 if (info->rx_get >= info->rx_buf_count)
3706 info->rx_get = 0;
3707 spin_unlock_irqrestore(&info->lock,flags);
3708
3709 return true;
3710 }
3711
3712 static bool register_test(MGSLPC_INFO *info)
3713 {
3714 static unsigned char patterns[] =
3715 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
3716 static unsigned int count = ARRAY_SIZE(patterns);
3717 unsigned int i;
3718 bool rc = true;
3719 unsigned long flags;
3720
3721 spin_lock_irqsave(&info->lock,flags);
3722 reset_device(info);
3723
3724 for (i = 0; i < count; i++) {
3725 write_reg(info, XAD1, patterns[i]);
3726 write_reg(info, XAD2, patterns[(i + 1) % count]);
3727 if ((read_reg(info, XAD1) != patterns[i]) ||
3728 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
3729 rc = false;
3730 break;
3731 }
3732 }
3733
3734 spin_unlock_irqrestore(&info->lock,flags);
3735 return rc;
3736 }
3737
3738 static bool irq_test(MGSLPC_INFO *info)
3739 {
3740 unsigned long end_time;
3741 unsigned long flags;
3742
3743 spin_lock_irqsave(&info->lock,flags);
3744 reset_device(info);
3745
3746 info->testing_irq = true;
3747 hdlc_mode(info);
3748
3749 info->irq_occurred = false;
3750
3751 /* init hdlc mode */
3752
3753 irq_enable(info, CHA, IRQ_TIMER);
3754 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
3755 issue_command(info, CHA, CMD_START_TIMER);
3756
3757 spin_unlock_irqrestore(&info->lock,flags);
3758
3759 end_time=100;
3760 while(end_time-- && !info->irq_occurred) {
3761 msleep_interruptible(10);
3762 }
3763
3764 info->testing_irq = false;
3765
3766 spin_lock_irqsave(&info->lock,flags);
3767 reset_device(info);
3768 spin_unlock_irqrestore(&info->lock,flags);
3769
3770 return info->irq_occurred;
3771 }
3772
3773 static int adapter_test(MGSLPC_INFO *info)
3774 {
3775 if (!register_test(info)) {
3776 info->init_error = DiagStatus_AddressFailure;
3777 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
3778 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
3779 return -ENODEV;
3780 }
3781
3782 if (!irq_test(info)) {
3783 info->init_error = DiagStatus_IrqFailure;
3784 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
3785 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
3786 return -ENODEV;
3787 }
3788
3789 if (debug_level >= DEBUG_LEVEL_INFO)
3790 printk("%s(%d):device %s passed diagnostics\n",
3791 __FILE__,__LINE__,info->device_name);
3792 return 0;
3793 }
3794
3795 static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
3796 {
3797 int i;
3798 int linecount;
3799 if (xmit)
3800 printk("%s tx data:\n",info->device_name);
3801 else
3802 printk("%s rx data:\n",info->device_name);
3803
3804 while(count) {
3805 if (count > 16)
3806 linecount = 16;
3807 else
3808 linecount = count;
3809
3810 for(i=0;i<linecount;i++)
3811 printk("%02X ",(unsigned char)data[i]);
3812 for(;i<17;i++)
3813 printk(" ");
3814 for(i=0;i<linecount;i++) {
3815 if (data[i]>=040 && data[i]<=0176)
3816 printk("%c",data[i]);
3817 else
3818 printk(".");
3819 }
3820 printk("\n");
3821
3822 data += linecount;
3823 count -= linecount;
3824 }
3825 }
3826
3827 /* HDLC frame time out
3828 * update stats and do tx completion processing
3829 */
3830 static void tx_timeout(unsigned long context)
3831 {
3832 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
3833 unsigned long flags;
3834
3835 if ( debug_level >= DEBUG_LEVEL_INFO )
3836 printk( "%s(%d):tx_timeout(%s)\n",
3837 __FILE__,__LINE__,info->device_name);
3838 if(info->tx_active &&
3839 info->params.mode == MGSL_MODE_HDLC) {
3840 info->icount.txtimeout++;
3841 }
3842 spin_lock_irqsave(&info->lock,flags);
3843 info->tx_active = false;
3844 info->tx_count = info->tx_put = info->tx_get = 0;
3845
3846 spin_unlock_irqrestore(&info->lock,flags);
3847
3848 #if SYNCLINK_GENERIC_HDLC
3849 if (info->netcount)
3850 hdlcdev_tx_done(info);
3851 else
3852 #endif
3853 {
3854 struct tty_struct *tty = tty_port_tty_get(&info->port);
3855 bh_transmit(info, tty);
3856 tty_kref_put(tty);
3857 }
3858 }
3859
3860 #if SYNCLINK_GENERIC_HDLC
3861
3862 /**
3863 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3864 * set encoding and frame check sequence (FCS) options
3865 *
3866 * dev pointer to network device structure
3867 * encoding serial encoding setting
3868 * parity FCS setting
3869 *
3870 * returns 0 if success, otherwise error code
3871 */
3872 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
3873 unsigned short parity)
3874 {
3875 MGSLPC_INFO *info = dev_to_port(dev);
3876 struct tty_struct *tty;
3877 unsigned char new_encoding;
3878 unsigned short new_crctype;
3879
3880 /* return error if TTY interface open */
3881 if (info->port.count)
3882 return -EBUSY;
3883
3884 switch (encoding)
3885 {
3886 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
3887 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
3888 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
3889 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
3890 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
3891 default: return -EINVAL;
3892 }
3893
3894 switch (parity)
3895 {
3896 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
3897 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
3898 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
3899 default: return -EINVAL;
3900 }
3901
3902 info->params.encoding = new_encoding;
3903 info->params.crc_type = new_crctype;
3904
3905 /* if network interface up, reprogram hardware */
3906 if (info->netcount) {
3907 tty = tty_port_tty_get(&info->port);
3908 mgslpc_program_hw(info, tty);
3909 tty_kref_put(tty);
3910 }
3911
3912 return 0;
3913 }
3914
3915 /**
3916 * called by generic HDLC layer to send frame
3917 *
3918 * skb socket buffer containing HDLC frame
3919 * dev pointer to network device structure
3920 */
3921 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
3922 struct net_device *dev)
3923 {
3924 MGSLPC_INFO *info = dev_to_port(dev);
3925 unsigned long flags;
3926
3927 if (debug_level >= DEBUG_LEVEL_INFO)
3928 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
3929
3930 /* stop sending until this frame completes */
3931 netif_stop_queue(dev);
3932
3933 /* copy data to device buffers */
3934 skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
3935 info->tx_get = 0;
3936 info->tx_put = info->tx_count = skb->len;
3937
3938 /* update network statistics */
3939 dev->stats.tx_packets++;
3940 dev->stats.tx_bytes += skb->len;
3941
3942 /* done with socket buffer, so free it */
3943 dev_kfree_skb(skb);
3944
3945 /* save start time for transmit timeout detection */
3946 dev->trans_start = jiffies;
3947
3948 /* start hardware transmitter if necessary */
3949 spin_lock_irqsave(&info->lock,flags);
3950 if (!info->tx_active) {
3951 struct tty_struct *tty = tty_port_tty_get(&info->port);
3952 tx_start(info, tty);
3953 tty_kref_put(tty);
3954 }
3955 spin_unlock_irqrestore(&info->lock,flags);
3956
3957 return NETDEV_TX_OK;
3958 }
3959
3960 /**
3961 * called by network layer when interface enabled
3962 * claim resources and initialize hardware
3963 *
3964 * dev pointer to network device structure
3965 *
3966 * returns 0 if success, otherwise error code
3967 */
3968 static int hdlcdev_open(struct net_device *dev)
3969 {
3970 MGSLPC_INFO *info = dev_to_port(dev);
3971 struct tty_struct *tty;
3972 int rc;
3973 unsigned long flags;
3974
3975 if (debug_level >= DEBUG_LEVEL_INFO)
3976 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
3977
3978 /* generic HDLC layer open processing */
3979 if ((rc = hdlc_open(dev)))
3980 return rc;
3981
3982 /* arbitrate between network and tty opens */
3983 spin_lock_irqsave(&info->netlock, flags);
3984 if (info->port.count != 0 || info->netcount != 0) {
3985 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
3986 spin_unlock_irqrestore(&info->netlock, flags);
3987 return -EBUSY;
3988 }
3989 info->netcount=1;
3990 spin_unlock_irqrestore(&info->netlock, flags);
3991
3992 tty = tty_port_tty_get(&info->port);
3993 /* claim resources and init adapter */
3994 if ((rc = startup(info, tty)) != 0) {
3995 tty_kref_put(tty);
3996 spin_lock_irqsave(&info->netlock, flags);
3997 info->netcount=0;
3998 spin_unlock_irqrestore(&info->netlock, flags);
3999 return rc;
4000 }
4001 /* assert DTR and RTS, apply hardware settings */
4002 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
4003 mgslpc_program_hw(info, tty);
4004 tty_kref_put(tty);
4005
4006 /* enable network layer transmit */
4007 dev->trans_start = jiffies;
4008 netif_start_queue(dev);
4009
4010 /* inform generic HDLC layer of current DCD status */
4011 spin_lock_irqsave(&info->lock, flags);
4012 get_signals(info);
4013 spin_unlock_irqrestore(&info->lock, flags);
4014 if (info->serial_signals & SerialSignal_DCD)
4015 netif_carrier_on(dev);
4016 else
4017 netif_carrier_off(dev);
4018 return 0;
4019 }
4020
4021 /**
4022 * called by network layer when interface is disabled
4023 * shutdown hardware and release resources
4024 *
4025 * dev pointer to network device structure
4026 *
4027 * returns 0 if success, otherwise error code
4028 */
4029 static int hdlcdev_close(struct net_device *dev)
4030 {
4031 MGSLPC_INFO *info = dev_to_port(dev);
4032 struct tty_struct *tty = tty_port_tty_get(&info->port);
4033 unsigned long flags;
4034
4035 if (debug_level >= DEBUG_LEVEL_INFO)
4036 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
4037
4038 netif_stop_queue(dev);
4039
4040 /* shutdown adapter and release resources */
4041 shutdown(info, tty);
4042 tty_kref_put(tty);
4043 hdlc_close(dev);
4044
4045 spin_lock_irqsave(&info->netlock, flags);
4046 info->netcount=0;
4047 spin_unlock_irqrestore(&info->netlock, flags);
4048
4049 return 0;
4050 }
4051
4052 /**
4053 * called by network layer to process IOCTL call to network device
4054 *
4055 * dev pointer to network device structure
4056 * ifr pointer to network interface request structure
4057 * cmd IOCTL command code
4058 *
4059 * returns 0 if success, otherwise error code
4060 */
4061 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4062 {
4063 const size_t size = sizeof(sync_serial_settings);
4064 sync_serial_settings new_line;
4065 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4066 MGSLPC_INFO *info = dev_to_port(dev);
4067 unsigned int flags;
4068
4069 if (debug_level >= DEBUG_LEVEL_INFO)
4070 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
4071
4072 /* return error if TTY interface open */
4073 if (info->port.count)
4074 return -EBUSY;
4075
4076 if (cmd != SIOCWANDEV)
4077 return hdlc_ioctl(dev, ifr, cmd);
4078
4079 memset(&new_line, 0, size);
4080
4081 switch(ifr->ifr_settings.type) {
4082 case IF_GET_IFACE: /* return current sync_serial_settings */
4083
4084 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4085 if (ifr->ifr_settings.size < size) {
4086 ifr->ifr_settings.size = size; /* data size wanted */
4087 return -ENOBUFS;
4088 }
4089
4090 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4091 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4092 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4093 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4094
4095 switch (flags){
4096 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4097 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4098 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4099 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4100 default: new_line.clock_type = CLOCK_DEFAULT;
4101 }
4102
4103 new_line.clock_rate = info->params.clock_speed;
4104 new_line.loopback = info->params.loopback ? 1:0;
4105
4106 if (copy_to_user(line, &new_line, size))
4107 return -EFAULT;
4108 return 0;
4109
4110 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4111
4112 if(!capable(CAP_NET_ADMIN))
4113 return -EPERM;
4114 if (copy_from_user(&new_line, line, size))
4115 return -EFAULT;
4116
4117 switch (new_line.clock_type)
4118 {
4119 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4120 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4121 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4122 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4123 case CLOCK_DEFAULT: flags = info->params.flags &
4124 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4125 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4126 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4127 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4128 default: return -EINVAL;
4129 }
4130
4131 if (new_line.loopback != 0 && new_line.loopback != 1)
4132 return -EINVAL;
4133
4134 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4135 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4136 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4137 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4138 info->params.flags |= flags;
4139
4140 info->params.loopback = new_line.loopback;
4141
4142 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4143 info->params.clock_speed = new_line.clock_rate;
4144 else
4145 info->params.clock_speed = 0;
4146
4147 /* if network interface up, reprogram hardware */
4148 if (info->netcount) {
4149 struct tty_struct *tty = tty_port_tty_get(&info->port);
4150 mgslpc_program_hw(info, tty);
4151 tty_kref_put(tty);
4152 }
4153 return 0;
4154
4155 default:
4156 return hdlc_ioctl(dev, ifr, cmd);
4157 }
4158 }
4159
4160 /**
4161 * called by network layer when transmit timeout is detected
4162 *
4163 * dev pointer to network device structure
4164 */
4165 static void hdlcdev_tx_timeout(struct net_device *dev)
4166 {
4167 MGSLPC_INFO *info = dev_to_port(dev);
4168 unsigned long flags;
4169
4170 if (debug_level >= DEBUG_LEVEL_INFO)
4171 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
4172
4173 dev->stats.tx_errors++;
4174 dev->stats.tx_aborted_errors++;
4175
4176 spin_lock_irqsave(&info->lock,flags);
4177 tx_stop(info);
4178 spin_unlock_irqrestore(&info->lock,flags);
4179
4180 netif_wake_queue(dev);
4181 }
4182
4183 /**
4184 * called by device driver when transmit completes
4185 * reenable network layer transmit if stopped
4186 *
4187 * info pointer to device instance information
4188 */
4189 static void hdlcdev_tx_done(MGSLPC_INFO *info)
4190 {
4191 if (netif_queue_stopped(info->netdev))
4192 netif_wake_queue(info->netdev);
4193 }
4194
4195 /**
4196 * called by device driver when frame received
4197 * pass frame to network layer
4198 *
4199 * info pointer to device instance information
4200 * buf pointer to buffer contianing frame data
4201 * size count of data bytes in buf
4202 */
4203 static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4204 {
4205 struct sk_buff *skb = dev_alloc_skb(size);
4206 struct net_device *dev = info->netdev;
4207
4208 if (debug_level >= DEBUG_LEVEL_INFO)
4209 printk("hdlcdev_rx(%s)\n",dev->name);
4210
4211 if (skb == NULL) {
4212 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
4213 dev->stats.rx_dropped++;
4214 return;
4215 }
4216
4217 memcpy(skb_put(skb, size), buf, size);
4218
4219 skb->protocol = hdlc_type_trans(skb, dev);
4220
4221 dev->stats.rx_packets++;
4222 dev->stats.rx_bytes += size;
4223
4224 netif_rx(skb);
4225 }
4226
4227 static const struct net_device_ops hdlcdev_ops = {
4228 .ndo_open = hdlcdev_open,
4229 .ndo_stop = hdlcdev_close,
4230 .ndo_change_mtu = hdlc_change_mtu,
4231 .ndo_start_xmit = hdlc_start_xmit,
4232 .ndo_do_ioctl = hdlcdev_ioctl,
4233 .ndo_tx_timeout = hdlcdev_tx_timeout,
4234 };
4235
4236 /**
4237 * called by device driver when adding device instance
4238 * do generic HDLC initialization
4239 *
4240 * info pointer to device instance information
4241 *
4242 * returns 0 if success, otherwise error code
4243 */
4244 static int hdlcdev_init(MGSLPC_INFO *info)
4245 {
4246 int rc;
4247 struct net_device *dev;
4248 hdlc_device *hdlc;
4249
4250 /* allocate and initialize network and HDLC layer objects */
4251
4252 if (!(dev = alloc_hdlcdev(info))) {
4253 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
4254 return -ENOMEM;
4255 }
4256
4257 /* for network layer reporting purposes only */
4258 dev->base_addr = info->io_base;
4259 dev->irq = info->irq_level;
4260
4261 /* network layer callbacks and settings */
4262 dev->netdev_ops = &hdlcdev_ops;
4263 dev->watchdog_timeo = 10 * HZ;
4264 dev->tx_queue_len = 50;
4265
4266 /* generic HDLC layer callbacks and settings */
4267 hdlc = dev_to_hdlc(dev);
4268 hdlc->attach = hdlcdev_attach;
4269 hdlc->xmit = hdlcdev_xmit;
4270
4271 /* register objects with HDLC layer */
4272 if ((rc = register_hdlc_device(dev))) {
4273 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
4274 free_netdev(dev);
4275 return rc;
4276 }
4277
4278 info->netdev = dev;
4279 return 0;
4280 }
4281
4282 /**
4283 * called by device driver when removing device instance
4284 * do generic HDLC cleanup
4285 *
4286 * info pointer to device instance information
4287 */
4288 static void hdlcdev_exit(MGSLPC_INFO *info)
4289 {
4290 unregister_hdlc_device(info->netdev);
4291 free_netdev(info->netdev);
4292 info->netdev = NULL;
4293 }
4294
4295 #endif /* CONFIG_HDLC */
4296
Linux kernel - Deliverables
This page took 0.119577 seconds and 4 git commands to generate.