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[deliverable/linux.git] / drivers / char / rocket.c
1 /*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42 /****** Defines ******/
43 #ifdef PCI_NUM_RESOURCES
44 #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
45 #else
46 #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
47 #endif
48
49 #define ROCKET_PARANOIA_CHECK
50 #define ROCKET_DISABLE_SIMUSAGE
51
52 #undef ROCKET_SOFT_FLOW
53 #undef ROCKET_DEBUG_OPEN
54 #undef ROCKET_DEBUG_INTR
55 #undef ROCKET_DEBUG_WRITE
56 #undef ROCKET_DEBUG_FLOW
57 #undef ROCKET_DEBUG_THROTTLE
58 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
59 #undef ROCKET_DEBUG_RECEIVE
60 #undef ROCKET_DEBUG_HANGUP
61 #undef REV_PCI_ORDER
62 #undef ROCKET_DEBUG_IO
63
64 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
65
66 /****** Kernel includes ******/
67
68 #ifdef MODVERSIONS
69 #include <config/modversions.h>
70 #endif
71
72 #include <linux/module.h>
73 #include <linux/errno.h>
74 #include <linux/major.h>
75 #include <linux/kernel.h>
76 #include <linux/signal.h>
77 #include <linux/slab.h>
78 #include <linux/mm.h>
79 #include <linux/sched.h>
80 #include <linux/timer.h>
81 #include <linux/interrupt.h>
82 #include <linux/tty.h>
83 #include <linux/tty_driver.h>
84 #include <linux/tty_flip.h>
85 #include <linux/string.h>
86 #include <linux/fcntl.h>
87 #include <linux/ptrace.h>
88 #include <linux/ioport.h>
89 #include <linux/delay.h>
90 #include <linux/wait.h>
91 #include <linux/pci.h>
92 #include <asm/uaccess.h>
93 #include <asm/atomic.h>
94 #include <linux/bitops.h>
95 #include <linux/spinlock.h>
96 #include <asm/semaphore.h>
97 #include <linux/init.h>
98
99 /****** RocketPort includes ******/
100
101 #include "rocket_int.h"
102 #include "rocket.h"
103
104 #define ROCKET_VERSION "2.09"
105 #define ROCKET_DATE "12-June-2003"
106
107 /****** RocketPort Local Variables ******/
108
109 static struct tty_driver *rocket_driver;
110
111 static struct rocket_version driver_version = {
112 ROCKET_VERSION, ROCKET_DATE
113 };
114
115 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
116 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
117 /* eg. Bit 0 indicates port 0 has xmit data, ... */
118 static atomic_t rp_num_ports_open; /* Number of serial ports open */
119 static struct timer_list rocket_timer;
120
121 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
122 static unsigned long board2;
123 static unsigned long board3;
124 static unsigned long board4;
125 static unsigned long controller;
126 static int support_low_speed;
127 static unsigned long modem1;
128 static unsigned long modem2;
129 static unsigned long modem3;
130 static unsigned long modem4;
131 static unsigned long pc104_1[8];
132 static unsigned long pc104_2[8];
133 static unsigned long pc104_3[8];
134 static unsigned long pc104_4[8];
135 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
136
137 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
138 static unsigned long rcktpt_io_addr[NUM_BOARDS];
139 static int rcktpt_type[NUM_BOARDS];
140 static int is_PCI[NUM_BOARDS];
141 static rocketModel_t rocketModel[NUM_BOARDS];
142 static int max_board;
143
144 /*
145 * The following arrays define the interrupt bits corresponding to each AIOP.
146 * These bits are different between the ISA and regular PCI boards and the
147 * Universal PCI boards.
148 */
149
150 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
151 AIOP_INTR_BIT_0,
152 AIOP_INTR_BIT_1,
153 AIOP_INTR_BIT_2,
154 AIOP_INTR_BIT_3
155 };
156
157 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
158 UPCI_AIOP_INTR_BIT_0,
159 UPCI_AIOP_INTR_BIT_1,
160 UPCI_AIOP_INTR_BIT_2,
161 UPCI_AIOP_INTR_BIT_3
162 };
163
164 static Byte_t RData[RDATASIZE] = {
165 0x00, 0x09, 0xf6, 0x82,
166 0x02, 0x09, 0x86, 0xfb,
167 0x04, 0x09, 0x00, 0x0a,
168 0x06, 0x09, 0x01, 0x0a,
169 0x08, 0x09, 0x8a, 0x13,
170 0x0a, 0x09, 0xc5, 0x11,
171 0x0c, 0x09, 0x86, 0x85,
172 0x0e, 0x09, 0x20, 0x0a,
173 0x10, 0x09, 0x21, 0x0a,
174 0x12, 0x09, 0x41, 0xff,
175 0x14, 0x09, 0x82, 0x00,
176 0x16, 0x09, 0x82, 0x7b,
177 0x18, 0x09, 0x8a, 0x7d,
178 0x1a, 0x09, 0x88, 0x81,
179 0x1c, 0x09, 0x86, 0x7a,
180 0x1e, 0x09, 0x84, 0x81,
181 0x20, 0x09, 0x82, 0x7c,
182 0x22, 0x09, 0x0a, 0x0a
183 };
184
185 static Byte_t RRegData[RREGDATASIZE] = {
186 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
187 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
188 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
189 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
190 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
191 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
192 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
193 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
194 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
195 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
196 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
197 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
198 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
199 };
200
201 static CONTROLLER_T sController[CTL_SIZE] = {
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
208 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
209 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
210 };
211
212 static Byte_t sBitMapClrTbl[8] = {
213 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
214 };
215
216 static Byte_t sBitMapSetTbl[8] = {
217 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
218 };
219
220 static int sClockPrescale = 0x14;
221
222 /*
223 * Line number is the ttySIx number (x), the Minor number. We
224 * assign them sequentially, starting at zero. The following
225 * array keeps track of the line number assigned to a given board/aiop/channel.
226 */
227 static unsigned char lineNumbers[MAX_RP_PORTS];
228 static unsigned long nextLineNumber;
229
230 /***** RocketPort Static Prototypes *********/
231 static int __init init_ISA(int i);
232 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
233 static void rp_flush_buffer(struct tty_struct *tty);
234 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
235 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
236 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
237 static void rp_start(struct tty_struct *tty);
238 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
239 int ChanNum);
240 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
241 static void sFlushRxFIFO(CHANNEL_T * ChP);
242 static void sFlushTxFIFO(CHANNEL_T * ChP);
243 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
244 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
245 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
246 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
247 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
248 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
249 ByteIO_t * AiopIOList, int AiopIOListSize,
250 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
251 int PeriodicOnly, int altChanRingIndicator,
252 int UPCIRingInd);
253 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
254 ByteIO_t * AiopIOList, int AiopIOListSize,
255 int IRQNum, Byte_t Frequency, int PeriodicOnly);
256 static int sReadAiopID(ByteIO_t io);
257 static int sReadAiopNumChan(WordIO_t io);
258
259 MODULE_AUTHOR("Theodore Ts'o");
260 MODULE_DESCRIPTION("Comtrol RocketPort driver");
261 module_param(board1, ulong, 0);
262 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
263 module_param(board2, ulong, 0);
264 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
265 module_param(board3, ulong, 0);
266 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
267 module_param(board4, ulong, 0);
268 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
269 module_param(controller, ulong, 0);
270 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
271 module_param(support_low_speed, bool, 0);
272 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
273 module_param(modem1, ulong, 0);
274 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
275 module_param(modem2, ulong, 0);
276 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
277 module_param(modem3, ulong, 0);
278 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
279 module_param(modem4, ulong, 0);
280 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
281 module_param_array(pc104_1, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
283 module_param_array(pc104_2, ulong, NULL, 0);
284 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
285 module_param_array(pc104_3, ulong, NULL, 0);
286 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
287 module_param_array(pc104_4, ulong, NULL, 0);
288 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
289
290 static int rp_init(void);
291 static void rp_cleanup_module(void);
292
293 module_init(rp_init);
294 module_exit(rp_cleanup_module);
295
296
297 MODULE_LICENSE("Dual BSD/GPL");
298
299 /*************************************************************************/
300 /* Module code starts here */
301
302 static inline int rocket_paranoia_check(struct r_port *info,
303 const char *routine)
304 {
305 #ifdef ROCKET_PARANOIA_CHECK
306 if (!info)
307 return 1;
308 if (info->magic != RPORT_MAGIC) {
309 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
310 routine);
311 return 1;
312 }
313 #endif
314 return 0;
315 }
316
317
318 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
319 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
320 * tty layer.
321 */
322 static void rp_do_receive(struct r_port *info,
323 struct tty_struct *tty,
324 CHANNEL_t * cp, unsigned int ChanStatus)
325 {
326 unsigned int CharNStat;
327 int ToRecv, wRecv, space;
328 unsigned char *cbuf;
329
330 ToRecv = sGetRxCnt(cp);
331 #ifdef ROCKET_DEBUG_INTR
332 printk(KERN_INFO "rp_do_receive(%d)...", ToRecv);
333 #endif
334 if (ToRecv == 0)
335 return;
336
337 /*
338 * if status indicates there are errored characters in the
339 * FIFO, then enter status mode (a word in FIFO holds
340 * character and status).
341 */
342 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
343 if (!(ChanStatus & STATMODE)) {
344 #ifdef ROCKET_DEBUG_RECEIVE
345 printk(KERN_INFO "Entering STATMODE...");
346 #endif
347 ChanStatus |= STATMODE;
348 sEnRxStatusMode(cp);
349 }
350 }
351
352 /*
353 * if we previously entered status mode, then read down the
354 * FIFO one word at a time, pulling apart the character and
355 * the status. Update error counters depending on status
356 */
357 if (ChanStatus & STATMODE) {
358 #ifdef ROCKET_DEBUG_RECEIVE
359 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
360 info->read_status_mask);
361 #endif
362 while (ToRecv) {
363 char flag;
364
365 CharNStat = sInW(sGetTxRxDataIO(cp));
366 #ifdef ROCKET_DEBUG_RECEIVE
367 printk(KERN_INFO "%x...", CharNStat);
368 #endif
369 if (CharNStat & STMBREAKH)
370 CharNStat &= ~(STMFRAMEH | STMPARITYH);
371 if (CharNStat & info->ignore_status_mask) {
372 ToRecv--;
373 continue;
374 }
375 CharNStat &= info->read_status_mask;
376 if (CharNStat & STMBREAKH)
377 flag = TTY_BREAK;
378 else if (CharNStat & STMPARITYH)
379 flag = TTY_PARITY;
380 else if (CharNStat & STMFRAMEH)
381 flag = TTY_FRAME;
382 else if (CharNStat & STMRCVROVRH)
383 flag = TTY_OVERRUN;
384 else
385 flag = TTY_NORMAL;
386 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
387 ToRecv--;
388 }
389
390 /*
391 * after we've emptied the FIFO in status mode, turn
392 * status mode back off
393 */
394 if (sGetRxCnt(cp) == 0) {
395 #ifdef ROCKET_DEBUG_RECEIVE
396 printk(KERN_INFO "Status mode off.\n");
397 #endif
398 sDisRxStatusMode(cp);
399 }
400 } else {
401 /*
402 * we aren't in status mode, so read down the FIFO two
403 * characters at time by doing repeated word IO
404 * transfer.
405 */
406 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
407 if (space < ToRecv) {
408 #ifdef ROCKET_DEBUG_RECEIVE
409 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
410 #endif
411 if (space <= 0)
412 return;
413 ToRecv = space;
414 }
415 wRecv = ToRecv >> 1;
416 if (wRecv)
417 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
418 if (ToRecv & 1)
419 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
420 }
421 /* Push the data up to the tty layer */
422 tty_flip_buffer_push(tty);
423 }
424
425 /*
426 * Serial port transmit data function. Called from the timer polling loop as a
427 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
428 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
429 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
430 */
431 static void rp_do_transmit(struct r_port *info)
432 {
433 int c;
434 CHANNEL_t *cp = &info->channel;
435 struct tty_struct *tty;
436 unsigned long flags;
437
438 #ifdef ROCKET_DEBUG_INTR
439 printk(KERN_INFO "rp_do_transmit ");
440 #endif
441 if (!info)
442 return;
443 if (!info->tty) {
444 printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
445 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
446 return;
447 }
448
449 spin_lock_irqsave(&info->slock, flags);
450 tty = info->tty;
451 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
452
453 /* Loop sending data to FIFO until done or FIFO full */
454 while (1) {
455 if (tty->stopped || tty->hw_stopped)
456 break;
457 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
458 if (c <= 0 || info->xmit_fifo_room <= 0)
459 break;
460 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
461 if (c & 1)
462 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
463 info->xmit_tail += c;
464 info->xmit_tail &= XMIT_BUF_SIZE - 1;
465 info->xmit_cnt -= c;
466 info->xmit_fifo_room -= c;
467 #ifdef ROCKET_DEBUG_INTR
468 printk(KERN_INFO "tx %d chars...", c);
469 #endif
470 }
471
472 if (info->xmit_cnt == 0)
473 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
474
475 if (info->xmit_cnt < WAKEUP_CHARS) {
476 tty_wakeup(tty);
477 wake_up_interruptible(&tty->write_wait);
478 #ifdef ROCKETPORT_HAVE_POLL_WAIT
479 wake_up_interruptible(&tty->poll_wait);
480 #endif
481 }
482
483 spin_unlock_irqrestore(&info->slock, flags);
484
485 #ifdef ROCKET_DEBUG_INTR
486 printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
487 info->xmit_tail, info->xmit_fifo_room);
488 #endif
489 }
490
491 /*
492 * Called when a serial port signals it has read data in it's RX FIFO.
493 * It checks what interrupts are pending and services them, including
494 * receiving serial data.
495 */
496 static void rp_handle_port(struct r_port *info)
497 {
498 CHANNEL_t *cp;
499 struct tty_struct *tty;
500 unsigned int IntMask, ChanStatus;
501
502 if (!info)
503 return;
504
505 if ((info->flags & ROCKET_INITIALIZED) == 0) {
506 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
507 return;
508 }
509 if (!info->tty) {
510 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
511 return;
512 }
513 cp = &info->channel;
514 tty = info->tty;
515
516 IntMask = sGetChanIntID(cp) & info->intmask;
517 #ifdef ROCKET_DEBUG_INTR
518 printk(KERN_INFO "rp_interrupt %02x...", IntMask);
519 #endif
520 ChanStatus = sGetChanStatus(cp);
521 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
522 rp_do_receive(info, tty, cp, ChanStatus);
523 }
524 if (IntMask & DELTA_CD) { /* CD change */
525 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
526 printk(KERN_INFO "ttyR%d CD now %s...", info->line,
527 (ChanStatus & CD_ACT) ? "on" : "off");
528 #endif
529 if (!(ChanStatus & CD_ACT) && info->cd_status) {
530 #ifdef ROCKET_DEBUG_HANGUP
531 printk(KERN_INFO "CD drop, calling hangup.\n");
532 #endif
533 tty_hangup(tty);
534 }
535 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
536 wake_up_interruptible(&info->open_wait);
537 }
538 #ifdef ROCKET_DEBUG_INTR
539 if (IntMask & DELTA_CTS) { /* CTS change */
540 printk(KERN_INFO "CTS change...\n");
541 }
542 if (IntMask & DELTA_DSR) { /* DSR change */
543 printk(KERN_INFO "DSR change...\n");
544 }
545 #endif
546 }
547
548 /*
549 * The top level polling routine. Repeats every 1/100 HZ (10ms).
550 */
551 static void rp_do_poll(unsigned long dummy)
552 {
553 CONTROLLER_t *ctlp;
554 int ctrl, aiop, ch, line, i;
555 unsigned int xmitmask;
556 unsigned int CtlMask;
557 unsigned char AiopMask;
558 Word_t bit;
559
560 /* Walk through all the boards (ctrl's) */
561 for (ctrl = 0; ctrl < max_board; ctrl++) {
562 if (rcktpt_io_addr[ctrl] <= 0)
563 continue;
564
565 /* Get a ptr to the board's control struct */
566 ctlp = sCtlNumToCtlPtr(ctrl);
567
568 /* Get the interupt status from the board */
569 #ifdef CONFIG_PCI
570 if (ctlp->BusType == isPCI)
571 CtlMask = sPCIGetControllerIntStatus(ctlp);
572 else
573 #endif
574 CtlMask = sGetControllerIntStatus(ctlp);
575
576 /* Check if any AIOP read bits are set */
577 for (aiop = 0; CtlMask; aiop++) {
578 bit = ctlp->AiopIntrBits[aiop];
579 if (CtlMask & bit) {
580 CtlMask &= ~bit;
581 AiopMask = sGetAiopIntStatus(ctlp, aiop);
582
583 /* Check if any port read bits are set */
584 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
585 if (AiopMask & 1) {
586
587 /* Get the line number (/dev/ttyRx number). */
588 /* Read the data from the port. */
589 line = GetLineNumber(ctrl, aiop, ch);
590 rp_handle_port(rp_table[line]);
591 }
592 }
593 }
594 }
595
596 xmitmask = xmit_flags[ctrl];
597
598 /*
599 * xmit_flags contains bit-significant flags, indicating there is data
600 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
601 * 1, ... (32 total possible). The variable i has the aiop and ch
602 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
603 */
604 if (xmitmask) {
605 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
606 if (xmitmask & (1 << i)) {
607 aiop = (i & 0x18) >> 3;
608 ch = i & 0x07;
609 line = GetLineNumber(ctrl, aiop, ch);
610 rp_do_transmit(rp_table[line]);
611 }
612 }
613 }
614 }
615
616 /*
617 * Reset the timer so we get called at the next clock tick (10ms).
618 */
619 if (atomic_read(&rp_num_ports_open))
620 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
621 }
622
623 /*
624 * Initializes the r_port structure for a port, as well as enabling the port on
625 * the board.
626 * Inputs: board, aiop, chan numbers
627 */
628 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
629 {
630 unsigned rocketMode;
631 struct r_port *info;
632 int line;
633 CONTROLLER_T *ctlp;
634
635 /* Get the next available line number */
636 line = SetLineNumber(board, aiop, chan);
637
638 ctlp = sCtlNumToCtlPtr(board);
639
640 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
641 info = kmalloc(sizeof (struct r_port), GFP_KERNEL);
642 if (!info) {
643 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
644 return;
645 }
646 memset(info, 0, sizeof (struct r_port));
647
648 info->magic = RPORT_MAGIC;
649 info->line = line;
650 info->ctlp = ctlp;
651 info->board = board;
652 info->aiop = aiop;
653 info->chan = chan;
654 info->closing_wait = 3000;
655 info->close_delay = 50;
656 init_waitqueue_head(&info->open_wait);
657 init_waitqueue_head(&info->close_wait);
658 info->flags &= ~ROCKET_MODE_MASK;
659 switch (pc104[board][line]) {
660 case 422:
661 info->flags |= ROCKET_MODE_RS422;
662 break;
663 case 485:
664 info->flags |= ROCKET_MODE_RS485;
665 break;
666 case 232:
667 default:
668 info->flags |= ROCKET_MODE_RS232;
669 break;
670 }
671
672 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
673 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
674 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
675 kfree(info);
676 return;
677 }
678
679 rocketMode = info->flags & ROCKET_MODE_MASK;
680
681 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
682 sEnRTSToggle(&info->channel);
683 else
684 sDisRTSToggle(&info->channel);
685
686 if (ctlp->boardType == ROCKET_TYPE_PC104) {
687 switch (rocketMode) {
688 case ROCKET_MODE_RS485:
689 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
690 break;
691 case ROCKET_MODE_RS422:
692 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
693 break;
694 case ROCKET_MODE_RS232:
695 default:
696 if (info->flags & ROCKET_RTS_TOGGLE)
697 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
698 else
699 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
700 break;
701 }
702 }
703 spin_lock_init(&info->slock);
704 sema_init(&info->write_sem, 1);
705 rp_table[line] = info;
706 if (pci_dev)
707 tty_register_device(rocket_driver, line, &pci_dev->dev);
708 }
709
710 /*
711 * Configures a rocketport port according to its termio settings. Called from
712 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
713 */
714 static void configure_r_port(struct r_port *info,
715 struct termios *old_termios)
716 {
717 unsigned cflag;
718 unsigned long flags;
719 unsigned rocketMode;
720 int bits, baud, divisor;
721 CHANNEL_t *cp;
722
723 if (!info->tty || !info->tty->termios)
724 return;
725 cp = &info->channel;
726 cflag = info->tty->termios->c_cflag;
727
728 /* Byte size and parity */
729 if ((cflag & CSIZE) == CS8) {
730 sSetData8(cp);
731 bits = 10;
732 } else {
733 sSetData7(cp);
734 bits = 9;
735 }
736 if (cflag & CSTOPB) {
737 sSetStop2(cp);
738 bits++;
739 } else {
740 sSetStop1(cp);
741 }
742
743 if (cflag & PARENB) {
744 sEnParity(cp);
745 bits++;
746 if (cflag & PARODD) {
747 sSetOddParity(cp);
748 } else {
749 sSetEvenParity(cp);
750 }
751 } else {
752 sDisParity(cp);
753 }
754
755 /* baud rate */
756 baud = tty_get_baud_rate(info->tty);
757 if (!baud)
758 baud = 9600;
759 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
760 if ((divisor >= 8192 || divisor < 0) && old_termios) {
761 info->tty->termios->c_cflag &= ~CBAUD;
762 info->tty->termios->c_cflag |=
763 (old_termios->c_cflag & CBAUD);
764 baud = tty_get_baud_rate(info->tty);
765 if (!baud)
766 baud = 9600;
767 divisor = (rp_baud_base[info->board] / baud) - 1;
768 }
769 if (divisor >= 8192 || divisor < 0) {
770 baud = 9600;
771 divisor = (rp_baud_base[info->board] / baud) - 1;
772 }
773 info->cps = baud / bits;
774 sSetBaud(cp, divisor);
775
776 if (cflag & CRTSCTS) {
777 info->intmask |= DELTA_CTS;
778 sEnCTSFlowCtl(cp);
779 } else {
780 info->intmask &= ~DELTA_CTS;
781 sDisCTSFlowCtl(cp);
782 }
783 if (cflag & CLOCAL) {
784 info->intmask &= ~DELTA_CD;
785 } else {
786 spin_lock_irqsave(&info->slock, flags);
787 if (sGetChanStatus(cp) & CD_ACT)
788 info->cd_status = 1;
789 else
790 info->cd_status = 0;
791 info->intmask |= DELTA_CD;
792 spin_unlock_irqrestore(&info->slock, flags);
793 }
794
795 /*
796 * Handle software flow control in the board
797 */
798 #ifdef ROCKET_SOFT_FLOW
799 if (I_IXON(info->tty)) {
800 sEnTxSoftFlowCtl(cp);
801 if (I_IXANY(info->tty)) {
802 sEnIXANY(cp);
803 } else {
804 sDisIXANY(cp);
805 }
806 sSetTxXONChar(cp, START_CHAR(info->tty));
807 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
808 } else {
809 sDisTxSoftFlowCtl(cp);
810 sDisIXANY(cp);
811 sClrTxXOFF(cp);
812 }
813 #endif
814
815 /*
816 * Set up ignore/read mask words
817 */
818 info->read_status_mask = STMRCVROVRH | 0xFF;
819 if (I_INPCK(info->tty))
820 info->read_status_mask |= STMFRAMEH | STMPARITYH;
821 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
822 info->read_status_mask |= STMBREAKH;
823
824 /*
825 * Characters to ignore
826 */
827 info->ignore_status_mask = 0;
828 if (I_IGNPAR(info->tty))
829 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
830 if (I_IGNBRK(info->tty)) {
831 info->ignore_status_mask |= STMBREAKH;
832 /*
833 * If we're ignoring parity and break indicators,
834 * ignore overruns too. (For real raw support).
835 */
836 if (I_IGNPAR(info->tty))
837 info->ignore_status_mask |= STMRCVROVRH;
838 }
839
840 rocketMode = info->flags & ROCKET_MODE_MASK;
841
842 if ((info->flags & ROCKET_RTS_TOGGLE)
843 || (rocketMode == ROCKET_MODE_RS485))
844 sEnRTSToggle(cp);
845 else
846 sDisRTSToggle(cp);
847
848 sSetRTS(&info->channel);
849
850 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
851 switch (rocketMode) {
852 case ROCKET_MODE_RS485:
853 sSetInterfaceMode(cp, InterfaceModeRS485);
854 break;
855 case ROCKET_MODE_RS422:
856 sSetInterfaceMode(cp, InterfaceModeRS422);
857 break;
858 case ROCKET_MODE_RS232:
859 default:
860 if (info->flags & ROCKET_RTS_TOGGLE)
861 sSetInterfaceMode(cp, InterfaceModeRS232T);
862 else
863 sSetInterfaceMode(cp, InterfaceModeRS232);
864 break;
865 }
866 }
867 }
868
869 /* info->count is considered critical, protected by spinlocks. */
870 static int block_til_ready(struct tty_struct *tty, struct file *filp,
871 struct r_port *info)
872 {
873 DECLARE_WAITQUEUE(wait, current);
874 int retval;
875 int do_clocal = 0, extra_count = 0;
876 unsigned long flags;
877
878 /*
879 * If the device is in the middle of being closed, then block
880 * until it's done, and then try again.
881 */
882 if (tty_hung_up_p(filp))
883 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
884 if (info->flags & ROCKET_CLOSING) {
885 interruptible_sleep_on(&info->close_wait);
886 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
887 }
888
889 /*
890 * If non-blocking mode is set, or the port is not enabled,
891 * then make the check up front and then exit.
892 */
893 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
894 info->flags |= ROCKET_NORMAL_ACTIVE;
895 return 0;
896 }
897 if (tty->termios->c_cflag & CLOCAL)
898 do_clocal = 1;
899
900 /*
901 * Block waiting for the carrier detect and the line to become free. While we are in
902 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
903 * We restore it upon exit, either normal or abnormal.
904 */
905 retval = 0;
906 add_wait_queue(&info->open_wait, &wait);
907 #ifdef ROCKET_DEBUG_OPEN
908 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
909 #endif
910 spin_lock_irqsave(&info->slock, flags);
911
912 #ifdef ROCKET_DISABLE_SIMUSAGE
913 info->flags |= ROCKET_NORMAL_ACTIVE;
914 #else
915 if (!tty_hung_up_p(filp)) {
916 extra_count = 1;
917 info->count--;
918 }
919 #endif
920 info->blocked_open++;
921
922 spin_unlock_irqrestore(&info->slock, flags);
923
924 while (1) {
925 if (tty->termios->c_cflag & CBAUD) {
926 sSetDTR(&info->channel);
927 sSetRTS(&info->channel);
928 }
929 set_current_state(TASK_INTERRUPTIBLE);
930 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
931 if (info->flags & ROCKET_HUP_NOTIFY)
932 retval = -EAGAIN;
933 else
934 retval = -ERESTARTSYS;
935 break;
936 }
937 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
938 break;
939 if (signal_pending(current)) {
940 retval = -ERESTARTSYS;
941 break;
942 }
943 #ifdef ROCKET_DEBUG_OPEN
944 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
945 info->line, info->count, info->flags);
946 #endif
947 schedule(); /* Don't hold spinlock here, will hang PC */
948 }
949 current->state = TASK_RUNNING;
950 remove_wait_queue(&info->open_wait, &wait);
951
952 spin_lock_irqsave(&info->slock, flags);
953
954 if (extra_count)
955 info->count++;
956 info->blocked_open--;
957
958 spin_unlock_irqrestore(&info->slock, flags);
959
960 #ifdef ROCKET_DEBUG_OPEN
961 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
962 info->line, info->count);
963 #endif
964 if (retval)
965 return retval;
966 info->flags |= ROCKET_NORMAL_ACTIVE;
967 return 0;
968 }
969
970 /*
971 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
972 * port's r_port struct. Initializes the port hardware.
973 */
974 static int rp_open(struct tty_struct *tty, struct file *filp)
975 {
976 struct r_port *info;
977 int line = 0, retval;
978 CHANNEL_t *cp;
979 unsigned long page;
980
981 line = TTY_GET_LINE(tty);
982 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
983 return -ENXIO;
984
985 page = __get_free_page(GFP_KERNEL);
986 if (!page)
987 return -ENOMEM;
988
989 if (info->flags & ROCKET_CLOSING) {
990 interruptible_sleep_on(&info->close_wait);
991 free_page(page);
992 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
993 }
994
995 /*
996 * We must not sleep from here until the port is marked fully in use.
997 */
998 if (info->xmit_buf)
999 free_page(page);
1000 else
1001 info->xmit_buf = (unsigned char *) page;
1002
1003 tty->driver_data = info;
1004 info->tty = tty;
1005
1006 if (info->count++ == 0) {
1007 atomic_inc(&rp_num_ports_open);
1008
1009 #ifdef ROCKET_DEBUG_OPEN
1010 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
1011 #endif
1012 }
1013 #ifdef ROCKET_DEBUG_OPEN
1014 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1015 #endif
1016
1017 /*
1018 * Info->count is now 1; so it's safe to sleep now.
1019 */
1020 info->session = current->signal->session;
1021 info->pgrp = process_group(current);
1022
1023 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1024 cp = &info->channel;
1025 sSetRxTrigger(cp, TRIG_1);
1026 if (sGetChanStatus(cp) & CD_ACT)
1027 info->cd_status = 1;
1028 else
1029 info->cd_status = 0;
1030 sDisRxStatusMode(cp);
1031 sFlushRxFIFO(cp);
1032 sFlushTxFIFO(cp);
1033
1034 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1035 sSetRxTrigger(cp, TRIG_1);
1036
1037 sGetChanStatus(cp);
1038 sDisRxStatusMode(cp);
1039 sClrTxXOFF(cp);
1040
1041 sDisCTSFlowCtl(cp);
1042 sDisTxSoftFlowCtl(cp);
1043
1044 sEnRxFIFO(cp);
1045 sEnTransmit(cp);
1046
1047 info->flags |= ROCKET_INITIALIZED;
1048
1049 /*
1050 * Set up the tty->alt_speed kludge
1051 */
1052 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1053 info->tty->alt_speed = 57600;
1054 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1055 info->tty->alt_speed = 115200;
1056 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1057 info->tty->alt_speed = 230400;
1058 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1059 info->tty->alt_speed = 460800;
1060
1061 configure_r_port(info, NULL);
1062 if (tty->termios->c_cflag & CBAUD) {
1063 sSetDTR(cp);
1064 sSetRTS(cp);
1065 }
1066 }
1067 /* Starts (or resets) the maint polling loop */
1068 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1069
1070 retval = block_til_ready(tty, filp, info);
1071 if (retval) {
1072 #ifdef ROCKET_DEBUG_OPEN
1073 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1074 #endif
1075 return retval;
1076 }
1077 return 0;
1078 }
1079
1080 /*
1081 * Exception handler that closes a serial port. info->count is considered critical.
1082 */
1083 static void rp_close(struct tty_struct *tty, struct file *filp)
1084 {
1085 struct r_port *info = (struct r_port *) tty->driver_data;
1086 unsigned long flags;
1087 int timeout;
1088 CHANNEL_t *cp;
1089
1090 if (rocket_paranoia_check(info, "rp_close"))
1091 return;
1092
1093 #ifdef ROCKET_DEBUG_OPEN
1094 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1095 #endif
1096
1097 if (tty_hung_up_p(filp))
1098 return;
1099 spin_lock_irqsave(&info->slock, flags);
1100
1101 if ((tty->count == 1) && (info->count != 1)) {
1102 /*
1103 * Uh, oh. tty->count is 1, which means that the tty
1104 * structure will be freed. Info->count should always
1105 * be one in these conditions. If it's greater than
1106 * one, we've got real problems, since it means the
1107 * serial port won't be shutdown.
1108 */
1109 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
1110 "info->count is %d\n", info->count);
1111 info->count = 1;
1112 }
1113 if (--info->count < 0) {
1114 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
1115 info->line, info->count);
1116 info->count = 0;
1117 }
1118 if (info->count) {
1119 spin_unlock_irqrestore(&info->slock, flags);
1120 return;
1121 }
1122 info->flags |= ROCKET_CLOSING;
1123 spin_unlock_irqrestore(&info->slock, flags);
1124
1125 cp = &info->channel;
1126
1127 /*
1128 * Notify the line discpline to only process XON/XOFF characters
1129 */
1130 tty->closing = 1;
1131
1132 /*
1133 * If transmission was throttled by the application request,
1134 * just flush the xmit buffer.
1135 */
1136 if (tty->flow_stopped)
1137 rp_flush_buffer(tty);
1138
1139 /*
1140 * Wait for the transmit buffer to clear
1141 */
1142 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1143 tty_wait_until_sent(tty, info->closing_wait);
1144 /*
1145 * Before we drop DTR, make sure the UART transmitter
1146 * has completely drained; this is especially
1147 * important if there is a transmit FIFO!
1148 */
1149 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1150 if (timeout == 0)
1151 timeout = 1;
1152 rp_wait_until_sent(tty, timeout);
1153 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1154
1155 sDisTransmit(cp);
1156 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1157 sDisCTSFlowCtl(cp);
1158 sDisTxSoftFlowCtl(cp);
1159 sClrTxXOFF(cp);
1160 sFlushRxFIFO(cp);
1161 sFlushTxFIFO(cp);
1162 sClrRTS(cp);
1163 if (C_HUPCL(tty))
1164 sClrDTR(cp);
1165
1166 if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
1167 TTY_DRIVER_FLUSH_BUFFER(tty);
1168
1169 tty_ldisc_flush(tty);
1170
1171 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1172
1173 if (info->blocked_open) {
1174 if (info->close_delay) {
1175 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1176 }
1177 wake_up_interruptible(&info->open_wait);
1178 } else {
1179 if (info->xmit_buf) {
1180 free_page((unsigned long) info->xmit_buf);
1181 info->xmit_buf = NULL;
1182 }
1183 }
1184 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1185 tty->closing = 0;
1186 wake_up_interruptible(&info->close_wait);
1187 atomic_dec(&rp_num_ports_open);
1188
1189 #ifdef ROCKET_DEBUG_OPEN
1190 printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
1191 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1192 #endif
1193
1194 }
1195
1196 static void rp_set_termios(struct tty_struct *tty,
1197 struct termios *old_termios)
1198 {
1199 struct r_port *info = (struct r_port *) tty->driver_data;
1200 CHANNEL_t *cp;
1201 unsigned cflag;
1202
1203 if (rocket_paranoia_check(info, "rp_set_termios"))
1204 return;
1205
1206 cflag = tty->termios->c_cflag;
1207
1208 if (cflag == old_termios->c_cflag)
1209 return;
1210
1211 /*
1212 * This driver doesn't support CS5 or CS6
1213 */
1214 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1215 tty->termios->c_cflag =
1216 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1217
1218 configure_r_port(info, old_termios);
1219
1220 cp = &info->channel;
1221
1222 /* Handle transition to B0 status */
1223 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1224 sClrDTR(cp);
1225 sClrRTS(cp);
1226 }
1227
1228 /* Handle transition away from B0 status */
1229 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1230 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1231 sSetRTS(cp);
1232 sSetDTR(cp);
1233 }
1234
1235 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1236 tty->hw_stopped = 0;
1237 rp_start(tty);
1238 }
1239 }
1240
1241 static void rp_break(struct tty_struct *tty, int break_state)
1242 {
1243 struct r_port *info = (struct r_port *) tty->driver_data;
1244 unsigned long flags;
1245
1246 if (rocket_paranoia_check(info, "rp_break"))
1247 return;
1248
1249 spin_lock_irqsave(&info->slock, flags);
1250 if (break_state == -1)
1251 sSendBreak(&info->channel);
1252 else
1253 sClrBreak(&info->channel);
1254 spin_unlock_irqrestore(&info->slock, flags);
1255 }
1256
1257 /*
1258 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1259 * the UPCI boards was added, it was decided to make this a function because
1260 * the macro was getting too complicated. All cases except the first one
1261 * (UPCIRingInd) are taken directly from the original macro.
1262 */
1263 static int sGetChanRI(CHANNEL_T * ChP)
1264 {
1265 CONTROLLER_t *CtlP = ChP->CtlP;
1266 int ChanNum = ChP->ChanNum;
1267 int RingInd = 0;
1268
1269 if (CtlP->UPCIRingInd)
1270 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1271 else if (CtlP->AltChanRingIndicator)
1272 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1273 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1274 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1275
1276 return RingInd;
1277 }
1278
1279 /********************************************************************************************/
1280 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1281
1282 /*
1283 * Returns the state of the serial modem control lines. These next 2 functions
1284 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1285 */
1286 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1287 {
1288 struct r_port *info = (struct r_port *)tty->driver_data;
1289 unsigned int control, result, ChanStatus;
1290
1291 ChanStatus = sGetChanStatusLo(&info->channel);
1292 control = info->channel.TxControl[3];
1293 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1294 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1295 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1296 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1297 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1298 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1299
1300 return result;
1301 }
1302
1303 /*
1304 * Sets the modem control lines
1305 */
1306 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1307 unsigned int set, unsigned int clear)
1308 {
1309 struct r_port *info = (struct r_port *)tty->driver_data;
1310
1311 if (set & TIOCM_RTS)
1312 info->channel.TxControl[3] |= SET_RTS;
1313 if (set & TIOCM_DTR)
1314 info->channel.TxControl[3] |= SET_DTR;
1315 if (clear & TIOCM_RTS)
1316 info->channel.TxControl[3] &= ~SET_RTS;
1317 if (clear & TIOCM_DTR)
1318 info->channel.TxControl[3] &= ~SET_DTR;
1319
1320 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1321 return 0;
1322 }
1323
1324 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1325 {
1326 struct rocket_config tmp;
1327
1328 if (!retinfo)
1329 return -EFAULT;
1330 memset(&tmp, 0, sizeof (tmp));
1331 tmp.line = info->line;
1332 tmp.flags = info->flags;
1333 tmp.close_delay = info->close_delay;
1334 tmp.closing_wait = info->closing_wait;
1335 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1336
1337 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1338 return -EFAULT;
1339 return 0;
1340 }
1341
1342 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1343 {
1344 struct rocket_config new_serial;
1345
1346 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1347 return -EFAULT;
1348
1349 if (!capable(CAP_SYS_ADMIN))
1350 {
1351 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1352 return -EPERM;
1353 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1354 configure_r_port(info, NULL);
1355 return 0;
1356 }
1357
1358 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1359 info->close_delay = new_serial.close_delay;
1360 info->closing_wait = new_serial.closing_wait;
1361
1362 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1363 info->tty->alt_speed = 57600;
1364 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1365 info->tty->alt_speed = 115200;
1366 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1367 info->tty->alt_speed = 230400;
1368 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1369 info->tty->alt_speed = 460800;
1370
1371 configure_r_port(info, NULL);
1372 return 0;
1373 }
1374
1375 /*
1376 * This function fills in a rocket_ports struct with information
1377 * about what boards/ports are in the system. This info is passed
1378 * to user space. See setrocket.c where the info is used to create
1379 * the /dev/ttyRx ports.
1380 */
1381 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1382 {
1383 struct rocket_ports tmp;
1384 int board;
1385
1386 if (!retports)
1387 return -EFAULT;
1388 memset(&tmp, 0, sizeof (tmp));
1389 tmp.tty_major = rocket_driver->major;
1390
1391 for (board = 0; board < 4; board++) {
1392 tmp.rocketModel[board].model = rocketModel[board].model;
1393 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1394 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1395 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1396 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1397 }
1398 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1399 return -EFAULT;
1400 return 0;
1401 }
1402
1403 static int reset_rm2(struct r_port *info, void __user *arg)
1404 {
1405 int reset;
1406
1407 if (copy_from_user(&reset, arg, sizeof (int)))
1408 return -EFAULT;
1409 if (reset)
1410 reset = 1;
1411
1412 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1413 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1414 return -EINVAL;
1415
1416 if (info->ctlp->BusType == isISA)
1417 sModemReset(info->ctlp, info->chan, reset);
1418 else
1419 sPCIModemReset(info->ctlp, info->chan, reset);
1420
1421 return 0;
1422 }
1423
1424 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1425 {
1426 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1427 return -EFAULT;
1428 return 0;
1429 }
1430
1431 /* IOCTL call handler into the driver */
1432 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1433 unsigned int cmd, unsigned long arg)
1434 {
1435 struct r_port *info = (struct r_port *) tty->driver_data;
1436 void __user *argp = (void __user *)arg;
1437
1438 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1439 return -ENXIO;
1440
1441 switch (cmd) {
1442 case RCKP_GET_STRUCT:
1443 if (copy_to_user(argp, info, sizeof (struct r_port)))
1444 return -EFAULT;
1445 return 0;
1446 case RCKP_GET_CONFIG:
1447 return get_config(info, argp);
1448 case RCKP_SET_CONFIG:
1449 return set_config(info, argp);
1450 case RCKP_GET_PORTS:
1451 return get_ports(info, argp);
1452 case RCKP_RESET_RM2:
1453 return reset_rm2(info, argp);
1454 case RCKP_GET_VERSION:
1455 return get_version(info, argp);
1456 default:
1457 return -ENOIOCTLCMD;
1458 }
1459 return 0;
1460 }
1461
1462 static void rp_send_xchar(struct tty_struct *tty, char ch)
1463 {
1464 struct r_port *info = (struct r_port *) tty->driver_data;
1465 CHANNEL_t *cp;
1466
1467 if (rocket_paranoia_check(info, "rp_send_xchar"))
1468 return;
1469
1470 cp = &info->channel;
1471 if (sGetTxCnt(cp))
1472 sWriteTxPrioByte(cp, ch);
1473 else
1474 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1475 }
1476
1477 static void rp_throttle(struct tty_struct *tty)
1478 {
1479 struct r_port *info = (struct r_port *) tty->driver_data;
1480 CHANNEL_t *cp;
1481
1482 #ifdef ROCKET_DEBUG_THROTTLE
1483 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1484 tty->ldisc.chars_in_buffer(tty));
1485 #endif
1486
1487 if (rocket_paranoia_check(info, "rp_throttle"))
1488 return;
1489
1490 cp = &info->channel;
1491 if (I_IXOFF(tty))
1492 rp_send_xchar(tty, STOP_CHAR(tty));
1493
1494 sClrRTS(&info->channel);
1495 }
1496
1497 static void rp_unthrottle(struct tty_struct *tty)
1498 {
1499 struct r_port *info = (struct r_port *) tty->driver_data;
1500 CHANNEL_t *cp;
1501 #ifdef ROCKET_DEBUG_THROTTLE
1502 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1503 tty->ldisc.chars_in_buffer(tty));
1504 #endif
1505
1506 if (rocket_paranoia_check(info, "rp_throttle"))
1507 return;
1508
1509 cp = &info->channel;
1510 if (I_IXOFF(tty))
1511 rp_send_xchar(tty, START_CHAR(tty));
1512
1513 sSetRTS(&info->channel);
1514 }
1515
1516 /*
1517 * ------------------------------------------------------------
1518 * rp_stop() and rp_start()
1519 *
1520 * This routines are called before setting or resetting tty->stopped.
1521 * They enable or disable transmitter interrupts, as necessary.
1522 * ------------------------------------------------------------
1523 */
1524 static void rp_stop(struct tty_struct *tty)
1525 {
1526 struct r_port *info = (struct r_port *) tty->driver_data;
1527
1528 #ifdef ROCKET_DEBUG_FLOW
1529 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1530 info->xmit_cnt, info->xmit_fifo_room);
1531 #endif
1532
1533 if (rocket_paranoia_check(info, "rp_stop"))
1534 return;
1535
1536 if (sGetTxCnt(&info->channel))
1537 sDisTransmit(&info->channel);
1538 }
1539
1540 static void rp_start(struct tty_struct *tty)
1541 {
1542 struct r_port *info = (struct r_port *) tty->driver_data;
1543
1544 #ifdef ROCKET_DEBUG_FLOW
1545 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1546 info->xmit_cnt, info->xmit_fifo_room);
1547 #endif
1548
1549 if (rocket_paranoia_check(info, "rp_stop"))
1550 return;
1551
1552 sEnTransmit(&info->channel);
1553 set_bit((info->aiop * 8) + info->chan,
1554 (void *) &xmit_flags[info->board]);
1555 }
1556
1557 /*
1558 * rp_wait_until_sent() --- wait until the transmitter is empty
1559 */
1560 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1561 {
1562 struct r_port *info = (struct r_port *) tty->driver_data;
1563 CHANNEL_t *cp;
1564 unsigned long orig_jiffies;
1565 int check_time, exit_time;
1566 int txcnt;
1567
1568 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1569 return;
1570
1571 cp = &info->channel;
1572
1573 orig_jiffies = jiffies;
1574 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1575 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
1576 jiffies);
1577 printk(KERN_INFO "cps=%d...", info->cps);
1578 #endif
1579 while (1) {
1580 txcnt = sGetTxCnt(cp);
1581 if (!txcnt) {
1582 if (sGetChanStatusLo(cp) & TXSHRMT)
1583 break;
1584 check_time = (HZ / info->cps) / 5;
1585 } else {
1586 check_time = HZ * txcnt / info->cps;
1587 }
1588 if (timeout) {
1589 exit_time = orig_jiffies + timeout - jiffies;
1590 if (exit_time <= 0)
1591 break;
1592 if (exit_time < check_time)
1593 check_time = exit_time;
1594 }
1595 if (check_time == 0)
1596 check_time = 1;
1597 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1598 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
1599 #endif
1600 msleep_interruptible(jiffies_to_msecs(check_time));
1601 if (signal_pending(current))
1602 break;
1603 }
1604 current->state = TASK_RUNNING;
1605 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1606 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1607 #endif
1608 }
1609
1610 /*
1611 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1612 */
1613 static void rp_hangup(struct tty_struct *tty)
1614 {
1615 CHANNEL_t *cp;
1616 struct r_port *info = (struct r_port *) tty->driver_data;
1617
1618 if (rocket_paranoia_check(info, "rp_hangup"))
1619 return;
1620
1621 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1622 printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
1623 #endif
1624 rp_flush_buffer(tty);
1625 if (info->flags & ROCKET_CLOSING)
1626 return;
1627 if (info->count)
1628 atomic_dec(&rp_num_ports_open);
1629 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1630
1631 info->count = 0;
1632 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1633 info->tty = NULL;
1634
1635 cp = &info->channel;
1636 sDisRxFIFO(cp);
1637 sDisTransmit(cp);
1638 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1639 sDisCTSFlowCtl(cp);
1640 sDisTxSoftFlowCtl(cp);
1641 sClrTxXOFF(cp);
1642 info->flags &= ~ROCKET_INITIALIZED;
1643
1644 wake_up_interruptible(&info->open_wait);
1645 }
1646
1647 /*
1648 * Exception handler - write char routine. The RocketPort driver uses a
1649 * double-buffering strategy, with the twist that if the in-memory CPU
1650 * buffer is empty, and there's space in the transmit FIFO, the
1651 * writing routines will write directly to transmit FIFO.
1652 * Write buffer and counters protected by spinlocks
1653 */
1654 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1655 {
1656 struct r_port *info = (struct r_port *) tty->driver_data;
1657 CHANNEL_t *cp;
1658 unsigned long flags;
1659
1660 if (rocket_paranoia_check(info, "rp_put_char"))
1661 return;
1662
1663 /* Grab the port write semaphore, locking out other processes that try to write to this port */
1664 down(&info->write_sem);
1665
1666 #ifdef ROCKET_DEBUG_WRITE
1667 printk(KERN_INFO "rp_put_char %c...", ch);
1668 #endif
1669
1670 spin_lock_irqsave(&info->slock, flags);
1671 cp = &info->channel;
1672
1673 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1674 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1675
1676 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1677 info->xmit_buf[info->xmit_head++] = ch;
1678 info->xmit_head &= XMIT_BUF_SIZE - 1;
1679 info->xmit_cnt++;
1680 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1681 } else {
1682 sOutB(sGetTxRxDataIO(cp), ch);
1683 info->xmit_fifo_room--;
1684 }
1685 spin_unlock_irqrestore(&info->slock, flags);
1686 up(&info->write_sem);
1687 }
1688
1689 /*
1690 * Exception handler - write routine, called when user app writes to the device.
1691 * A per port write semaphore is used to protect from another process writing to
1692 * this port at the same time. This other process could be running on the other CPU
1693 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1694 * Spinlocks protect the info xmit members.
1695 */
1696 static int rp_write(struct tty_struct *tty,
1697 const unsigned char *buf, int count)
1698 {
1699 struct r_port *info = (struct r_port *) tty->driver_data;
1700 CHANNEL_t *cp;
1701 const unsigned char *b;
1702 int c, retval = 0;
1703 unsigned long flags;
1704
1705 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1706 return 0;
1707
1708 down_interruptible(&info->write_sem);
1709
1710 #ifdef ROCKET_DEBUG_WRITE
1711 printk(KERN_INFO "rp_write %d chars...", count);
1712 #endif
1713 cp = &info->channel;
1714
1715 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1716 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1717
1718 /*
1719 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1720 * into FIFO. Use the write queue for temp storage.
1721 */
1722 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1723 c = min(count, info->xmit_fifo_room);
1724 b = buf;
1725
1726 /* Push data into FIFO, 2 bytes at a time */
1727 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1728
1729 /* If there is a byte remaining, write it */
1730 if (c & 1)
1731 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1732
1733 retval += c;
1734 buf += c;
1735 count -= c;
1736
1737 spin_lock_irqsave(&info->slock, flags);
1738 info->xmit_fifo_room -= c;
1739 spin_unlock_irqrestore(&info->slock, flags);
1740 }
1741
1742 /* If count is zero, we wrote it all and are done */
1743 if (!count)
1744 goto end;
1745
1746 /* Write remaining data into the port's xmit_buf */
1747 while (1) {
1748 if (info->tty == 0) /* Seemingly obligatory check... */
1749 goto end;
1750
1751 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1752 if (c <= 0)
1753 break;
1754
1755 b = buf;
1756 memcpy(info->xmit_buf + info->xmit_head, b, c);
1757
1758 spin_lock_irqsave(&info->slock, flags);
1759 info->xmit_head =
1760 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1761 info->xmit_cnt += c;
1762 spin_unlock_irqrestore(&info->slock, flags);
1763
1764 buf += c;
1765 count -= c;
1766 retval += c;
1767 }
1768
1769 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1770 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1771
1772 end:
1773 if (info->xmit_cnt < WAKEUP_CHARS) {
1774 tty_wakeup(tty);
1775 wake_up_interruptible(&tty->write_wait);
1776 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1777 wake_up_interruptible(&tty->poll_wait);
1778 #endif
1779 }
1780 up(&info->write_sem);
1781 return retval;
1782 }
1783
1784 /*
1785 * Return the number of characters that can be sent. We estimate
1786 * only using the in-memory transmit buffer only, and ignore the
1787 * potential space in the transmit FIFO.
1788 */
1789 static int rp_write_room(struct tty_struct *tty)
1790 {
1791 struct r_port *info = (struct r_port *) tty->driver_data;
1792 int ret;
1793
1794 if (rocket_paranoia_check(info, "rp_write_room"))
1795 return 0;
1796
1797 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1798 if (ret < 0)
1799 ret = 0;
1800 #ifdef ROCKET_DEBUG_WRITE
1801 printk(KERN_INFO "rp_write_room returns %d...", ret);
1802 #endif
1803 return ret;
1804 }
1805
1806 /*
1807 * Return the number of characters in the buffer. Again, this only
1808 * counts those characters in the in-memory transmit buffer.
1809 */
1810 static int rp_chars_in_buffer(struct tty_struct *tty)
1811 {
1812 struct r_port *info = (struct r_port *) tty->driver_data;
1813 CHANNEL_t *cp;
1814
1815 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1816 return 0;
1817
1818 cp = &info->channel;
1819
1820 #ifdef ROCKET_DEBUG_WRITE
1821 printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
1822 #endif
1823 return info->xmit_cnt;
1824 }
1825
1826 /*
1827 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1828 * r_port struct for the port. Note that spinlock are used to protect info members,
1829 * do not call this function if the spinlock is already held.
1830 */
1831 static void rp_flush_buffer(struct tty_struct *tty)
1832 {
1833 struct r_port *info = (struct r_port *) tty->driver_data;
1834 CHANNEL_t *cp;
1835 unsigned long flags;
1836
1837 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1838 return;
1839
1840 spin_lock_irqsave(&info->slock, flags);
1841 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1842 spin_unlock_irqrestore(&info->slock, flags);
1843
1844 wake_up_interruptible(&tty->write_wait);
1845 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1846 wake_up_interruptible(&tty->poll_wait);
1847 #endif
1848 tty_wakeup(tty);
1849
1850 cp = &info->channel;
1851 sFlushTxFIFO(cp);
1852 }
1853
1854 #ifdef CONFIG_PCI
1855
1856 /*
1857 * Called when a PCI card is found. Retrieves and stores model information,
1858 * init's aiopic and serial port hardware.
1859 * Inputs: i is the board number (0-n)
1860 */
1861 static __init int register_PCI(int i, struct pci_dev *dev)
1862 {
1863 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1864 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1865 char *str, *board_type;
1866 CONTROLLER_t *ctlp;
1867
1868 int fast_clock = 0;
1869 int altChanRingIndicator = 0;
1870 int ports_per_aiop = 8;
1871 int ret;
1872 unsigned int class_rev;
1873 WordIO_t ConfigIO = 0;
1874 ByteIO_t UPCIRingInd = 0;
1875
1876 if (!dev || pci_enable_device(dev))
1877 return 0;
1878
1879 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1880 ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1881
1882 if (ret) {
1883 printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n");
1884 return 0;
1885 }
1886
1887 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1888 rocketModel[i].loadrm2 = 0;
1889 rocketModel[i].startingPortNumber = nextLineNumber;
1890
1891 /* Depending on the model, set up some config variables */
1892 switch (dev->device) {
1893 case PCI_DEVICE_ID_RP4QUAD:
1894 str = "Quadcable";
1895 max_num_aiops = 1;
1896 ports_per_aiop = 4;
1897 rocketModel[i].model = MODEL_RP4QUAD;
1898 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1899 rocketModel[i].numPorts = 4;
1900 break;
1901 case PCI_DEVICE_ID_RP8OCTA:
1902 str = "Octacable";
1903 max_num_aiops = 1;
1904 rocketModel[i].model = MODEL_RP8OCTA;
1905 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1906 rocketModel[i].numPorts = 8;
1907 break;
1908 case PCI_DEVICE_ID_URP8OCTA:
1909 str = "Octacable";
1910 max_num_aiops = 1;
1911 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1912 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1913 rocketModel[i].numPorts = 8;
1914 break;
1915 case PCI_DEVICE_ID_RP8INTF:
1916 str = "8";
1917 max_num_aiops = 1;
1918 rocketModel[i].model = MODEL_RP8INTF;
1919 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1920 rocketModel[i].numPorts = 8;
1921 break;
1922 case PCI_DEVICE_ID_URP8INTF:
1923 str = "8";
1924 max_num_aiops = 1;
1925 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1926 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1927 rocketModel[i].numPorts = 8;
1928 break;
1929 case PCI_DEVICE_ID_RP8J:
1930 str = "8J";
1931 max_num_aiops = 1;
1932 rocketModel[i].model = MODEL_RP8J;
1933 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1934 rocketModel[i].numPorts = 8;
1935 break;
1936 case PCI_DEVICE_ID_RP4J:
1937 str = "4J";
1938 max_num_aiops = 1;
1939 ports_per_aiop = 4;
1940 rocketModel[i].model = MODEL_RP4J;
1941 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1942 rocketModel[i].numPorts = 4;
1943 break;
1944 case PCI_DEVICE_ID_RP8SNI:
1945 str = "8 (DB78 Custom)";
1946 max_num_aiops = 1;
1947 rocketModel[i].model = MODEL_RP8SNI;
1948 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1949 rocketModel[i].numPorts = 8;
1950 break;
1951 case PCI_DEVICE_ID_RP16SNI:
1952 str = "16 (DB78 Custom)";
1953 max_num_aiops = 2;
1954 rocketModel[i].model = MODEL_RP16SNI;
1955 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1956 rocketModel[i].numPorts = 16;
1957 break;
1958 case PCI_DEVICE_ID_RP16INTF:
1959 str = "16";
1960 max_num_aiops = 2;
1961 rocketModel[i].model = MODEL_RP16INTF;
1962 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1963 rocketModel[i].numPorts = 16;
1964 break;
1965 case PCI_DEVICE_ID_URP16INTF:
1966 str = "16";
1967 max_num_aiops = 2;
1968 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1969 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1970 rocketModel[i].numPorts = 16;
1971 break;
1972 case PCI_DEVICE_ID_CRP16INTF:
1973 str = "16";
1974 max_num_aiops = 2;
1975 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1976 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1977 rocketModel[i].numPorts = 16;
1978 break;
1979 case PCI_DEVICE_ID_RP32INTF:
1980 str = "32";
1981 max_num_aiops = 4;
1982 rocketModel[i].model = MODEL_RP32INTF;
1983 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1984 rocketModel[i].numPorts = 32;
1985 break;
1986 case PCI_DEVICE_ID_URP32INTF:
1987 str = "32";
1988 max_num_aiops = 4;
1989 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1990 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1991 rocketModel[i].numPorts = 32;
1992 break;
1993 case PCI_DEVICE_ID_RPP4:
1994 str = "Plus Quadcable";
1995 max_num_aiops = 1;
1996 ports_per_aiop = 4;
1997 altChanRingIndicator++;
1998 fast_clock++;
1999 rocketModel[i].model = MODEL_RPP4;
2000 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2001 rocketModel[i].numPorts = 4;
2002 break;
2003 case PCI_DEVICE_ID_RPP8:
2004 str = "Plus Octacable";
2005 max_num_aiops = 2;
2006 ports_per_aiop = 4;
2007 altChanRingIndicator++;
2008 fast_clock++;
2009 rocketModel[i].model = MODEL_RPP8;
2010 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2011 rocketModel[i].numPorts = 8;
2012 break;
2013 case PCI_DEVICE_ID_RP2_232:
2014 str = "Plus 2 (RS-232)";
2015 max_num_aiops = 1;
2016 ports_per_aiop = 2;
2017 altChanRingIndicator++;
2018 fast_clock++;
2019 rocketModel[i].model = MODEL_RP2_232;
2020 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2021 rocketModel[i].numPorts = 2;
2022 break;
2023 case PCI_DEVICE_ID_RP2_422:
2024 str = "Plus 2 (RS-422)";
2025 max_num_aiops = 1;
2026 ports_per_aiop = 2;
2027 altChanRingIndicator++;
2028 fast_clock++;
2029 rocketModel[i].model = MODEL_RP2_422;
2030 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2031 rocketModel[i].numPorts = 2;
2032 break;
2033 case PCI_DEVICE_ID_RP6M:
2034
2035 max_num_aiops = 1;
2036 ports_per_aiop = 6;
2037 str = "6-port";
2038
2039 /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */
2040 if ((class_rev & 0xFF) == 1) {
2041 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2042 rocketModel[i].loadrm2 = 1;
2043 } else {
2044 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2045 }
2046
2047 rocketModel[i].model = MODEL_RP6M;
2048 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2049 rocketModel[i].numPorts = 6;
2050 break;
2051 case PCI_DEVICE_ID_RP4M:
2052 max_num_aiops = 1;
2053 ports_per_aiop = 4;
2054 str = "4-port";
2055 if ((class_rev & 0xFF) == 1) {
2056 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2057 rocketModel[i].loadrm2 = 1;
2058 } else {
2059 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2060 }
2061
2062 rocketModel[i].model = MODEL_RP4M;
2063 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2064 rocketModel[i].numPorts = 4;
2065 break;
2066 default:
2067 str = "(unknown/unsupported)";
2068 max_num_aiops = 0;
2069 break;
2070 }
2071
2072 /*
2073 * Check for UPCI boards.
2074 */
2075
2076 switch (dev->device) {
2077 case PCI_DEVICE_ID_URP32INTF:
2078 case PCI_DEVICE_ID_URP8INTF:
2079 case PCI_DEVICE_ID_URP16INTF:
2080 case PCI_DEVICE_ID_CRP16INTF:
2081 case PCI_DEVICE_ID_URP8OCTA:
2082 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2083 ConfigIO = pci_resource_start(dev, 1);
2084 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2085 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2086
2087 /*
2088 * Check for octa or quad cable.
2089 */
2090 if (!
2091 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2092 PCI_GPIO_CTRL_8PORT)) {
2093 str = "Quadcable";
2094 ports_per_aiop = 4;
2095 rocketModel[i].numPorts = 4;
2096 }
2097 }
2098 break;
2099 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2100 str = "8 ports";
2101 max_num_aiops = 1;
2102 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2103 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2104 rocketModel[i].numPorts = 8;
2105 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2106 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2107 ConfigIO = pci_resource_start(dev, 1);
2108 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2109 break;
2110 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2111 str = "4 ports";
2112 max_num_aiops = 1;
2113 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2114 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2115 rocketModel[i].numPorts = 4;
2116 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2117 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2118 ConfigIO = pci_resource_start(dev, 1);
2119 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2120 break;
2121 default:
2122 break;
2123 }
2124
2125 switch (rcktpt_type[i]) {
2126 case ROCKET_TYPE_MODEM:
2127 board_type = "RocketModem";
2128 break;
2129 case ROCKET_TYPE_MODEMII:
2130 board_type = "RocketModem II";
2131 break;
2132 case ROCKET_TYPE_MODEMIII:
2133 board_type = "RocketModem III";
2134 break;
2135 default:
2136 board_type = "RocketPort";
2137 break;
2138 }
2139
2140 if (fast_clock) {
2141 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2142 rp_baud_base[i] = 921600;
2143 } else {
2144 /*
2145 * If support_low_speed is set, use the slow clock
2146 * prescale, which supports 50 bps
2147 */
2148 if (support_low_speed) {
2149 /* mod 9 (divide by 10) prescale */
2150 sClockPrescale = 0x19;
2151 rp_baud_base[i] = 230400;
2152 } else {
2153 /* mod 4 (devide by 5) prescale */
2154 sClockPrescale = 0x14;
2155 rp_baud_base[i] = 460800;
2156 }
2157 }
2158
2159 for (aiop = 0; aiop < max_num_aiops; aiop++)
2160 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2161 ctlp = sCtlNumToCtlPtr(i);
2162 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2163 for (aiop = 0; aiop < max_num_aiops; aiop++)
2164 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2165
2166 printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
2167 "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
2168 rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
2169 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2170 rocketModel[i].modelString,
2171 rocketModel[i].startingPortNumber,
2172 rocketModel[i].startingPortNumber +
2173 rocketModel[i].numPorts - 1);
2174
2175 if (num_aiops <= 0) {
2176 rcktpt_io_addr[i] = 0;
2177 return (0);
2178 }
2179 is_PCI[i] = 1;
2180
2181 /* Reset the AIOPIC, init the serial ports */
2182 for (aiop = 0; aiop < num_aiops; aiop++) {
2183 sResetAiopByNum(ctlp, aiop);
2184 num_chan = ports_per_aiop;
2185 for (chan = 0; chan < num_chan; chan++)
2186 init_r_port(i, aiop, chan, dev);
2187 }
2188
2189 /* Rocket modems must be reset */
2190 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2191 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2192 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2193 num_chan = ports_per_aiop;
2194 for (chan = 0; chan < num_chan; chan++)
2195 sPCIModemReset(ctlp, chan, 1);
2196 mdelay(500);
2197 for (chan = 0; chan < num_chan; chan++)
2198 sPCIModemReset(ctlp, chan, 0);
2199 mdelay(500);
2200 rmSpeakerReset(ctlp, rocketModel[i].model);
2201 }
2202 return (1);
2203 }
2204
2205 /*
2206 * Probes for PCI cards, inits them if found
2207 * Input: board_found = number of ISA boards already found, or the
2208 * starting board number
2209 * Returns: Number of PCI boards found
2210 */
2211 static int __init init_PCI(int boards_found)
2212 {
2213 struct pci_dev *dev = NULL;
2214 int count = 0;
2215
2216 /* Work through the PCI device list, pulling out ours */
2217 while ((dev = pci_find_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2218 if (register_PCI(count + boards_found, dev))
2219 count++;
2220 }
2221 return (count);
2222 }
2223
2224 #endif /* CONFIG_PCI */
2225
2226 /*
2227 * Probes for ISA cards
2228 * Input: i = the board number to look for
2229 * Returns: 1 if board found, 0 else
2230 */
2231 static int __init init_ISA(int i)
2232 {
2233 int num_aiops, num_chan = 0, total_num_chan = 0;
2234 int aiop, chan;
2235 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2236 CONTROLLER_t *ctlp;
2237 char *type_string;
2238
2239 /* If io_addr is zero, no board configured */
2240 if (rcktpt_io_addr[i] == 0)
2241 return (0);
2242
2243 /* Reserve the IO region */
2244 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2245 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
2246 rcktpt_io_addr[i] = 0;
2247 return (0);
2248 }
2249
2250 ctlp = sCtlNumToCtlPtr(i);
2251
2252 ctlp->boardType = rcktpt_type[i];
2253
2254 switch (rcktpt_type[i]) {
2255 case ROCKET_TYPE_PC104:
2256 type_string = "(PC104)";
2257 break;
2258 case ROCKET_TYPE_MODEM:
2259 type_string = "(RocketModem)";
2260 break;
2261 case ROCKET_TYPE_MODEMII:
2262 type_string = "(RocketModem II)";
2263 break;
2264 default:
2265 type_string = "";
2266 break;
2267 }
2268
2269 /*
2270 * If support_low_speed is set, use the slow clock prescale,
2271 * which supports 50 bps
2272 */
2273 if (support_low_speed) {
2274 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2275 rp_baud_base[i] = 230400;
2276 } else {
2277 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2278 rp_baud_base[i] = 460800;
2279 }
2280
2281 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2282 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2283
2284 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2285
2286 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2287 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2288 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2289 }
2290
2291 /* If something went wrong initing the AIOP's release the ISA IO memory */
2292 if (num_aiops <= 0) {
2293 release_region(rcktpt_io_addr[i], 64);
2294 rcktpt_io_addr[i] = 0;
2295 return (0);
2296 }
2297
2298 rocketModel[i].startingPortNumber = nextLineNumber;
2299
2300 for (aiop = 0; aiop < num_aiops; aiop++) {
2301 sResetAiopByNum(ctlp, aiop);
2302 sEnAiop(ctlp, aiop);
2303 num_chan = sGetAiopNumChan(ctlp, aiop);
2304 total_num_chan += num_chan;
2305 for (chan = 0; chan < num_chan; chan++)
2306 init_r_port(i, aiop, chan, NULL);
2307 }
2308 is_PCI[i] = 0;
2309 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2310 num_chan = sGetAiopNumChan(ctlp, 0);
2311 total_num_chan = num_chan;
2312 for (chan = 0; chan < num_chan; chan++)
2313 sModemReset(ctlp, chan, 1);
2314 mdelay(500);
2315 for (chan = 0; chan < num_chan; chan++)
2316 sModemReset(ctlp, chan, 0);
2317 mdelay(500);
2318 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2319 } else {
2320 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2321 }
2322 rocketModel[i].numPorts = total_num_chan;
2323 rocketModel[i].model = MODEL_ISA;
2324
2325 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2326 i, rcktpt_io_addr[i], num_aiops, type_string);
2327
2328 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2329 rocketModel[i].modelString,
2330 rocketModel[i].startingPortNumber,
2331 rocketModel[i].startingPortNumber +
2332 rocketModel[i].numPorts - 1);
2333
2334 return (1);
2335 }
2336
2337 static struct tty_operations rocket_ops = {
2338 .open = rp_open,
2339 .close = rp_close,
2340 .write = rp_write,
2341 .put_char = rp_put_char,
2342 .write_room = rp_write_room,
2343 .chars_in_buffer = rp_chars_in_buffer,
2344 .flush_buffer = rp_flush_buffer,
2345 .ioctl = rp_ioctl,
2346 .throttle = rp_throttle,
2347 .unthrottle = rp_unthrottle,
2348 .set_termios = rp_set_termios,
2349 .stop = rp_stop,
2350 .start = rp_start,
2351 .hangup = rp_hangup,
2352 .break_ctl = rp_break,
2353 .send_xchar = rp_send_xchar,
2354 .wait_until_sent = rp_wait_until_sent,
2355 .tiocmget = rp_tiocmget,
2356 .tiocmset = rp_tiocmset,
2357 };
2358
2359 /*
2360 * The module "startup" routine; it's run when the module is loaded.
2361 */
2362 static int __init rp_init(void)
2363 {
2364 int retval, pci_boards_found, isa_boards_found, i;
2365
2366 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2367 ROCKET_VERSION, ROCKET_DATE);
2368
2369 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2370 if (!rocket_driver)
2371 return -ENOMEM;
2372
2373 /*
2374 * Set up the timer channel.
2375 */
2376 init_timer(&rocket_timer);
2377 rocket_timer.function = rp_do_poll;
2378
2379 /*
2380 * Initialize the array of pointers to our own internal state
2381 * structures.
2382 */
2383 memset(rp_table, 0, sizeof (rp_table));
2384 memset(xmit_flags, 0, sizeof (xmit_flags));
2385
2386 for (i = 0; i < MAX_RP_PORTS; i++)
2387 lineNumbers[i] = 0;
2388 nextLineNumber = 0;
2389 memset(rocketModel, 0, sizeof (rocketModel));
2390
2391 /*
2392 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2393 * zero, use the default controller IO address of board1 + 0x40.
2394 */
2395 if (board1) {
2396 if (controller == 0)
2397 controller = board1 + 0x40;
2398 } else {
2399 controller = 0; /* Used as a flag, meaning no ISA boards */
2400 }
2401
2402 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2403 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2404 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller);
2405 return -EBUSY;
2406 }
2407
2408 /* Store ISA variable retrieved from command line or .conf file. */
2409 rcktpt_io_addr[0] = board1;
2410 rcktpt_io_addr[1] = board2;
2411 rcktpt_io_addr[2] = board3;
2412 rcktpt_io_addr[3] = board4;
2413
2414 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2415 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2416 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2417 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2418 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2419 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2420 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2421 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2422
2423 /*
2424 * Set up the tty driver structure and then register this
2425 * driver with the tty layer.
2426 */
2427
2428 rocket_driver->owner = THIS_MODULE;
2429 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2430 rocket_driver->name = "ttyR";
2431 rocket_driver->driver_name = "Comtrol RocketPort";
2432 rocket_driver->major = TTY_ROCKET_MAJOR;
2433 rocket_driver->minor_start = 0;
2434 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2435 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2436 rocket_driver->init_termios = tty_std_termios;
2437 rocket_driver->init_termios.c_cflag =
2438 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2439 #ifdef ROCKET_SOFT_FLOW
2440 rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
2441 #endif
2442 tty_set_operations(rocket_driver, &rocket_ops);
2443
2444 retval = tty_register_driver(rocket_driver);
2445 if (retval < 0) {
2446 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
2447 put_tty_driver(rocket_driver);
2448 return -1;
2449 }
2450
2451 #ifdef ROCKET_DEBUG_OPEN
2452 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2453 #endif
2454
2455 /*
2456 * OK, let's probe each of the controllers looking for boards. Any boards found
2457 * will be initialized here.
2458 */
2459 isa_boards_found = 0;
2460 pci_boards_found = 0;
2461
2462 for (i = 0; i < NUM_BOARDS; i++) {
2463 if (init_ISA(i))
2464 isa_boards_found++;
2465 }
2466
2467 #ifdef CONFIG_PCI
2468 if (isa_boards_found < NUM_BOARDS)
2469 pci_boards_found = init_PCI(isa_boards_found);
2470 #endif
2471
2472 max_board = pci_boards_found + isa_boards_found;
2473
2474 if (max_board == 0) {
2475 printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
2476 del_timer_sync(&rocket_timer);
2477 tty_unregister_driver(rocket_driver);
2478 put_tty_driver(rocket_driver);
2479 return -ENXIO;
2480 }
2481
2482 return 0;
2483 }
2484
2485
2486 static void rp_cleanup_module(void)
2487 {
2488 int retval;
2489 int i;
2490
2491 del_timer_sync(&rocket_timer);
2492
2493 retval = tty_unregister_driver(rocket_driver);
2494 if (retval)
2495 printk(KERN_INFO "Error %d while trying to unregister "
2496 "rocketport driver\n", -retval);
2497 put_tty_driver(rocket_driver);
2498
2499 for (i = 0; i < MAX_RP_PORTS; i++)
2500 kfree(rp_table[i]);
2501
2502 for (i = 0; i < NUM_BOARDS; i++) {
2503 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2504 continue;
2505 release_region(rcktpt_io_addr[i], 64);
2506 }
2507 if (controller)
2508 release_region(controller, 4);
2509 }
2510
2511 /***************************************************************************
2512 Function: sInitController
2513 Purpose: Initialization of controller global registers and controller
2514 structure.
2515 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2516 IRQNum,Frequency,PeriodicOnly)
2517 CONTROLLER_T *CtlP; Ptr to controller structure
2518 int CtlNum; Controller number
2519 ByteIO_t MudbacIO; Mudbac base I/O address.
2520 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2521 This list must be in the order the AIOPs will be found on the
2522 controller. Once an AIOP in the list is not found, it is
2523 assumed that there are no more AIOPs on the controller.
2524 int AiopIOListSize; Number of addresses in AiopIOList
2525 int IRQNum; Interrupt Request number. Can be any of the following:
2526 0: Disable global interrupts
2527 3: IRQ 3
2528 4: IRQ 4
2529 5: IRQ 5
2530 9: IRQ 9
2531 10: IRQ 10
2532 11: IRQ 11
2533 12: IRQ 12
2534 15: IRQ 15
2535 Byte_t Frequency: A flag identifying the frequency
2536 of the periodic interrupt, can be any one of the following:
2537 FREQ_DIS - periodic interrupt disabled
2538 FREQ_137HZ - 137 Hertz
2539 FREQ_69HZ - 69 Hertz
2540 FREQ_34HZ - 34 Hertz
2541 FREQ_17HZ - 17 Hertz
2542 FREQ_9HZ - 9 Hertz
2543 FREQ_4HZ - 4 Hertz
2544 If IRQNum is set to 0 the Frequency parameter is
2545 overidden, it is forced to a value of FREQ_DIS.
2546 int PeriodicOnly: 1 if all interrupts except the periodic
2547 interrupt are to be blocked.
2548 0 is both the periodic interrupt and
2549 other channel interrupts are allowed.
2550 If IRQNum is set to 0 the PeriodicOnly parameter is
2551 overidden, it is forced to a value of 0.
2552 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2553 initialization failed.
2554
2555 Comments:
2556 If periodic interrupts are to be disabled but AIOP interrupts
2557 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2558
2559 If interrupts are to be completely disabled set IRQNum to 0.
2560
2561 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2562 invalid combination.
2563
2564 This function performs initialization of global interrupt modes,
2565 but it does not actually enable global interrupts. To enable
2566 and disable global interrupts use functions sEnGlobalInt() and
2567 sDisGlobalInt(). Enabling of global interrupts is normally not
2568 done until all other initializations are complete.
2569
2570 Even if interrupts are globally enabled, they must also be
2571 individually enabled for each channel that is to generate
2572 interrupts.
2573
2574 Warnings: No range checking on any of the parameters is done.
2575
2576 No context switches are allowed while executing this function.
2577
2578 After this function all AIOPs on the controller are disabled,
2579 they can be enabled with sEnAiop().
2580 */
2581 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2582 ByteIO_t * AiopIOList, int AiopIOListSize,
2583 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2584 {
2585 int i;
2586 ByteIO_t io;
2587 int done;
2588
2589 CtlP->AiopIntrBits = aiop_intr_bits;
2590 CtlP->AltChanRingIndicator = 0;
2591 CtlP->CtlNum = CtlNum;
2592 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2593 CtlP->BusType = isISA;
2594 CtlP->MBaseIO = MudbacIO;
2595 CtlP->MReg1IO = MudbacIO + 1;
2596 CtlP->MReg2IO = MudbacIO + 2;
2597 CtlP->MReg3IO = MudbacIO + 3;
2598 #if 1
2599 CtlP->MReg2 = 0; /* interrupt disable */
2600 CtlP->MReg3 = 0; /* no periodic interrupts */
2601 #else
2602 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2603 CtlP->MReg2 = 0; /* interrupt disable */
2604 CtlP->MReg3 = 0; /* no periodic interrupts */
2605 } else {
2606 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2607 CtlP->MReg3 = Frequency; /* set frequency */
2608 if (PeriodicOnly) { /* periodic interrupt only */
2609 CtlP->MReg3 |= PERIODIC_ONLY;
2610 }
2611 }
2612 #endif
2613 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2614 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2615 sControllerEOI(CtlP); /* clear EOI if warm init */
2616 /* Init AIOPs */
2617 CtlP->NumAiop = 0;
2618 for (i = done = 0; i < AiopIOListSize; i++) {
2619 io = AiopIOList[i];
2620 CtlP->AiopIO[i] = (WordIO_t) io;
2621 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2622 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2623 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2624 if (done)
2625 continue;
2626 sEnAiop(CtlP, i); /* enable the AIOP */
2627 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2628 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2629 done = 1; /* done looking for AIOPs */
2630 else {
2631 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2632 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2633 sOutB(io + _INDX_DATA, sClockPrescale);
2634 CtlP->NumAiop++; /* bump count of AIOPs */
2635 }
2636 sDisAiop(CtlP, i); /* disable AIOP */
2637 }
2638
2639 if (CtlP->NumAiop == 0)
2640 return (-1);
2641 else
2642 return (CtlP->NumAiop);
2643 }
2644
2645 /***************************************************************************
2646 Function: sPCIInitController
2647 Purpose: Initialization of controller global registers and controller
2648 structure.
2649 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2650 IRQNum,Frequency,PeriodicOnly)
2651 CONTROLLER_T *CtlP; Ptr to controller structure
2652 int CtlNum; Controller number
2653 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2654 This list must be in the order the AIOPs will be found on the
2655 controller. Once an AIOP in the list is not found, it is
2656 assumed that there are no more AIOPs on the controller.
2657 int AiopIOListSize; Number of addresses in AiopIOList
2658 int IRQNum; Interrupt Request number. Can be any of the following:
2659 0: Disable global interrupts
2660 3: IRQ 3
2661 4: IRQ 4
2662 5: IRQ 5
2663 9: IRQ 9
2664 10: IRQ 10
2665 11: IRQ 11
2666 12: IRQ 12
2667 15: IRQ 15
2668 Byte_t Frequency: A flag identifying the frequency
2669 of the periodic interrupt, can be any one of the following:
2670 FREQ_DIS - periodic interrupt disabled
2671 FREQ_137HZ - 137 Hertz
2672 FREQ_69HZ - 69 Hertz
2673 FREQ_34HZ - 34 Hertz
2674 FREQ_17HZ - 17 Hertz
2675 FREQ_9HZ - 9 Hertz
2676 FREQ_4HZ - 4 Hertz
2677 If IRQNum is set to 0 the Frequency parameter is
2678 overidden, it is forced to a value of FREQ_DIS.
2679 int PeriodicOnly: 1 if all interrupts except the periodic
2680 interrupt are to be blocked.
2681 0 is both the periodic interrupt and
2682 other channel interrupts are allowed.
2683 If IRQNum is set to 0 the PeriodicOnly parameter is
2684 overidden, it is forced to a value of 0.
2685 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2686 initialization failed.
2687
2688 Comments:
2689 If periodic interrupts are to be disabled but AIOP interrupts
2690 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2691
2692 If interrupts are to be completely disabled set IRQNum to 0.
2693
2694 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2695 invalid combination.
2696
2697 This function performs initialization of global interrupt modes,
2698 but it does not actually enable global interrupts. To enable
2699 and disable global interrupts use functions sEnGlobalInt() and
2700 sDisGlobalInt(). Enabling of global interrupts is normally not
2701 done until all other initializations are complete.
2702
2703 Even if interrupts are globally enabled, they must also be
2704 individually enabled for each channel that is to generate
2705 interrupts.
2706
2707 Warnings: No range checking on any of the parameters is done.
2708
2709 No context switches are allowed while executing this function.
2710
2711 After this function all AIOPs on the controller are disabled,
2712 they can be enabled with sEnAiop().
2713 */
2714 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2715 ByteIO_t * AiopIOList, int AiopIOListSize,
2716 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2717 int PeriodicOnly, int altChanRingIndicator,
2718 int UPCIRingInd)
2719 {
2720 int i;
2721 ByteIO_t io;
2722
2723 CtlP->AltChanRingIndicator = altChanRingIndicator;
2724 CtlP->UPCIRingInd = UPCIRingInd;
2725 CtlP->CtlNum = CtlNum;
2726 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2727 CtlP->BusType = isPCI; /* controller release 1 */
2728
2729 if (ConfigIO) {
2730 CtlP->isUPCI = 1;
2731 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2732 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2733 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2734 } else {
2735 CtlP->isUPCI = 0;
2736 CtlP->PCIIO =
2737 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2738 CtlP->AiopIntrBits = aiop_intr_bits;
2739 }
2740
2741 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2742 /* Init AIOPs */
2743 CtlP->NumAiop = 0;
2744 for (i = 0; i < AiopIOListSize; i++) {
2745 io = AiopIOList[i];
2746 CtlP->AiopIO[i] = (WordIO_t) io;
2747 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2748
2749 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2750 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2751 break; /* done looking for AIOPs */
2752
2753 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2754 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2755 sOutB(io + _INDX_DATA, sClockPrescale);
2756 CtlP->NumAiop++; /* bump count of AIOPs */
2757 }
2758
2759 if (CtlP->NumAiop == 0)
2760 return (-1);
2761 else
2762 return (CtlP->NumAiop);
2763 }
2764
2765 /***************************************************************************
2766 Function: sReadAiopID
2767 Purpose: Read the AIOP idenfication number directly from an AIOP.
2768 Call: sReadAiopID(io)
2769 ByteIO_t io: AIOP base I/O address
2770 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2771 is replace by an identifying number.
2772 Flag AIOPID_NULL if no valid AIOP is found
2773 Warnings: No context switches are allowed while executing this function.
2774
2775 */
2776 static int sReadAiopID(ByteIO_t io)
2777 {
2778 Byte_t AiopID; /* ID byte from AIOP */
2779
2780 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2781 sOutB(io + _CMD_REG, 0x0);
2782 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2783 if (AiopID == 0x06)
2784 return (1);
2785 else /* AIOP does not exist */
2786 return (-1);
2787 }
2788
2789 /***************************************************************************
2790 Function: sReadAiopNumChan
2791 Purpose: Read the number of channels available in an AIOP directly from
2792 an AIOP.
2793 Call: sReadAiopNumChan(io)
2794 WordIO_t io: AIOP base I/O address
2795 Return: int: The number of channels available
2796 Comments: The number of channels is determined by write/reads from identical
2797 offsets within the SRAM address spaces for channels 0 and 4.
2798 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2799 AIOP, otherwise it is an 8 channel.
2800 Warnings: No context switches are allowed while executing this function.
2801 */
2802 static int sReadAiopNumChan(WordIO_t io)
2803 {
2804 Word_t x;
2805 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2806
2807 /* write to chan 0 SRAM */
2808 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2809 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2810 x = sInW(io + _INDX_DATA);
2811 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2812 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2813 return (8);
2814 else
2815 return (4);
2816 }
2817
2818 /***************************************************************************
2819 Function: sInitChan
2820 Purpose: Initialization of a channel and channel structure
2821 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2822 CONTROLLER_T *CtlP; Ptr to controller structure
2823 CHANNEL_T *ChP; Ptr to channel structure
2824 int AiopNum; AIOP number within controller
2825 int ChanNum; Channel number within AIOP
2826 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2827 number exceeds number of channels available in AIOP.
2828 Comments: This function must be called before a channel can be used.
2829 Warnings: No range checking on any of the parameters is done.
2830
2831 No context switches are allowed while executing this function.
2832 */
2833 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2834 int ChanNum)
2835 {
2836 int i;
2837 WordIO_t AiopIO;
2838 WordIO_t ChIOOff;
2839 Byte_t *ChR;
2840 Word_t ChOff;
2841 static Byte_t R[4];
2842 int brd9600;
2843
2844 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2845 return 0; /* exceeds num chans in AIOP */
2846
2847 /* Channel, AIOP, and controller identifiers */
2848 ChP->CtlP = CtlP;
2849 ChP->ChanID = CtlP->AiopID[AiopNum];
2850 ChP->AiopNum = AiopNum;
2851 ChP->ChanNum = ChanNum;
2852
2853 /* Global direct addresses */
2854 AiopIO = CtlP->AiopIO[AiopNum];
2855 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2856 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2857 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2858 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2859 ChP->IndexData = AiopIO + _INDX_DATA;
2860
2861 /* Channel direct addresses */
2862 ChIOOff = AiopIO + ChP->ChanNum * 2;
2863 ChP->TxRxData = ChIOOff + _TD0;
2864 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2865 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2866 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2867
2868 /* Initialize the channel from the RData array */
2869 for (i = 0; i < RDATASIZE; i += 4) {
2870 R[0] = RData[i];
2871 R[1] = RData[i + 1] + 0x10 * ChanNum;
2872 R[2] = RData[i + 2];
2873 R[3] = RData[i + 3];
2874 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2875 }
2876
2877 ChR = ChP->R;
2878 for (i = 0; i < RREGDATASIZE; i += 4) {
2879 ChR[i] = RRegData[i];
2880 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2881 ChR[i + 2] = RRegData[i + 2];
2882 ChR[i + 3] = RRegData[i + 3];
2883 }
2884
2885 /* Indexed registers */
2886 ChOff = (Word_t) ChanNum *0x1000;
2887
2888 if (sClockPrescale == 0x14)
2889 brd9600 = 47;
2890 else
2891 brd9600 = 23;
2892
2893 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2894 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2895 ChP->BaudDiv[2] = (Byte_t) brd9600;
2896 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2897 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2898
2899 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2900 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2901 ChP->TxControl[2] = 0;
2902 ChP->TxControl[3] = 0;
2903 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2904
2905 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2906 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2907 ChP->RxControl[2] = 0;
2908 ChP->RxControl[3] = 0;
2909 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2910
2911 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2912 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2913 ChP->TxEnables[2] = 0;
2914 ChP->TxEnables[3] = 0;
2915 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2916
2917 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2918 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2919 ChP->TxCompare[2] = 0;
2920 ChP->TxCompare[3] = 0;
2921 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2922
2923 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2924 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2925 ChP->TxReplace1[2] = 0;
2926 ChP->TxReplace1[3] = 0;
2927 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2928
2929 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2930 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2931 ChP->TxReplace2[2] = 0;
2932 ChP->TxReplace2[3] = 0;
2933 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2934
2935 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2936 ChP->TxFIFO = ChOff + _TX_FIFO;
2937
2938 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2939 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2940 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2941 sOutW(ChP->IndexData, 0);
2942 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2943 ChP->RxFIFO = ChOff + _RX_FIFO;
2944
2945 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2946 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2947 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2948 sOutW(ChP->IndexData, 0);
2949 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2950 sOutW(ChP->IndexData, 0);
2951 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2952 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2953 sOutB(ChP->IndexData, 0);
2954 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2955 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2956 sOutB(ChP->IndexData, 0);
2957 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2958 sEnRxProcessor(ChP); /* start the Rx processor */
2959
2960 return 1;
2961 }
2962
2963 /***************************************************************************
2964 Function: sStopRxProcessor
2965 Purpose: Stop the receive processor from processing a channel.
2966 Call: sStopRxProcessor(ChP)
2967 CHANNEL_T *ChP; Ptr to channel structure
2968
2969 Comments: The receive processor can be started again with sStartRxProcessor().
2970 This function causes the receive processor to skip over the
2971 stopped channel. It does not stop it from processing other channels.
2972
2973 Warnings: No context switches are allowed while executing this function.
2974
2975 Do not leave the receive processor stopped for more than one
2976 character time.
2977
2978 After calling this function a delay of 4 uS is required to ensure
2979 that the receive processor is no longer processing this channel.
2980 */
2981 static void sStopRxProcessor(CHANNEL_T * ChP)
2982 {
2983 Byte_t R[4];
2984
2985 R[0] = ChP->R[0];
2986 R[1] = ChP->R[1];
2987 R[2] = 0x0a;
2988 R[3] = ChP->R[3];
2989 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
2990 }
2991
2992 /***************************************************************************
2993 Function: sFlushRxFIFO
2994 Purpose: Flush the Rx FIFO
2995 Call: sFlushRxFIFO(ChP)
2996 CHANNEL_T *ChP; Ptr to channel structure
2997 Return: void
2998 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2999 while it is being flushed the receive processor is stopped
3000 and the transmitter is disabled. After these operations a
3001 4 uS delay is done before clearing the pointers to allow
3002 the receive processor to stop. These items are handled inside
3003 this function.
3004 Warnings: No context switches are allowed while executing this function.
3005 */
3006 static void sFlushRxFIFO(CHANNEL_T * ChP)
3007 {
3008 int i;
3009 Byte_t Ch; /* channel number within AIOP */
3010 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3011
3012 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3013 return; /* don't need to flush */
3014
3015 RxFIFOEnabled = 0;
3016 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3017 RxFIFOEnabled = 1;
3018 sDisRxFIFO(ChP); /* disable it */
3019 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3020 sInB(ChP->IntChan); /* depends on bus i/o timing */
3021 }
3022 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3023 Ch = (Byte_t) sGetChanNum(ChP);
3024 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3025 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3026 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3027 sOutW(ChP->IndexData, 0);
3028 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3029 sOutW(ChP->IndexData, 0);
3030 if (RxFIFOEnabled)
3031 sEnRxFIFO(ChP); /* enable Rx FIFO */
3032 }
3033
3034 /***************************************************************************
3035 Function: sFlushTxFIFO
3036 Purpose: Flush the Tx FIFO
3037 Call: sFlushTxFIFO(ChP)
3038 CHANNEL_T *ChP; Ptr to channel structure
3039 Return: void
3040 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3041 while it is being flushed the receive processor is stopped
3042 and the transmitter is disabled. After these operations a
3043 4 uS delay is done before clearing the pointers to allow
3044 the receive processor to stop. These items are handled inside
3045 this function.
3046 Warnings: No context switches are allowed while executing this function.
3047 */
3048 static void sFlushTxFIFO(CHANNEL_T * ChP)
3049 {
3050 int i;
3051 Byte_t Ch; /* channel number within AIOP */
3052 int TxEnabled; /* 1 if transmitter enabled */
3053
3054 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3055 return; /* don't need to flush */
3056
3057 TxEnabled = 0;
3058 if (ChP->TxControl[3] & TX_ENABLE) {
3059 TxEnabled = 1;
3060 sDisTransmit(ChP); /* disable transmitter */
3061 }
3062 sStopRxProcessor(ChP); /* stop Rx processor */
3063 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3064 sInB(ChP->IntChan); /* depends on bus i/o timing */
3065 Ch = (Byte_t) sGetChanNum(ChP);
3066 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3067 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3068 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3069 sOutW(ChP->IndexData, 0);
3070 if (TxEnabled)
3071 sEnTransmit(ChP); /* enable transmitter */
3072 sStartRxProcessor(ChP); /* restart Rx processor */
3073 }
3074
3075 /***************************************************************************
3076 Function: sWriteTxPrioByte
3077 Purpose: Write a byte of priority transmit data to a channel
3078 Call: sWriteTxPrioByte(ChP,Data)
3079 CHANNEL_T *ChP; Ptr to channel structure
3080 Byte_t Data; The transmit data byte
3081
3082 Return: int: 1 if the bytes is successfully written, otherwise 0.
3083
3084 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3085
3086 Warnings: No context switches are allowed while executing this function.
3087 */
3088 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3089 {
3090 Byte_t DWBuf[4]; /* buffer for double word writes */
3091 Word_t *WordPtr; /* must be far because Win SS != DS */
3092 register DWordIO_t IndexAddr;
3093
3094 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3095 IndexAddr = ChP->IndexAddr;
3096 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3097 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3098 return (0); /* nothing sent */
3099
3100 WordPtr = (Word_t *) (&DWBuf[0]);
3101 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3102
3103 DWBuf[2] = Data; /* data byte value */
3104 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3105
3106 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3107
3108 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3109 DWBuf[3] = 0; /* priority buffer pointer */
3110 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3111 } else { /* write it to Tx FIFO */
3112
3113 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3114 }
3115 return (1); /* 1 byte sent */
3116 }
3117
3118 /***************************************************************************
3119 Function: sEnInterrupts
3120 Purpose: Enable one or more interrupts for a channel
3121 Call: sEnInterrupts(ChP,Flags)
3122 CHANNEL_T *ChP; Ptr to channel structure
3123 Word_t Flags: Interrupt enable flags, can be any combination
3124 of the following flags:
3125 TXINT_EN: Interrupt on Tx FIFO empty
3126 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3127 sSetRxTrigger())
3128 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3129 MCINT_EN: Interrupt on modem input change
3130 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3131 Interrupt Channel Register.
3132 Return: void
3133 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3134 enabled. If an interrupt enable flag is not set in Flags, that
3135 interrupt will not be changed. Interrupts can be disabled with
3136 function sDisInterrupts().
3137
3138 This function sets the appropriate bit for the channel in the AIOP's
3139 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3140 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3141
3142 Interrupts must also be globally enabled before channel interrupts
3143 will be passed on to the host. This is done with function
3144 sEnGlobalInt().
3145
3146 In some cases it may be desirable to disable interrupts globally but
3147 enable channel interrupts. This would allow the global interrupt
3148 status register to be used to determine which AIOPs need service.
3149 */
3150 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3151 {
3152 Byte_t Mask; /* Interrupt Mask Register */
3153
3154 ChP->RxControl[2] |=
3155 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3156
3157 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3158
3159 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3160
3161 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3162
3163 if (Flags & CHANINT_EN) {
3164 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3165 sOutB(ChP->IntMask, Mask);
3166 }
3167 }
3168
3169 /***************************************************************************
3170 Function: sDisInterrupts
3171 Purpose: Disable one or more interrupts for a channel
3172 Call: sDisInterrupts(ChP,Flags)
3173 CHANNEL_T *ChP; Ptr to channel structure
3174 Word_t Flags: Interrupt flags, can be any combination
3175 of the following flags:
3176 TXINT_EN: Interrupt on Tx FIFO empty
3177 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3178 sSetRxTrigger())
3179 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3180 MCINT_EN: Interrupt on modem input change
3181 CHANINT_EN: Disable channel interrupt signal to the
3182 AIOP's Interrupt Channel Register.
3183 Return: void
3184 Comments: If an interrupt flag is set in Flags, that interrupt will be
3185 disabled. If an interrupt flag is not set in Flags, that
3186 interrupt will not be changed. Interrupts can be enabled with
3187 function sEnInterrupts().
3188
3189 This function clears the appropriate bit for the channel in the AIOP's
3190 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3191 this channel's bit from being set in the AIOP's Interrupt Channel
3192 Register.
3193 */
3194 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3195 {
3196 Byte_t Mask; /* Interrupt Mask Register */
3197
3198 ChP->RxControl[2] &=
3199 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3200 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3201 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3202 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3203
3204 if (Flags & CHANINT_EN) {
3205 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3206 sOutB(ChP->IntMask, Mask);
3207 }
3208 }
3209
3210 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3211 {
3212 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3213 }
3214
3215 /*
3216 * Not an official SSCI function, but how to reset RocketModems.
3217 * ISA bus version
3218 */
3219 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3220 {
3221 ByteIO_t addr;
3222 Byte_t val;
3223
3224 addr = CtlP->AiopIO[0] + 0x400;
3225 val = sInB(CtlP->MReg3IO);
3226 /* if AIOP[1] is not enabled, enable it */
3227 if ((val & 2) == 0) {
3228 val = sInB(CtlP->MReg2IO);
3229 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3230 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3231 }
3232
3233 sEnAiop(CtlP, 1);
3234 if (!on)
3235 addr += 8;
3236 sOutB(addr + chan, 0); /* apply or remove reset */
3237 sDisAiop(CtlP, 1);
3238 }
3239
3240 /*
3241 * Not an official SSCI function, but how to reset RocketModems.
3242 * PCI bus version
3243 */
3244 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3245 {
3246 ByteIO_t addr;
3247
3248 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3249 if (!on)
3250 addr += 8;
3251 sOutB(addr + chan, 0); /* apply or remove reset */
3252 }
3253
3254 /* Resets the speaker controller on RocketModem II and III devices */
3255 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3256 {
3257 ByteIO_t addr;
3258
3259 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3260 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3261 addr = CtlP->AiopIO[0] + 0x4F;
3262 sOutB(addr, 0);
3263 }
3264
3265 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3266 if ((model == MODEL_UPCI_RM3_8PORT)
3267 || (model == MODEL_UPCI_RM3_4PORT)) {
3268 addr = CtlP->AiopIO[0] + 0x88;
3269 sOutB(addr, 0);
3270 }
3271 }
3272
3273 /* Returns the line number given the controller (board), aiop and channel number */
3274 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3275 {
3276 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3277 }
3278
3279 /*
3280 * Stores the line number associated with a given controller (board), aiop
3281 * and channel number.
3282 * Returns: The line number assigned
3283 */
3284 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3285 {
3286 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3287 return (nextLineNumber - 1);
3288 }
Linux kernel - Deliverables
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