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char: rocket.c: fix sparse variable shadowing and int as NULL pointer
[deliverable/linux.git] / drivers / char / rocket.c
1 /*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
45
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
55 #undef REV_PCI_ORDER
56 #undef ROCKET_DEBUG_IO
57
58 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
59
60 /****** Kernel includes ******/
61
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
68 #include <linux/mm.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/mutex.h>
79 #include <linux/ioport.h>
80 #include <linux/delay.h>
81 #include <linux/completion.h>
82 #include <linux/wait.h>
83 #include <linux/pci.h>
84 #include <asm/uaccess.h>
85 #include <asm/atomic.h>
86 #include <asm/unaligned.h>
87 #include <linux/bitops.h>
88 #include <linux/spinlock.h>
89 #include <linux/init.h>
90
91 /****** RocketPort includes ******/
92
93 #include "rocket_int.h"
94 #include "rocket.h"
95
96 #define ROCKET_VERSION "2.09"
97 #define ROCKET_DATE "12-June-2003"
98
99 /****** RocketPort Local Variables ******/
100
101 static void rp_do_poll(unsigned long dummy);
102
103 static struct tty_driver *rocket_driver;
104
105 static struct rocket_version driver_version = {
106 ROCKET_VERSION, ROCKET_DATE
107 };
108
109 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
110 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
111 /* eg. Bit 0 indicates port 0 has xmit data, ... */
112 static atomic_t rp_num_ports_open; /* Number of serial ports open */
113 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
114
115 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
116 static unsigned long board2;
117 static unsigned long board3;
118 static unsigned long board4;
119 static unsigned long controller;
120 static int support_low_speed;
121 static unsigned long modem1;
122 static unsigned long modem2;
123 static unsigned long modem3;
124 static unsigned long modem4;
125 static unsigned long pc104_1[8];
126 static unsigned long pc104_2[8];
127 static unsigned long pc104_3[8];
128 static unsigned long pc104_4[8];
129 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
130
131 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
132 static unsigned long rcktpt_io_addr[NUM_BOARDS];
133 static int rcktpt_type[NUM_BOARDS];
134 static int is_PCI[NUM_BOARDS];
135 static rocketModel_t rocketModel[NUM_BOARDS];
136 static int max_board;
137
138 /*
139 * The following arrays define the interrupt bits corresponding to each AIOP.
140 * These bits are different between the ISA and regular PCI boards and the
141 * Universal PCI boards.
142 */
143
144 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
145 AIOP_INTR_BIT_0,
146 AIOP_INTR_BIT_1,
147 AIOP_INTR_BIT_2,
148 AIOP_INTR_BIT_3
149 };
150
151 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
152 UPCI_AIOP_INTR_BIT_0,
153 UPCI_AIOP_INTR_BIT_1,
154 UPCI_AIOP_INTR_BIT_2,
155 UPCI_AIOP_INTR_BIT_3
156 };
157
158 static Byte_t RData[RDATASIZE] = {
159 0x00, 0x09, 0xf6, 0x82,
160 0x02, 0x09, 0x86, 0xfb,
161 0x04, 0x09, 0x00, 0x0a,
162 0x06, 0x09, 0x01, 0x0a,
163 0x08, 0x09, 0x8a, 0x13,
164 0x0a, 0x09, 0xc5, 0x11,
165 0x0c, 0x09, 0x86, 0x85,
166 0x0e, 0x09, 0x20, 0x0a,
167 0x10, 0x09, 0x21, 0x0a,
168 0x12, 0x09, 0x41, 0xff,
169 0x14, 0x09, 0x82, 0x00,
170 0x16, 0x09, 0x82, 0x7b,
171 0x18, 0x09, 0x8a, 0x7d,
172 0x1a, 0x09, 0x88, 0x81,
173 0x1c, 0x09, 0x86, 0x7a,
174 0x1e, 0x09, 0x84, 0x81,
175 0x20, 0x09, 0x82, 0x7c,
176 0x22, 0x09, 0x0a, 0x0a
177 };
178
179 static Byte_t RRegData[RREGDATASIZE] = {
180 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
181 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
182 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
183 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
184 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
185 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
186 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
187 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
188 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
189 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
190 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
191 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
192 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
193 };
194
195 static CONTROLLER_T sController[CTL_SIZE] = {
196 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
197 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
204 };
205
206 static Byte_t sBitMapClrTbl[8] = {
207 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
208 };
209
210 static Byte_t sBitMapSetTbl[8] = {
211 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
212 };
213
214 static int sClockPrescale = 0x14;
215
216 /*
217 * Line number is the ttySIx number (x), the Minor number. We
218 * assign them sequentially, starting at zero. The following
219 * array keeps track of the line number assigned to a given board/aiop/channel.
220 */
221 static unsigned char lineNumbers[MAX_RP_PORTS];
222 static unsigned long nextLineNumber;
223
224 /***** RocketPort Static Prototypes *********/
225 static int __init init_ISA(int i);
226 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
227 static void rp_flush_buffer(struct tty_struct *tty);
228 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
229 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
230 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
231 static void rp_start(struct tty_struct *tty);
232 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
233 int ChanNum);
234 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
235 static void sFlushRxFIFO(CHANNEL_T * ChP);
236 static void sFlushTxFIFO(CHANNEL_T * ChP);
237 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
238 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
239 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
240 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
241 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
242 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
243 ByteIO_t * AiopIOList, int AiopIOListSize,
244 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
245 int PeriodicOnly, int altChanRingIndicator,
246 int UPCIRingInd);
247 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
248 ByteIO_t * AiopIOList, int AiopIOListSize,
249 int IRQNum, Byte_t Frequency, int PeriodicOnly);
250 static int sReadAiopID(ByteIO_t io);
251 static int sReadAiopNumChan(WordIO_t io);
252
253 MODULE_AUTHOR("Theodore Ts'o");
254 MODULE_DESCRIPTION("Comtrol RocketPort driver");
255 module_param(board1, ulong, 0);
256 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
257 module_param(board2, ulong, 0);
258 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
259 module_param(board3, ulong, 0);
260 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
261 module_param(board4, ulong, 0);
262 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
263 module_param(controller, ulong, 0);
264 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
265 module_param(support_low_speed, bool, 0);
266 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
267 module_param(modem1, ulong, 0);
268 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
269 module_param(modem2, ulong, 0);
270 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
271 module_param(modem3, ulong, 0);
272 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
273 module_param(modem4, ulong, 0);
274 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
275 module_param_array(pc104_1, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
277 module_param_array(pc104_2, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
279 module_param_array(pc104_3, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
281 module_param_array(pc104_4, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
283
284 static int rp_init(void);
285 static void rp_cleanup_module(void);
286
287 module_init(rp_init);
288 module_exit(rp_cleanup_module);
289
290
291 MODULE_LICENSE("Dual BSD/GPL");
292
293 /*************************************************************************/
294 /* Module code starts here */
295
296 static inline int rocket_paranoia_check(struct r_port *info,
297 const char *routine)
298 {
299 #ifdef ROCKET_PARANOIA_CHECK
300 if (!info)
301 return 1;
302 if (info->magic != RPORT_MAGIC) {
303 printk(KERN_WARNING "Warning: bad magic number for rocketport "
304 "struct in %s\n", routine);
305 return 1;
306 }
307 #endif
308 return 0;
309 }
310
311
312 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
313 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
314 * tty layer.
315 */
316 static void rp_do_receive(struct r_port *info,
317 struct tty_struct *tty,
318 CHANNEL_t * cp, unsigned int ChanStatus)
319 {
320 unsigned int CharNStat;
321 int ToRecv, wRecv, space;
322 unsigned char *cbuf;
323
324 ToRecv = sGetRxCnt(cp);
325 #ifdef ROCKET_DEBUG_INTR
326 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
327 #endif
328 if (ToRecv == 0)
329 return;
330
331 /*
332 * if status indicates there are errored characters in the
333 * FIFO, then enter status mode (a word in FIFO holds
334 * character and status).
335 */
336 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
337 if (!(ChanStatus & STATMODE)) {
338 #ifdef ROCKET_DEBUG_RECEIVE
339 printk(KERN_INFO "Entering STATMODE...\n");
340 #endif
341 ChanStatus |= STATMODE;
342 sEnRxStatusMode(cp);
343 }
344 }
345
346 /*
347 * if we previously entered status mode, then read down the
348 * FIFO one word at a time, pulling apart the character and
349 * the status. Update error counters depending on status
350 */
351 if (ChanStatus & STATMODE) {
352 #ifdef ROCKET_DEBUG_RECEIVE
353 printk(KERN_INFO "Ignore %x, read %x...\n",
354 info->ignore_status_mask, info->read_status_mask);
355 #endif
356 while (ToRecv) {
357 char flag;
358
359 CharNStat = sInW(sGetTxRxDataIO(cp));
360 #ifdef ROCKET_DEBUG_RECEIVE
361 printk(KERN_INFO "%x...\n", CharNStat);
362 #endif
363 if (CharNStat & STMBREAKH)
364 CharNStat &= ~(STMFRAMEH | STMPARITYH);
365 if (CharNStat & info->ignore_status_mask) {
366 ToRecv--;
367 continue;
368 }
369 CharNStat &= info->read_status_mask;
370 if (CharNStat & STMBREAKH)
371 flag = TTY_BREAK;
372 else if (CharNStat & STMPARITYH)
373 flag = TTY_PARITY;
374 else if (CharNStat & STMFRAMEH)
375 flag = TTY_FRAME;
376 else if (CharNStat & STMRCVROVRH)
377 flag = TTY_OVERRUN;
378 else
379 flag = TTY_NORMAL;
380 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
381 ToRecv--;
382 }
383
384 /*
385 * after we've emptied the FIFO in status mode, turn
386 * status mode back off
387 */
388 if (sGetRxCnt(cp) == 0) {
389 #ifdef ROCKET_DEBUG_RECEIVE
390 printk(KERN_INFO "Status mode off.\n");
391 #endif
392 sDisRxStatusMode(cp);
393 }
394 } else {
395 /*
396 * we aren't in status mode, so read down the FIFO two
397 * characters at time by doing repeated word IO
398 * transfer.
399 */
400 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
401 if (space < ToRecv) {
402 #ifdef ROCKET_DEBUG_RECEIVE
403 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
404 #endif
405 if (space <= 0)
406 return;
407 ToRecv = space;
408 }
409 wRecv = ToRecv >> 1;
410 if (wRecv)
411 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
412 if (ToRecv & 1)
413 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
414 }
415 /* Push the data up to the tty layer */
416 tty_flip_buffer_push(tty);
417 }
418
419 /*
420 * Serial port transmit data function. Called from the timer polling loop as a
421 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
422 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
423 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
424 */
425 static void rp_do_transmit(struct r_port *info)
426 {
427 int c;
428 CHANNEL_t *cp = &info->channel;
429 struct tty_struct *tty;
430 unsigned long flags;
431
432 #ifdef ROCKET_DEBUG_INTR
433 printk(KERN_DEBUG "%s\n", __func__);
434 #endif
435 if (!info)
436 return;
437 if (!info->tty) {
438 printk(KERN_WARNING "rp: WARNING %s called with "
439 "info->tty==NULL\n", __func__);
440 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
441 return;
442 }
443
444 spin_lock_irqsave(&info->slock, flags);
445 tty = info->tty;
446 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
447
448 /* Loop sending data to FIFO until done or FIFO full */
449 while (1) {
450 if (tty->stopped || tty->hw_stopped)
451 break;
452 c = min(info->xmit_fifo_room, info->xmit_cnt);
453 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
454 if (c <= 0 || info->xmit_fifo_room <= 0)
455 break;
456 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
457 if (c & 1)
458 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
459 info->xmit_tail += c;
460 info->xmit_tail &= XMIT_BUF_SIZE - 1;
461 info->xmit_cnt -= c;
462 info->xmit_fifo_room -= c;
463 #ifdef ROCKET_DEBUG_INTR
464 printk(KERN_INFO "tx %d chars...\n", c);
465 #endif
466 }
467
468 if (info->xmit_cnt == 0)
469 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
470
471 if (info->xmit_cnt < WAKEUP_CHARS) {
472 tty_wakeup(tty);
473 #ifdef ROCKETPORT_HAVE_POLL_WAIT
474 wake_up_interruptible(&tty->poll_wait);
475 #endif
476 }
477
478 spin_unlock_irqrestore(&info->slock, flags);
479
480 #ifdef ROCKET_DEBUG_INTR
481 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
482 info->xmit_tail, info->xmit_fifo_room);
483 #endif
484 }
485
486 /*
487 * Called when a serial port signals it has read data in it's RX FIFO.
488 * It checks what interrupts are pending and services them, including
489 * receiving serial data.
490 */
491 static void rp_handle_port(struct r_port *info)
492 {
493 CHANNEL_t *cp;
494 struct tty_struct *tty;
495 unsigned int IntMask, ChanStatus;
496
497 if (!info)
498 return;
499
500 if ((info->flags & ROCKET_INITIALIZED) == 0) {
501 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
502 "info->flags & NOT_INIT\n");
503 return;
504 }
505 if (!info->tty) {
506 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
507 "info->tty==NULL\n");
508 return;
509 }
510 cp = &info->channel;
511 tty = info->tty;
512
513 IntMask = sGetChanIntID(cp) & info->intmask;
514 #ifdef ROCKET_DEBUG_INTR
515 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
516 #endif
517 ChanStatus = sGetChanStatus(cp);
518 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
519 rp_do_receive(info, tty, cp, ChanStatus);
520 }
521 if (IntMask & DELTA_CD) { /* CD change */
522 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
523 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
524 (ChanStatus & CD_ACT) ? "on" : "off");
525 #endif
526 if (!(ChanStatus & CD_ACT) && info->cd_status) {
527 #ifdef ROCKET_DEBUG_HANGUP
528 printk(KERN_INFO "CD drop, calling hangup.\n");
529 #endif
530 tty_hangup(tty);
531 }
532 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
533 wake_up_interruptible(&info->open_wait);
534 }
535 #ifdef ROCKET_DEBUG_INTR
536 if (IntMask & DELTA_CTS) { /* CTS change */
537 printk(KERN_INFO "CTS change...\n");
538 }
539 if (IntMask & DELTA_DSR) { /* DSR change */
540 printk(KERN_INFO "DSR change...\n");
541 }
542 #endif
543 }
544
545 /*
546 * The top level polling routine. Repeats every 1/100 HZ (10ms).
547 */
548 static void rp_do_poll(unsigned long dummy)
549 {
550 CONTROLLER_t *ctlp;
551 int ctrl, aiop, ch, line;
552 unsigned int xmitmask, i;
553 unsigned int CtlMask;
554 unsigned char AiopMask;
555 Word_t bit;
556
557 /* Walk through all the boards (ctrl's) */
558 for (ctrl = 0; ctrl < max_board; ctrl++) {
559 if (rcktpt_io_addr[ctrl] <= 0)
560 continue;
561
562 /* Get a ptr to the board's control struct */
563 ctlp = sCtlNumToCtlPtr(ctrl);
564
565 /* Get the interrupt status from the board */
566 #ifdef CONFIG_PCI
567 if (ctlp->BusType == isPCI)
568 CtlMask = sPCIGetControllerIntStatus(ctlp);
569 else
570 #endif
571 CtlMask = sGetControllerIntStatus(ctlp);
572
573 /* Check if any AIOP read bits are set */
574 for (aiop = 0; CtlMask; aiop++) {
575 bit = ctlp->AiopIntrBits[aiop];
576 if (CtlMask & bit) {
577 CtlMask &= ~bit;
578 AiopMask = sGetAiopIntStatus(ctlp, aiop);
579
580 /* Check if any port read bits are set */
581 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
582 if (AiopMask & 1) {
583
584 /* Get the line number (/dev/ttyRx number). */
585 /* Read the data from the port. */
586 line = GetLineNumber(ctrl, aiop, ch);
587 rp_handle_port(rp_table[line]);
588 }
589 }
590 }
591 }
592
593 xmitmask = xmit_flags[ctrl];
594
595 /*
596 * xmit_flags contains bit-significant flags, indicating there is data
597 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
598 * 1, ... (32 total possible). The variable i has the aiop and ch
599 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
600 */
601 if (xmitmask) {
602 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
603 if (xmitmask & (1 << i)) {
604 aiop = (i & 0x18) >> 3;
605 ch = i & 0x07;
606 line = GetLineNumber(ctrl, aiop, ch);
607 rp_do_transmit(rp_table[line]);
608 }
609 }
610 }
611 }
612
613 /*
614 * Reset the timer so we get called at the next clock tick (10ms).
615 */
616 if (atomic_read(&rp_num_ports_open))
617 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
618 }
619
620 /*
621 * Initializes the r_port structure for a port, as well as enabling the port on
622 * the board.
623 * Inputs: board, aiop, chan numbers
624 */
625 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
626 {
627 unsigned rocketMode;
628 struct r_port *info;
629 int line;
630 CONTROLLER_T *ctlp;
631
632 /* Get the next available line number */
633 line = SetLineNumber(board, aiop, chan);
634
635 ctlp = sCtlNumToCtlPtr(board);
636
637 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
638 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
639 if (!info) {
640 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
641 line);
642 return;
643 }
644
645 info->magic = RPORT_MAGIC;
646 info->line = line;
647 info->ctlp = ctlp;
648 info->board = board;
649 info->aiop = aiop;
650 info->chan = chan;
651 info->closing_wait = 3000;
652 info->close_delay = 50;
653 init_waitqueue_head(&info->open_wait);
654 init_completion(&info->close_wait);
655 info->flags &= ~ROCKET_MODE_MASK;
656 switch (pc104[board][line]) {
657 case 422:
658 info->flags |= ROCKET_MODE_RS422;
659 break;
660 case 485:
661 info->flags |= ROCKET_MODE_RS485;
662 break;
663 case 232:
664 default:
665 info->flags |= ROCKET_MODE_RS232;
666 break;
667 }
668
669 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
670 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
671 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
672 board, aiop, chan);
673 kfree(info);
674 return;
675 }
676
677 rocketMode = info->flags & ROCKET_MODE_MASK;
678
679 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
680 sEnRTSToggle(&info->channel);
681 else
682 sDisRTSToggle(&info->channel);
683
684 if (ctlp->boardType == ROCKET_TYPE_PC104) {
685 switch (rocketMode) {
686 case ROCKET_MODE_RS485:
687 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
688 break;
689 case ROCKET_MODE_RS422:
690 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
691 break;
692 case ROCKET_MODE_RS232:
693 default:
694 if (info->flags & ROCKET_RTS_TOGGLE)
695 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
696 else
697 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
698 break;
699 }
700 }
701 spin_lock_init(&info->slock);
702 mutex_init(&info->write_mtx);
703 rp_table[line] = info;
704 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
705 NULL);
706 }
707
708 /*
709 * Configures a rocketport port according to its termio settings. Called from
710 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
711 */
712 static void configure_r_port(struct r_port *info,
713 struct ktermios *old_termios)
714 {
715 unsigned cflag;
716 unsigned long flags;
717 unsigned rocketMode;
718 int bits, baud, divisor;
719 CHANNEL_t *cp;
720 struct ktermios *t = info->tty->termios;
721
722 cp = &info->channel;
723 cflag = t->c_cflag;
724
725 /* Byte size and parity */
726 if ((cflag & CSIZE) == CS8) {
727 sSetData8(cp);
728 bits = 10;
729 } else {
730 sSetData7(cp);
731 bits = 9;
732 }
733 if (cflag & CSTOPB) {
734 sSetStop2(cp);
735 bits++;
736 } else {
737 sSetStop1(cp);
738 }
739
740 if (cflag & PARENB) {
741 sEnParity(cp);
742 bits++;
743 if (cflag & PARODD) {
744 sSetOddParity(cp);
745 } else {
746 sSetEvenParity(cp);
747 }
748 } else {
749 sDisParity(cp);
750 }
751
752 /* baud rate */
753 baud = tty_get_baud_rate(info->tty);
754 if (!baud)
755 baud = 9600;
756 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
757 if ((divisor >= 8192 || divisor < 0) && old_termios) {
758 baud = tty_termios_baud_rate(old_termios);
759 if (!baud)
760 baud = 9600;
761 divisor = (rp_baud_base[info->board] / baud) - 1;
762 }
763 if (divisor >= 8192 || divisor < 0) {
764 baud = 9600;
765 divisor = (rp_baud_base[info->board] / baud) - 1;
766 }
767 info->cps = baud / bits;
768 sSetBaud(cp, divisor);
769
770 /* FIXME: Should really back compute a baud rate from the divisor */
771 tty_encode_baud_rate(info->tty, baud, baud);
772
773 if (cflag & CRTSCTS) {
774 info->intmask |= DELTA_CTS;
775 sEnCTSFlowCtl(cp);
776 } else {
777 info->intmask &= ~DELTA_CTS;
778 sDisCTSFlowCtl(cp);
779 }
780 if (cflag & CLOCAL) {
781 info->intmask &= ~DELTA_CD;
782 } else {
783 spin_lock_irqsave(&info->slock, flags);
784 if (sGetChanStatus(cp) & CD_ACT)
785 info->cd_status = 1;
786 else
787 info->cd_status = 0;
788 info->intmask |= DELTA_CD;
789 spin_unlock_irqrestore(&info->slock, flags);
790 }
791
792 /*
793 * Handle software flow control in the board
794 */
795 #ifdef ROCKET_SOFT_FLOW
796 if (I_IXON(info->tty)) {
797 sEnTxSoftFlowCtl(cp);
798 if (I_IXANY(info->tty)) {
799 sEnIXANY(cp);
800 } else {
801 sDisIXANY(cp);
802 }
803 sSetTxXONChar(cp, START_CHAR(info->tty));
804 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
805 } else {
806 sDisTxSoftFlowCtl(cp);
807 sDisIXANY(cp);
808 sClrTxXOFF(cp);
809 }
810 #endif
811
812 /*
813 * Set up ignore/read mask words
814 */
815 info->read_status_mask = STMRCVROVRH | 0xFF;
816 if (I_INPCK(info->tty))
817 info->read_status_mask |= STMFRAMEH | STMPARITYH;
818 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
819 info->read_status_mask |= STMBREAKH;
820
821 /*
822 * Characters to ignore
823 */
824 info->ignore_status_mask = 0;
825 if (I_IGNPAR(info->tty))
826 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
827 if (I_IGNBRK(info->tty)) {
828 info->ignore_status_mask |= STMBREAKH;
829 /*
830 * If we're ignoring parity and break indicators,
831 * ignore overruns too. (For real raw support).
832 */
833 if (I_IGNPAR(info->tty))
834 info->ignore_status_mask |= STMRCVROVRH;
835 }
836
837 rocketMode = info->flags & ROCKET_MODE_MASK;
838
839 if ((info->flags & ROCKET_RTS_TOGGLE)
840 || (rocketMode == ROCKET_MODE_RS485))
841 sEnRTSToggle(cp);
842 else
843 sDisRTSToggle(cp);
844
845 sSetRTS(&info->channel);
846
847 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
848 switch (rocketMode) {
849 case ROCKET_MODE_RS485:
850 sSetInterfaceMode(cp, InterfaceModeRS485);
851 break;
852 case ROCKET_MODE_RS422:
853 sSetInterfaceMode(cp, InterfaceModeRS422);
854 break;
855 case ROCKET_MODE_RS232:
856 default:
857 if (info->flags & ROCKET_RTS_TOGGLE)
858 sSetInterfaceMode(cp, InterfaceModeRS232T);
859 else
860 sSetInterfaceMode(cp, InterfaceModeRS232);
861 break;
862 }
863 }
864 }
865
866 /* info->count is considered critical, protected by spinlocks. */
867 static int block_til_ready(struct tty_struct *tty, struct file *filp,
868 struct r_port *info)
869 {
870 DECLARE_WAITQUEUE(wait, current);
871 int retval;
872 int do_clocal = 0, extra_count = 0;
873 unsigned long flags;
874
875 /*
876 * If the device is in the middle of being closed, then block
877 * until it's done, and then try again.
878 */
879 if (tty_hung_up_p(filp))
880 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
881 if (info->flags & ROCKET_CLOSING) {
882 if (wait_for_completion_interruptible(&info->close_wait))
883 return -ERESTARTSYS;
884 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
885 }
886
887 /*
888 * If non-blocking mode is set, or the port is not enabled,
889 * then make the check up front and then exit.
890 */
891 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
892 info->flags |= ROCKET_NORMAL_ACTIVE;
893 return 0;
894 }
895 if (tty->termios->c_cflag & CLOCAL)
896 do_clocal = 1;
897
898 /*
899 * Block waiting for the carrier detect and the line to become free. While we are in
900 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
901 * We restore it upon exit, either normal or abnormal.
902 */
903 retval = 0;
904 add_wait_queue(&info->open_wait, &wait);
905 #ifdef ROCKET_DEBUG_OPEN
906 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
907 #endif
908 spin_lock_irqsave(&info->slock, flags);
909
910 #ifdef ROCKET_DISABLE_SIMUSAGE
911 info->flags |= ROCKET_NORMAL_ACTIVE;
912 #else
913 if (!tty_hung_up_p(filp)) {
914 extra_count = 1;
915 info->count--;
916 }
917 #endif
918 info->blocked_open++;
919
920 spin_unlock_irqrestore(&info->slock, flags);
921
922 while (1) {
923 if (tty->termios->c_cflag & CBAUD) {
924 sSetDTR(&info->channel);
925 sSetRTS(&info->channel);
926 }
927 set_current_state(TASK_INTERRUPTIBLE);
928 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
929 if (info->flags & ROCKET_HUP_NOTIFY)
930 retval = -EAGAIN;
931 else
932 retval = -ERESTARTSYS;
933 break;
934 }
935 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
936 break;
937 if (signal_pending(current)) {
938 retval = -ERESTARTSYS;
939 break;
940 }
941 #ifdef ROCKET_DEBUG_OPEN
942 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
943 info->line, info->count, info->flags);
944 #endif
945 schedule(); /* Don't hold spinlock here, will hang PC */
946 }
947 __set_current_state(TASK_RUNNING);
948 remove_wait_queue(&info->open_wait, &wait);
949
950 spin_lock_irqsave(&info->slock, flags);
951
952 if (extra_count)
953 info->count++;
954 info->blocked_open--;
955
956 spin_unlock_irqrestore(&info->slock, flags);
957
958 #ifdef ROCKET_DEBUG_OPEN
959 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
960 info->line, info->count);
961 #endif
962 if (retval)
963 return retval;
964 info->flags |= ROCKET_NORMAL_ACTIVE;
965 return 0;
966 }
967
968 /*
969 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
970 * port's r_port struct. Initializes the port hardware.
971 */
972 static int rp_open(struct tty_struct *tty, struct file *filp)
973 {
974 struct r_port *info;
975 int line = 0, retval;
976 CHANNEL_t *cp;
977 unsigned long page;
978
979 line = tty->index;
980 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
981 return -ENXIO;
982
983 page = __get_free_page(GFP_KERNEL);
984 if (!page)
985 return -ENOMEM;
986
987 if (info->flags & ROCKET_CLOSING) {
988 retval = wait_for_completion_interruptible(&info->close_wait);
989 free_page(page);
990 if (retval)
991 return retval;
992 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
993 }
994
995 /*
996 * We must not sleep from here until the port is marked fully in use.
997 */
998 if (info->xmit_buf)
999 free_page(page);
1000 else
1001 info->xmit_buf = (unsigned char *) page;
1002
1003 tty->driver_data = info;
1004 info->tty = tty;
1005
1006 if (info->count++ == 0) {
1007 atomic_inc(&rp_num_ports_open);
1008
1009 #ifdef ROCKET_DEBUG_OPEN
1010 printk(KERN_INFO "rocket mod++ = %d...\n",
1011 atomic_read(&rp_num_ports_open));
1012 #endif
1013 }
1014 #ifdef ROCKET_DEBUG_OPEN
1015 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1016 #endif
1017
1018 /*
1019 * Info->count is now 1; so it's safe to sleep now.
1020 */
1021 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1022 cp = &info->channel;
1023 sSetRxTrigger(cp, TRIG_1);
1024 if (sGetChanStatus(cp) & CD_ACT)
1025 info->cd_status = 1;
1026 else
1027 info->cd_status = 0;
1028 sDisRxStatusMode(cp);
1029 sFlushRxFIFO(cp);
1030 sFlushTxFIFO(cp);
1031
1032 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1033 sSetRxTrigger(cp, TRIG_1);
1034
1035 sGetChanStatus(cp);
1036 sDisRxStatusMode(cp);
1037 sClrTxXOFF(cp);
1038
1039 sDisCTSFlowCtl(cp);
1040 sDisTxSoftFlowCtl(cp);
1041
1042 sEnRxFIFO(cp);
1043 sEnTransmit(cp);
1044
1045 info->flags |= ROCKET_INITIALIZED;
1046
1047 /*
1048 * Set up the tty->alt_speed kludge
1049 */
1050 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1051 info->tty->alt_speed = 57600;
1052 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1053 info->tty->alt_speed = 115200;
1054 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1055 info->tty->alt_speed = 230400;
1056 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1057 info->tty->alt_speed = 460800;
1058
1059 configure_r_port(info, NULL);
1060 if (tty->termios->c_cflag & CBAUD) {
1061 sSetDTR(cp);
1062 sSetRTS(cp);
1063 }
1064 }
1065 /* Starts (or resets) the maint polling loop */
1066 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1067
1068 retval = block_til_ready(tty, filp, info);
1069 if (retval) {
1070 #ifdef ROCKET_DEBUG_OPEN
1071 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1072 #endif
1073 return retval;
1074 }
1075 return 0;
1076 }
1077
1078 /*
1079 * Exception handler that closes a serial port. info->count is considered critical.
1080 */
1081 static void rp_close(struct tty_struct *tty, struct file *filp)
1082 {
1083 struct r_port *info = (struct r_port *) tty->driver_data;
1084 unsigned long flags;
1085 int timeout;
1086 CHANNEL_t *cp;
1087
1088 if (rocket_paranoia_check(info, "rp_close"))
1089 return;
1090
1091 #ifdef ROCKET_DEBUG_OPEN
1092 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1093 #endif
1094
1095 if (tty_hung_up_p(filp))
1096 return;
1097 spin_lock_irqsave(&info->slock, flags);
1098
1099 if ((tty->count == 1) && (info->count != 1)) {
1100 /*
1101 * Uh, oh. tty->count is 1, which means that the tty
1102 * structure will be freed. Info->count should always
1103 * be one in these conditions. If it's greater than
1104 * one, we've got real problems, since it means the
1105 * serial port won't be shutdown.
1106 */
1107 printk(KERN_WARNING "rp_close: bad serial port count; "
1108 "tty->count is 1, info->count is %d\n", info->count);
1109 info->count = 1;
1110 }
1111 if (--info->count < 0) {
1112 printk(KERN_WARNING "rp_close: bad serial port count for "
1113 "ttyR%d: %d\n", info->line, info->count);
1114 info->count = 0;
1115 }
1116 if (info->count) {
1117 spin_unlock_irqrestore(&info->slock, flags);
1118 return;
1119 }
1120 info->flags |= ROCKET_CLOSING;
1121 spin_unlock_irqrestore(&info->slock, flags);
1122
1123 cp = &info->channel;
1124
1125 /*
1126 * Notify the line discpline to only process XON/XOFF characters
1127 */
1128 tty->closing = 1;
1129
1130 /*
1131 * If transmission was throttled by the application request,
1132 * just flush the xmit buffer.
1133 */
1134 if (tty->flow_stopped)
1135 rp_flush_buffer(tty);
1136
1137 /*
1138 * Wait for the transmit buffer to clear
1139 */
1140 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1141 tty_wait_until_sent(tty, info->closing_wait);
1142 /*
1143 * Before we drop DTR, make sure the UART transmitter
1144 * has completely drained; this is especially
1145 * important if there is a transmit FIFO!
1146 */
1147 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1148 if (timeout == 0)
1149 timeout = 1;
1150 rp_wait_until_sent(tty, timeout);
1151 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1152
1153 sDisTransmit(cp);
1154 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1155 sDisCTSFlowCtl(cp);
1156 sDisTxSoftFlowCtl(cp);
1157 sClrTxXOFF(cp);
1158 sFlushRxFIFO(cp);
1159 sFlushTxFIFO(cp);
1160 sClrRTS(cp);
1161 if (C_HUPCL(tty))
1162 sClrDTR(cp);
1163
1164 rp_flush_buffer(tty);
1165
1166 tty_ldisc_flush(tty);
1167
1168 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1169
1170 if (info->blocked_open) {
1171 if (info->close_delay) {
1172 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1173 }
1174 wake_up_interruptible(&info->open_wait);
1175 } else {
1176 if (info->xmit_buf) {
1177 free_page((unsigned long) info->xmit_buf);
1178 info->xmit_buf = NULL;
1179 }
1180 }
1181 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1182 tty->closing = 0;
1183 complete_all(&info->close_wait);
1184 atomic_dec(&rp_num_ports_open);
1185
1186 #ifdef ROCKET_DEBUG_OPEN
1187 printk(KERN_INFO "rocket mod-- = %d...\n",
1188 atomic_read(&rp_num_ports_open));
1189 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1190 #endif
1191
1192 }
1193
1194 static void rp_set_termios(struct tty_struct *tty,
1195 struct ktermios *old_termios)
1196 {
1197 struct r_port *info = (struct r_port *) tty->driver_data;
1198 CHANNEL_t *cp;
1199 unsigned cflag;
1200
1201 if (rocket_paranoia_check(info, "rp_set_termios"))
1202 return;
1203
1204 cflag = tty->termios->c_cflag;
1205
1206 /*
1207 * This driver doesn't support CS5 or CS6
1208 */
1209 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1210 tty->termios->c_cflag =
1211 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1212 /* Or CMSPAR */
1213 tty->termios->c_cflag &= ~CMSPAR;
1214
1215 configure_r_port(info, old_termios);
1216
1217 cp = &info->channel;
1218
1219 /* Handle transition to B0 status */
1220 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1221 sClrDTR(cp);
1222 sClrRTS(cp);
1223 }
1224
1225 /* Handle transition away from B0 status */
1226 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1227 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1228 sSetRTS(cp);
1229 sSetDTR(cp);
1230 }
1231
1232 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1233 tty->hw_stopped = 0;
1234 rp_start(tty);
1235 }
1236 }
1237
1238 static void rp_break(struct tty_struct *tty, int break_state)
1239 {
1240 struct r_port *info = (struct r_port *) tty->driver_data;
1241 unsigned long flags;
1242
1243 if (rocket_paranoia_check(info, "rp_break"))
1244 return;
1245
1246 spin_lock_irqsave(&info->slock, flags);
1247 if (break_state == -1)
1248 sSendBreak(&info->channel);
1249 else
1250 sClrBreak(&info->channel);
1251 spin_unlock_irqrestore(&info->slock, flags);
1252 }
1253
1254 /*
1255 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1256 * the UPCI boards was added, it was decided to make this a function because
1257 * the macro was getting too complicated. All cases except the first one
1258 * (UPCIRingInd) are taken directly from the original macro.
1259 */
1260 static int sGetChanRI(CHANNEL_T * ChP)
1261 {
1262 CONTROLLER_t *CtlP = ChP->CtlP;
1263 int ChanNum = ChP->ChanNum;
1264 int RingInd = 0;
1265
1266 if (CtlP->UPCIRingInd)
1267 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1268 else if (CtlP->AltChanRingIndicator)
1269 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1270 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1271 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1272
1273 return RingInd;
1274 }
1275
1276 /********************************************************************************************/
1277 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1278
1279 /*
1280 * Returns the state of the serial modem control lines. These next 2 functions
1281 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1282 */
1283 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1284 {
1285 struct r_port *info = (struct r_port *)tty->driver_data;
1286 unsigned int control, result, ChanStatus;
1287
1288 ChanStatus = sGetChanStatusLo(&info->channel);
1289 control = info->channel.TxControl[3];
1290 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1291 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1292 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1293 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1294 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1295 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1296
1297 return result;
1298 }
1299
1300 /*
1301 * Sets the modem control lines
1302 */
1303 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1304 unsigned int set, unsigned int clear)
1305 {
1306 struct r_port *info = (struct r_port *)tty->driver_data;
1307
1308 if (set & TIOCM_RTS)
1309 info->channel.TxControl[3] |= SET_RTS;
1310 if (set & TIOCM_DTR)
1311 info->channel.TxControl[3] |= SET_DTR;
1312 if (clear & TIOCM_RTS)
1313 info->channel.TxControl[3] &= ~SET_RTS;
1314 if (clear & TIOCM_DTR)
1315 info->channel.TxControl[3] &= ~SET_DTR;
1316
1317 out32(info->channel.IndexAddr, info->channel.TxControl);
1318 return 0;
1319 }
1320
1321 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1322 {
1323 struct rocket_config tmp;
1324
1325 if (!retinfo)
1326 return -EFAULT;
1327 memset(&tmp, 0, sizeof (tmp));
1328 tmp.line = info->line;
1329 tmp.flags = info->flags;
1330 tmp.close_delay = info->close_delay;
1331 tmp.closing_wait = info->closing_wait;
1332 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1333
1334 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1335 return -EFAULT;
1336 return 0;
1337 }
1338
1339 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1340 {
1341 struct rocket_config new_serial;
1342
1343 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1344 return -EFAULT;
1345
1346 if (!capable(CAP_SYS_ADMIN))
1347 {
1348 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1349 return -EPERM;
1350 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1351 configure_r_port(info, NULL);
1352 return 0;
1353 }
1354
1355 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1356 info->close_delay = new_serial.close_delay;
1357 info->closing_wait = new_serial.closing_wait;
1358
1359 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1360 info->tty->alt_speed = 57600;
1361 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1362 info->tty->alt_speed = 115200;
1363 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1364 info->tty->alt_speed = 230400;
1365 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1366 info->tty->alt_speed = 460800;
1367
1368 configure_r_port(info, NULL);
1369 return 0;
1370 }
1371
1372 /*
1373 * This function fills in a rocket_ports struct with information
1374 * about what boards/ports are in the system. This info is passed
1375 * to user space. See setrocket.c where the info is used to create
1376 * the /dev/ttyRx ports.
1377 */
1378 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1379 {
1380 struct rocket_ports tmp;
1381 int board;
1382
1383 if (!retports)
1384 return -EFAULT;
1385 memset(&tmp, 0, sizeof (tmp));
1386 tmp.tty_major = rocket_driver->major;
1387
1388 for (board = 0; board < 4; board++) {
1389 tmp.rocketModel[board].model = rocketModel[board].model;
1390 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1391 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1392 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1393 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1394 }
1395 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1396 return -EFAULT;
1397 return 0;
1398 }
1399
1400 static int reset_rm2(struct r_port *info, void __user *arg)
1401 {
1402 int reset;
1403
1404 if (!capable(CAP_SYS_ADMIN))
1405 return -EPERM;
1406
1407 if (copy_from_user(&reset, arg, sizeof (int)))
1408 return -EFAULT;
1409 if (reset)
1410 reset = 1;
1411
1412 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1413 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1414 return -EINVAL;
1415
1416 if (info->ctlp->BusType == isISA)
1417 sModemReset(info->ctlp, info->chan, reset);
1418 else
1419 sPCIModemReset(info->ctlp, info->chan, reset);
1420
1421 return 0;
1422 }
1423
1424 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1425 {
1426 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1427 return -EFAULT;
1428 return 0;
1429 }
1430
1431 /* IOCTL call handler into the driver */
1432 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1433 unsigned int cmd, unsigned long arg)
1434 {
1435 struct r_port *info = (struct r_port *) tty->driver_data;
1436 void __user *argp = (void __user *)arg;
1437 int ret = 0;
1438
1439 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1440 return -ENXIO;
1441
1442 lock_kernel();
1443
1444 switch (cmd) {
1445 case RCKP_GET_STRUCT:
1446 if (copy_to_user(argp, info, sizeof (struct r_port)))
1447 ret = -EFAULT;
1448 break;
1449 case RCKP_GET_CONFIG:
1450 ret = get_config(info, argp);
1451 break;
1452 case RCKP_SET_CONFIG:
1453 ret = set_config(info, argp);
1454 break;
1455 case RCKP_GET_PORTS:
1456 ret = get_ports(info, argp);
1457 break;
1458 case RCKP_RESET_RM2:
1459 ret = reset_rm2(info, argp);
1460 break;
1461 case RCKP_GET_VERSION:
1462 ret = get_version(info, argp);
1463 break;
1464 default:
1465 ret = -ENOIOCTLCMD;
1466 }
1467 unlock_kernel();
1468 return ret;
1469 }
1470
1471 static void rp_send_xchar(struct tty_struct *tty, char ch)
1472 {
1473 struct r_port *info = (struct r_port *) tty->driver_data;
1474 CHANNEL_t *cp;
1475
1476 if (rocket_paranoia_check(info, "rp_send_xchar"))
1477 return;
1478
1479 cp = &info->channel;
1480 if (sGetTxCnt(cp))
1481 sWriteTxPrioByte(cp, ch);
1482 else
1483 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1484 }
1485
1486 static void rp_throttle(struct tty_struct *tty)
1487 {
1488 struct r_port *info = (struct r_port *) tty->driver_data;
1489 CHANNEL_t *cp;
1490
1491 #ifdef ROCKET_DEBUG_THROTTLE
1492 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1493 tty->ldisc.chars_in_buffer(tty));
1494 #endif
1495
1496 if (rocket_paranoia_check(info, "rp_throttle"))
1497 return;
1498
1499 cp = &info->channel;
1500 if (I_IXOFF(tty))
1501 rp_send_xchar(tty, STOP_CHAR(tty));
1502
1503 sClrRTS(&info->channel);
1504 }
1505
1506 static void rp_unthrottle(struct tty_struct *tty)
1507 {
1508 struct r_port *info = (struct r_port *) tty->driver_data;
1509 CHANNEL_t *cp;
1510 #ifdef ROCKET_DEBUG_THROTTLE
1511 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1512 tty->ldisc.chars_in_buffer(tty));
1513 #endif
1514
1515 if (rocket_paranoia_check(info, "rp_throttle"))
1516 return;
1517
1518 cp = &info->channel;
1519 if (I_IXOFF(tty))
1520 rp_send_xchar(tty, START_CHAR(tty));
1521
1522 sSetRTS(&info->channel);
1523 }
1524
1525 /*
1526 * ------------------------------------------------------------
1527 * rp_stop() and rp_start()
1528 *
1529 * This routines are called before setting or resetting tty->stopped.
1530 * They enable or disable transmitter interrupts, as necessary.
1531 * ------------------------------------------------------------
1532 */
1533 static void rp_stop(struct tty_struct *tty)
1534 {
1535 struct r_port *info = (struct r_port *) tty->driver_data;
1536
1537 #ifdef ROCKET_DEBUG_FLOW
1538 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1539 info->xmit_cnt, info->xmit_fifo_room);
1540 #endif
1541
1542 if (rocket_paranoia_check(info, "rp_stop"))
1543 return;
1544
1545 if (sGetTxCnt(&info->channel))
1546 sDisTransmit(&info->channel);
1547 }
1548
1549 static void rp_start(struct tty_struct *tty)
1550 {
1551 struct r_port *info = (struct r_port *) tty->driver_data;
1552
1553 #ifdef ROCKET_DEBUG_FLOW
1554 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1555 info->xmit_cnt, info->xmit_fifo_room);
1556 #endif
1557
1558 if (rocket_paranoia_check(info, "rp_stop"))
1559 return;
1560
1561 sEnTransmit(&info->channel);
1562 set_bit((info->aiop * 8) + info->chan,
1563 (void *) &xmit_flags[info->board]);
1564 }
1565
1566 /*
1567 * rp_wait_until_sent() --- wait until the transmitter is empty
1568 */
1569 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1570 {
1571 struct r_port *info = (struct r_port *) tty->driver_data;
1572 CHANNEL_t *cp;
1573 unsigned long orig_jiffies;
1574 int check_time, exit_time;
1575 int txcnt;
1576
1577 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1578 return;
1579
1580 cp = &info->channel;
1581
1582 orig_jiffies = jiffies;
1583 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1584 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1585 jiffies);
1586 printk(KERN_INFO "cps=%d...\n", info->cps);
1587 #endif
1588 while (1) {
1589 txcnt = sGetTxCnt(cp);
1590 if (!txcnt) {
1591 if (sGetChanStatusLo(cp) & TXSHRMT)
1592 break;
1593 check_time = (HZ / info->cps) / 5;
1594 } else {
1595 check_time = HZ * txcnt / info->cps;
1596 }
1597 if (timeout) {
1598 exit_time = orig_jiffies + timeout - jiffies;
1599 if (exit_time <= 0)
1600 break;
1601 if (exit_time < check_time)
1602 check_time = exit_time;
1603 }
1604 if (check_time == 0)
1605 check_time = 1;
1606 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1607 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1608 jiffies, check_time);
1609 #endif
1610 msleep_interruptible(jiffies_to_msecs(check_time));
1611 if (signal_pending(current))
1612 break;
1613 }
1614 __set_current_state(TASK_RUNNING);
1615 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1616 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1617 #endif
1618 }
1619
1620 /*
1621 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1622 */
1623 static void rp_hangup(struct tty_struct *tty)
1624 {
1625 CHANNEL_t *cp;
1626 struct r_port *info = (struct r_port *) tty->driver_data;
1627
1628 if (rocket_paranoia_check(info, "rp_hangup"))
1629 return;
1630
1631 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1632 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1633 #endif
1634 rp_flush_buffer(tty);
1635 if (info->flags & ROCKET_CLOSING)
1636 return;
1637 if (info->count)
1638 atomic_dec(&rp_num_ports_open);
1639 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1640
1641 info->count = 0;
1642 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1643 info->tty = NULL;
1644
1645 cp = &info->channel;
1646 sDisRxFIFO(cp);
1647 sDisTransmit(cp);
1648 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1649 sDisCTSFlowCtl(cp);
1650 sDisTxSoftFlowCtl(cp);
1651 sClrTxXOFF(cp);
1652 info->flags &= ~ROCKET_INITIALIZED;
1653
1654 wake_up_interruptible(&info->open_wait);
1655 }
1656
1657 /*
1658 * Exception handler - write char routine. The RocketPort driver uses a
1659 * double-buffering strategy, with the twist that if the in-memory CPU
1660 * buffer is empty, and there's space in the transmit FIFO, the
1661 * writing routines will write directly to transmit FIFO.
1662 * Write buffer and counters protected by spinlocks
1663 */
1664 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1665 {
1666 struct r_port *info = (struct r_port *) tty->driver_data;
1667 CHANNEL_t *cp;
1668 unsigned long flags;
1669
1670 if (rocket_paranoia_check(info, "rp_put_char"))
1671 return;
1672
1673 /*
1674 * Grab the port write mutex, locking out other processes that try to
1675 * write to this port
1676 */
1677 mutex_lock(&info->write_mtx);
1678
1679 #ifdef ROCKET_DEBUG_WRITE
1680 printk(KERN_INFO "rp_put_char %c...\n", ch);
1681 #endif
1682
1683 spin_lock_irqsave(&info->slock, flags);
1684 cp = &info->channel;
1685
1686 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1687 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1688
1689 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1690 info->xmit_buf[info->xmit_head++] = ch;
1691 info->xmit_head &= XMIT_BUF_SIZE - 1;
1692 info->xmit_cnt++;
1693 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1694 } else {
1695 sOutB(sGetTxRxDataIO(cp), ch);
1696 info->xmit_fifo_room--;
1697 }
1698 spin_unlock_irqrestore(&info->slock, flags);
1699 mutex_unlock(&info->write_mtx);
1700 }
1701
1702 /*
1703 * Exception handler - write routine, called when user app writes to the device.
1704 * A per port write mutex is used to protect from another process writing to
1705 * this port at the same time. This other process could be running on the other CPU
1706 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1707 * Spinlocks protect the info xmit members.
1708 */
1709 static int rp_write(struct tty_struct *tty,
1710 const unsigned char *buf, int count)
1711 {
1712 struct r_port *info = (struct r_port *) tty->driver_data;
1713 CHANNEL_t *cp;
1714 const unsigned char *b;
1715 int c, retval = 0;
1716 unsigned long flags;
1717
1718 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1719 return 0;
1720
1721 if (mutex_lock_interruptible(&info->write_mtx))
1722 return -ERESTARTSYS;
1723
1724 #ifdef ROCKET_DEBUG_WRITE
1725 printk(KERN_INFO "rp_write %d chars...\n", count);
1726 #endif
1727 cp = &info->channel;
1728
1729 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1730 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1731
1732 /*
1733 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1734 * into FIFO. Use the write queue for temp storage.
1735 */
1736 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1737 c = min(count, info->xmit_fifo_room);
1738 b = buf;
1739
1740 /* Push data into FIFO, 2 bytes at a time */
1741 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1742
1743 /* If there is a byte remaining, write it */
1744 if (c & 1)
1745 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1746
1747 retval += c;
1748 buf += c;
1749 count -= c;
1750
1751 spin_lock_irqsave(&info->slock, flags);
1752 info->xmit_fifo_room -= c;
1753 spin_unlock_irqrestore(&info->slock, flags);
1754 }
1755
1756 /* If count is zero, we wrote it all and are done */
1757 if (!count)
1758 goto end;
1759
1760 /* Write remaining data into the port's xmit_buf */
1761 while (1) {
1762 if (!info->tty) /* Seemingly obligatory check... */
1763 goto end;
1764 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1765 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1766 if (c <= 0)
1767 break;
1768
1769 b = buf;
1770 memcpy(info->xmit_buf + info->xmit_head, b, c);
1771
1772 spin_lock_irqsave(&info->slock, flags);
1773 info->xmit_head =
1774 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1775 info->xmit_cnt += c;
1776 spin_unlock_irqrestore(&info->slock, flags);
1777
1778 buf += c;
1779 count -= c;
1780 retval += c;
1781 }
1782
1783 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1784 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1785
1786 end:
1787 if (info->xmit_cnt < WAKEUP_CHARS) {
1788 tty_wakeup(tty);
1789 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1790 wake_up_interruptible(&tty->poll_wait);
1791 #endif
1792 }
1793 mutex_unlock(&info->write_mtx);
1794 return retval;
1795 }
1796
1797 /*
1798 * Return the number of characters that can be sent. We estimate
1799 * only using the in-memory transmit buffer only, and ignore the
1800 * potential space in the transmit FIFO.
1801 */
1802 static int rp_write_room(struct tty_struct *tty)
1803 {
1804 struct r_port *info = (struct r_port *) tty->driver_data;
1805 int ret;
1806
1807 if (rocket_paranoia_check(info, "rp_write_room"))
1808 return 0;
1809
1810 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1811 if (ret < 0)
1812 ret = 0;
1813 #ifdef ROCKET_DEBUG_WRITE
1814 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1815 #endif
1816 return ret;
1817 }
1818
1819 /*
1820 * Return the number of characters in the buffer. Again, this only
1821 * counts those characters in the in-memory transmit buffer.
1822 */
1823 static int rp_chars_in_buffer(struct tty_struct *tty)
1824 {
1825 struct r_port *info = (struct r_port *) tty->driver_data;
1826 CHANNEL_t *cp;
1827
1828 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1829 return 0;
1830
1831 cp = &info->channel;
1832
1833 #ifdef ROCKET_DEBUG_WRITE
1834 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1835 #endif
1836 return info->xmit_cnt;
1837 }
1838
1839 /*
1840 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1841 * r_port struct for the port. Note that spinlock are used to protect info members,
1842 * do not call this function if the spinlock is already held.
1843 */
1844 static void rp_flush_buffer(struct tty_struct *tty)
1845 {
1846 struct r_port *info = (struct r_port *) tty->driver_data;
1847 CHANNEL_t *cp;
1848 unsigned long flags;
1849
1850 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1851 return;
1852
1853 spin_lock_irqsave(&info->slock, flags);
1854 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1855 spin_unlock_irqrestore(&info->slock, flags);
1856
1857 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1858 wake_up_interruptible(&tty->poll_wait);
1859 #endif
1860 tty_wakeup(tty);
1861
1862 cp = &info->channel;
1863 sFlushTxFIFO(cp);
1864 }
1865
1866 #ifdef CONFIG_PCI
1867
1868 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1869 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1870 { }
1871 };
1872 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1873
1874 /*
1875 * Called when a PCI card is found. Retrieves and stores model information,
1876 * init's aiopic and serial port hardware.
1877 * Inputs: i is the board number (0-n)
1878 */
1879 static __init int register_PCI(int i, struct pci_dev *dev)
1880 {
1881 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1882 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1883 char *str, *board_type;
1884 CONTROLLER_t *ctlp;
1885
1886 int fast_clock = 0;
1887 int altChanRingIndicator = 0;
1888 int ports_per_aiop = 8;
1889 WordIO_t ConfigIO = 0;
1890 ByteIO_t UPCIRingInd = 0;
1891
1892 if (!dev || pci_enable_device(dev))
1893 return 0;
1894
1895 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1896
1897 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1898 rocketModel[i].loadrm2 = 0;
1899 rocketModel[i].startingPortNumber = nextLineNumber;
1900
1901 /* Depending on the model, set up some config variables */
1902 switch (dev->device) {
1903 case PCI_DEVICE_ID_RP4QUAD:
1904 str = "Quadcable";
1905 max_num_aiops = 1;
1906 ports_per_aiop = 4;
1907 rocketModel[i].model = MODEL_RP4QUAD;
1908 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1909 rocketModel[i].numPorts = 4;
1910 break;
1911 case PCI_DEVICE_ID_RP8OCTA:
1912 str = "Octacable";
1913 max_num_aiops = 1;
1914 rocketModel[i].model = MODEL_RP8OCTA;
1915 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1916 rocketModel[i].numPorts = 8;
1917 break;
1918 case PCI_DEVICE_ID_URP8OCTA:
1919 str = "Octacable";
1920 max_num_aiops = 1;
1921 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1922 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1923 rocketModel[i].numPorts = 8;
1924 break;
1925 case PCI_DEVICE_ID_RP8INTF:
1926 str = "8";
1927 max_num_aiops = 1;
1928 rocketModel[i].model = MODEL_RP8INTF;
1929 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1930 rocketModel[i].numPorts = 8;
1931 break;
1932 case PCI_DEVICE_ID_URP8INTF:
1933 str = "8";
1934 max_num_aiops = 1;
1935 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1936 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1937 rocketModel[i].numPorts = 8;
1938 break;
1939 case PCI_DEVICE_ID_RP8J:
1940 str = "8J";
1941 max_num_aiops = 1;
1942 rocketModel[i].model = MODEL_RP8J;
1943 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1944 rocketModel[i].numPorts = 8;
1945 break;
1946 case PCI_DEVICE_ID_RP4J:
1947 str = "4J";
1948 max_num_aiops = 1;
1949 ports_per_aiop = 4;
1950 rocketModel[i].model = MODEL_RP4J;
1951 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1952 rocketModel[i].numPorts = 4;
1953 break;
1954 case PCI_DEVICE_ID_RP8SNI:
1955 str = "8 (DB78 Custom)";
1956 max_num_aiops = 1;
1957 rocketModel[i].model = MODEL_RP8SNI;
1958 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1959 rocketModel[i].numPorts = 8;
1960 break;
1961 case PCI_DEVICE_ID_RP16SNI:
1962 str = "16 (DB78 Custom)";
1963 max_num_aiops = 2;
1964 rocketModel[i].model = MODEL_RP16SNI;
1965 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1966 rocketModel[i].numPorts = 16;
1967 break;
1968 case PCI_DEVICE_ID_RP16INTF:
1969 str = "16";
1970 max_num_aiops = 2;
1971 rocketModel[i].model = MODEL_RP16INTF;
1972 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1973 rocketModel[i].numPorts = 16;
1974 break;
1975 case PCI_DEVICE_ID_URP16INTF:
1976 str = "16";
1977 max_num_aiops = 2;
1978 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1979 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1980 rocketModel[i].numPorts = 16;
1981 break;
1982 case PCI_DEVICE_ID_CRP16INTF:
1983 str = "16";
1984 max_num_aiops = 2;
1985 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1986 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1987 rocketModel[i].numPorts = 16;
1988 break;
1989 case PCI_DEVICE_ID_RP32INTF:
1990 str = "32";
1991 max_num_aiops = 4;
1992 rocketModel[i].model = MODEL_RP32INTF;
1993 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1994 rocketModel[i].numPorts = 32;
1995 break;
1996 case PCI_DEVICE_ID_URP32INTF:
1997 str = "32";
1998 max_num_aiops = 4;
1999 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2000 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2001 rocketModel[i].numPorts = 32;
2002 break;
2003 case PCI_DEVICE_ID_RPP4:
2004 str = "Plus Quadcable";
2005 max_num_aiops = 1;
2006 ports_per_aiop = 4;
2007 altChanRingIndicator++;
2008 fast_clock++;
2009 rocketModel[i].model = MODEL_RPP4;
2010 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2011 rocketModel[i].numPorts = 4;
2012 break;
2013 case PCI_DEVICE_ID_RPP8:
2014 str = "Plus Octacable";
2015 max_num_aiops = 2;
2016 ports_per_aiop = 4;
2017 altChanRingIndicator++;
2018 fast_clock++;
2019 rocketModel[i].model = MODEL_RPP8;
2020 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2021 rocketModel[i].numPorts = 8;
2022 break;
2023 case PCI_DEVICE_ID_RP2_232:
2024 str = "Plus 2 (RS-232)";
2025 max_num_aiops = 1;
2026 ports_per_aiop = 2;
2027 altChanRingIndicator++;
2028 fast_clock++;
2029 rocketModel[i].model = MODEL_RP2_232;
2030 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2031 rocketModel[i].numPorts = 2;
2032 break;
2033 case PCI_DEVICE_ID_RP2_422:
2034 str = "Plus 2 (RS-422)";
2035 max_num_aiops = 1;
2036 ports_per_aiop = 2;
2037 altChanRingIndicator++;
2038 fast_clock++;
2039 rocketModel[i].model = MODEL_RP2_422;
2040 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2041 rocketModel[i].numPorts = 2;
2042 break;
2043 case PCI_DEVICE_ID_RP6M:
2044
2045 max_num_aiops = 1;
2046 ports_per_aiop = 6;
2047 str = "6-port";
2048
2049 /* If revision is 1, the rocketmodem flash must be loaded.
2050 * If it is 2 it is a "socketed" version. */
2051 if (dev->revision == 1) {
2052 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2053 rocketModel[i].loadrm2 = 1;
2054 } else {
2055 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2056 }
2057
2058 rocketModel[i].model = MODEL_RP6M;
2059 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2060 rocketModel[i].numPorts = 6;
2061 break;
2062 case PCI_DEVICE_ID_RP4M:
2063 max_num_aiops = 1;
2064 ports_per_aiop = 4;
2065 str = "4-port";
2066 if (dev->revision == 1) {
2067 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2068 rocketModel[i].loadrm2 = 1;
2069 } else {
2070 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2071 }
2072
2073 rocketModel[i].model = MODEL_RP4M;
2074 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2075 rocketModel[i].numPorts = 4;
2076 break;
2077 default:
2078 str = "(unknown/unsupported)";
2079 max_num_aiops = 0;
2080 break;
2081 }
2082
2083 /*
2084 * Check for UPCI boards.
2085 */
2086
2087 switch (dev->device) {
2088 case PCI_DEVICE_ID_URP32INTF:
2089 case PCI_DEVICE_ID_URP8INTF:
2090 case PCI_DEVICE_ID_URP16INTF:
2091 case PCI_DEVICE_ID_CRP16INTF:
2092 case PCI_DEVICE_ID_URP8OCTA:
2093 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2094 ConfigIO = pci_resource_start(dev, 1);
2095 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2096 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2097
2098 /*
2099 * Check for octa or quad cable.
2100 */
2101 if (!
2102 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2103 PCI_GPIO_CTRL_8PORT)) {
2104 str = "Quadcable";
2105 ports_per_aiop = 4;
2106 rocketModel[i].numPorts = 4;
2107 }
2108 }
2109 break;
2110 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2111 str = "8 ports";
2112 max_num_aiops = 1;
2113 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2114 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2115 rocketModel[i].numPorts = 8;
2116 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2117 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2118 ConfigIO = pci_resource_start(dev, 1);
2119 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2120 break;
2121 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2122 str = "4 ports";
2123 max_num_aiops = 1;
2124 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2125 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2126 rocketModel[i].numPorts = 4;
2127 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2128 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2129 ConfigIO = pci_resource_start(dev, 1);
2130 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2131 break;
2132 default:
2133 break;
2134 }
2135
2136 switch (rcktpt_type[i]) {
2137 case ROCKET_TYPE_MODEM:
2138 board_type = "RocketModem";
2139 break;
2140 case ROCKET_TYPE_MODEMII:
2141 board_type = "RocketModem II";
2142 break;
2143 case ROCKET_TYPE_MODEMIII:
2144 board_type = "RocketModem III";
2145 break;
2146 default:
2147 board_type = "RocketPort";
2148 break;
2149 }
2150
2151 if (fast_clock) {
2152 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2153 rp_baud_base[i] = 921600;
2154 } else {
2155 /*
2156 * If support_low_speed is set, use the slow clock
2157 * prescale, which supports 50 bps
2158 */
2159 if (support_low_speed) {
2160 /* mod 9 (divide by 10) prescale */
2161 sClockPrescale = 0x19;
2162 rp_baud_base[i] = 230400;
2163 } else {
2164 /* mod 4 (devide by 5) prescale */
2165 sClockPrescale = 0x14;
2166 rp_baud_base[i] = 460800;
2167 }
2168 }
2169
2170 for (aiop = 0; aiop < max_num_aiops; aiop++)
2171 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2172 ctlp = sCtlNumToCtlPtr(i);
2173 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2174 for (aiop = 0; aiop < max_num_aiops; aiop++)
2175 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2176
2177 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2178 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2179 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2180 rocketModel[i].startingPortNumber,
2181 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2182
2183 if (num_aiops <= 0) {
2184 rcktpt_io_addr[i] = 0;
2185 return (0);
2186 }
2187 is_PCI[i] = 1;
2188
2189 /* Reset the AIOPIC, init the serial ports */
2190 for (aiop = 0; aiop < num_aiops; aiop++) {
2191 sResetAiopByNum(ctlp, aiop);
2192 num_chan = ports_per_aiop;
2193 for (chan = 0; chan < num_chan; chan++)
2194 init_r_port(i, aiop, chan, dev);
2195 }
2196
2197 /* Rocket modems must be reset */
2198 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2199 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2200 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2201 num_chan = ports_per_aiop;
2202 for (chan = 0; chan < num_chan; chan++)
2203 sPCIModemReset(ctlp, chan, 1);
2204 msleep(500);
2205 for (chan = 0; chan < num_chan; chan++)
2206 sPCIModemReset(ctlp, chan, 0);
2207 msleep(500);
2208 rmSpeakerReset(ctlp, rocketModel[i].model);
2209 }
2210 return (1);
2211 }
2212
2213 /*
2214 * Probes for PCI cards, inits them if found
2215 * Input: board_found = number of ISA boards already found, or the
2216 * starting board number
2217 * Returns: Number of PCI boards found
2218 */
2219 static int __init init_PCI(int boards_found)
2220 {
2221 struct pci_dev *dev = NULL;
2222 int count = 0;
2223
2224 /* Work through the PCI device list, pulling out ours */
2225 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2226 if (register_PCI(count + boards_found, dev))
2227 count++;
2228 }
2229 return (count);
2230 }
2231
2232 #endif /* CONFIG_PCI */
2233
2234 /*
2235 * Probes for ISA cards
2236 * Input: i = the board number to look for
2237 * Returns: 1 if board found, 0 else
2238 */
2239 static int __init init_ISA(int i)
2240 {
2241 int num_aiops, num_chan = 0, total_num_chan = 0;
2242 int aiop, chan;
2243 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2244 CONTROLLER_t *ctlp;
2245 char *type_string;
2246
2247 /* If io_addr is zero, no board configured */
2248 if (rcktpt_io_addr[i] == 0)
2249 return (0);
2250
2251 /* Reserve the IO region */
2252 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2253 printk(KERN_ERR "Unable to reserve IO region for configured "
2254 "ISA RocketPort at address 0x%lx, board not "
2255 "installed...\n", rcktpt_io_addr[i]);
2256 rcktpt_io_addr[i] = 0;
2257 return (0);
2258 }
2259
2260 ctlp = sCtlNumToCtlPtr(i);
2261
2262 ctlp->boardType = rcktpt_type[i];
2263
2264 switch (rcktpt_type[i]) {
2265 case ROCKET_TYPE_PC104:
2266 type_string = "(PC104)";
2267 break;
2268 case ROCKET_TYPE_MODEM:
2269 type_string = "(RocketModem)";
2270 break;
2271 case ROCKET_TYPE_MODEMII:
2272 type_string = "(RocketModem II)";
2273 break;
2274 default:
2275 type_string = "";
2276 break;
2277 }
2278
2279 /*
2280 * If support_low_speed is set, use the slow clock prescale,
2281 * which supports 50 bps
2282 */
2283 if (support_low_speed) {
2284 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2285 rp_baud_base[i] = 230400;
2286 } else {
2287 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2288 rp_baud_base[i] = 460800;
2289 }
2290
2291 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2292 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2293
2294 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2295
2296 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2297 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2298 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2299 }
2300
2301 /* If something went wrong initing the AIOP's release the ISA IO memory */
2302 if (num_aiops <= 0) {
2303 release_region(rcktpt_io_addr[i], 64);
2304 rcktpt_io_addr[i] = 0;
2305 return (0);
2306 }
2307
2308 rocketModel[i].startingPortNumber = nextLineNumber;
2309
2310 for (aiop = 0; aiop < num_aiops; aiop++) {
2311 sResetAiopByNum(ctlp, aiop);
2312 sEnAiop(ctlp, aiop);
2313 num_chan = sGetAiopNumChan(ctlp, aiop);
2314 total_num_chan += num_chan;
2315 for (chan = 0; chan < num_chan; chan++)
2316 init_r_port(i, aiop, chan, NULL);
2317 }
2318 is_PCI[i] = 0;
2319 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2320 num_chan = sGetAiopNumChan(ctlp, 0);
2321 total_num_chan = num_chan;
2322 for (chan = 0; chan < num_chan; chan++)
2323 sModemReset(ctlp, chan, 1);
2324 msleep(500);
2325 for (chan = 0; chan < num_chan; chan++)
2326 sModemReset(ctlp, chan, 0);
2327 msleep(500);
2328 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2329 } else {
2330 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2331 }
2332 rocketModel[i].numPorts = total_num_chan;
2333 rocketModel[i].model = MODEL_ISA;
2334
2335 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2336 i, rcktpt_io_addr[i], num_aiops, type_string);
2337
2338 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2339 rocketModel[i].modelString,
2340 rocketModel[i].startingPortNumber,
2341 rocketModel[i].startingPortNumber +
2342 rocketModel[i].numPorts - 1);
2343
2344 return (1);
2345 }
2346
2347 static const struct tty_operations rocket_ops = {
2348 .open = rp_open,
2349 .close = rp_close,
2350 .write = rp_write,
2351 .put_char = rp_put_char,
2352 .write_room = rp_write_room,
2353 .chars_in_buffer = rp_chars_in_buffer,
2354 .flush_buffer = rp_flush_buffer,
2355 .ioctl = rp_ioctl,
2356 .throttle = rp_throttle,
2357 .unthrottle = rp_unthrottle,
2358 .set_termios = rp_set_termios,
2359 .stop = rp_stop,
2360 .start = rp_start,
2361 .hangup = rp_hangup,
2362 .break_ctl = rp_break,
2363 .send_xchar = rp_send_xchar,
2364 .wait_until_sent = rp_wait_until_sent,
2365 .tiocmget = rp_tiocmget,
2366 .tiocmset = rp_tiocmset,
2367 };
2368
2369 /*
2370 * The module "startup" routine; it's run when the module is loaded.
2371 */
2372 static int __init rp_init(void)
2373 {
2374 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2375
2376 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2377 ROCKET_VERSION, ROCKET_DATE);
2378
2379 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2380 if (!rocket_driver)
2381 goto err;
2382
2383 /*
2384 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2385 * zero, use the default controller IO address of board1 + 0x40.
2386 */
2387 if (board1) {
2388 if (controller == 0)
2389 controller = board1 + 0x40;
2390 } else {
2391 controller = 0; /* Used as a flag, meaning no ISA boards */
2392 }
2393
2394 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2395 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2396 printk(KERN_ERR "Unable to reserve IO region for first "
2397 "configured ISA RocketPort controller 0x%lx. "
2398 "Driver exiting\n", controller);
2399 ret = -EBUSY;
2400 goto err_tty;
2401 }
2402
2403 /* Store ISA variable retrieved from command line or .conf file. */
2404 rcktpt_io_addr[0] = board1;
2405 rcktpt_io_addr[1] = board2;
2406 rcktpt_io_addr[2] = board3;
2407 rcktpt_io_addr[3] = board4;
2408
2409 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2410 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2411 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2412 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2413 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2414 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2415 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2416 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2417
2418 /*
2419 * Set up the tty driver structure and then register this
2420 * driver with the tty layer.
2421 */
2422
2423 rocket_driver->owner = THIS_MODULE;
2424 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2425 rocket_driver->name = "ttyR";
2426 rocket_driver->driver_name = "Comtrol RocketPort";
2427 rocket_driver->major = TTY_ROCKET_MAJOR;
2428 rocket_driver->minor_start = 0;
2429 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2430 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2431 rocket_driver->init_termios = tty_std_termios;
2432 rocket_driver->init_termios.c_cflag =
2433 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2434 rocket_driver->init_termios.c_ispeed = 9600;
2435 rocket_driver->init_termios.c_ospeed = 9600;
2436 #ifdef ROCKET_SOFT_FLOW
2437 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2438 #endif
2439 tty_set_operations(rocket_driver, &rocket_ops);
2440
2441 ret = tty_register_driver(rocket_driver);
2442 if (ret < 0) {
2443 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2444 goto err_tty;
2445 }
2446
2447 #ifdef ROCKET_DEBUG_OPEN
2448 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2449 #endif
2450
2451 /*
2452 * OK, let's probe each of the controllers looking for boards. Any boards found
2453 * will be initialized here.
2454 */
2455 isa_boards_found = 0;
2456 pci_boards_found = 0;
2457
2458 for (i = 0; i < NUM_BOARDS; i++) {
2459 if (init_ISA(i))
2460 isa_boards_found++;
2461 }
2462
2463 #ifdef CONFIG_PCI
2464 if (isa_boards_found < NUM_BOARDS)
2465 pci_boards_found = init_PCI(isa_boards_found);
2466 #endif
2467
2468 max_board = pci_boards_found + isa_boards_found;
2469
2470 if (max_board == 0) {
2471 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2472 ret = -ENXIO;
2473 goto err_ttyu;
2474 }
2475
2476 return 0;
2477 err_ttyu:
2478 tty_unregister_driver(rocket_driver);
2479 err_tty:
2480 put_tty_driver(rocket_driver);
2481 err:
2482 return ret;
2483 }
2484
2485
2486 static void rp_cleanup_module(void)
2487 {
2488 int retval;
2489 int i;
2490
2491 del_timer_sync(&rocket_timer);
2492
2493 retval = tty_unregister_driver(rocket_driver);
2494 if (retval)
2495 printk(KERN_ERR "Error %d while trying to unregister "
2496 "rocketport driver\n", -retval);
2497
2498 for (i = 0; i < MAX_RP_PORTS; i++)
2499 if (rp_table[i]) {
2500 tty_unregister_device(rocket_driver, i);
2501 kfree(rp_table[i]);
2502 }
2503
2504 put_tty_driver(rocket_driver);
2505
2506 for (i = 0; i < NUM_BOARDS; i++) {
2507 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2508 continue;
2509 release_region(rcktpt_io_addr[i], 64);
2510 }
2511 if (controller)
2512 release_region(controller, 4);
2513 }
2514
2515 /***************************************************************************
2516 Function: sInitController
2517 Purpose: Initialization of controller global registers and controller
2518 structure.
2519 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2520 IRQNum,Frequency,PeriodicOnly)
2521 CONTROLLER_T *CtlP; Ptr to controller structure
2522 int CtlNum; Controller number
2523 ByteIO_t MudbacIO; Mudbac base I/O address.
2524 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2525 This list must be in the order the AIOPs will be found on the
2526 controller. Once an AIOP in the list is not found, it is
2527 assumed that there are no more AIOPs on the controller.
2528 int AiopIOListSize; Number of addresses in AiopIOList
2529 int IRQNum; Interrupt Request number. Can be any of the following:
2530 0: Disable global interrupts
2531 3: IRQ 3
2532 4: IRQ 4
2533 5: IRQ 5
2534 9: IRQ 9
2535 10: IRQ 10
2536 11: IRQ 11
2537 12: IRQ 12
2538 15: IRQ 15
2539 Byte_t Frequency: A flag identifying the frequency
2540 of the periodic interrupt, can be any one of the following:
2541 FREQ_DIS - periodic interrupt disabled
2542 FREQ_137HZ - 137 Hertz
2543 FREQ_69HZ - 69 Hertz
2544 FREQ_34HZ - 34 Hertz
2545 FREQ_17HZ - 17 Hertz
2546 FREQ_9HZ - 9 Hertz
2547 FREQ_4HZ - 4 Hertz
2548 If IRQNum is set to 0 the Frequency parameter is
2549 overidden, it is forced to a value of FREQ_DIS.
2550 int PeriodicOnly: 1 if all interrupts except the periodic
2551 interrupt are to be blocked.
2552 0 is both the periodic interrupt and
2553 other channel interrupts are allowed.
2554 If IRQNum is set to 0 the PeriodicOnly parameter is
2555 overidden, it is forced to a value of 0.
2556 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2557 initialization failed.
2558
2559 Comments:
2560 If periodic interrupts are to be disabled but AIOP interrupts
2561 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2562
2563 If interrupts are to be completely disabled set IRQNum to 0.
2564
2565 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2566 invalid combination.
2567
2568 This function performs initialization of global interrupt modes,
2569 but it does not actually enable global interrupts. To enable
2570 and disable global interrupts use functions sEnGlobalInt() and
2571 sDisGlobalInt(). Enabling of global interrupts is normally not
2572 done until all other initializations are complete.
2573
2574 Even if interrupts are globally enabled, they must also be
2575 individually enabled for each channel that is to generate
2576 interrupts.
2577
2578 Warnings: No range checking on any of the parameters is done.
2579
2580 No context switches are allowed while executing this function.
2581
2582 After this function all AIOPs on the controller are disabled,
2583 they can be enabled with sEnAiop().
2584 */
2585 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2586 ByteIO_t * AiopIOList, int AiopIOListSize,
2587 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2588 {
2589 int i;
2590 ByteIO_t io;
2591 int done;
2592
2593 CtlP->AiopIntrBits = aiop_intr_bits;
2594 CtlP->AltChanRingIndicator = 0;
2595 CtlP->CtlNum = CtlNum;
2596 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2597 CtlP->BusType = isISA;
2598 CtlP->MBaseIO = MudbacIO;
2599 CtlP->MReg1IO = MudbacIO + 1;
2600 CtlP->MReg2IO = MudbacIO + 2;
2601 CtlP->MReg3IO = MudbacIO + 3;
2602 #if 1
2603 CtlP->MReg2 = 0; /* interrupt disable */
2604 CtlP->MReg3 = 0; /* no periodic interrupts */
2605 #else
2606 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2607 CtlP->MReg2 = 0; /* interrupt disable */
2608 CtlP->MReg3 = 0; /* no periodic interrupts */
2609 } else {
2610 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2611 CtlP->MReg3 = Frequency; /* set frequency */
2612 if (PeriodicOnly) { /* periodic interrupt only */
2613 CtlP->MReg3 |= PERIODIC_ONLY;
2614 }
2615 }
2616 #endif
2617 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2618 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2619 sControllerEOI(CtlP); /* clear EOI if warm init */
2620 /* Init AIOPs */
2621 CtlP->NumAiop = 0;
2622 for (i = done = 0; i < AiopIOListSize; i++) {
2623 io = AiopIOList[i];
2624 CtlP->AiopIO[i] = (WordIO_t) io;
2625 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2626 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2627 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2628 if (done)
2629 continue;
2630 sEnAiop(CtlP, i); /* enable the AIOP */
2631 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2632 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2633 done = 1; /* done looking for AIOPs */
2634 else {
2635 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2636 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2637 sOutB(io + _INDX_DATA, sClockPrescale);
2638 CtlP->NumAiop++; /* bump count of AIOPs */
2639 }
2640 sDisAiop(CtlP, i); /* disable AIOP */
2641 }
2642
2643 if (CtlP->NumAiop == 0)
2644 return (-1);
2645 else
2646 return (CtlP->NumAiop);
2647 }
2648
2649 /***************************************************************************
2650 Function: sPCIInitController
2651 Purpose: Initialization of controller global registers and controller
2652 structure.
2653 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2654 IRQNum,Frequency,PeriodicOnly)
2655 CONTROLLER_T *CtlP; Ptr to controller structure
2656 int CtlNum; Controller number
2657 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2658 This list must be in the order the AIOPs will be found on the
2659 controller. Once an AIOP in the list is not found, it is
2660 assumed that there are no more AIOPs on the controller.
2661 int AiopIOListSize; Number of addresses in AiopIOList
2662 int IRQNum; Interrupt Request number. Can be any of the following:
2663 0: Disable global interrupts
2664 3: IRQ 3
2665 4: IRQ 4
2666 5: IRQ 5
2667 9: IRQ 9
2668 10: IRQ 10
2669 11: IRQ 11
2670 12: IRQ 12
2671 15: IRQ 15
2672 Byte_t Frequency: A flag identifying the frequency
2673 of the periodic interrupt, can be any one of the following:
2674 FREQ_DIS - periodic interrupt disabled
2675 FREQ_137HZ - 137 Hertz
2676 FREQ_69HZ - 69 Hertz
2677 FREQ_34HZ - 34 Hertz
2678 FREQ_17HZ - 17 Hertz
2679 FREQ_9HZ - 9 Hertz
2680 FREQ_4HZ - 4 Hertz
2681 If IRQNum is set to 0 the Frequency parameter is
2682 overidden, it is forced to a value of FREQ_DIS.
2683 int PeriodicOnly: 1 if all interrupts except the periodic
2684 interrupt are to be blocked.
2685 0 is both the periodic interrupt and
2686 other channel interrupts are allowed.
2687 If IRQNum is set to 0 the PeriodicOnly parameter is
2688 overidden, it is forced to a value of 0.
2689 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2690 initialization failed.
2691
2692 Comments:
2693 If periodic interrupts are to be disabled but AIOP interrupts
2694 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2695
2696 If interrupts are to be completely disabled set IRQNum to 0.
2697
2698 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2699 invalid combination.
2700
2701 This function performs initialization of global interrupt modes,
2702 but it does not actually enable global interrupts. To enable
2703 and disable global interrupts use functions sEnGlobalInt() and
2704 sDisGlobalInt(). Enabling of global interrupts is normally not
2705 done until all other initializations are complete.
2706
2707 Even if interrupts are globally enabled, they must also be
2708 individually enabled for each channel that is to generate
2709 interrupts.
2710
2711 Warnings: No range checking on any of the parameters is done.
2712
2713 No context switches are allowed while executing this function.
2714
2715 After this function all AIOPs on the controller are disabled,
2716 they can be enabled with sEnAiop().
2717 */
2718 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2719 ByteIO_t * AiopIOList, int AiopIOListSize,
2720 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2721 int PeriodicOnly, int altChanRingIndicator,
2722 int UPCIRingInd)
2723 {
2724 int i;
2725 ByteIO_t io;
2726
2727 CtlP->AltChanRingIndicator = altChanRingIndicator;
2728 CtlP->UPCIRingInd = UPCIRingInd;
2729 CtlP->CtlNum = CtlNum;
2730 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2731 CtlP->BusType = isPCI; /* controller release 1 */
2732
2733 if (ConfigIO) {
2734 CtlP->isUPCI = 1;
2735 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2736 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2737 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2738 } else {
2739 CtlP->isUPCI = 0;
2740 CtlP->PCIIO =
2741 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2742 CtlP->AiopIntrBits = aiop_intr_bits;
2743 }
2744
2745 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2746 /* Init AIOPs */
2747 CtlP->NumAiop = 0;
2748 for (i = 0; i < AiopIOListSize; i++) {
2749 io = AiopIOList[i];
2750 CtlP->AiopIO[i] = (WordIO_t) io;
2751 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2752
2753 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2754 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2755 break; /* done looking for AIOPs */
2756
2757 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2758 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2759 sOutB(io + _INDX_DATA, sClockPrescale);
2760 CtlP->NumAiop++; /* bump count of AIOPs */
2761 }
2762
2763 if (CtlP->NumAiop == 0)
2764 return (-1);
2765 else
2766 return (CtlP->NumAiop);
2767 }
2768
2769 /***************************************************************************
2770 Function: sReadAiopID
2771 Purpose: Read the AIOP idenfication number directly from an AIOP.
2772 Call: sReadAiopID(io)
2773 ByteIO_t io: AIOP base I/O address
2774 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2775 is replace by an identifying number.
2776 Flag AIOPID_NULL if no valid AIOP is found
2777 Warnings: No context switches are allowed while executing this function.
2778
2779 */
2780 static int sReadAiopID(ByteIO_t io)
2781 {
2782 Byte_t AiopID; /* ID byte from AIOP */
2783
2784 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2785 sOutB(io + _CMD_REG, 0x0);
2786 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2787 if (AiopID == 0x06)
2788 return (1);
2789 else /* AIOP does not exist */
2790 return (-1);
2791 }
2792
2793 /***************************************************************************
2794 Function: sReadAiopNumChan
2795 Purpose: Read the number of channels available in an AIOP directly from
2796 an AIOP.
2797 Call: sReadAiopNumChan(io)
2798 WordIO_t io: AIOP base I/O address
2799 Return: int: The number of channels available
2800 Comments: The number of channels is determined by write/reads from identical
2801 offsets within the SRAM address spaces for channels 0 and 4.
2802 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2803 AIOP, otherwise it is an 8 channel.
2804 Warnings: No context switches are allowed while executing this function.
2805 */
2806 static int sReadAiopNumChan(WordIO_t io)
2807 {
2808 Word_t x;
2809 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2810
2811 /* write to chan 0 SRAM */
2812 out32((DWordIO_t) io + _INDX_ADDR, R);
2813 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2814 x = sInW(io + _INDX_DATA);
2815 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2816 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2817 return (8);
2818 else
2819 return (4);
2820 }
2821
2822 /***************************************************************************
2823 Function: sInitChan
2824 Purpose: Initialization of a channel and channel structure
2825 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2826 CONTROLLER_T *CtlP; Ptr to controller structure
2827 CHANNEL_T *ChP; Ptr to channel structure
2828 int AiopNum; AIOP number within controller
2829 int ChanNum; Channel number within AIOP
2830 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2831 number exceeds number of channels available in AIOP.
2832 Comments: This function must be called before a channel can be used.
2833 Warnings: No range checking on any of the parameters is done.
2834
2835 No context switches are allowed while executing this function.
2836 */
2837 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2838 int ChanNum)
2839 {
2840 int i;
2841 WordIO_t AiopIO;
2842 WordIO_t ChIOOff;
2843 Byte_t *ChR;
2844 Word_t ChOff;
2845 static Byte_t R[4];
2846 int brd9600;
2847
2848 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2849 return 0; /* exceeds num chans in AIOP */
2850
2851 /* Channel, AIOP, and controller identifiers */
2852 ChP->CtlP = CtlP;
2853 ChP->ChanID = CtlP->AiopID[AiopNum];
2854 ChP->AiopNum = AiopNum;
2855 ChP->ChanNum = ChanNum;
2856
2857 /* Global direct addresses */
2858 AiopIO = CtlP->AiopIO[AiopNum];
2859 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2860 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2861 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2862 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2863 ChP->IndexData = AiopIO + _INDX_DATA;
2864
2865 /* Channel direct addresses */
2866 ChIOOff = AiopIO + ChP->ChanNum * 2;
2867 ChP->TxRxData = ChIOOff + _TD0;
2868 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2869 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2870 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2871
2872 /* Initialize the channel from the RData array */
2873 for (i = 0; i < RDATASIZE; i += 4) {
2874 R[0] = RData[i];
2875 R[1] = RData[i + 1] + 0x10 * ChanNum;
2876 R[2] = RData[i + 2];
2877 R[3] = RData[i + 3];
2878 out32(ChP->IndexAddr, R);
2879 }
2880
2881 ChR = ChP->R;
2882 for (i = 0; i < RREGDATASIZE; i += 4) {
2883 ChR[i] = RRegData[i];
2884 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2885 ChR[i + 2] = RRegData[i + 2];
2886 ChR[i + 3] = RRegData[i + 3];
2887 }
2888
2889 /* Indexed registers */
2890 ChOff = (Word_t) ChanNum *0x1000;
2891
2892 if (sClockPrescale == 0x14)
2893 brd9600 = 47;
2894 else
2895 brd9600 = 23;
2896
2897 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2898 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2899 ChP->BaudDiv[2] = (Byte_t) brd9600;
2900 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2901 out32(ChP->IndexAddr, ChP->BaudDiv);
2902
2903 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2904 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2905 ChP->TxControl[2] = 0;
2906 ChP->TxControl[3] = 0;
2907 out32(ChP->IndexAddr, ChP->TxControl);
2908
2909 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2910 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2911 ChP->RxControl[2] = 0;
2912 ChP->RxControl[3] = 0;
2913 out32(ChP->IndexAddr, ChP->RxControl);
2914
2915 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2916 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2917 ChP->TxEnables[2] = 0;
2918 ChP->TxEnables[3] = 0;
2919 out32(ChP->IndexAddr, ChP->TxEnables);
2920
2921 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2922 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2923 ChP->TxCompare[2] = 0;
2924 ChP->TxCompare[3] = 0;
2925 out32(ChP->IndexAddr, ChP->TxCompare);
2926
2927 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2928 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2929 ChP->TxReplace1[2] = 0;
2930 ChP->TxReplace1[3] = 0;
2931 out32(ChP->IndexAddr, ChP->TxReplace1);
2932
2933 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2934 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2935 ChP->TxReplace2[2] = 0;
2936 ChP->TxReplace2[3] = 0;
2937 out32(ChP->IndexAddr, ChP->TxReplace2);
2938
2939 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2940 ChP->TxFIFO = ChOff + _TX_FIFO;
2941
2942 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2943 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2944 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2945 sOutW(ChP->IndexData, 0);
2946 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2947 ChP->RxFIFO = ChOff + _RX_FIFO;
2948
2949 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2950 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2951 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2952 sOutW(ChP->IndexData, 0);
2953 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2954 sOutW(ChP->IndexData, 0);
2955 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2956 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2957 sOutB(ChP->IndexData, 0);
2958 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2959 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2960 sOutB(ChP->IndexData, 0);
2961 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2962 sEnRxProcessor(ChP); /* start the Rx processor */
2963
2964 return 1;
2965 }
2966
2967 /***************************************************************************
2968 Function: sStopRxProcessor
2969 Purpose: Stop the receive processor from processing a channel.
2970 Call: sStopRxProcessor(ChP)
2971 CHANNEL_T *ChP; Ptr to channel structure
2972
2973 Comments: The receive processor can be started again with sStartRxProcessor().
2974 This function causes the receive processor to skip over the
2975 stopped channel. It does not stop it from processing other channels.
2976
2977 Warnings: No context switches are allowed while executing this function.
2978
2979 Do not leave the receive processor stopped for more than one
2980 character time.
2981
2982 After calling this function a delay of 4 uS is required to ensure
2983 that the receive processor is no longer processing this channel.
2984 */
2985 static void sStopRxProcessor(CHANNEL_T * ChP)
2986 {
2987 Byte_t R[4];
2988
2989 R[0] = ChP->R[0];
2990 R[1] = ChP->R[1];
2991 R[2] = 0x0a;
2992 R[3] = ChP->R[3];
2993 out32(ChP->IndexAddr, R);
2994 }
2995
2996 /***************************************************************************
2997 Function: sFlushRxFIFO
2998 Purpose: Flush the Rx FIFO
2999 Call: sFlushRxFIFO(ChP)
3000 CHANNEL_T *ChP; Ptr to channel structure
3001 Return: void
3002 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3003 while it is being flushed the receive processor is stopped
3004 and the transmitter is disabled. After these operations a
3005 4 uS delay is done before clearing the pointers to allow
3006 the receive processor to stop. These items are handled inside
3007 this function.
3008 Warnings: No context switches are allowed while executing this function.
3009 */
3010 static void sFlushRxFIFO(CHANNEL_T * ChP)
3011 {
3012 int i;
3013 Byte_t Ch; /* channel number within AIOP */
3014 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3015
3016 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3017 return; /* don't need to flush */
3018
3019 RxFIFOEnabled = 0;
3020 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3021 RxFIFOEnabled = 1;
3022 sDisRxFIFO(ChP); /* disable it */
3023 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3024 sInB(ChP->IntChan); /* depends on bus i/o timing */
3025 }
3026 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3027 Ch = (Byte_t) sGetChanNum(ChP);
3028 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3029 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3030 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3031 sOutW(ChP->IndexData, 0);
3032 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3033 sOutW(ChP->IndexData, 0);
3034 if (RxFIFOEnabled)
3035 sEnRxFIFO(ChP); /* enable Rx FIFO */
3036 }
3037
3038 /***************************************************************************
3039 Function: sFlushTxFIFO
3040 Purpose: Flush the Tx FIFO
3041 Call: sFlushTxFIFO(ChP)
3042 CHANNEL_T *ChP; Ptr to channel structure
3043 Return: void
3044 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3045 while it is being flushed the receive processor is stopped
3046 and the transmitter is disabled. After these operations a
3047 4 uS delay is done before clearing the pointers to allow
3048 the receive processor to stop. These items are handled inside
3049 this function.
3050 Warnings: No context switches are allowed while executing this function.
3051 */
3052 static void sFlushTxFIFO(CHANNEL_T * ChP)
3053 {
3054 int i;
3055 Byte_t Ch; /* channel number within AIOP */
3056 int TxEnabled; /* 1 if transmitter enabled */
3057
3058 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3059 return; /* don't need to flush */
3060
3061 TxEnabled = 0;
3062 if (ChP->TxControl[3] & TX_ENABLE) {
3063 TxEnabled = 1;
3064 sDisTransmit(ChP); /* disable transmitter */
3065 }
3066 sStopRxProcessor(ChP); /* stop Rx processor */
3067 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3068 sInB(ChP->IntChan); /* depends on bus i/o timing */
3069 Ch = (Byte_t) sGetChanNum(ChP);
3070 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3071 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3072 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3073 sOutW(ChP->IndexData, 0);
3074 if (TxEnabled)
3075 sEnTransmit(ChP); /* enable transmitter */
3076 sStartRxProcessor(ChP); /* restart Rx processor */
3077 }
3078
3079 /***************************************************************************
3080 Function: sWriteTxPrioByte
3081 Purpose: Write a byte of priority transmit data to a channel
3082 Call: sWriteTxPrioByte(ChP,Data)
3083 CHANNEL_T *ChP; Ptr to channel structure
3084 Byte_t Data; The transmit data byte
3085
3086 Return: int: 1 if the bytes is successfully written, otherwise 0.
3087
3088 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3089
3090 Warnings: No context switches are allowed while executing this function.
3091 */
3092 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3093 {
3094 Byte_t DWBuf[4]; /* buffer for double word writes */
3095 Word_t *WordPtr; /* must be far because Win SS != DS */
3096 register DWordIO_t IndexAddr;
3097
3098 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3099 IndexAddr = ChP->IndexAddr;
3100 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3101 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3102 return (0); /* nothing sent */
3103
3104 WordPtr = (Word_t *) (&DWBuf[0]);
3105 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3106
3107 DWBuf[2] = Data; /* data byte value */
3108 out32(IndexAddr, DWBuf); /* write it out */
3109
3110 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3111
3112 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3113 DWBuf[3] = 0; /* priority buffer pointer */
3114 out32(IndexAddr, DWBuf); /* write it out */
3115 } else { /* write it to Tx FIFO */
3116
3117 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3118 }
3119 return (1); /* 1 byte sent */
3120 }
3121
3122 /***************************************************************************
3123 Function: sEnInterrupts
3124 Purpose: Enable one or more interrupts for a channel
3125 Call: sEnInterrupts(ChP,Flags)
3126 CHANNEL_T *ChP; Ptr to channel structure
3127 Word_t Flags: Interrupt enable flags, can be any combination
3128 of the following flags:
3129 TXINT_EN: Interrupt on Tx FIFO empty
3130 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3131 sSetRxTrigger())
3132 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3133 MCINT_EN: Interrupt on modem input change
3134 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3135 Interrupt Channel Register.
3136 Return: void
3137 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3138 enabled. If an interrupt enable flag is not set in Flags, that
3139 interrupt will not be changed. Interrupts can be disabled with
3140 function sDisInterrupts().
3141
3142 This function sets the appropriate bit for the channel in the AIOP's
3143 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3144 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3145
3146 Interrupts must also be globally enabled before channel interrupts
3147 will be passed on to the host. This is done with function
3148 sEnGlobalInt().
3149
3150 In some cases it may be desirable to disable interrupts globally but
3151 enable channel interrupts. This would allow the global interrupt
3152 status register to be used to determine which AIOPs need service.
3153 */
3154 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3155 {
3156 Byte_t Mask; /* Interrupt Mask Register */
3157
3158 ChP->RxControl[2] |=
3159 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3160
3161 out32(ChP->IndexAddr, ChP->RxControl);
3162
3163 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3164
3165 out32(ChP->IndexAddr, ChP->TxControl);
3166
3167 if (Flags & CHANINT_EN) {
3168 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3169 sOutB(ChP->IntMask, Mask);
3170 }
3171 }
3172
3173 /***************************************************************************
3174 Function: sDisInterrupts
3175 Purpose: Disable one or more interrupts for a channel
3176 Call: sDisInterrupts(ChP,Flags)
3177 CHANNEL_T *ChP; Ptr to channel structure
3178 Word_t Flags: Interrupt flags, can be any combination
3179 of the following flags:
3180 TXINT_EN: Interrupt on Tx FIFO empty
3181 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3182 sSetRxTrigger())
3183 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3184 MCINT_EN: Interrupt on modem input change
3185 CHANINT_EN: Disable channel interrupt signal to the
3186 AIOP's Interrupt Channel Register.
3187 Return: void
3188 Comments: If an interrupt flag is set in Flags, that interrupt will be
3189 disabled. If an interrupt flag is not set in Flags, that
3190 interrupt will not be changed. Interrupts can be enabled with
3191 function sEnInterrupts().
3192
3193 This function clears the appropriate bit for the channel in the AIOP's
3194 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3195 this channel's bit from being set in the AIOP's Interrupt Channel
3196 Register.
3197 */
3198 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3199 {
3200 Byte_t Mask; /* Interrupt Mask Register */
3201
3202 ChP->RxControl[2] &=
3203 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3204 out32(ChP->IndexAddr, ChP->RxControl);
3205 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3206 out32(ChP->IndexAddr, ChP->TxControl);
3207
3208 if (Flags & CHANINT_EN) {
3209 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3210 sOutB(ChP->IntMask, Mask);
3211 }
3212 }
3213
3214 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3215 {
3216 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3217 }
3218
3219 /*
3220 * Not an official SSCI function, but how to reset RocketModems.
3221 * ISA bus version
3222 */
3223 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3224 {
3225 ByteIO_t addr;
3226 Byte_t val;
3227
3228 addr = CtlP->AiopIO[0] + 0x400;
3229 val = sInB(CtlP->MReg3IO);
3230 /* if AIOP[1] is not enabled, enable it */
3231 if ((val & 2) == 0) {
3232 val = sInB(CtlP->MReg2IO);
3233 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3234 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3235 }
3236
3237 sEnAiop(CtlP, 1);
3238 if (!on)
3239 addr += 8;
3240 sOutB(addr + chan, 0); /* apply or remove reset */
3241 sDisAiop(CtlP, 1);
3242 }
3243
3244 /*
3245 * Not an official SSCI function, but how to reset RocketModems.
3246 * PCI bus version
3247 */
3248 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3249 {
3250 ByteIO_t addr;
3251
3252 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3253 if (!on)
3254 addr += 8;
3255 sOutB(addr + chan, 0); /* apply or remove reset */
3256 }
3257
3258 /* Resets the speaker controller on RocketModem II and III devices */
3259 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3260 {
3261 ByteIO_t addr;
3262
3263 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3264 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3265 addr = CtlP->AiopIO[0] + 0x4F;
3266 sOutB(addr, 0);
3267 }
3268
3269 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3270 if ((model == MODEL_UPCI_RM3_8PORT)
3271 || (model == MODEL_UPCI_RM3_4PORT)) {
3272 addr = CtlP->AiopIO[0] + 0x88;
3273 sOutB(addr, 0);
3274 }
3275 }
3276
3277 /* Returns the line number given the controller (board), aiop and channel number */
3278 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3279 {
3280 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3281 }
3282
3283 /*
3284 * Stores the line number associated with a given controller (board), aiop
3285 * and channel number.
3286 * Returns: The line number assigned
3287 */
3288 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3289 {
3290 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3291 return (nextLineNumber - 1);
3292 }
Linux kernel - Deliverables
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