2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
82 #include <linux/slab.h>
83 #include <linux/delay.h>
85 #include <linux/netdevice.h>
87 #include <linux/vmalloc.h>
88 #include <linux/init.h>
90 #include <linux/delay.h>
91 #include <linux/ioctl.h>
93 #include <asm/system.h>
97 #include <linux/bitops.h>
98 #include <asm/types.h>
99 #include <linux/termios.h>
100 #include <linux/workqueue.h>
101 #include <linux/hdlc.h>
102 #include <linux/dma-mapping.h>
104 #ifdef CONFIG_HDLC_MODULE
105 #define CONFIG_HDLC 1
108 #define GET_USER(error,value,addr) error = get_user(value,addr)
109 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
110 #define PUT_USER(error,value,addr) error = put_user(value,addr)
111 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
113 #include <asm/uaccess.h>
115 #include "linux/synclink.h"
117 #define RCLRVALUE 0xffff
119 static MGSL_PARAMS default_params
= {
120 MGSL_MODE_HDLC
, /* unsigned long mode */
121 0, /* unsigned char loopback; */
122 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
123 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
124 0, /* unsigned long clock_speed; */
125 0xff, /* unsigned char addr_filter; */
126 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
127 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
128 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
129 9600, /* unsigned long data_rate; */
130 8, /* unsigned char data_bits; */
131 1, /* unsigned char stop_bits; */
132 ASYNC_PARITY_NONE
/* unsigned char parity; */
135 #define SHARED_MEM_ADDRESS_SIZE 0x40000
136 #define BUFFERLISTSIZE (PAGE_SIZE)
137 #define DMABUFFERSIZE (PAGE_SIZE)
138 #define MAXRXFRAMES 7
140 typedef struct _DMABUFFERENTRY
142 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
143 volatile u16 count
; /* buffer size/data count */
144 volatile u16 status
; /* Control/status field */
145 volatile u16 rcc
; /* character count field */
146 u16 reserved
; /* padding required by 16C32 */
147 u32 link
; /* 32-bit flat link to next buffer entry */
148 char *virt_addr
; /* virtual address of data buffer */
149 u32 phys_entry
; /* physical address of this buffer entry */
151 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
153 /* The queue of BH actions to be performed */
156 #define BH_TRANSMIT 2
159 #define IO_PIN_SHUTDOWN_LIMIT 100
161 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
163 struct _input_signal_events
{
174 /* transmit holding buffer definitions*/
175 #define MAX_TX_HOLDING_BUFFERS 5
176 struct tx_holding_buffer
{
178 unsigned char * buffer
;
183 * Device instance data structure
189 int count
; /* count of opens */
192 unsigned short close_delay
;
193 unsigned short closing_wait
; /* time to wait before closing */
195 struct mgsl_icount icount
;
197 struct tty_struct
*tty
;
199 int x_char
; /* xon/xoff character */
200 int blocked_open
; /* # of blocked opens */
201 u16 read_status_mask
;
202 u16 ignore_status_mask
;
203 unsigned char *xmit_buf
;
208 wait_queue_head_t open_wait
;
209 wait_queue_head_t close_wait
;
211 wait_queue_head_t status_event_wait_q
;
212 wait_queue_head_t event_wait_q
;
213 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
214 struct mgsl_struct
*next_device
; /* device list link */
216 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
217 struct work_struct task
; /* task structure for scheduling bh */
219 u32 EventMask
; /* event trigger mask */
220 u32 RecordedEvents
; /* pending events */
222 u32 max_frame_size
; /* as set by device config */
226 int bh_running
; /* Protection from multiple */
230 int dcd_chkcount
; /* check counts to prevent */
231 int cts_chkcount
; /* too many IRQs if a signal */
232 int dsr_chkcount
; /* is floating */
235 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
236 u32 buffer_list_phys
;
237 dma_addr_t buffer_list_dma_addr
;
239 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
240 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
241 unsigned int current_rx_buffer
;
243 int num_tx_dma_buffers
; /* number of tx dma frames required */
244 int tx_dma_buffers_used
;
245 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
246 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
247 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
248 int current_tx_buffer
; /* next tx dma buffer to be loaded */
250 unsigned char *intermediate_rxbuffer
;
252 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
253 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
254 int put_tx_holding_index
; /* next tx holding buffer to store user request */
255 int tx_holding_count
; /* number of tx holding buffers waiting */
256 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
269 char device_name
[25]; /* device instance name */
271 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
272 unsigned char bus
; /* expansion bus number (zero based) */
273 unsigned char function
; /* PCI device number */
275 unsigned int io_base
; /* base I/O address of adapter */
276 unsigned int io_addr_size
; /* size of the I/O address range */
277 int io_addr_requested
; /* nonzero if I/O address requested */
279 unsigned int irq_level
; /* interrupt level */
280 unsigned long irq_flags
;
281 int irq_requested
; /* nonzero if IRQ requested */
283 unsigned int dma_level
; /* DMA channel */
284 int dma_requested
; /* nonzero if dma channel requested */
290 MGSL_PARAMS params
; /* communications parameters */
292 unsigned char serial_signals
; /* current serial signal states */
294 int irq_occurred
; /* for diagnostics use */
295 unsigned int init_error
; /* Initialization startup error (DIAGS) */
296 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
299 unsigned char* memory_base
; /* shared memory address (PCI only) */
300 u32 phys_memory_base
;
301 int shared_mem_requested
;
303 unsigned char* lcr_base
; /* local config registers (PCI only) */
306 int lcr_mem_requested
;
309 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
310 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
311 BOOLEAN drop_rts_on_tx_done
;
313 BOOLEAN loopmode_insert_requested
;
314 BOOLEAN loopmode_send_done_requested
;
316 struct _input_signal_events input_signal_events
;
318 /* generic HDLC device parts */
324 struct net_device
*netdev
;
328 #define MGSL_MAGIC 0x5401
331 * The size of the serial xmit buffer is 1 page, or 4096 bytes
333 #ifndef SERIAL_XMIT_SIZE
334 #define SERIAL_XMIT_SIZE 4096
338 * These macros define the offsets used in calculating the
339 * I/O address of the specified USC registers.
343 #define DCPIN 2 /* Bit 1 of I/O address */
344 #define SDPIN 4 /* Bit 2 of I/O address */
346 #define DCAR 0 /* DMA command/address register */
347 #define CCAR SDPIN /* channel command/address register */
348 #define DATAREG DCPIN + SDPIN /* serial data register */
353 * These macros define the register address (ordinal number)
354 * used for writing address/value pairs to the USC.
357 #define CMR 0x02 /* Channel mode Register */
358 #define CCSR 0x04 /* Channel Command/status Register */
359 #define CCR 0x06 /* Channel Control Register */
360 #define PSR 0x08 /* Port status Register */
361 #define PCR 0x0a /* Port Control Register */
362 #define TMDR 0x0c /* Test mode Data Register */
363 #define TMCR 0x0e /* Test mode Control Register */
364 #define CMCR 0x10 /* Clock mode Control Register */
365 #define HCR 0x12 /* Hardware Configuration Register */
366 #define IVR 0x14 /* Interrupt Vector Register */
367 #define IOCR 0x16 /* Input/Output Control Register */
368 #define ICR 0x18 /* Interrupt Control Register */
369 #define DCCR 0x1a /* Daisy Chain Control Register */
370 #define MISR 0x1c /* Misc Interrupt status Register */
371 #define SICR 0x1e /* status Interrupt Control Register */
372 #define RDR 0x20 /* Receive Data Register */
373 #define RMR 0x22 /* Receive mode Register */
374 #define RCSR 0x24 /* Receive Command/status Register */
375 #define RICR 0x26 /* Receive Interrupt Control Register */
376 #define RSR 0x28 /* Receive Sync Register */
377 #define RCLR 0x2a /* Receive count Limit Register */
378 #define RCCR 0x2c /* Receive Character count Register */
379 #define TC0R 0x2e /* Time Constant 0 Register */
380 #define TDR 0x30 /* Transmit Data Register */
381 #define TMR 0x32 /* Transmit mode Register */
382 #define TCSR 0x34 /* Transmit Command/status Register */
383 #define TICR 0x36 /* Transmit Interrupt Control Register */
384 #define TSR 0x38 /* Transmit Sync Register */
385 #define TCLR 0x3a /* Transmit count Limit Register */
386 #define TCCR 0x3c /* Transmit Character count Register */
387 #define TC1R 0x3e /* Time Constant 1 Register */
391 * MACRO DEFINITIONS FOR DMA REGISTERS
394 #define DCR 0x06 /* DMA Control Register (shared) */
395 #define DACR 0x08 /* DMA Array count Register (shared) */
396 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
397 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
398 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
399 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
400 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
402 #define TDMR 0x02 /* Transmit DMA mode Register */
403 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
404 #define TBCR 0x2a /* Transmit Byte count Register */
405 #define TARL 0x2c /* Transmit Address Register (low) */
406 #define TARU 0x2e /* Transmit Address Register (high) */
407 #define NTBCR 0x3a /* Next Transmit Byte count Register */
408 #define NTARL 0x3c /* Next Transmit Address Register (low) */
409 #define NTARU 0x3e /* Next Transmit Address Register (high) */
411 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
412 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
413 #define RBCR 0xaa /* Receive Byte count Register */
414 #define RARL 0xac /* Receive Address Register (low) */
415 #define RARU 0xae /* Receive Address Register (high) */
416 #define NRBCR 0xba /* Next Receive Byte count Register */
417 #define NRARL 0xbc /* Next Receive Address Register (low) */
418 #define NRARU 0xbe /* Next Receive Address Register (high) */
422 * MACRO DEFINITIONS FOR MODEM STATUS BITS
425 #define MODEMSTATUS_DTR 0x80
426 #define MODEMSTATUS_DSR 0x40
427 #define MODEMSTATUS_RTS 0x20
428 #define MODEMSTATUS_CTS 0x10
429 #define MODEMSTATUS_RI 0x04
430 #define MODEMSTATUS_DCD 0x01
434 * Channel Command/Address Register (CCAR) Command Codes
437 #define RTCmd_Null 0x0000
438 #define RTCmd_ResetHighestIus 0x1000
439 #define RTCmd_TriggerChannelLoadDma 0x2000
440 #define RTCmd_TriggerRxDma 0x2800
441 #define RTCmd_TriggerTxDma 0x3000
442 #define RTCmd_TriggerRxAndTxDma 0x3800
443 #define RTCmd_PurgeRxFifo 0x4800
444 #define RTCmd_PurgeTxFifo 0x5000
445 #define RTCmd_PurgeRxAndTxFifo 0x5800
446 #define RTCmd_LoadRcc 0x6800
447 #define RTCmd_LoadTcc 0x7000
448 #define RTCmd_LoadRccAndTcc 0x7800
449 #define RTCmd_LoadTC0 0x8800
450 #define RTCmd_LoadTC1 0x9000
451 #define RTCmd_LoadTC0AndTC1 0x9800
452 #define RTCmd_SerialDataLSBFirst 0xa000
453 #define RTCmd_SerialDataMSBFirst 0xa800
454 #define RTCmd_SelectBigEndian 0xb000
455 #define RTCmd_SelectLittleEndian 0xb800
459 * DMA Command/Address Register (DCAR) Command Codes
462 #define DmaCmd_Null 0x0000
463 #define DmaCmd_ResetTxChannel 0x1000
464 #define DmaCmd_ResetRxChannel 0x1200
465 #define DmaCmd_StartTxChannel 0x2000
466 #define DmaCmd_StartRxChannel 0x2200
467 #define DmaCmd_ContinueTxChannel 0x3000
468 #define DmaCmd_ContinueRxChannel 0x3200
469 #define DmaCmd_PauseTxChannel 0x4000
470 #define DmaCmd_PauseRxChannel 0x4200
471 #define DmaCmd_AbortTxChannel 0x5000
472 #define DmaCmd_AbortRxChannel 0x5200
473 #define DmaCmd_InitTxChannel 0x7000
474 #define DmaCmd_InitRxChannel 0x7200
475 #define DmaCmd_ResetHighestDmaIus 0x8000
476 #define DmaCmd_ResetAllChannels 0x9000
477 #define DmaCmd_StartAllChannels 0xa000
478 #define DmaCmd_ContinueAllChannels 0xb000
479 #define DmaCmd_PauseAllChannels 0xc000
480 #define DmaCmd_AbortAllChannels 0xd000
481 #define DmaCmd_InitAllChannels 0xf000
483 #define TCmd_Null 0x0000
484 #define TCmd_ClearTxCRC 0x2000
485 #define TCmd_SelectTicrTtsaData 0x4000
486 #define TCmd_SelectTicrTxFifostatus 0x5000
487 #define TCmd_SelectTicrIntLevel 0x6000
488 #define TCmd_SelectTicrdma_level 0x7000
489 #define TCmd_SendFrame 0x8000
490 #define TCmd_SendAbort 0x9000
491 #define TCmd_EnableDleInsertion 0xc000
492 #define TCmd_DisableDleInsertion 0xd000
493 #define TCmd_ClearEofEom 0xe000
494 #define TCmd_SetEofEom 0xf000
496 #define RCmd_Null 0x0000
497 #define RCmd_ClearRxCRC 0x2000
498 #define RCmd_EnterHuntmode 0x3000
499 #define RCmd_SelectRicrRtsaData 0x4000
500 #define RCmd_SelectRicrRxFifostatus 0x5000
501 #define RCmd_SelectRicrIntLevel 0x6000
502 #define RCmd_SelectRicrdma_level 0x7000
505 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
508 #define RECEIVE_STATUS BIT5
509 #define RECEIVE_DATA BIT4
510 #define TRANSMIT_STATUS BIT3
511 #define TRANSMIT_DATA BIT2
517 * Receive status Bits in Receive Command/status Register RCSR
520 #define RXSTATUS_SHORT_FRAME BIT8
521 #define RXSTATUS_CODE_VIOLATION BIT8
522 #define RXSTATUS_EXITED_HUNT BIT7
523 #define RXSTATUS_IDLE_RECEIVED BIT6
524 #define RXSTATUS_BREAK_RECEIVED BIT5
525 #define RXSTATUS_ABORT_RECEIVED BIT5
526 #define RXSTATUS_RXBOUND BIT4
527 #define RXSTATUS_CRC_ERROR BIT3
528 #define RXSTATUS_FRAMING_ERROR BIT3
529 #define RXSTATUS_ABORT BIT2
530 #define RXSTATUS_PARITY_ERROR BIT2
531 #define RXSTATUS_OVERRUN BIT1
532 #define RXSTATUS_DATA_AVAILABLE BIT0
533 #define RXSTATUS_ALL 0x01f6
534 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
537 * Values for setting transmit idle mode in
538 * Transmit Control/status Register (TCSR)
540 #define IDLEMODE_FLAGS 0x0000
541 #define IDLEMODE_ALT_ONE_ZERO 0x0100
542 #define IDLEMODE_ZERO 0x0200
543 #define IDLEMODE_ONE 0x0300
544 #define IDLEMODE_ALT_MARK_SPACE 0x0500
545 #define IDLEMODE_SPACE 0x0600
546 #define IDLEMODE_MARK 0x0700
547 #define IDLEMODE_MASK 0x0700
550 * IUSC revision identifiers
552 #define IUSC_SL1660 0x4d44
553 #define IUSC_PRE_SL1660 0x4553
556 * Transmit status Bits in Transmit Command/status Register (TCSR)
559 #define TCSR_PRESERVE 0x0F00
561 #define TCSR_UNDERWAIT BIT11
562 #define TXSTATUS_PREAMBLE_SENT BIT7
563 #define TXSTATUS_IDLE_SENT BIT6
564 #define TXSTATUS_ABORT_SENT BIT5
565 #define TXSTATUS_EOF_SENT BIT4
566 #define TXSTATUS_EOM_SENT BIT4
567 #define TXSTATUS_CRC_SENT BIT3
568 #define TXSTATUS_ALL_SENT BIT2
569 #define TXSTATUS_UNDERRUN BIT1
570 #define TXSTATUS_FIFO_EMPTY BIT0
571 #define TXSTATUS_ALL 0x00fa
572 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
575 #define MISCSTATUS_RXC_LATCHED BIT15
576 #define MISCSTATUS_RXC BIT14
577 #define MISCSTATUS_TXC_LATCHED BIT13
578 #define MISCSTATUS_TXC BIT12
579 #define MISCSTATUS_RI_LATCHED BIT11
580 #define MISCSTATUS_RI BIT10
581 #define MISCSTATUS_DSR_LATCHED BIT9
582 #define MISCSTATUS_DSR BIT8
583 #define MISCSTATUS_DCD_LATCHED BIT7
584 #define MISCSTATUS_DCD BIT6
585 #define MISCSTATUS_CTS_LATCHED BIT5
586 #define MISCSTATUS_CTS BIT4
587 #define MISCSTATUS_RCC_UNDERRUN BIT3
588 #define MISCSTATUS_DPLL_NO_SYNC BIT2
589 #define MISCSTATUS_BRG1_ZERO BIT1
590 #define MISCSTATUS_BRG0_ZERO BIT0
592 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
593 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
595 #define SICR_RXC_ACTIVE BIT15
596 #define SICR_RXC_INACTIVE BIT14
597 #define SICR_RXC (BIT15+BIT14)
598 #define SICR_TXC_ACTIVE BIT13
599 #define SICR_TXC_INACTIVE BIT12
600 #define SICR_TXC (BIT13+BIT12)
601 #define SICR_RI_ACTIVE BIT11
602 #define SICR_RI_INACTIVE BIT10
603 #define SICR_RI (BIT11+BIT10)
604 #define SICR_DSR_ACTIVE BIT9
605 #define SICR_DSR_INACTIVE BIT8
606 #define SICR_DSR (BIT9+BIT8)
607 #define SICR_DCD_ACTIVE BIT7
608 #define SICR_DCD_INACTIVE BIT6
609 #define SICR_DCD (BIT7+BIT6)
610 #define SICR_CTS_ACTIVE BIT5
611 #define SICR_CTS_INACTIVE BIT4
612 #define SICR_CTS (BIT5+BIT4)
613 #define SICR_RCC_UNDERFLOW BIT3
614 #define SICR_DPLL_NO_SYNC BIT2
615 #define SICR_BRG1_ZERO BIT1
616 #define SICR_BRG0_ZERO BIT0
618 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
619 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
620 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
621 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
622 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
624 #define usc_EnableInterrupts( a, b ) \
625 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
627 #define usc_DisableInterrupts( a, b ) \
628 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
630 #define usc_EnableMasterIrqBit(a) \
631 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
633 #define usc_DisableMasterIrqBit(a) \
634 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
636 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
639 * Transmit status Bits in Transmit Control status Register (TCSR)
640 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
643 #define TXSTATUS_PREAMBLE_SENT BIT7
644 #define TXSTATUS_IDLE_SENT BIT6
645 #define TXSTATUS_ABORT_SENT BIT5
646 #define TXSTATUS_EOF BIT4
647 #define TXSTATUS_CRC_SENT BIT3
648 #define TXSTATUS_ALL_SENT BIT2
649 #define TXSTATUS_UNDERRUN BIT1
650 #define TXSTATUS_FIFO_EMPTY BIT0
652 #define DICR_MASTER BIT15
653 #define DICR_TRANSMIT BIT0
654 #define DICR_RECEIVE BIT1
656 #define usc_EnableDmaInterrupts(a,b) \
657 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
659 #define usc_DisableDmaInterrupts(a,b) \
660 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
662 #define usc_EnableStatusIrqs(a,b) \
663 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
665 #define usc_DisablestatusIrqs(a,b) \
666 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
668 /* Transmit status Bits in Transmit Control status Register (TCSR) */
669 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
672 #define DISABLE_UNCONDITIONAL 0
673 #define DISABLE_END_OF_FRAME 1
674 #define ENABLE_UNCONDITIONAL 2
675 #define ENABLE_AUTO_CTS 3
676 #define ENABLE_AUTO_DCD 3
677 #define usc_EnableTransmitter(a,b) \
678 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
679 #define usc_EnableReceiver(a,b) \
680 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
682 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
683 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
684 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
686 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
687 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
688 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
689 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
690 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
692 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
693 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
695 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
697 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
698 static void usc_start_receiver( struct mgsl_struct
*info
);
699 static void usc_stop_receiver( struct mgsl_struct
*info
);
701 static void usc_start_transmitter( struct mgsl_struct
*info
);
702 static void usc_stop_transmitter( struct mgsl_struct
*info
);
703 static void usc_set_txidle( struct mgsl_struct
*info
);
704 static void usc_load_txfifo( struct mgsl_struct
*info
);
706 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
707 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
709 static void usc_get_serial_signals( struct mgsl_struct
*info
);
710 static void usc_set_serial_signals( struct mgsl_struct
*info
);
712 static void usc_reset( struct mgsl_struct
*info
);
714 static void usc_set_sync_mode( struct mgsl_struct
*info
);
715 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
716 static void usc_set_async_mode( struct mgsl_struct
*info
);
717 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
719 static void usc_loopback_frame( struct mgsl_struct
*info
);
721 static void mgsl_tx_timeout(unsigned long context
);
724 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
725 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
726 static int usc_loopmode_active( struct mgsl_struct
* info
);
727 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
729 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
732 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
733 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
734 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
735 static int hdlcdev_init(struct mgsl_struct
*info
);
736 static void hdlcdev_exit(struct mgsl_struct
*info
);
740 * Defines a BUS descriptor value for the PCI adapter
741 * local bus address ranges.
744 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
755 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
758 * Adapter diagnostic routines
760 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
);
761 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
);
762 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
);
763 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
);
764 static int mgsl_adapter_test( struct mgsl_struct
*info
);
767 * device and resource management routines
769 static int mgsl_claim_resources(struct mgsl_struct
*info
);
770 static void mgsl_release_resources(struct mgsl_struct
*info
);
771 static void mgsl_add_device(struct mgsl_struct
*info
);
772 static struct mgsl_struct
* mgsl_allocate_device(void);
775 * DMA buffer manupulation functions.
777 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
778 static int mgsl_get_rx_frame( struct mgsl_struct
*info
);
779 static int mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
780 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
781 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
782 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
783 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
784 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
787 * DMA and Shared Memory buffer allocation and formatting
789 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
790 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
791 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
792 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
793 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
794 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
795 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
796 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
797 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
798 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
799 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
);
800 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
803 * Bottom half interrupt handlers
805 static void mgsl_bh_handler(void* Context
);
806 static void mgsl_bh_receive(struct mgsl_struct
*info
);
807 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
808 static void mgsl_bh_status(struct mgsl_struct
*info
);
811 * Interrupt handler routines and dispatch table.
813 static void mgsl_isr_null( struct mgsl_struct
*info
);
814 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
815 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
816 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
817 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
818 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
819 static void mgsl_isr_misc( struct mgsl_struct
*info
);
820 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
821 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
823 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
825 static isr_dispatch_func UscIsrTable
[7] =
830 mgsl_isr_transmit_data
,
831 mgsl_isr_transmit_status
,
832 mgsl_isr_receive_data
,
833 mgsl_isr_receive_status
837 * ioctl call handlers
839 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
840 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
841 unsigned int set
, unsigned int clear
);
842 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
843 __user
*user_icount
);
844 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
845 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
846 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
847 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
848 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
849 static int mgsl_txabort(struct mgsl_struct
* info
);
850 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
851 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
852 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
854 /* set non-zero on successful registration with PCI subsystem */
855 static int pci_registered
;
858 * Global linked list of SyncLink devices
860 static struct mgsl_struct
*mgsl_device_list
;
861 static int mgsl_device_count
;
864 * Set this param to non-zero to load eax with the
865 * .text section address and breakpoint on module load.
866 * This is useful for use with gdb and add-symbol-file command.
868 static int break_on_load
;
871 * Driver major number, defaults to zero to get auto
872 * assigned major number. May be forced as module parameter.
877 * Array of user specified options for ISA adapters.
879 static int io
[MAX_ISA_DEVICES
];
880 static int irq
[MAX_ISA_DEVICES
];
881 static int dma
[MAX_ISA_DEVICES
];
882 static int debug_level
;
883 static int maxframe
[MAX_TOTAL_DEVICES
];
884 static int dosyncppp
[MAX_TOTAL_DEVICES
];
885 static int txdmabufs
[MAX_TOTAL_DEVICES
];
886 static int txholdbufs
[MAX_TOTAL_DEVICES
];
888 module_param(break_on_load
, bool, 0);
889 module_param(ttymajor
, int, 0);
890 module_param_array(io
, int, NULL
, 0);
891 module_param_array(irq
, int, NULL
, 0);
892 module_param_array(dma
, int, NULL
, 0);
893 module_param(debug_level
, int, 0);
894 module_param_array(maxframe
, int, NULL
, 0);
895 module_param_array(dosyncppp
, int, NULL
, 0);
896 module_param_array(txdmabufs
, int, NULL
, 0);
897 module_param_array(txholdbufs
, int, NULL
, 0);
899 static char *driver_name
= "SyncLink serial driver";
900 static char *driver_version
= "$Revision: 4.38 $";
902 static int synclink_init_one (struct pci_dev
*dev
,
903 const struct pci_device_id
*ent
);
904 static void synclink_remove_one (struct pci_dev
*dev
);
906 static struct pci_device_id synclink_pci_tbl
[] = {
907 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
908 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
909 { 0, }, /* terminate list */
911 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
913 MODULE_LICENSE("GPL");
915 static struct pci_driver synclink_pci_driver
= {
917 .id_table
= synclink_pci_tbl
,
918 .probe
= synclink_init_one
,
919 .remove
= __devexit_p(synclink_remove_one
),
922 static struct tty_driver
*serial_driver
;
924 /* number of characters left in xmit buffer before we ask for more */
925 #define WAKEUP_CHARS 256
928 static void mgsl_change_params(struct mgsl_struct
*info
);
929 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
932 * 1st function defined in .text section. Calling this function in
933 * init_module() followed by a breakpoint allows a remote debugger
934 * (gdb) to get the .text address for the add-symbol-file command.
935 * This allows remote debugging of dynamically loadable modules.
937 static void* mgsl_get_text_ptr(void)
939 return mgsl_get_text_ptr
;
942 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
943 char *name
, const char *routine
)
945 #ifdef MGSL_PARANOIA_CHECK
946 static const char *badmagic
=
947 "Warning: bad magic number for mgsl struct (%s) in %s\n";
948 static const char *badinfo
=
949 "Warning: null mgsl_struct for (%s) in %s\n";
952 printk(badinfo
, name
, routine
);
955 if (info
->magic
!= MGSL_MAGIC
) {
956 printk(badmagic
, name
, routine
);
967 * line discipline callback wrappers
969 * The wrappers maintain line discipline references
970 * while calling into the line discipline.
972 * ldisc_receive_buf - pass receive data to line discipline
975 static void ldisc_receive_buf(struct tty_struct
*tty
,
976 const __u8
*data
, char *flags
, int count
)
978 struct tty_ldisc
*ld
;
981 ld
= tty_ldisc_ref(tty
);
984 ld
->receive_buf(tty
, data
, flags
, count
);
989 /* mgsl_stop() throttle (stop) transmitter
991 * Arguments: tty pointer to tty info structure
994 static void mgsl_stop(struct tty_struct
*tty
)
996 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
999 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
1002 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1003 printk("mgsl_stop(%s)\n",info
->device_name
);
1005 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1006 if (info
->tx_enabled
)
1007 usc_stop_transmitter(info
);
1008 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1010 } /* end of mgsl_stop() */
1012 /* mgsl_start() release (start) transmitter
1014 * Arguments: tty pointer to tty info structure
1015 * Return Value: None
1017 static void mgsl_start(struct tty_struct
*tty
)
1019 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1020 unsigned long flags
;
1022 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1025 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1026 printk("mgsl_start(%s)\n",info
->device_name
);
1028 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1029 if (!info
->tx_enabled
)
1030 usc_start_transmitter(info
);
1031 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1033 } /* end of mgsl_start() */
1036 * Bottom half work queue access functions
1039 /* mgsl_bh_action() Return next bottom half action to perform.
1040 * Return Value: BH action code or 0 if nothing to do.
1042 static int mgsl_bh_action(struct mgsl_struct
*info
)
1044 unsigned long flags
;
1047 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1049 if (info
->pending_bh
& BH_RECEIVE
) {
1050 info
->pending_bh
&= ~BH_RECEIVE
;
1052 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1053 info
->pending_bh
&= ~BH_TRANSMIT
;
1055 } else if (info
->pending_bh
& BH_STATUS
) {
1056 info
->pending_bh
&= ~BH_STATUS
;
1061 /* Mark BH routine as complete */
1062 info
->bh_running
= 0;
1063 info
->bh_requested
= 0;
1066 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1072 * Perform bottom half processing of work items queued by ISR.
1074 static void mgsl_bh_handler(void* Context
)
1076 struct mgsl_struct
*info
= (struct mgsl_struct
*)Context
;
1082 if ( debug_level
>= DEBUG_LEVEL_BH
)
1083 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1084 __FILE__
,__LINE__
,info
->device_name
);
1086 info
->bh_running
= 1;
1088 while((action
= mgsl_bh_action(info
)) != 0) {
1090 /* Process work item */
1091 if ( debug_level
>= DEBUG_LEVEL_BH
)
1092 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1093 __FILE__
,__LINE__
,action
);
1098 mgsl_bh_receive(info
);
1101 mgsl_bh_transmit(info
);
1104 mgsl_bh_status(info
);
1107 /* unknown work item ID */
1108 printk("Unknown work item ID=%08X!\n", action
);
1113 if ( debug_level
>= DEBUG_LEVEL_BH
)
1114 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1115 __FILE__
,__LINE__
,info
->device_name
);
1118 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1120 int (*get_rx_frame
)(struct mgsl_struct
*info
) =
1121 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1123 if ( debug_level
>= DEBUG_LEVEL_BH
)
1124 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1125 __FILE__
,__LINE__
,info
->device_name
);
1129 if (info
->rx_rcc_underrun
) {
1130 unsigned long flags
;
1131 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1132 usc_start_receiver(info
);
1133 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1136 } while(get_rx_frame(info
));
1139 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1141 struct tty_struct
*tty
= info
->tty
;
1142 unsigned long flags
;
1144 if ( debug_level
>= DEBUG_LEVEL_BH
)
1145 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1146 __FILE__
,__LINE__
,info
->device_name
);
1150 wake_up_interruptible(&tty
->write_wait
);
1153 /* if transmitter idle and loopmode_send_done_requested
1154 * then start echoing RxD to TxD
1156 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1157 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1158 usc_loopmode_send_done( info
);
1159 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1162 static void mgsl_bh_status(struct mgsl_struct
*info
)
1164 if ( debug_level
>= DEBUG_LEVEL_BH
)
1165 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1166 __FILE__
,__LINE__
,info
->device_name
);
1168 info
->ri_chkcount
= 0;
1169 info
->dsr_chkcount
= 0;
1170 info
->dcd_chkcount
= 0;
1171 info
->cts_chkcount
= 0;
1174 /* mgsl_isr_receive_status()
1176 * Service a receive status interrupt. The type of status
1177 * interrupt is indicated by the state of the RCSR.
1178 * This is only used for HDLC mode.
1180 * Arguments: info pointer to device instance data
1181 * Return Value: None
1183 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1185 u16 status
= usc_InReg( info
, RCSR
);
1187 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1188 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1189 __FILE__
,__LINE__
,status
);
1191 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1192 info
->loopmode_insert_requested
&&
1193 usc_loopmode_active(info
) )
1195 ++info
->icount
.rxabort
;
1196 info
->loopmode_insert_requested
= FALSE
;
1198 /* clear CMR:13 to start echoing RxD to TxD */
1199 info
->cmr_value
&= ~BIT13
;
1200 usc_OutReg(info
, CMR
, info
->cmr_value
);
1202 /* disable received abort irq (no longer required) */
1203 usc_OutReg(info
, RICR
,
1204 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1207 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1208 if (status
& RXSTATUS_EXITED_HUNT
)
1209 info
->icount
.exithunt
++;
1210 if (status
& RXSTATUS_IDLE_RECEIVED
)
1211 info
->icount
.rxidle
++;
1212 wake_up_interruptible(&info
->event_wait_q
);
1215 if (status
& RXSTATUS_OVERRUN
){
1216 info
->icount
.rxover
++;
1217 usc_process_rxoverrun_sync( info
);
1220 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1221 usc_UnlatchRxstatusBits( info
, status
);
1223 } /* end of mgsl_isr_receive_status() */
1225 /* mgsl_isr_transmit_status()
1227 * Service a transmit status interrupt
1228 * HDLC mode :end of transmit frame
1229 * Async mode:all data is sent
1230 * transmit status is indicated by bits in the TCSR.
1232 * Arguments: info pointer to device instance data
1233 * Return Value: None
1235 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1237 u16 status
= usc_InReg( info
, TCSR
);
1239 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1240 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1241 __FILE__
,__LINE__
,status
);
1243 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1244 usc_UnlatchTxstatusBits( info
, status
);
1246 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1248 /* finished sending HDLC abort. This may leave */
1249 /* the TxFifo with data from the aborted frame */
1250 /* so purge the TxFifo. Also shutdown the DMA */
1251 /* channel in case there is data remaining in */
1252 /* the DMA buffer */
1253 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1254 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1257 if ( status
& TXSTATUS_EOF_SENT
)
1258 info
->icount
.txok
++;
1259 else if ( status
& TXSTATUS_UNDERRUN
)
1260 info
->icount
.txunder
++;
1261 else if ( status
& TXSTATUS_ABORT_SENT
)
1262 info
->icount
.txabort
++;
1264 info
->icount
.txunder
++;
1266 info
->tx_active
= 0;
1267 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1268 del_timer(&info
->tx_timer
);
1270 if ( info
->drop_rts_on_tx_done
) {
1271 usc_get_serial_signals( info
);
1272 if ( info
->serial_signals
& SerialSignal_RTS
) {
1273 info
->serial_signals
&= ~SerialSignal_RTS
;
1274 usc_set_serial_signals( info
);
1276 info
->drop_rts_on_tx_done
= 0;
1281 hdlcdev_tx_done(info
);
1285 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1286 usc_stop_transmitter(info
);
1289 info
->pending_bh
|= BH_TRANSMIT
;
1292 } /* end of mgsl_isr_transmit_status() */
1294 /* mgsl_isr_io_pin()
1296 * Service an Input/Output pin interrupt. The type of
1297 * interrupt is indicated by bits in the MISR
1299 * Arguments: info pointer to device instance data
1300 * Return Value: None
1302 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1304 struct mgsl_icount
*icount
;
1305 u16 status
= usc_InReg( info
, MISR
);
1307 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1308 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1309 __FILE__
,__LINE__
,status
);
1311 usc_ClearIrqPendingBits( info
, IO_PIN
);
1312 usc_UnlatchIostatusBits( info
, status
);
1314 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1315 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1316 icount
= &info
->icount
;
1317 /* update input line counters */
1318 if (status
& MISCSTATUS_RI_LATCHED
) {
1319 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1320 usc_DisablestatusIrqs(info
,SICR_RI
);
1322 if ( status
& MISCSTATUS_RI
)
1323 info
->input_signal_events
.ri_up
++;
1325 info
->input_signal_events
.ri_down
++;
1327 if (status
& MISCSTATUS_DSR_LATCHED
) {
1328 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1329 usc_DisablestatusIrqs(info
,SICR_DSR
);
1331 if ( status
& MISCSTATUS_DSR
)
1332 info
->input_signal_events
.dsr_up
++;
1334 info
->input_signal_events
.dsr_down
++;
1336 if (status
& MISCSTATUS_DCD_LATCHED
) {
1337 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1338 usc_DisablestatusIrqs(info
,SICR_DCD
);
1340 if (status
& MISCSTATUS_DCD
) {
1341 info
->input_signal_events
.dcd_up
++;
1343 info
->input_signal_events
.dcd_down
++;
1345 if (info
->netcount
) {
1346 if (status
& MISCSTATUS_DCD
)
1347 netif_carrier_on(info
->netdev
);
1349 netif_carrier_off(info
->netdev
);
1353 if (status
& MISCSTATUS_CTS_LATCHED
)
1355 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1356 usc_DisablestatusIrqs(info
,SICR_CTS
);
1358 if ( status
& MISCSTATUS_CTS
)
1359 info
->input_signal_events
.cts_up
++;
1361 info
->input_signal_events
.cts_down
++;
1363 wake_up_interruptible(&info
->status_event_wait_q
);
1364 wake_up_interruptible(&info
->event_wait_q
);
1366 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
1367 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1368 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1369 printk("%s CD now %s...", info
->device_name
,
1370 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1371 if (status
& MISCSTATUS_DCD
)
1372 wake_up_interruptible(&info
->open_wait
);
1374 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1375 printk("doing serial hangup...");
1377 tty_hangup(info
->tty
);
1381 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
1382 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1383 if (info
->tty
->hw_stopped
) {
1384 if (status
& MISCSTATUS_CTS
) {
1385 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1386 printk("CTS tx start...");
1388 info
->tty
->hw_stopped
= 0;
1389 usc_start_transmitter(info
);
1390 info
->pending_bh
|= BH_TRANSMIT
;
1394 if (!(status
& MISCSTATUS_CTS
)) {
1395 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1396 printk("CTS tx stop...");
1398 info
->tty
->hw_stopped
= 1;
1399 usc_stop_transmitter(info
);
1405 info
->pending_bh
|= BH_STATUS
;
1407 /* for diagnostics set IRQ flag */
1408 if ( status
& MISCSTATUS_TXC_LATCHED
){
1409 usc_OutReg( info
, SICR
,
1410 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1411 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1412 info
->irq_occurred
= 1;
1415 } /* end of mgsl_isr_io_pin() */
1417 /* mgsl_isr_transmit_data()
1419 * Service a transmit data interrupt (async mode only).
1421 * Arguments: info pointer to device instance data
1422 * Return Value: None
1424 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1426 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1427 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1428 __FILE__
,__LINE__
,info
->xmit_cnt
);
1430 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1432 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1433 usc_stop_transmitter(info
);
1437 if ( info
->xmit_cnt
)
1438 usc_load_txfifo( info
);
1440 info
->tx_active
= 0;
1442 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1443 info
->pending_bh
|= BH_TRANSMIT
;
1445 } /* end of mgsl_isr_transmit_data() */
1447 /* mgsl_isr_receive_data()
1449 * Service a receive data interrupt. This occurs
1450 * when operating in asynchronous interrupt transfer mode.
1451 * The receive data FIFO is flushed to the receive data buffers.
1453 * Arguments: info pointer to device instance data
1454 * Return Value: None
1456 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1461 unsigned char DataByte
;
1462 struct tty_struct
*tty
= info
->tty
;
1463 struct mgsl_icount
*icount
= &info
->icount
;
1465 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1466 printk("%s(%d):mgsl_isr_receive_data\n",
1469 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1471 /* select FIFO status for RICR readback */
1472 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1474 /* clear the Wordstatus bit so that status readback */
1475 /* only reflects the status of this byte */
1476 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1478 /* flush the receive FIFO */
1480 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1483 /* read one byte from RxFIFO */
1484 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1485 info
->io_base
+ CCAR
);
1486 DataByte
= inb( info
->io_base
+ CCAR
);
1488 /* get the status of the received byte */
1489 status
= usc_InReg(info
, RCSR
);
1490 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1491 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1492 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1497 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1498 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1499 printk("rxerr=%04X\n",status
);
1500 /* update error statistics */
1501 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1502 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1504 } else if (status
& RXSTATUS_PARITY_ERROR
)
1506 else if (status
& RXSTATUS_FRAMING_ERROR
)
1508 else if (status
& RXSTATUS_OVERRUN
) {
1509 /* must issue purge fifo cmd before */
1510 /* 16C32 accepts more receive chars */
1511 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1515 /* discard char if tty control flags say so */
1516 if (status
& info
->ignore_status_mask
)
1519 status
&= info
->read_status_mask
;
1521 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1523 if (info
->flags
& ASYNC_SAK
)
1525 } else if (status
& RXSTATUS_PARITY_ERROR
)
1527 else if (status
& RXSTATUS_FRAMING_ERROR
)
1529 } /* end of if (error) */
1530 tty_insert_flip_char(tty
, DataByte
, flag
);
1531 if (status
& RXSTATUS_OVERRUN
) {
1532 /* Overrun is special, since it's
1533 * reported immediately, and doesn't
1534 * affect the current character
1536 work
+= tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
1540 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1541 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1542 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1543 icount
->parity
,icount
->frame
,icount
->overrun
);
1547 tty_flip_buffer_push(tty
);
1552 * Service a miscellaneos interrupt source.
1554 * Arguments: info pointer to device extension (instance data)
1555 * Return Value: None
1557 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1559 u16 status
= usc_InReg( info
, MISR
);
1561 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1562 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1563 __FILE__
,__LINE__
,status
);
1565 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1566 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1568 /* turn off receiver and rx DMA */
1569 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1570 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1571 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1572 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1573 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1575 /* schedule BH handler to restart receiver */
1576 info
->pending_bh
|= BH_RECEIVE
;
1577 info
->rx_rcc_underrun
= 1;
1580 usc_ClearIrqPendingBits( info
, MISC
);
1581 usc_UnlatchMiscstatusBits( info
, status
);
1583 } /* end of mgsl_isr_misc() */
1587 * Services undefined interrupt vectors from the
1588 * USC. (hence this function SHOULD never be called)
1590 * Arguments: info pointer to device extension (instance data)
1591 * Return Value: None
1593 static void mgsl_isr_null( struct mgsl_struct
*info
)
1596 } /* end of mgsl_isr_null() */
1598 /* mgsl_isr_receive_dma()
1600 * Service a receive DMA channel interrupt.
1601 * For this driver there are two sources of receive DMA interrupts
1602 * as identified in the Receive DMA mode Register (RDMR):
1604 * BIT3 EOA/EOL End of List, all receive buffers in receive
1605 * buffer list have been filled (no more free buffers
1606 * available). The DMA controller has shut down.
1608 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1609 * DMA buffer is terminated in response to completion
1610 * of a good frame or a frame with errors. The status
1611 * of the frame is stored in the buffer entry in the
1612 * list of receive buffer entries.
1614 * Arguments: info pointer to device instance data
1615 * Return Value: None
1617 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1621 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1622 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1624 /* Read the receive DMA status to identify interrupt type. */
1625 /* This also clears the status bits. */
1626 status
= usc_InDmaReg( info
, RDMR
);
1628 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1629 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1630 __FILE__
,__LINE__
,info
->device_name
,status
);
1632 info
->pending_bh
|= BH_RECEIVE
;
1634 if ( status
& BIT3
) {
1635 info
->rx_overflow
= 1;
1636 info
->icount
.buf_overrun
++;
1639 } /* end of mgsl_isr_receive_dma() */
1641 /* mgsl_isr_transmit_dma()
1643 * This function services a transmit DMA channel interrupt.
1645 * For this driver there is one source of transmit DMA interrupts
1646 * as identified in the Transmit DMA Mode Register (TDMR):
1648 * BIT2 EOB End of Buffer. This interrupt occurs when a
1649 * transmit DMA buffer has been emptied.
1651 * The driver maintains enough transmit DMA buffers to hold at least
1652 * one max frame size transmit frame. When operating in a buffered
1653 * transmit mode, there may be enough transmit DMA buffers to hold at
1654 * least two or more max frame size frames. On an EOB condition,
1655 * determine if there are any queued transmit buffers and copy into
1656 * transmit DMA buffers if we have room.
1658 * Arguments: info pointer to device instance data
1659 * Return Value: None
1661 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1665 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1666 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1668 /* Read the transmit DMA status to identify interrupt type. */
1669 /* This also clears the status bits. */
1671 status
= usc_InDmaReg( info
, TDMR
);
1673 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1674 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1675 __FILE__
,__LINE__
,info
->device_name
,status
);
1677 if ( status
& BIT2
) {
1678 --info
->tx_dma_buffers_used
;
1680 /* if there are transmit frames queued,
1681 * try to load the next one
1683 if ( load_next_tx_holding_buffer(info
) ) {
1684 /* if call returns non-zero value, we have
1685 * at least one free tx holding buffer
1687 info
->pending_bh
|= BH_TRANSMIT
;
1691 } /* end of mgsl_isr_transmit_dma() */
1695 * Interrupt service routine entry point.
1699 * irq interrupt number that caused interrupt
1700 * dev_id device ID supplied during interrupt registration
1701 * regs interrupted processor context
1703 * Return Value: None
1705 static irqreturn_t
mgsl_interrupt(int irq
, void *dev_id
, struct pt_regs
* regs
)
1707 struct mgsl_struct
* info
;
1711 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1712 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1713 __FILE__
,__LINE__
,irq
);
1715 info
= (struct mgsl_struct
*)dev_id
;
1719 spin_lock(&info
->irq_spinlock
);
1722 /* Read the interrupt vectors from hardware. */
1723 UscVector
= usc_InReg(info
, IVR
) >> 9;
1724 DmaVector
= usc_InDmaReg(info
, DIVR
);
1726 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1727 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1728 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1730 if ( !UscVector
&& !DmaVector
)
1733 /* Dispatch interrupt vector */
1735 (*UscIsrTable
[UscVector
])(info
);
1736 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1737 mgsl_isr_transmit_dma(info
);
1739 mgsl_isr_receive_dma(info
);
1741 if ( info
->isr_overflow
) {
1742 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1743 __FILE__
,__LINE__
,info
->device_name
, irq
);
1744 usc_DisableMasterIrqBit(info
);
1745 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1750 /* Request bottom half processing if there's something
1751 * for it to do and the bh is not already running
1754 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1755 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1756 printk("%s(%d):%s queueing bh task.\n",
1757 __FILE__
,__LINE__
,info
->device_name
);
1758 schedule_work(&info
->task
);
1759 info
->bh_requested
= 1;
1762 spin_unlock(&info
->irq_spinlock
);
1764 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1765 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1766 __FILE__
,__LINE__
,irq
);
1768 } /* end of mgsl_interrupt() */
1772 * Initialize and start device.
1774 * Arguments: info pointer to device instance data
1775 * Return Value: 0 if success, otherwise error code
1777 static int startup(struct mgsl_struct
* info
)
1781 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1782 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1784 if (info
->flags
& ASYNC_INITIALIZED
)
1787 if (!info
->xmit_buf
) {
1788 /* allocate a page of memory for a transmit buffer */
1789 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1790 if (!info
->xmit_buf
) {
1791 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1792 __FILE__
,__LINE__
,info
->device_name
);
1797 info
->pending_bh
= 0;
1799 memset(&info
->icount
, 0, sizeof(info
->icount
));
1801 init_timer(&info
->tx_timer
);
1802 info
->tx_timer
.data
= (unsigned long)info
;
1803 info
->tx_timer
.function
= mgsl_tx_timeout
;
1805 /* Allocate and claim adapter resources */
1806 retval
= mgsl_claim_resources(info
);
1808 /* perform existence check and diagnostics */
1810 retval
= mgsl_adapter_test(info
);
1813 if (capable(CAP_SYS_ADMIN
) && info
->tty
)
1814 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1815 mgsl_release_resources(info
);
1819 /* program hardware for current parameters */
1820 mgsl_change_params(info
);
1823 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1825 info
->flags
|= ASYNC_INITIALIZED
;
1829 } /* end of startup() */
1833 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1835 * Arguments: info pointer to device instance data
1836 * Return Value: None
1838 static void shutdown(struct mgsl_struct
* info
)
1840 unsigned long flags
;
1842 if (!(info
->flags
& ASYNC_INITIALIZED
))
1845 if (debug_level
>= DEBUG_LEVEL_INFO
)
1846 printk("%s(%d):mgsl_shutdown(%s)\n",
1847 __FILE__
,__LINE__
, info
->device_name
);
1849 /* clear status wait queue because status changes */
1850 /* can't happen after shutting down the hardware */
1851 wake_up_interruptible(&info
->status_event_wait_q
);
1852 wake_up_interruptible(&info
->event_wait_q
);
1854 del_timer(&info
->tx_timer
);
1856 if (info
->xmit_buf
) {
1857 free_page((unsigned long) info
->xmit_buf
);
1858 info
->xmit_buf
= NULL
;
1861 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1862 usc_DisableMasterIrqBit(info
);
1863 usc_stop_receiver(info
);
1864 usc_stop_transmitter(info
);
1865 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1866 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1867 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1869 /* Disable DMAEN (Port 7, Bit 14) */
1870 /* This disconnects the DMA request signal from the ISA bus */
1871 /* on the ISA adapter. This has no effect for the PCI adapter */
1872 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1874 /* Disable INTEN (Port 6, Bit12) */
1875 /* This disconnects the IRQ request signal to the ISA bus */
1876 /* on the ISA adapter. This has no effect for the PCI adapter */
1877 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1879 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
1880 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1881 usc_set_serial_signals(info
);
1884 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1886 mgsl_release_resources(info
);
1889 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1891 info
->flags
&= ~ASYNC_INITIALIZED
;
1893 } /* end of shutdown() */
1895 static void mgsl_program_hw(struct mgsl_struct
*info
)
1897 unsigned long flags
;
1899 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1901 usc_stop_receiver(info
);
1902 usc_stop_transmitter(info
);
1903 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1905 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1906 info
->params
.mode
== MGSL_MODE_RAW
||
1908 usc_set_sync_mode(info
);
1910 usc_set_async_mode(info
);
1912 usc_set_serial_signals(info
);
1914 info
->dcd_chkcount
= 0;
1915 info
->cts_chkcount
= 0;
1916 info
->ri_chkcount
= 0;
1917 info
->dsr_chkcount
= 0;
1919 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1920 usc_EnableInterrupts(info
, IO_PIN
);
1921 usc_get_serial_signals(info
);
1923 if (info
->netcount
|| info
->tty
->termios
->c_cflag
& CREAD
)
1924 usc_start_receiver(info
);
1926 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1929 /* Reconfigure adapter based on new parameters
1931 static void mgsl_change_params(struct mgsl_struct
*info
)
1936 if (!info
->tty
|| !info
->tty
->termios
)
1939 if (debug_level
>= DEBUG_LEVEL_INFO
)
1940 printk("%s(%d):mgsl_change_params(%s)\n",
1941 __FILE__
,__LINE__
, info
->device_name
);
1943 cflag
= info
->tty
->termios
->c_cflag
;
1945 /* if B0 rate (hangup) specified then negate DTR and RTS */
1946 /* otherwise assert DTR and RTS */
1948 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1950 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1952 /* byte size and parity */
1954 switch (cflag
& CSIZE
) {
1955 case CS5
: info
->params
.data_bits
= 5; break;
1956 case CS6
: info
->params
.data_bits
= 6; break;
1957 case CS7
: info
->params
.data_bits
= 7; break;
1958 case CS8
: info
->params
.data_bits
= 8; break;
1959 /* Never happens, but GCC is too dumb to figure it out */
1960 default: info
->params
.data_bits
= 7; break;
1964 info
->params
.stop_bits
= 2;
1966 info
->params
.stop_bits
= 1;
1968 info
->params
.parity
= ASYNC_PARITY_NONE
;
1969 if (cflag
& PARENB
) {
1971 info
->params
.parity
= ASYNC_PARITY_ODD
;
1973 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1976 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1980 /* calculate number of jiffies to transmit a full
1981 * FIFO (32 bytes) at specified data rate
1983 bits_per_char
= info
->params
.data_bits
+
1984 info
->params
.stop_bits
+ 1;
1986 /* if port data rate is set to 460800 or less then
1987 * allow tty settings to override, otherwise keep the
1988 * current data rate.
1990 if (info
->params
.data_rate
<= 460800)
1991 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
1993 if ( info
->params
.data_rate
) {
1994 info
->timeout
= (32*HZ
*bits_per_char
) /
1995 info
->params
.data_rate
;
1997 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1999 if (cflag
& CRTSCTS
)
2000 info
->flags
|= ASYNC_CTS_FLOW
;
2002 info
->flags
&= ~ASYNC_CTS_FLOW
;
2005 info
->flags
&= ~ASYNC_CHECK_CD
;
2007 info
->flags
|= ASYNC_CHECK_CD
;
2009 /* process tty input control flags */
2011 info
->read_status_mask
= RXSTATUS_OVERRUN
;
2012 if (I_INPCK(info
->tty
))
2013 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2014 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2015 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2017 if (I_IGNPAR(info
->tty
))
2018 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2019 if (I_IGNBRK(info
->tty
)) {
2020 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2021 /* If ignoring parity and break indicators, ignore
2022 * overruns too. (For real raw support).
2024 if (I_IGNPAR(info
->tty
))
2025 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
2028 mgsl_program_hw(info
);
2030 } /* end of mgsl_change_params() */
2034 * Add a character to the transmit buffer.
2036 * Arguments: tty pointer to tty information structure
2037 * ch character to add to transmit buffer
2039 * Return Value: None
2041 static void mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2043 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2044 unsigned long flags
;
2046 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
2047 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2048 __FILE__
,__LINE__
,ch
,info
->device_name
);
2051 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2054 if (!tty
|| !info
->xmit_buf
)
2057 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2059 if ( (info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2061 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2062 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2063 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2068 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2070 } /* end of mgsl_put_char() */
2072 /* mgsl_flush_chars()
2074 * Enable transmitter so remaining characters in the
2075 * transmit buffer are sent.
2077 * Arguments: tty pointer to tty information structure
2078 * Return Value: None
2080 static void mgsl_flush_chars(struct tty_struct
*tty
)
2082 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2083 unsigned long flags
;
2085 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2086 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2087 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2089 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2092 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2096 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2097 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2098 __FILE__
,__LINE__
,info
->device_name
);
2100 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2102 if (!info
->tx_active
) {
2103 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2104 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2105 /* operating in synchronous (frame oriented) mode */
2106 /* copy data from circular xmit_buf to */
2107 /* transmit DMA buffer. */
2108 mgsl_load_tx_dma_buffer(info
,
2109 info
->xmit_buf
,info
->xmit_cnt
);
2111 usc_start_transmitter(info
);
2114 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2116 } /* end of mgsl_flush_chars() */
2120 * Send a block of data
2124 * tty pointer to tty information structure
2125 * buf pointer to buffer containing send data
2126 * count size of send data in bytes
2128 * Return Value: number of characters written
2130 static int mgsl_write(struct tty_struct
* tty
,
2131 const unsigned char *buf
, int count
)
2134 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2135 unsigned long flags
;
2137 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2138 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2139 __FILE__
,__LINE__
,info
->device_name
,count
);
2141 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2144 if (!tty
|| !info
->xmit_buf
)
2147 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2148 info
->params
.mode
== MGSL_MODE_RAW
) {
2149 /* operating in synchronous (frame oriented) mode */
2150 /* operating in synchronous (frame oriented) mode */
2151 if (info
->tx_active
) {
2153 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2157 /* transmitter is actively sending data -
2158 * if we have multiple transmit dma and
2159 * holding buffers, attempt to queue this
2160 * frame for transmission at a later time.
2162 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2163 /* no tx holding buffers available */
2168 /* queue transmit frame request */
2170 save_tx_buffer_request(info
,buf
,count
);
2172 /* if we have sufficient tx dma buffers,
2173 * load the next buffered tx request
2175 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2176 load_next_tx_holding_buffer(info
);
2177 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2181 /* if operating in HDLC LoopMode and the adapter */
2182 /* has yet to be inserted into the loop, we can't */
2185 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2186 !usc_loopmode_active(info
) )
2192 if ( info
->xmit_cnt
) {
2193 /* Send accumulated from send_char() calls */
2194 /* as frame and wait before accepting more data. */
2197 /* copy data from circular xmit_buf to */
2198 /* transmit DMA buffer. */
2199 mgsl_load_tx_dma_buffer(info
,
2200 info
->xmit_buf
,info
->xmit_cnt
);
2201 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2202 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2203 __FILE__
,__LINE__
,info
->device_name
);
2205 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2206 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2207 __FILE__
,__LINE__
,info
->device_name
);
2209 info
->xmit_cnt
= count
;
2210 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2214 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2215 c
= min_t(int, count
,
2216 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2217 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2219 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2222 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2223 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2224 (SERIAL_XMIT_SIZE
-1));
2225 info
->xmit_cnt
+= c
;
2226 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2233 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2234 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2235 if (!info
->tx_active
)
2236 usc_start_transmitter(info
);
2237 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2240 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2241 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2242 __FILE__
,__LINE__
,info
->device_name
,ret
);
2246 } /* end of mgsl_write() */
2248 /* mgsl_write_room()
2250 * Return the count of free bytes in transmit buffer
2252 * Arguments: tty pointer to tty info structure
2253 * Return Value: None
2255 static int mgsl_write_room(struct tty_struct
*tty
)
2257 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2260 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2262 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2266 if (debug_level
>= DEBUG_LEVEL_INFO
)
2267 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2268 __FILE__
,__LINE__
, info
->device_name
,ret
);
2270 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2271 info
->params
.mode
== MGSL_MODE_RAW
) {
2272 /* operating in synchronous (frame oriented) mode */
2273 if ( info
->tx_active
)
2276 return HDLC_MAX_FRAME_SIZE
;
2281 } /* end of mgsl_write_room() */
2283 /* mgsl_chars_in_buffer()
2285 * Return the count of bytes in transmit buffer
2287 * Arguments: tty pointer to tty info structure
2288 * Return Value: None
2290 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2292 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2294 if (debug_level
>= DEBUG_LEVEL_INFO
)
2295 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2296 __FILE__
,__LINE__
, info
->device_name
);
2298 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2301 if (debug_level
>= DEBUG_LEVEL_INFO
)
2302 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2303 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2305 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2306 info
->params
.mode
== MGSL_MODE_RAW
) {
2307 /* operating in synchronous (frame oriented) mode */
2308 if ( info
->tx_active
)
2309 return info
->max_frame_size
;
2314 return info
->xmit_cnt
;
2315 } /* end of mgsl_chars_in_buffer() */
2317 /* mgsl_flush_buffer()
2319 * Discard all data in the send buffer
2321 * Arguments: tty pointer to tty info structure
2322 * Return Value: None
2324 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2326 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2327 unsigned long flags
;
2329 if (debug_level
>= DEBUG_LEVEL_INFO
)
2330 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2331 __FILE__
,__LINE__
, info
->device_name
);
2333 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2336 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2337 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2338 del_timer(&info
->tx_timer
);
2339 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2341 wake_up_interruptible(&tty
->write_wait
);
2345 /* mgsl_send_xchar()
2347 * Send a high-priority XON/XOFF character
2349 * Arguments: tty pointer to tty info structure
2350 * ch character to send
2351 * Return Value: None
2353 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2355 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2356 unsigned long flags
;
2358 if (debug_level
>= DEBUG_LEVEL_INFO
)
2359 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2360 __FILE__
,__LINE__
, info
->device_name
, ch
);
2362 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2367 /* Make sure transmit interrupts are on */
2368 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2369 if (!info
->tx_enabled
)
2370 usc_start_transmitter(info
);
2371 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2373 } /* end of mgsl_send_xchar() */
2377 * Signal remote device to throttle send data (our receive data)
2379 * Arguments: tty pointer to tty info structure
2380 * Return Value: None
2382 static void mgsl_throttle(struct tty_struct
* tty
)
2384 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2385 unsigned long flags
;
2387 if (debug_level
>= DEBUG_LEVEL_INFO
)
2388 printk("%s(%d):mgsl_throttle(%s) entry\n",
2389 __FILE__
,__LINE__
, info
->device_name
);
2391 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2395 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2397 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2398 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2399 info
->serial_signals
&= ~SerialSignal_RTS
;
2400 usc_set_serial_signals(info
);
2401 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2403 } /* end of mgsl_throttle() */
2405 /* mgsl_unthrottle()
2407 * Signal remote device to stop throttling send data (our receive data)
2409 * Arguments: tty pointer to tty info structure
2410 * Return Value: None
2412 static void mgsl_unthrottle(struct tty_struct
* tty
)
2414 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2415 unsigned long flags
;
2417 if (debug_level
>= DEBUG_LEVEL_INFO
)
2418 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2419 __FILE__
,__LINE__
, info
->device_name
);
2421 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2428 mgsl_send_xchar(tty
, START_CHAR(tty
));
2431 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2432 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2433 info
->serial_signals
|= SerialSignal_RTS
;
2434 usc_set_serial_signals(info
);
2435 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2438 } /* end of mgsl_unthrottle() */
2442 * get the current serial parameters information
2444 * Arguments: info pointer to device instance data
2445 * user_icount pointer to buffer to hold returned stats
2447 * Return Value: 0 if success, otherwise error code
2449 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2453 if (debug_level
>= DEBUG_LEVEL_INFO
)
2454 printk("%s(%d):mgsl_get_params(%s)\n",
2455 __FILE__
,__LINE__
, info
->device_name
);
2458 memset(&info
->icount
, 0, sizeof(info
->icount
));
2460 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2467 } /* end of mgsl_get_stats() */
2469 /* mgsl_get_params()
2471 * get the current serial parameters information
2473 * Arguments: info pointer to device instance data
2474 * user_params pointer to buffer to hold returned params
2476 * Return Value: 0 if success, otherwise error code
2478 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2481 if (debug_level
>= DEBUG_LEVEL_INFO
)
2482 printk("%s(%d):mgsl_get_params(%s)\n",
2483 __FILE__
,__LINE__
, info
->device_name
);
2485 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2487 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2488 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2489 __FILE__
,__LINE__
,info
->device_name
);
2495 } /* end of mgsl_get_params() */
2497 /* mgsl_set_params()
2499 * set the serial parameters
2503 * info pointer to device instance data
2504 * new_params user buffer containing new serial params
2506 * Return Value: 0 if success, otherwise error code
2508 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2510 unsigned long flags
;
2511 MGSL_PARAMS tmp_params
;
2514 if (debug_level
>= DEBUG_LEVEL_INFO
)
2515 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2516 info
->device_name
);
2517 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2519 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2520 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2521 __FILE__
,__LINE__
,info
->device_name
);
2525 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2526 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2527 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2529 mgsl_change_params(info
);
2533 } /* end of mgsl_set_params() */
2535 /* mgsl_get_txidle()
2537 * get the current transmit idle mode
2539 * Arguments: info pointer to device instance data
2540 * idle_mode pointer to buffer to hold returned idle mode
2542 * Return Value: 0 if success, otherwise error code
2544 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2548 if (debug_level
>= DEBUG_LEVEL_INFO
)
2549 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2550 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2552 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2554 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2555 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2556 __FILE__
,__LINE__
,info
->device_name
);
2562 } /* end of mgsl_get_txidle() */
2564 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2566 * Arguments: info pointer to device instance data
2567 * idle_mode new idle mode
2569 * Return Value: 0 if success, otherwise error code
2571 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2573 unsigned long flags
;
2575 if (debug_level
>= DEBUG_LEVEL_INFO
)
2576 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2577 info
->device_name
, idle_mode
);
2579 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2580 info
->idle_mode
= idle_mode
;
2581 usc_set_txidle( info
);
2582 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2585 } /* end of mgsl_set_txidle() */
2589 * enable or disable the transmitter
2593 * info pointer to device instance data
2594 * enable 1 = enable, 0 = disable
2596 * Return Value: 0 if success, otherwise error code
2598 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2600 unsigned long flags
;
2602 if (debug_level
>= DEBUG_LEVEL_INFO
)
2603 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2604 info
->device_name
, enable
);
2606 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2608 if ( !info
->tx_enabled
) {
2610 usc_start_transmitter(info
);
2611 /*--------------------------------------------------
2612 * if HDLC/SDLC Loop mode, attempt to insert the
2613 * station in the 'loop' by setting CMR:13. Upon
2614 * receipt of the next GoAhead (RxAbort) sequence,
2615 * the OnLoop indicator (CCSR:7) should go active
2616 * to indicate that we are on the loop
2617 *--------------------------------------------------*/
2618 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2619 usc_loopmode_insert_request( info
);
2622 if ( info
->tx_enabled
)
2623 usc_stop_transmitter(info
);
2625 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2628 } /* end of mgsl_txenable() */
2630 /* mgsl_txabort() abort send HDLC frame
2632 * Arguments: info pointer to device instance data
2633 * Return Value: 0 if success, otherwise error code
2635 static int mgsl_txabort(struct mgsl_struct
* info
)
2637 unsigned long flags
;
2639 if (debug_level
>= DEBUG_LEVEL_INFO
)
2640 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2643 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2644 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2646 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2647 usc_loopmode_cancel_transmit( info
);
2649 usc_TCmd(info
,TCmd_SendAbort
);
2651 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2654 } /* end of mgsl_txabort() */
2656 /* mgsl_rxenable() enable or disable the receiver
2658 * Arguments: info pointer to device instance data
2659 * enable 1 = enable, 0 = disable
2660 * Return Value: 0 if success, otherwise error code
2662 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2664 unsigned long flags
;
2666 if (debug_level
>= DEBUG_LEVEL_INFO
)
2667 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2668 info
->device_name
, enable
);
2670 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2672 if ( !info
->rx_enabled
)
2673 usc_start_receiver(info
);
2675 if ( info
->rx_enabled
)
2676 usc_stop_receiver(info
);
2678 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2681 } /* end of mgsl_rxenable() */
2683 /* mgsl_wait_event() wait for specified event to occur
2685 * Arguments: info pointer to device instance data
2686 * mask pointer to bitmask of events to wait for
2687 * Return Value: 0 if successful and bit mask updated with
2688 * of events triggerred,
2689 * otherwise error code
2691 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2693 unsigned long flags
;
2696 struct mgsl_icount cprev
, cnow
;
2699 struct _input_signal_events oldsigs
, newsigs
;
2700 DECLARE_WAITQUEUE(wait
, current
);
2702 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2707 if (debug_level
>= DEBUG_LEVEL_INFO
)
2708 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2709 info
->device_name
, mask
);
2711 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2713 /* return immediately if state matches requested events */
2714 usc_get_serial_signals(info
);
2715 s
= info
->serial_signals
;
2717 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2718 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2719 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2720 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2722 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2726 /* save current irq counts */
2727 cprev
= info
->icount
;
2728 oldsigs
= info
->input_signal_events
;
2730 /* enable hunt and idle irqs if needed */
2731 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2732 u16 oldreg
= usc_InReg(info
,RICR
);
2733 u16 newreg
= oldreg
+
2734 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2735 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2736 if (oldreg
!= newreg
)
2737 usc_OutReg(info
, RICR
, newreg
);
2740 set_current_state(TASK_INTERRUPTIBLE
);
2741 add_wait_queue(&info
->event_wait_q
, &wait
);
2743 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2748 if (signal_pending(current
)) {
2753 /* get current irq counts */
2754 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2755 cnow
= info
->icount
;
2756 newsigs
= info
->input_signal_events
;
2757 set_current_state(TASK_INTERRUPTIBLE
);
2758 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2760 /* if no change, wait aborted for some reason */
2761 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2762 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2763 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2764 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2765 newsigs
.cts_up
== oldsigs
.cts_up
&&
2766 newsigs
.cts_down
== oldsigs
.cts_down
&&
2767 newsigs
.ri_up
== oldsigs
.ri_up
&&
2768 newsigs
.ri_down
== oldsigs
.ri_down
&&
2769 cnow
.exithunt
== cprev
.exithunt
&&
2770 cnow
.rxidle
== cprev
.rxidle
) {
2776 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2777 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2778 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2779 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2780 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2781 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2782 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2783 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2784 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2785 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2793 remove_wait_queue(&info
->event_wait_q
, &wait
);
2794 set_current_state(TASK_RUNNING
);
2796 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2797 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2798 if (!waitqueue_active(&info
->event_wait_q
)) {
2799 /* disable enable exit hunt mode/idle rcvd IRQs */
2800 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2801 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2803 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2807 PUT_USER(rc
, events
, mask_ptr
);
2811 } /* end of mgsl_wait_event() */
2813 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2815 unsigned long flags
;
2817 struct mgsl_icount cprev
, cnow
;
2818 DECLARE_WAITQUEUE(wait
, current
);
2820 /* save current irq counts */
2821 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2822 cprev
= info
->icount
;
2823 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2824 set_current_state(TASK_INTERRUPTIBLE
);
2825 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2829 if (signal_pending(current
)) {
2834 /* get new irq counts */
2835 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2836 cnow
= info
->icount
;
2837 set_current_state(TASK_INTERRUPTIBLE
);
2838 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2840 /* if no change, wait aborted for some reason */
2841 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2842 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2847 /* check for change in caller specified modem input */
2848 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2849 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2850 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2851 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2858 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2859 set_current_state(TASK_RUNNING
);
2863 /* return the state of the serial control and status signals
2865 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
2867 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2868 unsigned int result
;
2869 unsigned long flags
;
2871 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2872 usc_get_serial_signals(info
);
2873 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2875 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2876 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2877 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2878 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2879 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2880 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2882 if (debug_level
>= DEBUG_LEVEL_INFO
)
2883 printk("%s(%d):%s tiocmget() value=%08X\n",
2884 __FILE__
,__LINE__
, info
->device_name
, result
);
2888 /* set modem control signals (DTR/RTS)
2890 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
2891 unsigned int set
, unsigned int clear
)
2893 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2894 unsigned long flags
;
2896 if (debug_level
>= DEBUG_LEVEL_INFO
)
2897 printk("%s(%d):%s tiocmset(%x,%x)\n",
2898 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2900 if (set
& TIOCM_RTS
)
2901 info
->serial_signals
|= SerialSignal_RTS
;
2902 if (set
& TIOCM_DTR
)
2903 info
->serial_signals
|= SerialSignal_DTR
;
2904 if (clear
& TIOCM_RTS
)
2905 info
->serial_signals
&= ~SerialSignal_RTS
;
2906 if (clear
& TIOCM_DTR
)
2907 info
->serial_signals
&= ~SerialSignal_DTR
;
2909 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2910 usc_set_serial_signals(info
);
2911 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2916 /* mgsl_break() Set or clear transmit break condition
2918 * Arguments: tty pointer to tty instance data
2919 * break_state -1=set break condition, 0=clear
2920 * Return Value: None
2922 static void mgsl_break(struct tty_struct
*tty
, int break_state
)
2924 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2925 unsigned long flags
;
2927 if (debug_level
>= DEBUG_LEVEL_INFO
)
2928 printk("%s(%d):mgsl_break(%s,%d)\n",
2929 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2931 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2934 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2935 if (break_state
== -1)
2936 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2938 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2939 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2941 } /* end of mgsl_break() */
2943 /* mgsl_ioctl() Service an IOCTL request
2947 * tty pointer to tty instance data
2948 * file pointer to associated file object for device
2949 * cmd IOCTL command code
2950 * arg command argument/context
2952 * Return Value: 0 if success, otherwise error code
2954 static int mgsl_ioctl(struct tty_struct
*tty
, struct file
* file
,
2955 unsigned int cmd
, unsigned long arg
)
2957 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2959 if (debug_level
>= DEBUG_LEVEL_INFO
)
2960 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2961 info
->device_name
, cmd
);
2963 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2966 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2967 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
2968 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2972 return mgsl_ioctl_common(info
, cmd
, arg
);
2975 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2978 struct mgsl_icount cnow
; /* kernel counter temps */
2979 void __user
*argp
= (void __user
*)arg
;
2980 struct serial_icounter_struct __user
*p_cuser
; /* user space */
2981 unsigned long flags
;
2984 case MGSL_IOCGPARAMS
:
2985 return mgsl_get_params(info
, argp
);
2986 case MGSL_IOCSPARAMS
:
2987 return mgsl_set_params(info
, argp
);
2988 case MGSL_IOCGTXIDLE
:
2989 return mgsl_get_txidle(info
, argp
);
2990 case MGSL_IOCSTXIDLE
:
2991 return mgsl_set_txidle(info
,(int)arg
);
2992 case MGSL_IOCTXENABLE
:
2993 return mgsl_txenable(info
,(int)arg
);
2994 case MGSL_IOCRXENABLE
:
2995 return mgsl_rxenable(info
,(int)arg
);
2996 case MGSL_IOCTXABORT
:
2997 return mgsl_txabort(info
);
2998 case MGSL_IOCGSTATS
:
2999 return mgsl_get_stats(info
, argp
);
3000 case MGSL_IOCWAITEVENT
:
3001 return mgsl_wait_event(info
, argp
);
3002 case MGSL_IOCLOOPTXDONE
:
3003 return mgsl_loopmode_send_done(info
);
3004 /* Wait for modem input (DCD,RI,DSR,CTS) change
3005 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3008 return modem_input_wait(info
,(int)arg
);
3011 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3012 * Return: write counters to the user passed counter struct
3013 * NB: both 1->0 and 0->1 transitions are counted except for
3014 * RI where only 0->1 is counted.
3017 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3018 cnow
= info
->icount
;
3019 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3021 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
3022 if (error
) return error
;
3023 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
3024 if (error
) return error
;
3025 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
3026 if (error
) return error
;
3027 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
3028 if (error
) return error
;
3029 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
3030 if (error
) return error
;
3031 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
3032 if (error
) return error
;
3033 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
3034 if (error
) return error
;
3035 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
3036 if (error
) return error
;
3037 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
3038 if (error
) return error
;
3039 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
3040 if (error
) return error
;
3041 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
3042 if (error
) return error
;
3045 return -ENOIOCTLCMD
;
3050 /* mgsl_set_termios()
3052 * Set new termios settings
3056 * tty pointer to tty structure
3057 * termios pointer to buffer to hold returned old termios
3059 * Return Value: None
3061 static void mgsl_set_termios(struct tty_struct
*tty
, struct termios
*old_termios
)
3063 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
3064 unsigned long flags
;
3066 if (debug_level
>= DEBUG_LEVEL_INFO
)
3067 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3068 tty
->driver
->name
);
3070 /* just return if nothing has changed */
3071 if ((tty
->termios
->c_cflag
== old_termios
->c_cflag
)
3072 && (RELEVANT_IFLAG(tty
->termios
->c_iflag
)
3073 == RELEVANT_IFLAG(old_termios
->c_iflag
)))
3076 mgsl_change_params(info
);
3078 /* Handle transition to B0 status */
3079 if (old_termios
->c_cflag
& CBAUD
&&
3080 !(tty
->termios
->c_cflag
& CBAUD
)) {
3081 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3082 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3083 usc_set_serial_signals(info
);
3084 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3087 /* Handle transition away from B0 status */
3088 if (!(old_termios
->c_cflag
& CBAUD
) &&
3089 tty
->termios
->c_cflag
& CBAUD
) {
3090 info
->serial_signals
|= SerialSignal_DTR
;
3091 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
3092 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3093 info
->serial_signals
|= SerialSignal_RTS
;
3095 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3096 usc_set_serial_signals(info
);
3097 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3100 /* Handle turning off CRTSCTS */
3101 if (old_termios
->c_cflag
& CRTSCTS
&&
3102 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
3103 tty
->hw_stopped
= 0;
3107 } /* end of mgsl_set_termios() */
3111 * Called when port is closed. Wait for remaining data to be
3112 * sent. Disable port and free resources.
3116 * tty pointer to open tty structure
3117 * filp pointer to open file object
3119 * Return Value: None
3121 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3123 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3125 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3128 if (debug_level
>= DEBUG_LEVEL_INFO
)
3129 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3130 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
3135 if (tty_hung_up_p(filp
))
3138 if ((tty
->count
== 1) && (info
->count
!= 1)) {
3140 * tty->count is 1 and the tty structure will be freed.
3141 * info->count should be one in this case.
3142 * if it's not, correct it so that the port is shutdown.
3144 printk("mgsl_close: bad refcount; tty->count is 1, "
3145 "info->count is %d\n", info
->count
);
3151 /* if at least one open remaining, leave hardware active */
3155 info
->flags
|= ASYNC_CLOSING
;
3157 /* set tty->closing to notify line discipline to
3158 * only process XON/XOFF characters. Only the N_TTY
3159 * discipline appears to use this (ppp does not).
3163 /* wait for transmit data to clear all layers */
3165 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
3166 if (debug_level
>= DEBUG_LEVEL_INFO
)
3167 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3168 __FILE__
,__LINE__
, info
->device_name
);
3169 tty_wait_until_sent(tty
, info
->closing_wait
);
3172 if (info
->flags
& ASYNC_INITIALIZED
)
3173 mgsl_wait_until_sent(tty
, info
->timeout
);
3175 if (tty
->driver
->flush_buffer
)
3176 tty
->driver
->flush_buffer(tty
);
3178 tty_ldisc_flush(tty
);
3185 if (info
->blocked_open
) {
3186 if (info
->close_delay
) {
3187 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
3189 wake_up_interruptible(&info
->open_wait
);
3192 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
3194 wake_up_interruptible(&info
->close_wait
);
3197 if (debug_level
>= DEBUG_LEVEL_INFO
)
3198 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3199 tty
->driver
->name
, info
->count
);
3201 } /* end of mgsl_close() */
3203 /* mgsl_wait_until_sent()
3205 * Wait until the transmitter is empty.
3209 * tty pointer to tty info structure
3210 * timeout time to wait for send completion
3212 * Return Value: None
3214 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3216 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3217 unsigned long orig_jiffies
, char_time
;
3222 if (debug_level
>= DEBUG_LEVEL_INFO
)
3223 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3224 __FILE__
,__LINE__
, info
->device_name
);
3226 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3229 if (!(info
->flags
& ASYNC_INITIALIZED
))
3232 orig_jiffies
= jiffies
;
3234 /* Set check interval to 1/5 of estimated time to
3235 * send a character, and make it at least 1. The check
3236 * interval should also be less than the timeout.
3237 * Note: use tight timings here to satisfy the NIST-PCTS.
3240 if ( info
->params
.data_rate
) {
3241 char_time
= info
->timeout
/(32 * 5);
3248 char_time
= min_t(unsigned long, char_time
, timeout
);
3250 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3251 info
->params
.mode
== MGSL_MODE_RAW
) {
3252 while (info
->tx_active
) {
3253 msleep_interruptible(jiffies_to_msecs(char_time
));
3254 if (signal_pending(current
))
3256 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3260 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3262 msleep_interruptible(jiffies_to_msecs(char_time
));
3263 if (signal_pending(current
))
3265 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3271 if (debug_level
>= DEBUG_LEVEL_INFO
)
3272 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3273 __FILE__
,__LINE__
, info
->device_name
);
3275 } /* end of mgsl_wait_until_sent() */
3279 * Called by tty_hangup() when a hangup is signaled.
3280 * This is the same as to closing all open files for the port.
3282 * Arguments: tty pointer to associated tty object
3283 * Return Value: None
3285 static void mgsl_hangup(struct tty_struct
*tty
)
3287 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3289 if (debug_level
>= DEBUG_LEVEL_INFO
)
3290 printk("%s(%d):mgsl_hangup(%s)\n",
3291 __FILE__
,__LINE__
, info
->device_name
);
3293 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3296 mgsl_flush_buffer(tty
);
3300 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
3303 wake_up_interruptible(&info
->open_wait
);
3305 } /* end of mgsl_hangup() */
3307 /* block_til_ready()
3309 * Block the current process until the specified port
3310 * is ready to be opened.
3314 * tty pointer to tty info structure
3315 * filp pointer to open file object
3316 * info pointer to device instance data
3318 * Return Value: 0 if success, otherwise error code
3320 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3321 struct mgsl_struct
*info
)
3323 DECLARE_WAITQUEUE(wait
, current
);
3325 int do_clocal
= 0, extra_count
= 0;
3326 unsigned long flags
;
3328 if (debug_level
>= DEBUG_LEVEL_INFO
)
3329 printk("%s(%d):block_til_ready on %s\n",
3330 __FILE__
,__LINE__
, tty
->driver
->name
);
3332 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3333 /* nonblock mode is set or port is not enabled */
3334 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3338 if (tty
->termios
->c_cflag
& CLOCAL
)
3341 /* Wait for carrier detect and the line to become
3342 * free (i.e., not in use by the callout). While we are in
3343 * this loop, info->count is dropped by one, so that
3344 * mgsl_close() knows when to free things. We restore it upon
3345 * exit, either normal or abnormal.
3349 add_wait_queue(&info
->open_wait
, &wait
);
3351 if (debug_level
>= DEBUG_LEVEL_INFO
)
3352 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3353 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3355 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3356 if (!tty_hung_up_p(filp
)) {
3360 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3361 info
->blocked_open
++;
3364 if (tty
->termios
->c_cflag
& CBAUD
) {
3365 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3366 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3367 usc_set_serial_signals(info
);
3368 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3371 set_current_state(TASK_INTERRUPTIBLE
);
3373 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3374 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3375 -EAGAIN
: -ERESTARTSYS
;
3379 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3380 usc_get_serial_signals(info
);
3381 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3383 if (!(info
->flags
& ASYNC_CLOSING
) &&
3384 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3388 if (signal_pending(current
)) {
3389 retval
= -ERESTARTSYS
;
3393 if (debug_level
>= DEBUG_LEVEL_INFO
)
3394 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3395 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3400 set_current_state(TASK_RUNNING
);
3401 remove_wait_queue(&info
->open_wait
, &wait
);
3405 info
->blocked_open
--;
3407 if (debug_level
>= DEBUG_LEVEL_INFO
)
3408 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3409 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3412 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3416 } /* end of block_til_ready() */
3420 * Called when a port is opened. Init and enable port.
3421 * Perform serial-specific initialization for the tty structure.
3423 * Arguments: tty pointer to tty info structure
3424 * filp associated file pointer
3426 * Return Value: 0 if success, otherwise error code
3428 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3430 struct mgsl_struct
*info
;
3432 unsigned long flags
;
3434 /* verify range of specified line number */
3436 if ((line
< 0) || (line
>= mgsl_device_count
)) {
3437 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3438 __FILE__
,__LINE__
,line
);
3442 /* find the info structure for the specified line */
3443 info
= mgsl_device_list
;
3444 while(info
&& info
->line
!= line
)
3445 info
= info
->next_device
;
3446 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3449 tty
->driver_data
= info
;
3452 if (debug_level
>= DEBUG_LEVEL_INFO
)
3453 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3454 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
3456 /* If port is closing, signal caller to try again */
3457 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
3458 if (info
->flags
& ASYNC_CLOSING
)
3459 interruptible_sleep_on(&info
->close_wait
);
3460 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
3461 -EAGAIN
: -ERESTARTSYS
);
3465 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3467 spin_lock_irqsave(&info
->netlock
, flags
);
3468 if (info
->netcount
) {
3470 spin_unlock_irqrestore(&info
->netlock
, flags
);
3474 spin_unlock_irqrestore(&info
->netlock
, flags
);
3476 if (info
->count
== 1) {
3477 /* 1st open on this device, init hardware */
3478 retval
= startup(info
);
3483 retval
= block_til_ready(tty
, filp
, info
);
3485 if (debug_level
>= DEBUG_LEVEL_INFO
)
3486 printk("%s(%d):block_til_ready(%s) returned %d\n",
3487 __FILE__
,__LINE__
, info
->device_name
, retval
);
3491 if (debug_level
>= DEBUG_LEVEL_INFO
)
3492 printk("%s(%d):mgsl_open(%s) success\n",
3493 __FILE__
,__LINE__
, info
->device_name
);
3498 if (tty
->count
== 1)
3499 info
->tty
= NULL
; /* tty layer will release tty struct */
3506 } /* end of mgsl_open() */
3509 * /proc fs routines....
3512 static inline int line_info(char *buf
, struct mgsl_struct
*info
)
3516 unsigned long flags
;
3518 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3519 ret
= sprintf(buf
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3520 info
->device_name
, info
->io_base
, info
->irq_level
,
3521 info
->phys_memory_base
, info
->phys_lcr_base
);
3523 ret
= sprintf(buf
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3524 info
->device_name
, info
->io_base
,
3525 info
->irq_level
, info
->dma_level
);
3528 /* output current serial signal states */
3529 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3530 usc_get_serial_signals(info
);
3531 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3535 if (info
->serial_signals
& SerialSignal_RTS
)
3536 strcat(stat_buf
, "|RTS");
3537 if (info
->serial_signals
& SerialSignal_CTS
)
3538 strcat(stat_buf
, "|CTS");
3539 if (info
->serial_signals
& SerialSignal_DTR
)
3540 strcat(stat_buf
, "|DTR");
3541 if (info
->serial_signals
& SerialSignal_DSR
)
3542 strcat(stat_buf
, "|DSR");
3543 if (info
->serial_signals
& SerialSignal_DCD
)
3544 strcat(stat_buf
, "|CD");
3545 if (info
->serial_signals
& SerialSignal_RI
)
3546 strcat(stat_buf
, "|RI");
3548 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3549 info
->params
.mode
== MGSL_MODE_RAW
) {
3550 ret
+= sprintf(buf
+ret
, " HDLC txok:%d rxok:%d",
3551 info
->icount
.txok
, info
->icount
.rxok
);
3552 if (info
->icount
.txunder
)
3553 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
3554 if (info
->icount
.txabort
)
3555 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
3556 if (info
->icount
.rxshort
)
3557 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
3558 if (info
->icount
.rxlong
)
3559 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
3560 if (info
->icount
.rxover
)
3561 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
3562 if (info
->icount
.rxcrc
)
3563 ret
+= sprintf(buf
+ret
, " rxcrc:%d", info
->icount
.rxcrc
);
3565 ret
+= sprintf(buf
+ret
, " ASYNC tx:%d rx:%d",
3566 info
->icount
.tx
, info
->icount
.rx
);
3567 if (info
->icount
.frame
)
3568 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
3569 if (info
->icount
.parity
)
3570 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
3571 if (info
->icount
.brk
)
3572 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
3573 if (info
->icount
.overrun
)
3574 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
3577 /* Append serial signal status to end */
3578 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
3580 ret
+= sprintf(buf
+ret
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3581 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3584 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3586 u16 Tcsr
= usc_InReg( info
, TCSR
);
3587 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3588 u16 Ticr
= usc_InReg( info
, TICR
);
3589 u16 Rscr
= usc_InReg( info
, RCSR
);
3590 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3591 u16 Ricr
= usc_InReg( info
, RICR
);
3592 u16 Icr
= usc_InReg( info
, ICR
);
3593 u16 Dccr
= usc_InReg( info
, DCCR
);
3594 u16 Tmr
= usc_InReg( info
, TMR
);
3595 u16 Tccr
= usc_InReg( info
, TCCR
);
3596 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3597 ret
+= sprintf(buf
+ret
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3598 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3599 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3601 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3605 } /* end of line_info() */
3609 * Called to print information about devices
3612 * page page of memory to hold returned info
3621 static int mgsl_read_proc(char *page
, char **start
, off_t off
, int count
,
3622 int *eof
, void *data
)
3626 struct mgsl_struct
*info
;
3628 len
+= sprintf(page
, "synclink driver:%s\n", driver_version
);
3630 info
= mgsl_device_list
;
3632 l
= line_info(page
+ len
, info
);
3634 if (len
+begin
> off
+count
)
3636 if (len
+begin
< off
) {
3640 info
= info
->next_device
;
3645 if (off
>= len
+begin
)
3647 *start
= page
+ (off
-begin
);
3648 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
3650 } /* end of mgsl_read_proc() */
3652 /* mgsl_allocate_dma_buffers()
3654 * Allocate and format DMA buffers (ISA adapter)
3655 * or format shared memory buffers (PCI adapter).
3657 * Arguments: info pointer to device instance data
3658 * Return Value: 0 if success, otherwise error
3660 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3662 unsigned short BuffersPerFrame
;
3664 info
->last_mem_alloc
= 0;
3666 /* Calculate the number of DMA buffers necessary to hold the */
3667 /* largest allowable frame size. Note: If the max frame size is */
3668 /* not an even multiple of the DMA buffer size then we need to */
3669 /* round the buffer count per frame up one. */
3671 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3672 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3675 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3677 * The PCI adapter has 256KBytes of shared memory to use.
3678 * This is 64 PAGE_SIZE buffers.
3680 * The first page is used for padding at this time so the
3681 * buffer list does not begin at offset 0 of the PCI
3682 * adapter's shared memory.
3684 * The 2nd page is used for the buffer list. A 4K buffer
3685 * list can hold 128 DMA_BUFFER structures at 32 bytes
3688 * This leaves 62 4K pages.
3690 * The next N pages are used for transmit frame(s). We
3691 * reserve enough 4K page blocks to hold the required
3692 * number of transmit dma buffers (num_tx_dma_buffers),
3693 * each of MaxFrameSize size.
3695 * Of the remaining pages (62-N), determine how many can
3696 * be used to receive full MaxFrameSize inbound frames
3698 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3699 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3701 /* Calculate the number of PAGE_SIZE buffers needed for */
3702 /* receive and transmit DMA buffers. */
3705 /* Calculate the number of DMA buffers necessary to */
3706 /* hold 7 max size receive frames and one max size transmit frame. */
3707 /* The receive buffer count is bumped by one so we avoid an */
3708 /* End of List condition if all receive buffers are used when */
3709 /* using linked list DMA buffers. */
3711 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3712 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3715 * limit total TxBuffers & RxBuffers to 62 4K total
3716 * (ala PCI Allocation)
3719 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3720 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3724 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3725 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3726 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3728 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3729 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3730 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3731 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3732 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3733 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3737 mgsl_reset_rx_dma_buffers( info
);
3738 mgsl_reset_tx_dma_buffers( info
);
3742 } /* end of mgsl_allocate_dma_buffers() */
3745 * mgsl_alloc_buffer_list_memory()
3747 * Allocate a common DMA buffer for use as the
3748 * receive and transmit buffer lists.
3750 * A buffer list is a set of buffer entries where each entry contains
3751 * a pointer to an actual buffer and a pointer to the next buffer entry
3752 * (plus some other info about the buffer).
3754 * The buffer entries for a list are built to form a circular list so
3755 * that when the entire list has been traversed you start back at the
3758 * This function allocates memory for just the buffer entries.
3759 * The links (pointer to next entry) are filled in with the physical
3760 * address of the next entry so the adapter can navigate the list
3761 * using bus master DMA. The pointers to the actual buffers are filled
3762 * out later when the actual buffers are allocated.
3764 * Arguments: info pointer to device instance data
3765 * Return Value: 0 if success, otherwise error
3767 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3771 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3772 /* PCI adapter uses shared memory. */
3773 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3774 info
->buffer_list_phys
= info
->last_mem_alloc
;
3775 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3777 /* ISA adapter uses system memory. */
3778 /* The buffer lists are allocated as a common buffer that both */
3779 /* the processor and adapter can access. This allows the driver to */
3780 /* inspect portions of the buffer while other portions are being */
3781 /* updated by the adapter using Bus Master DMA. */
3783 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3784 if (info
->buffer_list
== NULL
)
3786 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3789 /* We got the memory for the buffer entry lists. */
3790 /* Initialize the memory block to all zeros. */
3791 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3793 /* Save virtual address pointers to the receive and */
3794 /* transmit buffer lists. (Receive 1st). These pointers will */
3795 /* be used by the processor to access the lists. */
3796 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3797 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3798 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3801 * Build the links for the buffer entry lists such that
3802 * two circular lists are built. (Transmit and Receive).
3804 * Note: the links are physical addresses
3805 * which are read by the adapter to determine the next
3806 * buffer entry to use.
3809 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3810 /* calculate and store physical address of this buffer entry */
3811 info
->rx_buffer_list
[i
].phys_entry
=
3812 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3814 /* calculate and store physical address of */
3815 /* next entry in cirular list of entries */
3817 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3819 if ( i
< info
->rx_buffer_count
- 1 )
3820 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3823 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3824 /* calculate and store physical address of this buffer entry */
3825 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3826 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3828 /* calculate and store physical address of */
3829 /* next entry in cirular list of entries */
3831 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3832 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3834 if ( i
< info
->tx_buffer_count
- 1 )
3835 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3840 } /* end of mgsl_alloc_buffer_list_memory() */
3842 /* Free DMA buffers allocated for use as the
3843 * receive and transmit buffer lists.
3846 * The data transfer buffers associated with the buffer list
3847 * MUST be freed before freeing the buffer list itself because
3848 * the buffer list contains the information necessary to free
3849 * the individual buffers!
3851 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3853 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3854 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3856 info
->buffer_list
= NULL
;
3857 info
->rx_buffer_list
= NULL
;
3858 info
->tx_buffer_list
= NULL
;
3860 } /* end of mgsl_free_buffer_list_memory() */
3863 * mgsl_alloc_frame_memory()
3865 * Allocate the frame DMA buffers used by the specified buffer list.
3866 * Each DMA buffer will be one memory page in size. This is necessary
3867 * because memory can fragment enough that it may be impossible
3872 * info pointer to device instance data
3873 * BufferList pointer to list of buffer entries
3874 * Buffercount count of buffer entries in buffer list
3876 * Return Value: 0 if success, otherwise -ENOMEM
3878 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3883 /* Allocate page sized buffers for the receive buffer list */
3885 for ( i
= 0; i
< Buffercount
; i
++ ) {
3886 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3887 /* PCI adapter uses shared memory buffers. */
3888 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3889 phys_addr
= info
->last_mem_alloc
;
3890 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3892 /* ISA adapter uses system memory. */
3893 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3894 if (BufferList
[i
].virt_addr
== NULL
)
3896 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3898 BufferList
[i
].phys_addr
= phys_addr
;
3903 } /* end of mgsl_alloc_frame_memory() */
3906 * mgsl_free_frame_memory()
3908 * Free the buffers associated with
3909 * each buffer entry of a buffer list.
3913 * info pointer to device instance data
3914 * BufferList pointer to list of buffer entries
3915 * Buffercount count of buffer entries in buffer list
3917 * Return Value: None
3919 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3924 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3925 if ( BufferList
[i
].virt_addr
) {
3926 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3927 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3928 BufferList
[i
].virt_addr
= NULL
;
3933 } /* end of mgsl_free_frame_memory() */
3935 /* mgsl_free_dma_buffers()
3939 * Arguments: info pointer to device instance data
3940 * Return Value: None
3942 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3944 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3945 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3946 mgsl_free_buffer_list_memory( info
);
3948 } /* end of mgsl_free_dma_buffers() */
3952 * mgsl_alloc_intermediate_rxbuffer_memory()
3954 * Allocate a buffer large enough to hold max_frame_size. This buffer
3955 * is used to pass an assembled frame to the line discipline.
3959 * info pointer to device instance data
3961 * Return Value: 0 if success, otherwise -ENOMEM
3963 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3965 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3966 if ( info
->intermediate_rxbuffer
== NULL
)
3971 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3974 * mgsl_free_intermediate_rxbuffer_memory()
3979 * info pointer to device instance data
3981 * Return Value: None
3983 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3985 kfree(info
->intermediate_rxbuffer
);
3986 info
->intermediate_rxbuffer
= NULL
;
3988 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3991 * mgsl_alloc_intermediate_txbuffer_memory()
3993 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3994 * This buffer is used to load transmit frames into the adapter's dma transfer
3995 * buffers when there is sufficient space.
3999 * info pointer to device instance data
4001 * Return Value: 0 if success, otherwise -ENOMEM
4003 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4007 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4008 printk("%s %s(%d) allocating %d tx holding buffers\n",
4009 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
4011 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
4013 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4014 info
->tx_holding_buffers
[i
].buffer
=
4015 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
4016 if ( info
->tx_holding_buffers
[i
].buffer
== NULL
)
4022 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4025 * mgsl_free_intermediate_txbuffer_memory()
4030 * info pointer to device instance data
4032 * Return Value: None
4034 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4038 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4039 kfree(info
->tx_holding_buffers
[i
].buffer
);
4040 info
->tx_holding_buffers
[i
].buffer
= NULL
;
4043 info
->get_tx_holding_index
= 0;
4044 info
->put_tx_holding_index
= 0;
4045 info
->tx_holding_count
= 0;
4047 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4051 * load_next_tx_holding_buffer()
4053 * attempts to load the next buffered tx request into the
4058 * info pointer to device instance data
4060 * Return Value: 1 if next buffered tx request loaded
4061 * into adapter's tx dma buffer,
4064 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4068 if ( info
->tx_holding_count
) {
4069 /* determine if we have enough tx dma buffers
4070 * to accommodate the next tx frame
4072 struct tx_holding_buffer
*ptx
=
4073 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4074 int num_free
= num_free_tx_dma_buffers(info
);
4075 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4076 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4079 if (num_needed
<= num_free
) {
4080 info
->xmit_cnt
= ptx
->buffer_size
;
4081 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4083 --info
->tx_holding_count
;
4084 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4085 info
->get_tx_holding_index
=0;
4087 /* restart transmit timer */
4088 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4098 * save_tx_buffer_request()
4100 * attempt to store transmit frame request for later transmission
4104 * info pointer to device instance data
4105 * Buffer pointer to buffer containing frame to load
4106 * BufferSize size in bytes of frame in Buffer
4108 * Return Value: 1 if able to store, 0 otherwise
4110 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4112 struct tx_holding_buffer
*ptx
;
4114 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4115 return 0; /* all buffers in use */
4118 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4119 ptx
->buffer_size
= BufferSize
;
4120 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4122 ++info
->tx_holding_count
;
4123 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4124 info
->put_tx_holding_index
=0;
4129 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4131 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4132 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4133 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4136 info
->io_addr_requested
= 1;
4138 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4139 info
->device_name
, info
) < 0 ) {
4140 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4141 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4144 info
->irq_requested
= 1;
4146 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4147 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4148 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4149 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4152 info
->shared_mem_requested
= 1;
4153 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4154 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4155 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4158 info
->lcr_mem_requested
= 1;
4160 info
->memory_base
= ioremap(info
->phys_memory_base
,0x40000);
4161 if (!info
->memory_base
) {
4162 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4163 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4167 if ( !mgsl_memory_test(info
) ) {
4168 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4169 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4173 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
) + info
->lcr_offset
;
4174 if (!info
->lcr_base
) {
4175 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4176 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4181 /* claim DMA channel */
4183 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4184 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4185 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4186 mgsl_release_resources( info
);
4189 info
->dma_requested
= 1;
4191 /* ISA adapter uses bus master DMA */
4192 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4193 enable_dma(info
->dma_level
);
4196 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4197 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4198 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4204 mgsl_release_resources(info
);
4207 } /* end of mgsl_claim_resources() */
4209 static void mgsl_release_resources(struct mgsl_struct
*info
)
4211 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4212 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4213 __FILE__
,__LINE__
,info
->device_name
);
4215 if ( info
->irq_requested
) {
4216 free_irq(info
->irq_level
, info
);
4217 info
->irq_requested
= 0;
4219 if ( info
->dma_requested
) {
4220 disable_dma(info
->dma_level
);
4221 free_dma(info
->dma_level
);
4222 info
->dma_requested
= 0;
4224 mgsl_free_dma_buffers(info
);
4225 mgsl_free_intermediate_rxbuffer_memory(info
);
4226 mgsl_free_intermediate_txbuffer_memory(info
);
4228 if ( info
->io_addr_requested
) {
4229 release_region(info
->io_base
,info
->io_addr_size
);
4230 info
->io_addr_requested
= 0;
4232 if ( info
->shared_mem_requested
) {
4233 release_mem_region(info
->phys_memory_base
,0x40000);
4234 info
->shared_mem_requested
= 0;
4236 if ( info
->lcr_mem_requested
) {
4237 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4238 info
->lcr_mem_requested
= 0;
4240 if (info
->memory_base
){
4241 iounmap(info
->memory_base
);
4242 info
->memory_base
= NULL
;
4244 if (info
->lcr_base
){
4245 iounmap(info
->lcr_base
- info
->lcr_offset
);
4246 info
->lcr_base
= NULL
;
4249 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4250 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4251 __FILE__
,__LINE__
,info
->device_name
);
4253 } /* end of mgsl_release_resources() */
4255 /* mgsl_add_device()
4257 * Add the specified device instance data structure to the
4258 * global linked list of devices and increment the device count.
4260 * Arguments: info pointer to device instance data
4261 * Return Value: None
4263 static void mgsl_add_device( struct mgsl_struct
*info
)
4265 info
->next_device
= NULL
;
4266 info
->line
= mgsl_device_count
;
4267 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4269 if (info
->line
< MAX_TOTAL_DEVICES
) {
4270 if (maxframe
[info
->line
])
4271 info
->max_frame_size
= maxframe
[info
->line
];
4272 info
->dosyncppp
= dosyncppp
[info
->line
];
4274 if (txdmabufs
[info
->line
]) {
4275 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4276 if (info
->num_tx_dma_buffers
< 1)
4277 info
->num_tx_dma_buffers
= 1;
4280 if (txholdbufs
[info
->line
]) {
4281 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4282 if (info
->num_tx_holding_buffers
< 1)
4283 info
->num_tx_holding_buffers
= 1;
4284 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4285 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4289 mgsl_device_count
++;
4291 if ( !mgsl_device_list
)
4292 mgsl_device_list
= info
;
4294 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4295 while( current_dev
->next_device
)
4296 current_dev
= current_dev
->next_device
;
4297 current_dev
->next_device
= info
;
4300 if ( info
->max_frame_size
< 4096 )
4301 info
->max_frame_size
= 4096;
4302 else if ( info
->max_frame_size
> 65535 )
4303 info
->max_frame_size
= 65535;
4305 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4306 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4307 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4308 info
->phys_memory_base
, info
->phys_lcr_base
,
4309 info
->max_frame_size
);
4311 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4312 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4313 info
->max_frame_size
);
4320 } /* end of mgsl_add_device() */
4322 /* mgsl_allocate_device()
4324 * Allocate and initialize a device instance structure
4327 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4329 static struct mgsl_struct
* mgsl_allocate_device(void)
4331 struct mgsl_struct
*info
;
4333 info
= (struct mgsl_struct
*)kmalloc(sizeof(struct mgsl_struct
),
4337 printk("Error can't allocate device instance data\n");
4339 memset(info
, 0, sizeof(struct mgsl_struct
));
4340 info
->magic
= MGSL_MAGIC
;
4341 INIT_WORK(&info
->task
, mgsl_bh_handler
, info
);
4342 info
->max_frame_size
= 4096;
4343 info
->close_delay
= 5*HZ
/10;
4344 info
->closing_wait
= 30*HZ
;
4345 init_waitqueue_head(&info
->open_wait
);
4346 init_waitqueue_head(&info
->close_wait
);
4347 init_waitqueue_head(&info
->status_event_wait_q
);
4348 init_waitqueue_head(&info
->event_wait_q
);
4349 spin_lock_init(&info
->irq_spinlock
);
4350 spin_lock_init(&info
->netlock
);
4351 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4352 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4353 info
->num_tx_dma_buffers
= 1;
4354 info
->num_tx_holding_buffers
= 0;
4359 } /* end of mgsl_allocate_device()*/
4361 static const struct tty_operations mgsl_ops
= {
4363 .close
= mgsl_close
,
4364 .write
= mgsl_write
,
4365 .put_char
= mgsl_put_char
,
4366 .flush_chars
= mgsl_flush_chars
,
4367 .write_room
= mgsl_write_room
,
4368 .chars_in_buffer
= mgsl_chars_in_buffer
,
4369 .flush_buffer
= mgsl_flush_buffer
,
4370 .ioctl
= mgsl_ioctl
,
4371 .throttle
= mgsl_throttle
,
4372 .unthrottle
= mgsl_unthrottle
,
4373 .send_xchar
= mgsl_send_xchar
,
4374 .break_ctl
= mgsl_break
,
4375 .wait_until_sent
= mgsl_wait_until_sent
,
4376 .read_proc
= mgsl_read_proc
,
4377 .set_termios
= mgsl_set_termios
,
4379 .start
= mgsl_start
,
4380 .hangup
= mgsl_hangup
,
4381 .tiocmget
= tiocmget
,
4382 .tiocmset
= tiocmset
,
4386 * perform tty device initialization
4388 static int mgsl_init_tty(void)
4392 serial_driver
= alloc_tty_driver(128);
4396 serial_driver
->owner
= THIS_MODULE
;
4397 serial_driver
->driver_name
= "synclink";
4398 serial_driver
->name
= "ttySL";
4399 serial_driver
->major
= ttymajor
;
4400 serial_driver
->minor_start
= 64;
4401 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4402 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4403 serial_driver
->init_termios
= tty_std_termios
;
4404 serial_driver
->init_termios
.c_cflag
=
4405 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4406 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4407 tty_set_operations(serial_driver
, &mgsl_ops
);
4408 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4409 printk("%s(%d):Couldn't register serial driver\n",
4411 put_tty_driver(serial_driver
);
4412 serial_driver
= NULL
;
4416 printk("%s %s, tty major#%d\n",
4417 driver_name
, driver_version
,
4418 serial_driver
->major
);
4422 /* enumerate user specified ISA adapters
4424 static void mgsl_enum_isa_devices(void)
4426 struct mgsl_struct
*info
;
4429 /* Check for user specified ISA devices */
4431 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4432 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4433 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4434 io
[i
], irq
[i
], dma
[i
] );
4436 info
= mgsl_allocate_device();
4438 /* error allocating device instance data */
4439 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4440 printk( "can't allocate device instance data.\n");
4444 /* Copy user configuration info to device instance data */
4445 info
->io_base
= (unsigned int)io
[i
];
4446 info
->irq_level
= (unsigned int)irq
[i
];
4447 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4448 info
->dma_level
= (unsigned int)dma
[i
];
4449 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4450 info
->io_addr_size
= 16;
4451 info
->irq_flags
= 0;
4453 mgsl_add_device( info
);
4457 static void synclink_cleanup(void)
4460 struct mgsl_struct
*info
;
4461 struct mgsl_struct
*tmp
;
4463 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4465 if (serial_driver
) {
4466 if ((rc
= tty_unregister_driver(serial_driver
)))
4467 printk("%s(%d) failed to unregister tty driver err=%d\n",
4468 __FILE__
,__LINE__
,rc
);
4469 put_tty_driver(serial_driver
);
4472 info
= mgsl_device_list
;
4477 mgsl_release_resources(info
);
4479 info
= info
->next_device
;
4484 pci_unregister_driver(&synclink_pci_driver
);
4487 static int __init
synclink_init(void)
4491 if (break_on_load
) {
4492 mgsl_get_text_ptr();
4496 printk("%s %s\n", driver_name
, driver_version
);
4498 mgsl_enum_isa_devices();
4499 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4500 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4504 if ((rc
= mgsl_init_tty()) < 0)
4514 static void __exit
synclink_exit(void)
4519 module_init(synclink_init
);
4520 module_exit(synclink_exit
);
4525 * Issue a USC Receive/Transmit command to the
4526 * Channel Command/Address Register (CCAR).
4530 * The command is encoded in the most significant 5 bits <15..11>
4531 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4532 * and Bits <6..0> must be written as zeros.
4536 * info pointer to device information structure
4537 * Cmd command mask (use symbolic macros)
4543 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4545 /* output command to CCAR in bits <15..11> */
4546 /* preserve bits <10..7>, bits <6..0> must be zero */
4548 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4550 /* Read to flush write to CCAR */
4551 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4552 inw( info
->io_base
+ CCAR
);
4554 } /* end of usc_RTCmd() */
4559 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4563 * info pointer to device information structure
4564 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4570 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4572 /* write command mask to DCAR */
4573 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4575 /* Read to flush write to DCAR */
4576 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4577 inw( info
->io_base
);
4579 } /* end of usc_DmaCmd() */
4584 * Write a 16-bit value to a USC DMA register
4588 * info pointer to device info structure
4589 * RegAddr register address (number) for write
4590 * RegValue 16-bit value to write to register
4597 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4599 /* Note: The DCAR is located at the adapter base address */
4600 /* Note: must preserve state of BIT8 in DCAR */
4602 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4603 outw( RegValue
, info
->io_base
);
4605 /* Read to flush write to DCAR */
4606 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4607 inw( info
->io_base
);
4609 } /* end of usc_OutDmaReg() */
4614 * Read a 16-bit value from a DMA register
4618 * info pointer to device info structure
4619 * RegAddr register address (number) to read from
4623 * The 16-bit value read from register
4626 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4628 /* Note: The DCAR is located at the adapter base address */
4629 /* Note: must preserve state of BIT8 in DCAR */
4631 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4632 return inw( info
->io_base
);
4634 } /* end of usc_InDmaReg() */
4640 * Write a 16-bit value to a USC serial channel register
4644 * info pointer to device info structure
4645 * RegAddr register address (number) to write to
4646 * RegValue 16-bit value to write to register
4653 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4655 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4656 outw( RegValue
, info
->io_base
+ CCAR
);
4658 /* Read to flush write to CCAR */
4659 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4660 inw( info
->io_base
+ CCAR
);
4662 } /* end of usc_OutReg() */
4667 * Reads a 16-bit value from a USC serial channel register
4671 * info pointer to device extension
4672 * RegAddr register address (number) to read from
4676 * 16-bit value read from register
4678 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4680 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4681 return inw( info
->io_base
+ CCAR
);
4683 } /* end of usc_InReg() */
4685 /* usc_set_sdlc_mode()
4687 * Set up the adapter for SDLC DMA communications.
4689 * Arguments: info pointer to device instance data
4690 * Return Value: NONE
4692 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4698 * determine if the IUSC on the adapter is pre-SL1660. If
4699 * not, take advantage of the UnderWait feature of more
4700 * modern chips. If an underrun occurs and this bit is set,
4701 * the transmitter will idle the programmed idle pattern
4702 * until the driver has time to service the underrun. Otherwise,
4703 * the dma controller may get the cycles previously requested
4704 * and begin transmitting queued tx data.
4706 usc_OutReg(info
,TMCR
,0x1f);
4707 RegValue
=usc_InReg(info
,TMDR
);
4708 if ( RegValue
== IUSC_PRE_SL1660
)
4714 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4717 ** Channel Mode Register (CMR)
4719 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4720 ** <13> 0 0 = Transmit Disabled (initially)
4721 ** <12> 0 1 = Consecutive Idles share common 0
4722 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4723 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4724 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4726 ** 1000 1110 0000 0110 = 0x8e06
4730 /*--------------------------------------------------
4731 * ignore user options for UnderRun Actions and
4733 *--------------------------------------------------*/
4737 /* Channel mode Register (CMR)
4739 * <15..14> 00 Tx Sub modes, Underrun Action
4740 * <13> 0 1 = Send Preamble before opening flag
4741 * <12> 0 1 = Consecutive Idles share common 0
4742 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4743 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4744 * <3..0> 0110 Receiver mode = HDLC/SDLC
4746 * 0000 0110 0000 0110 = 0x0606
4748 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4749 RegValue
= 0x0001; /* Set Receive mode = external sync */
4751 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4752 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4756 * CMR <15> 0 Don't send CRC on Tx Underrun
4757 * CMR <14> x undefined
4758 * CMR <13> 0 Send preamble before openning sync
4759 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4762 * CMR <11-8) 0100 MonoSync
4764 * 0x00 0100 xxxx xxxx 04xx
4772 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4774 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4776 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4777 RegValue
|= BIT15
+ BIT14
;
4780 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4784 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4785 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4788 if ( info
->params
.addr_filter
!= 0xff )
4790 /* set up receive address filtering */
4791 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4795 usc_OutReg( info
, CMR
, RegValue
);
4796 info
->cmr_value
= RegValue
;
4798 /* Receiver mode Register (RMR)
4800 * <15..13> 000 encoding
4801 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4802 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4803 * <9> 0 1 = Include Receive chars in CRC
4804 * <8> 1 1 = Use Abort/PE bit as abort indicator
4805 * <7..6> 00 Even parity
4806 * <5> 0 parity disabled
4807 * <4..2> 000 Receive Char Length = 8 bits
4808 * <1..0> 00 Disable Receiver
4810 * 0000 0101 0000 0000 = 0x0500
4815 switch ( info
->params
.encoding
) {
4816 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4817 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4818 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4819 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4820 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4821 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4822 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4825 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4827 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4828 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4830 usc_OutReg( info
, RMR
, RegValue
);
4832 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4833 /* When an opening flag of an SDLC frame is recognized the */
4834 /* Receive Character count (RCC) is loaded with the value in */
4835 /* RCLR. The RCC is decremented for each received byte. The */
4836 /* value of RCC is stored after the closing flag of the frame */
4837 /* allowing the frame size to be computed. */
4839 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4841 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4843 /* Receive Interrupt Control Register (RICR)
4845 * <15..8> ? RxFIFO DMA Request Level
4846 * <7> 0 Exited Hunt IA (Interrupt Arm)
4847 * <6> 0 Idle Received IA
4848 * <5> 0 Break/Abort IA
4850 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4852 * <1> 1 Rx Overrun IA
4853 * <0> 0 Select TC0 value for readback
4855 * 0000 0000 0000 1000 = 0x000a
4858 /* Carry over the Exit Hunt and Idle Received bits */
4859 /* in case they have been armed by usc_ArmEvents. */
4861 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4863 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4864 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4866 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4868 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4870 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4871 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4873 /* Transmit mode Register (TMR)
4875 * <15..13> 000 encoding
4876 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4877 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4878 * <9> 0 1 = Tx CRC Enabled
4879 * <8> 0 1 = Append CRC to end of transmit frame
4880 * <7..6> 00 Transmit parity Even
4881 * <5> 0 Transmit parity Disabled
4882 * <4..2> 000 Tx Char Length = 8 bits
4883 * <1..0> 00 Disable Transmitter
4885 * 0000 0100 0000 0000 = 0x0400
4890 switch ( info
->params
.encoding
) {
4891 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4892 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4893 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4894 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4895 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4896 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4897 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4900 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4901 RegValue
|= BIT9
+ BIT8
;
4902 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4903 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4905 usc_OutReg( info
, TMR
, RegValue
);
4907 usc_set_txidle( info
);
4910 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4912 /* Transmit Interrupt Control Register (TICR)
4914 * <15..8> ? Transmit FIFO DMA Level
4915 * <7> 0 Present IA (Interrupt Arm)
4916 * <6> 0 Idle Sent IA
4917 * <5> 1 Abort Sent IA
4918 * <4> 1 EOF/EOM Sent IA
4920 * <2> 1 1 = Wait for SW Trigger to Start Frame
4921 * <1> 1 Tx Underrun IA
4922 * <0> 0 TC0 constant on read back
4924 * 0000 0000 0011 0110 = 0x0036
4927 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4928 usc_OutReg( info
, TICR
, 0x0736 );
4930 usc_OutReg( info
, TICR
, 0x1436 );
4932 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4933 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4936 ** Transmit Command/Status Register (TCSR)
4938 ** <15..12> 0000 TCmd
4939 ** <11> 0/1 UnderWait
4940 ** <10..08> 000 TxIdle
4944 ** <4> x EOF/EOM Sent
4950 ** 0000 0000 0000 0000 = 0x0000
4952 info
->tcsr_value
= 0;
4955 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4957 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4959 /* Clock mode Control Register (CMCR)
4961 * <15..14> 00 counter 1 Source = Disabled
4962 * <13..12> 00 counter 0 Source = Disabled
4963 * <11..10> 11 BRG1 Input is TxC Pin
4964 * <9..8> 11 BRG0 Input is TxC Pin
4965 * <7..6> 01 DPLL Input is BRG1 Output
4966 * <5..3> XXX TxCLK comes from Port 0
4967 * <2..0> XXX RxCLK comes from Port 1
4969 * 0000 1111 0111 0111 = 0x0f77
4974 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4975 RegValue
|= 0x0003; /* RxCLK from DPLL */
4976 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4977 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4978 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4979 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4981 RegValue
|= 0x0007; /* RxCLK from Port1 */
4983 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4984 RegValue
|= 0x0018; /* TxCLK from DPLL */
4985 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4986 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4987 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4988 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4990 RegValue
|= 0x0030; /* TxCLK from Port0 */
4992 usc_OutReg( info
, CMCR
, RegValue
);
4995 /* Hardware Configuration Register (HCR)
4997 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4998 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4999 * <12> 0 CVOK:0=report code violation in biphase
5000 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5001 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5002 * <7..6> 00 reserved
5003 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5005 * <3..2> 00 reserved
5006 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5012 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
5017 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5018 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5020 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5021 XtalSpeed
= 11059200;
5023 XtalSpeed
= 14745600;
5025 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
5029 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
5036 /* Tc = (Xtal/Speed) - 1 */
5037 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5038 /* then rounding up gives a more precise time constant. Instead */
5039 /* of rounding up and then subtracting 1 we just don't subtract */
5040 /* the one in this case. */
5042 /*--------------------------------------------------
5043 * ejz: for DPLL mode, application should use the
5044 * same clock speed as the partner system, even
5045 * though clocking is derived from the input RxData.
5046 * In case the user uses a 0 for the clock speed,
5047 * default to 0xffffffff and don't try to divide by
5049 *--------------------------------------------------*/
5050 if ( info
->params
.clock_speed
)
5052 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
5053 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
5054 / info
->params
.clock_speed
) )
5061 /* Write 16-bit Time Constant for BRG1 */
5062 usc_OutReg( info
, TC1R
, Tc
);
5064 RegValue
|= BIT4
; /* enable BRG1 */
5066 switch ( info
->params
.encoding
) {
5067 case HDLC_ENCODING_NRZ
:
5068 case HDLC_ENCODING_NRZB
:
5069 case HDLC_ENCODING_NRZI_MARK
:
5070 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
5071 case HDLC_ENCODING_BIPHASE_MARK
:
5072 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5073 case HDLC_ENCODING_BIPHASE_LEVEL
:
5074 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5078 usc_OutReg( info
, HCR
, RegValue
);
5081 /* Channel Control/status Register (CCSR)
5083 * <15> X RCC FIFO Overflow status (RO)
5084 * <14> X RCC FIFO Not Empty status (RO)
5085 * <13> 0 1 = Clear RCC FIFO (WO)
5086 * <12> X DPLL Sync (RW)
5087 * <11> X DPLL 2 Missed Clocks status (RO)
5088 * <10> X DPLL 1 Missed Clock status (RO)
5089 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5090 * <7> X SDLC Loop On status (RO)
5091 * <6> X SDLC Loop Send status (RO)
5092 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5093 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5094 * <1..0> 00 reserved
5096 * 0000 0000 0010 0000 = 0x0020
5099 usc_OutReg( info
, CCSR
, 0x1020 );
5102 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5103 usc_OutReg( info
, SICR
,
5104 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5108 /* enable Master Interrupt Enable bit (MIE) */
5109 usc_EnableMasterIrqBit( info
);
5111 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5112 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5114 /* arm RCC underflow interrupt */
5115 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5116 usc_EnableInterrupts(info
, MISC
);
5119 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5120 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5121 info
->mbre_bit
= BIT8
;
5122 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5124 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5125 /* Enable DMAEN (Port 7, Bit 14) */
5126 /* This connects the DMA request signal to the ISA bus */
5127 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5130 /* DMA Control Register (DCR)
5132 * <15..14> 10 Priority mode = Alternating Tx/Rx
5133 * 01 Rx has priority
5134 * 00 Tx has priority
5136 * <13> 1 Enable Priority Preempt per DCR<15..14>
5137 * (WARNING DCR<11..10> must be 00 when this is 1)
5138 * 0 Choose activate channel per DCR<11..10>
5140 * <12> 0 Little Endian for Array/List
5141 * <11..10> 00 Both Channels can use each bus grant
5142 * <9..6> 0000 reserved
5143 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5144 * <4> 0 1 = drive D/C and S/D pins
5145 * <3> 1 1 = Add one wait state to all DMA cycles.
5146 * <2> 0 1 = Strobe /UAS on every transfer.
5147 * <1..0> 11 Addr incrementing only affects LS24 bits
5149 * 0110 0000 0000 1011 = 0x600b
5152 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5153 /* PCI adapter does not need DMA wait state */
5154 usc_OutDmaReg( info
, DCR
, 0xa00b );
5157 usc_OutDmaReg( info
, DCR
, 0x800b );
5160 /* Receive DMA mode Register (RDMR)
5162 * <15..14> 11 DMA mode = Linked List Buffer mode
5163 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5164 * <12> 1 Clear count of List Entry after fetching
5165 * <11..10> 00 Address mode = Increment
5166 * <9> 1 Terminate Buffer on RxBound
5167 * <8> 0 Bus Width = 16bits
5168 * <7..0> ? status Bits (write as 0s)
5170 * 1111 0010 0000 0000 = 0xf200
5173 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5176 /* Transmit DMA mode Register (TDMR)
5178 * <15..14> 11 DMA mode = Linked List Buffer mode
5179 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5180 * <12> 1 Clear count of List Entry after fetching
5181 * <11..10> 00 Address mode = Increment
5182 * <9> 1 Terminate Buffer on end of frame
5183 * <8> 0 Bus Width = 16bits
5184 * <7..0> ? status Bits (Read Only so write as 0)
5186 * 1111 0010 0000 0000 = 0xf200
5189 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5192 /* DMA Interrupt Control Register (DICR)
5194 * <15> 1 DMA Interrupt Enable
5195 * <14> 0 1 = Disable IEO from USC
5196 * <13> 0 1 = Don't provide vector during IntAck
5197 * <12> 1 1 = Include status in Vector
5198 * <10..2> 0 reserved, Must be 0s
5199 * <1> 0 1 = Rx DMA Interrupt Enabled
5200 * <0> 0 1 = Tx DMA Interrupt Enabled
5202 * 1001 0000 0000 0000 = 0x9000
5205 usc_OutDmaReg( info
, DICR
, 0x9000 );
5207 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5208 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5209 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5211 /* Channel Control Register (CCR)
5213 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5214 * <13> 0 Trigger Tx on SW Command Disabled
5215 * <12> 0 Flag Preamble Disabled
5216 * <11..10> 00 Preamble Length
5217 * <9..8> 00 Preamble Pattern
5218 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5219 * <5> 0 Trigger Rx on SW Command Disabled
5222 * 1000 0000 1000 0000 = 0x8080
5227 switch ( info
->params
.preamble_length
) {
5228 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5229 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5230 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5233 switch ( info
->params
.preamble
) {
5234 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5235 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5236 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5237 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5240 usc_OutReg( info
, CCR
, RegValue
);
5244 * Burst/Dwell Control Register
5246 * <15..8> 0x20 Maximum number of transfers per bus grant
5247 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5250 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5251 /* don't limit bus occupancy on PCI adapter */
5252 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5255 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5257 usc_stop_transmitter(info
);
5258 usc_stop_receiver(info
);
5260 } /* end of usc_set_sdlc_mode() */
5262 /* usc_enable_loopback()
5264 * Set the 16C32 for internal loopback mode.
5265 * The TxCLK and RxCLK signals are generated from the BRG0 and
5266 * the TxD is looped back to the RxD internally.
5268 * Arguments: info pointer to device instance data
5269 * enable 1 = enable loopback, 0 = disable
5270 * Return Value: None
5272 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5275 /* blank external TXD output */
5276 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5278 /* Clock mode Control Register (CMCR)
5280 * <15..14> 00 counter 1 Disabled
5281 * <13..12> 00 counter 0 Disabled
5282 * <11..10> 11 BRG1 Input is TxC Pin
5283 * <9..8> 11 BRG0 Input is TxC Pin
5284 * <7..6> 01 DPLL Input is BRG1 Output
5285 * <5..3> 100 TxCLK comes from BRG0
5286 * <2..0> 100 RxCLK comes from BRG0
5288 * 0000 1111 0110 0100 = 0x0f64
5291 usc_OutReg( info
, CMCR
, 0x0f64 );
5293 /* Write 16-bit Time Constant for BRG0 */
5294 /* use clock speed if available, otherwise use 8 for diagnostics */
5295 if (info
->params
.clock_speed
) {
5296 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5297 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5299 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5301 usc_OutReg(info
, TC0R
, (u16
)8);
5303 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5304 mode = Continuous Set Bit 0 to enable BRG0. */
5305 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5307 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5308 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5310 /* set Internal Data loopback mode */
5311 info
->loopback_bits
= 0x300;
5312 outw( 0x0300, info
->io_base
+ CCAR
);
5314 /* enable external TXD output */
5315 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5317 /* clear Internal Data loopback mode */
5318 info
->loopback_bits
= 0;
5319 outw( 0,info
->io_base
+ CCAR
);
5322 } /* end of usc_enable_loopback() */
5324 /* usc_enable_aux_clock()
5326 * Enabled the AUX clock output at the specified frequency.
5330 * info pointer to device extension
5331 * data_rate data rate of clock in bits per second
5332 * A data rate of 0 disables the AUX clock.
5334 * Return Value: None
5336 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5342 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5343 XtalSpeed
= 11059200;
5345 XtalSpeed
= 14745600;
5348 /* Tc = (Xtal/Speed) - 1 */
5349 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5350 /* then rounding up gives a more precise time constant. Instead */
5351 /* of rounding up and then subtracting 1 we just don't subtract */
5352 /* the one in this case. */
5355 Tc
= (u16
)(XtalSpeed
/data_rate
);
5356 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5359 /* Write 16-bit Time Constant for BRG0 */
5360 usc_OutReg( info
, TC0R
, Tc
);
5363 * Hardware Configuration Register (HCR)
5364 * Clear Bit 1, BRG0 mode = Continuous
5365 * Set Bit 0 to enable BRG0.
5368 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5370 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5371 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5373 /* data rate == 0 so turn off BRG0 */
5374 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5377 } /* end of usc_enable_aux_clock() */
5381 * usc_process_rxoverrun_sync()
5383 * This function processes a receive overrun by resetting the
5384 * receive DMA buffers and issuing a Purge Rx FIFO command
5385 * to allow the receiver to continue receiving.
5389 * info pointer to device extension
5391 * Return Value: None
5393 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5397 int frame_start_index
;
5398 int start_of_frame_found
= FALSE
;
5399 int end_of_frame_found
= FALSE
;
5400 int reprogram_dma
= FALSE
;
5402 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5405 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5406 usc_RCmd( info
, RCmd_EnterHuntmode
);
5407 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5409 /* CurrentRxBuffer points to the 1st buffer of the next */
5410 /* possibly available receive frame. */
5412 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5414 /* Search for an unfinished string of buffers. This means */
5415 /* that a receive frame started (at least one buffer with */
5416 /* count set to zero) but there is no terminiting buffer */
5417 /* (status set to non-zero). */
5419 while( !buffer_list
[end_index
].count
)
5421 /* Count field has been reset to zero by 16C32. */
5422 /* This buffer is currently in use. */
5424 if ( !start_of_frame_found
)
5426 start_of_frame_found
= TRUE
;
5427 frame_start_index
= end_index
;
5428 end_of_frame_found
= FALSE
;
5431 if ( buffer_list
[end_index
].status
)
5433 /* Status field has been set by 16C32. */
5434 /* This is the last buffer of a received frame. */
5436 /* We want to leave the buffers for this frame intact. */
5437 /* Move on to next possible frame. */
5439 start_of_frame_found
= FALSE
;
5440 end_of_frame_found
= TRUE
;
5443 /* advance to next buffer entry in linked list */
5445 if ( end_index
== info
->rx_buffer_count
)
5448 if ( start_index
== end_index
)
5450 /* The entire list has been searched with all Counts == 0 and */
5451 /* all Status == 0. The receive buffers are */
5452 /* completely screwed, reset all receive buffers! */
5453 mgsl_reset_rx_dma_buffers( info
);
5454 frame_start_index
= 0;
5455 start_of_frame_found
= FALSE
;
5456 reprogram_dma
= TRUE
;
5461 if ( start_of_frame_found
&& !end_of_frame_found
)
5463 /* There is an unfinished string of receive DMA buffers */
5464 /* as a result of the receiver overrun. */
5466 /* Reset the buffers for the unfinished frame */
5467 /* and reprogram the receive DMA controller to start */
5468 /* at the 1st buffer of unfinished frame. */
5470 start_index
= frame_start_index
;
5474 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5476 /* Adjust index for wrap around. */
5477 if ( start_index
== info
->rx_buffer_count
)
5480 } while( start_index
!= end_index
);
5482 reprogram_dma
= TRUE
;
5485 if ( reprogram_dma
)
5487 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5488 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5489 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5491 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5493 /* This empties the receive FIFO and loads the RCC with RCLR */
5494 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5496 /* program 16C32 with physical address of 1st DMA buffer entry */
5497 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5498 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5499 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5501 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5502 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5503 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5505 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5506 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5508 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5509 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5510 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5511 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5512 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5514 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5518 /* This empties the receive FIFO and loads the RCC with RCLR */
5519 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5520 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5523 } /* end of usc_process_rxoverrun_sync() */
5525 /* usc_stop_receiver()
5527 * Disable USC receiver
5529 * Arguments: info pointer to device instance data
5530 * Return Value: None
5532 static void usc_stop_receiver( struct mgsl_struct
*info
)
5534 if (debug_level
>= DEBUG_LEVEL_ISR
)
5535 printk("%s(%d):usc_stop_receiver(%s)\n",
5536 __FILE__
,__LINE__
, info
->device_name
);
5538 /* Disable receive DMA channel. */
5539 /* This also disables receive DMA channel interrupts */
5540 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5542 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5543 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5544 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5546 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5548 /* This empties the receive FIFO and loads the RCC with RCLR */
5549 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5550 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5552 info
->rx_enabled
= 0;
5553 info
->rx_overflow
= 0;
5554 info
->rx_rcc_underrun
= 0;
5556 } /* end of stop_receiver() */
5558 /* usc_start_receiver()
5560 * Enable the USC receiver
5562 * Arguments: info pointer to device instance data
5563 * Return Value: None
5565 static void usc_start_receiver( struct mgsl_struct
*info
)
5569 if (debug_level
>= DEBUG_LEVEL_ISR
)
5570 printk("%s(%d):usc_start_receiver(%s)\n",
5571 __FILE__
,__LINE__
, info
->device_name
);
5573 mgsl_reset_rx_dma_buffers( info
);
5574 usc_stop_receiver( info
);
5576 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5577 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5579 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5580 info
->params
.mode
== MGSL_MODE_RAW
) {
5581 /* DMA mode Transfers */
5582 /* Program the DMA controller. */
5583 /* Enable the DMA controller end of buffer interrupt. */
5585 /* program 16C32 with physical address of 1st DMA buffer entry */
5586 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5587 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5588 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5590 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5591 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5592 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5594 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5595 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5597 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5598 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5599 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5600 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5601 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5603 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5605 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5606 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5607 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5609 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5610 usc_RCmd( info
, RCmd_EnterHuntmode
);
5612 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5615 usc_OutReg( info
, CCSR
, 0x1020 );
5617 info
->rx_enabled
= 1;
5619 } /* end of usc_start_receiver() */
5621 /* usc_start_transmitter()
5623 * Enable the USC transmitter and send a transmit frame if
5624 * one is loaded in the DMA buffers.
5626 * Arguments: info pointer to device instance data
5627 * Return Value: None
5629 static void usc_start_transmitter( struct mgsl_struct
*info
)
5632 unsigned int FrameSize
;
5634 if (debug_level
>= DEBUG_LEVEL_ISR
)
5635 printk("%s(%d):usc_start_transmitter(%s)\n",
5636 __FILE__
,__LINE__
, info
->device_name
);
5638 if ( info
->xmit_cnt
) {
5640 /* If auto RTS enabled and RTS is inactive, then assert */
5641 /* RTS and set a flag indicating that the driver should */
5642 /* negate RTS when the transmission completes. */
5644 info
->drop_rts_on_tx_done
= 0;
5646 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5647 usc_get_serial_signals( info
);
5648 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5649 info
->serial_signals
|= SerialSignal_RTS
;
5650 usc_set_serial_signals( info
);
5651 info
->drop_rts_on_tx_done
= 1;
5656 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5657 if ( !info
->tx_active
) {
5658 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5659 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5660 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5661 usc_load_txfifo(info
);
5664 /* Disable transmit DMA controller while programming. */
5665 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5667 /* Transmit DMA buffer is loaded, so program USC */
5668 /* to send the frame contained in the buffers. */
5670 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5672 /* if operating in Raw sync mode, reset the rcc component
5673 * of the tx dma buffer entry, otherwise, the serial controller
5674 * will send a closing sync char after this count.
5676 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5677 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5679 /* Program the Transmit Character Length Register (TCLR) */
5680 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5681 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5683 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5685 /* Program the address of the 1st DMA Buffer Entry in linked list */
5686 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5687 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5688 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5690 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5691 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5692 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5694 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5695 info
->num_tx_dma_buffers
> 1 ) {
5696 /* When running external sync mode, attempt to 'stream' transmit */
5697 /* by filling tx dma buffers as they become available. To do this */
5698 /* we need to enable Tx DMA EOB Status interrupts : */
5700 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5701 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5703 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5704 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5707 /* Initialize Transmit DMA Channel */
5708 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5710 usc_TCmd( info
, TCmd_SendFrame
);
5712 info
->tx_timer
.expires
= jiffies
+ msecs_to_jiffies(5000);
5713 add_timer(&info
->tx_timer
);
5715 info
->tx_active
= 1;
5718 if ( !info
->tx_enabled
) {
5719 info
->tx_enabled
= 1;
5720 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5721 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5723 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5726 } /* end of usc_start_transmitter() */
5728 /* usc_stop_transmitter()
5730 * Stops the transmitter and DMA
5732 * Arguments: info pointer to device isntance data
5733 * Return Value: None
5735 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5737 if (debug_level
>= DEBUG_LEVEL_ISR
)
5738 printk("%s(%d):usc_stop_transmitter(%s)\n",
5739 __FILE__
,__LINE__
, info
->device_name
);
5741 del_timer(&info
->tx_timer
);
5743 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5744 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5745 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5747 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5748 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5749 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5751 info
->tx_enabled
= 0;
5752 info
->tx_active
= 0;
5754 } /* end of usc_stop_transmitter() */
5756 /* usc_load_txfifo()
5758 * Fill the transmit FIFO until the FIFO is full or
5759 * there is no more data to load.
5761 * Arguments: info pointer to device extension (instance data)
5762 * Return Value: None
5764 static void usc_load_txfifo( struct mgsl_struct
*info
)
5769 if ( !info
->xmit_cnt
&& !info
->x_char
)
5772 /* Select transmit FIFO status readback in TICR */
5773 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5775 /* load the Transmit FIFO until FIFOs full or all data sent */
5777 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5778 /* there is more space in the transmit FIFO and */
5779 /* there is more data in transmit buffer */
5781 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5782 /* write a 16-bit word from transmit buffer to 16C32 */
5784 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5785 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5786 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5787 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5789 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5791 info
->xmit_cnt
-= 2;
5792 info
->icount
.tx
+= 2;
5794 /* only 1 byte left to transmit or 1 FIFO slot left */
5796 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5797 info
->io_base
+ CCAR
);
5800 /* transmit pending high priority char */
5801 outw( info
->x_char
,info
->io_base
+ CCAR
);
5804 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5805 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5812 } /* end of usc_load_txfifo() */
5816 * Reset the adapter to a known state and prepare it for further use.
5818 * Arguments: info pointer to device instance data
5819 * Return Value: None
5821 static void usc_reset( struct mgsl_struct
*info
)
5823 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5827 /* Set BIT30 of Misc Control Register */
5828 /* (Local Control Register 0x50) to force reset of USC. */
5830 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5831 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5833 info
->misc_ctrl_value
|= BIT30
;
5834 *MiscCtrl
= info
->misc_ctrl_value
;
5837 * Force at least 170ns delay before clearing
5838 * reset bit. Each read from LCR takes at least
5839 * 30ns so 10 times for 300ns to be safe.
5842 readval
= *MiscCtrl
;
5844 info
->misc_ctrl_value
&= ~BIT30
;
5845 *MiscCtrl
= info
->misc_ctrl_value
;
5847 *LCR0BRDR
= BUS_DESCRIPTOR(
5848 1, // Write Strobe Hold (0-3)
5849 2, // Write Strobe Delay (0-3)
5850 2, // Read Strobe Delay (0-3)
5851 0, // NWDD (Write data-data) (0-3)
5852 4, // NWAD (Write Addr-data) (0-31)
5853 0, // NXDA (Read/Write Data-Addr) (0-3)
5854 0, // NRDD (Read Data-Data) (0-3)
5855 5 // NRAD (Read Addr-Data) (0-31)
5859 outb( 0,info
->io_base
+ 8 );
5863 info
->loopback_bits
= 0;
5864 info
->usc_idle_mode
= 0;
5867 * Program the Bus Configuration Register (BCR)
5869 * <15> 0 Don't use separate address
5870 * <14..6> 0 reserved
5871 * <5..4> 00 IAckmode = Default, don't care
5872 * <3> 1 Bus Request Totem Pole output
5873 * <2> 1 Use 16 Bit data bus
5874 * <1> 0 IRQ Totem Pole output
5875 * <0> 0 Don't Shift Right Addr
5877 * 0000 0000 0000 1100 = 0x000c
5879 * By writing to io_base + SDPIN the Wait/Ack pin is
5880 * programmed to work as a Wait pin.
5883 outw( 0x000c,info
->io_base
+ SDPIN
);
5886 outw( 0,info
->io_base
);
5887 outw( 0,info
->io_base
+ CCAR
);
5889 /* select little endian byte ordering */
5890 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5893 /* Port Control Register (PCR)
5895 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5896 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5897 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5898 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5899 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5900 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5901 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5902 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5904 * 1111 0000 1111 0101 = 0xf0f5
5907 usc_OutReg( info
, PCR
, 0xf0f5 );
5911 * Input/Output Control Register
5913 * <15..14> 00 CTS is active low input
5914 * <13..12> 00 DCD is active low input
5915 * <11..10> 00 TxREQ pin is input (DSR)
5916 * <9..8> 00 RxREQ pin is input (RI)
5917 * <7..6> 00 TxD is output (Transmit Data)
5918 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5919 * <2..0> 100 RxC is Output (drive with BRG0)
5921 * 0000 0000 0000 0100 = 0x0004
5924 usc_OutReg( info
, IOCR
, 0x0004 );
5926 } /* end of usc_reset() */
5928 /* usc_set_async_mode()
5930 * Program adapter for asynchronous communications.
5932 * Arguments: info pointer to device instance data
5933 * Return Value: None
5935 static void usc_set_async_mode( struct mgsl_struct
*info
)
5939 /* disable interrupts while programming USC */
5940 usc_DisableMasterIrqBit( info
);
5942 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5943 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5945 usc_loopback_frame( info
);
5947 /* Channel mode Register (CMR)
5949 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5950 * <13..12> 00 00 = 16X Clock
5951 * <11..8> 0000 Transmitter mode = Asynchronous
5952 * <7..6> 00 reserved?
5953 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5954 * <3..0> 0000 Receiver mode = Asynchronous
5956 * 0000 0000 0000 0000 = 0x0
5960 if ( info
->params
.stop_bits
!= 1 )
5962 usc_OutReg( info
, CMR
, RegValue
);
5965 /* Receiver mode Register (RMR)
5967 * <15..13> 000 encoding = None
5968 * <12..08> 00000 reserved (Sync Only)
5969 * <7..6> 00 Even parity
5970 * <5> 0 parity disabled
5971 * <4..2> 000 Receive Char Length = 8 bits
5972 * <1..0> 00 Disable Receiver
5974 * 0000 0000 0000 0000 = 0x0
5979 if ( info
->params
.data_bits
!= 8 )
5980 RegValue
|= BIT4
+BIT3
+BIT2
;
5982 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5984 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5988 usc_OutReg( info
, RMR
, RegValue
);
5991 /* Set IRQ trigger level */
5993 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5996 /* Receive Interrupt Control Register (RICR)
5998 * <15..8> ? RxFIFO IRQ Request Level
6000 * Note: For async mode the receive FIFO level must be set
6001 * to 0 to avoid the situation where the FIFO contains fewer bytes
6002 * than the trigger level and no more data is expected.
6004 * <7> 0 Exited Hunt IA (Interrupt Arm)
6005 * <6> 0 Idle Received IA
6006 * <5> 0 Break/Abort IA
6008 * <3> 0 Queued status reflects oldest byte in FIFO
6010 * <1> 0 Rx Overrun IA
6011 * <0> 0 Select TC0 value for readback
6013 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6016 usc_OutReg( info
, RICR
, 0x0000 );
6018 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
6019 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
6022 /* Transmit mode Register (TMR)
6024 * <15..13> 000 encoding = None
6025 * <12..08> 00000 reserved (Sync Only)
6026 * <7..6> 00 Transmit parity Even
6027 * <5> 0 Transmit parity Disabled
6028 * <4..2> 000 Tx Char Length = 8 bits
6029 * <1..0> 00 Disable Transmitter
6031 * 0000 0000 0000 0000 = 0x0
6036 if ( info
->params
.data_bits
!= 8 )
6037 RegValue
|= BIT4
+BIT3
+BIT2
;
6039 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
6041 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
6045 usc_OutReg( info
, TMR
, RegValue
);
6047 usc_set_txidle( info
);
6050 /* Set IRQ trigger level */
6052 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
6055 /* Transmit Interrupt Control Register (TICR)
6057 * <15..8> ? Transmit FIFO IRQ Level
6058 * <7> 0 Present IA (Interrupt Arm)
6059 * <6> 1 Idle Sent IA
6060 * <5> 0 Abort Sent IA
6061 * <4> 0 EOF/EOM Sent IA
6063 * <2> 0 1 = Wait for SW Trigger to Start Frame
6064 * <1> 0 Tx Underrun IA
6065 * <0> 0 TC0 constant on read back
6067 * 0000 0000 0100 0000 = 0x0040
6070 usc_OutReg( info
, TICR
, 0x1f40 );
6072 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6073 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6075 usc_enable_async_clock( info
, info
->params
.data_rate
);
6078 /* Channel Control/status Register (CCSR)
6080 * <15> X RCC FIFO Overflow status (RO)
6081 * <14> X RCC FIFO Not Empty status (RO)
6082 * <13> 0 1 = Clear RCC FIFO (WO)
6083 * <12> X DPLL in Sync status (RO)
6084 * <11> X DPLL 2 Missed Clocks status (RO)
6085 * <10> X DPLL 1 Missed Clock status (RO)
6086 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6087 * <7> X SDLC Loop On status (RO)
6088 * <6> X SDLC Loop Send status (RO)
6089 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6090 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6091 * <1..0> 00 reserved
6093 * 0000 0000 0010 0000 = 0x0020
6096 usc_OutReg( info
, CCSR
, 0x0020 );
6098 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6099 RECEIVE_DATA
+ RECEIVE_STATUS
);
6101 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6102 RECEIVE_DATA
+ RECEIVE_STATUS
);
6104 usc_EnableMasterIrqBit( info
);
6106 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6107 /* Enable INTEN (Port 6, Bit12) */
6108 /* This connects the IRQ request signal to the ISA bus */
6109 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6112 if (info
->params
.loopback
) {
6113 info
->loopback_bits
= 0x300;
6114 outw(0x0300, info
->io_base
+ CCAR
);
6117 } /* end of usc_set_async_mode() */
6119 /* usc_loopback_frame()
6121 * Loop back a small (2 byte) dummy SDLC frame.
6122 * Interrupts and DMA are NOT used. The purpose of this is to
6123 * clear any 'stale' status info left over from running in async mode.
6125 * The 16C32 shows the strange behaviour of marking the 1st
6126 * received SDLC frame with a CRC error even when there is no
6127 * CRC error. To get around this a small dummy from of 2 bytes
6128 * is looped back when switching from async to sync mode.
6130 * Arguments: info pointer to device instance data
6131 * Return Value: None
6133 static void usc_loopback_frame( struct mgsl_struct
*info
)
6136 unsigned long oldmode
= info
->params
.mode
;
6138 info
->params
.mode
= MGSL_MODE_HDLC
;
6140 usc_DisableMasterIrqBit( info
);
6142 usc_set_sdlc_mode( info
);
6143 usc_enable_loopback( info
, 1 );
6145 /* Write 16-bit Time Constant for BRG0 */
6146 usc_OutReg( info
, TC0R
, 0 );
6148 /* Channel Control Register (CCR)
6150 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6151 * <13> 0 Trigger Tx on SW Command Disabled
6152 * <12> 0 Flag Preamble Disabled
6153 * <11..10> 00 Preamble Length = 8-Bits
6154 * <9..8> 01 Preamble Pattern = flags
6155 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6156 * <5> 0 Trigger Rx on SW Command Disabled
6159 * 0000 0001 0000 0000 = 0x0100
6162 usc_OutReg( info
, CCR
, 0x0100 );
6164 /* SETUP RECEIVER */
6165 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6166 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6168 /* SETUP TRANSMITTER */
6169 /* Program the Transmit Character Length Register (TCLR) */
6170 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6171 usc_OutReg( info
, TCLR
, 2 );
6172 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6174 /* unlatch Tx status bits, and start transmit channel. */
6175 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6176 outw(0,info
->io_base
+ DATAREG
);
6178 /* ENABLE TRANSMITTER */
6179 usc_TCmd( info
, TCmd_SendFrame
);
6180 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6182 /* WAIT FOR RECEIVE COMPLETE */
6183 for (i
=0 ; i
<1000 ; i
++)
6184 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6187 /* clear Internal Data loopback mode */
6188 usc_enable_loopback(info
, 0);
6190 usc_EnableMasterIrqBit(info
);
6192 info
->params
.mode
= oldmode
;
6194 } /* end of usc_loopback_frame() */
6196 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6198 * Arguments: info pointer to adapter info structure
6199 * Return Value: None
6201 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6203 usc_loopback_frame( info
);
6204 usc_set_sdlc_mode( info
);
6206 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6207 /* Enable INTEN (Port 6, Bit12) */
6208 /* This connects the IRQ request signal to the ISA bus */
6209 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6212 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6214 if (info
->params
.loopback
)
6215 usc_enable_loopback(info
,1);
6217 } /* end of mgsl_set_sync_mode() */
6219 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6221 * Arguments: info pointer to device instance data
6222 * Return Value: None
6224 static void usc_set_txidle( struct mgsl_struct
*info
)
6226 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6228 /* Map API idle mode to USC register bits */
6230 switch( info
->idle_mode
){
6231 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6232 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6233 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6234 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6235 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6236 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6237 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6240 info
->usc_idle_mode
= usc_idle_mode
;
6241 //usc_OutReg(info, TCSR, usc_idle_mode);
6242 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6243 info
->tcsr_value
+= usc_idle_mode
;
6244 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6247 * if SyncLink WAN adapter is running in external sync mode, the
6248 * transmitter has been set to Monosync in order to try to mimic
6249 * a true raw outbound bit stream. Monosync still sends an open/close
6250 * sync char at the start/end of a frame. Try to match those sync
6251 * patterns to the idle mode set here
6253 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6254 unsigned char syncpat
= 0;
6255 switch( info
->idle_mode
) {
6256 case HDLC_TXIDLE_FLAGS
:
6259 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6262 case HDLC_TXIDLE_ZEROS
:
6263 case HDLC_TXIDLE_SPACE
:
6266 case HDLC_TXIDLE_ONES
:
6267 case HDLC_TXIDLE_MARK
:
6270 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6275 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6278 } /* end of usc_set_txidle() */
6280 /* usc_get_serial_signals()
6282 * Query the adapter for the state of the V24 status (input) signals.
6284 * Arguments: info pointer to device instance data
6285 * Return Value: None
6287 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6291 /* clear all serial signals except DTR and RTS */
6292 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6294 /* Read the Misc Interrupt status Register (MISR) to get */
6295 /* the V24 status signals. */
6297 status
= usc_InReg( info
, MISR
);
6299 /* set serial signal bits to reflect MISR */
6301 if ( status
& MISCSTATUS_CTS
)
6302 info
->serial_signals
|= SerialSignal_CTS
;
6304 if ( status
& MISCSTATUS_DCD
)
6305 info
->serial_signals
|= SerialSignal_DCD
;
6307 if ( status
& MISCSTATUS_RI
)
6308 info
->serial_signals
|= SerialSignal_RI
;
6310 if ( status
& MISCSTATUS_DSR
)
6311 info
->serial_signals
|= SerialSignal_DSR
;
6313 } /* end of usc_get_serial_signals() */
6315 /* usc_set_serial_signals()
6317 * Set the state of DTR and RTS based on contents of
6318 * serial_signals member of device extension.
6320 * Arguments: info pointer to device instance data
6321 * Return Value: None
6323 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6326 unsigned char V24Out
= info
->serial_signals
;
6328 /* get the current value of the Port Control Register (PCR) */
6330 Control
= usc_InReg( info
, PCR
);
6332 if ( V24Out
& SerialSignal_RTS
)
6337 if ( V24Out
& SerialSignal_DTR
)
6342 usc_OutReg( info
, PCR
, Control
);
6344 } /* end of usc_set_serial_signals() */
6346 /* usc_enable_async_clock()
6348 * Enable the async clock at the specified frequency.
6350 * Arguments: info pointer to device instance data
6351 * data_rate data rate of clock in bps
6352 * 0 disables the AUX clock.
6353 * Return Value: None
6355 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6359 * Clock mode Control Register (CMCR)
6361 * <15..14> 00 counter 1 Disabled
6362 * <13..12> 00 counter 0 Disabled
6363 * <11..10> 11 BRG1 Input is TxC Pin
6364 * <9..8> 11 BRG0 Input is TxC Pin
6365 * <7..6> 01 DPLL Input is BRG1 Output
6366 * <5..3> 100 TxCLK comes from BRG0
6367 * <2..0> 100 RxCLK comes from BRG0
6369 * 0000 1111 0110 0100 = 0x0f64
6372 usc_OutReg( info
, CMCR
, 0x0f64 );
6376 * Write 16-bit Time Constant for BRG0
6377 * Time Constant = (ClkSpeed / data_rate) - 1
6378 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6381 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6382 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6384 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6388 * Hardware Configuration Register (HCR)
6389 * Clear Bit 1, BRG0 mode = Continuous
6390 * Set Bit 0 to enable BRG0.
6393 usc_OutReg( info
, HCR
,
6394 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6397 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6399 usc_OutReg( info
, IOCR
,
6400 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6402 /* data rate == 0 so turn off BRG0 */
6403 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6406 } /* end of usc_enable_async_clock() */
6409 * Buffer Structures:
6411 * Normal memory access uses virtual addresses that can make discontiguous
6412 * physical memory pages appear to be contiguous in the virtual address
6413 * space (the processors memory mapping handles the conversions).
6415 * DMA transfers require physically contiguous memory. This is because
6416 * the DMA system controller and DMA bus masters deal with memory using
6417 * only physical addresses.
6419 * This causes a problem under Windows NT when large DMA buffers are
6420 * needed. Fragmentation of the nonpaged pool prevents allocations of
6421 * physically contiguous buffers larger than the PAGE_SIZE.
6423 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6424 * allows DMA transfers to physically discontiguous buffers. Information
6425 * about each data transfer buffer is contained in a memory structure
6426 * called a 'buffer entry'. A list of buffer entries is maintained
6427 * to track and control the use of the data transfer buffers.
6429 * To support this strategy we will allocate sufficient PAGE_SIZE
6430 * contiguous memory buffers to allow for the total required buffer
6433 * The 16C32 accesses the list of buffer entries using Bus Master
6434 * DMA. Control information is read from the buffer entries by the
6435 * 16C32 to control data transfers. status information is written to
6436 * the buffer entries by the 16C32 to indicate the status of completed
6439 * The CPU writes control information to the buffer entries to control
6440 * the 16C32 and reads status information from the buffer entries to
6441 * determine information about received and transmitted frames.
6443 * Because the CPU and 16C32 (adapter) both need simultaneous access
6444 * to the buffer entries, the buffer entry memory is allocated with
6445 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6446 * entry list to PAGE_SIZE.
6448 * The actual data buffers on the other hand will only be accessed
6449 * by the CPU or the adapter but not by both simultaneously. This allows
6450 * Scatter/Gather packet based DMA procedures for using physically
6451 * discontiguous pages.
6455 * mgsl_reset_tx_dma_buffers()
6457 * Set the count for all transmit buffers to 0 to indicate the
6458 * buffer is available for use and set the current buffer to the
6459 * first buffer. This effectively makes all buffers free and
6460 * discards any data in buffers.
6462 * Arguments: info pointer to device instance data
6463 * Return Value: None
6465 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6469 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6470 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6473 info
->current_tx_buffer
= 0;
6474 info
->start_tx_dma_buffer
= 0;
6475 info
->tx_dma_buffers_used
= 0;
6477 info
->get_tx_holding_index
= 0;
6478 info
->put_tx_holding_index
= 0;
6479 info
->tx_holding_count
= 0;
6481 } /* end of mgsl_reset_tx_dma_buffers() */
6484 * num_free_tx_dma_buffers()
6486 * returns the number of free tx dma buffers available
6488 * Arguments: info pointer to device instance data
6489 * Return Value: number of free tx dma buffers
6491 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6493 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6497 * mgsl_reset_rx_dma_buffers()
6499 * Set the count for all receive buffers to DMABUFFERSIZE
6500 * and set the current buffer to the first buffer. This effectively
6501 * makes all buffers free and discards any data in buffers.
6503 * Arguments: info pointer to device instance data
6504 * Return Value: None
6506 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6510 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6511 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6512 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6513 // info->rx_buffer_list[i].status = 0;
6516 info
->current_rx_buffer
= 0;
6518 } /* end of mgsl_reset_rx_dma_buffers() */
6521 * mgsl_free_rx_frame_buffers()
6523 * Free the receive buffers used by a received SDLC
6524 * frame such that the buffers can be reused.
6528 * info pointer to device instance data
6529 * StartIndex index of 1st receive buffer of frame
6530 * EndIndex index of last receive buffer of frame
6532 * Return Value: None
6534 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6537 DMABUFFERENTRY
*pBufEntry
;
6540 /* Starting with 1st buffer entry of the frame clear the status */
6541 /* field and set the count field to DMA Buffer Size. */
6546 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6548 if ( Index
== EndIndex
) {
6549 /* This is the last buffer of the frame! */
6553 /* reset current buffer for reuse */
6554 // pBufEntry->status = 0;
6555 // pBufEntry->count = DMABUFFERSIZE;
6556 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6558 /* advance to next buffer entry in linked list */
6560 if ( Index
== info
->rx_buffer_count
)
6564 /* set current buffer to next buffer after last buffer of frame */
6565 info
->current_rx_buffer
= Index
;
6567 } /* end of free_rx_frame_buffers() */
6569 /* mgsl_get_rx_frame()
6571 * This function attempts to return a received SDLC frame from the
6572 * receive DMA buffers. Only frames received without errors are returned.
6574 * Arguments: info pointer to device extension
6575 * Return Value: 1 if frame returned, otherwise 0
6577 static int mgsl_get_rx_frame(struct mgsl_struct
*info
)
6579 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6580 unsigned short status
;
6581 DMABUFFERENTRY
*pBufEntry
;
6582 unsigned int framesize
= 0;
6584 unsigned long flags
;
6585 struct tty_struct
*tty
= info
->tty
;
6586 int return_frame
= 0;
6589 * current_rx_buffer points to the 1st buffer of the next available
6590 * receive frame. To find the last buffer of the frame look for
6591 * a non-zero status field in the buffer entries. (The status
6592 * field is set by the 16C32 after completing a receive frame.
6595 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6597 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6599 * If the count field of the buffer entry is non-zero then
6600 * this buffer has not been used. (The 16C32 clears the count
6601 * field when it starts using the buffer.) If an unused buffer
6602 * is encountered then there are no frames available.
6605 if ( info
->rx_buffer_list
[EndIndex
].count
)
6608 /* advance to next buffer entry in linked list */
6610 if ( EndIndex
== info
->rx_buffer_count
)
6613 /* if entire list searched then no frame available */
6614 if ( EndIndex
== StartIndex
) {
6615 /* If this occurs then something bad happened,
6616 * all buffers have been 'used' but none mark
6617 * the end of a frame. Reset buffers and receiver.
6620 if ( info
->rx_enabled
){
6621 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6622 usc_start_receiver(info
);
6623 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6630 /* check status of receive frame */
6632 status
= info
->rx_buffer_list
[EndIndex
].status
;
6634 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6635 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6636 if ( status
& RXSTATUS_SHORT_FRAME
)
6637 info
->icount
.rxshort
++;
6638 else if ( status
& RXSTATUS_ABORT
)
6639 info
->icount
.rxabort
++;
6640 else if ( status
& RXSTATUS_OVERRUN
)
6641 info
->icount
.rxover
++;
6643 info
->icount
.rxcrc
++;
6644 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6650 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
6652 stats
->rx_frame_errors
++;
6658 if ( return_frame
) {
6659 /* receive frame has no errors, get frame size.
6660 * The frame size is the starting value of the RCC (which was
6661 * set to 0xffff) minus the ending value of the RCC (decremented
6662 * once for each receive character) minus 2 for the 16-bit CRC.
6665 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6667 /* adjust frame size for CRC if any */
6668 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6670 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6674 if ( debug_level
>= DEBUG_LEVEL_BH
)
6675 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6676 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6678 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6679 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6680 min_t(int, framesize
, DMABUFFERSIZE
),0);
6683 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6684 ((framesize
+1) > info
->max_frame_size
) ) ||
6685 (framesize
> info
->max_frame_size
) )
6686 info
->icount
.rxlong
++;
6688 /* copy dma buffer(s) to contiguous intermediate buffer */
6689 int copy_count
= framesize
;
6690 int index
= StartIndex
;
6691 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6693 if ( !(status
& RXSTATUS_CRC_ERROR
))
6694 info
->icount
.rxok
++;
6698 if ( copy_count
> DMABUFFERSIZE
)
6699 partial_count
= DMABUFFERSIZE
;
6701 partial_count
= copy_count
;
6703 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6704 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6705 ptmp
+= partial_count
;
6706 copy_count
-= partial_count
;
6708 if ( ++index
== info
->rx_buffer_count
)
6712 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6714 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6718 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6719 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6720 __FILE__
,__LINE__
,info
->device_name
,
6726 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6729 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6732 /* Free the buffers used by this frame. */
6733 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6739 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6740 /* The receiver needs to restarted because of
6741 * a receive overflow (buffer or FIFO). If the
6742 * receive buffers are now empty, then restart receiver.
6745 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6746 info
->rx_buffer_list
[EndIndex
].count
) {
6747 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6748 usc_start_receiver(info
);
6749 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6755 } /* end of mgsl_get_rx_frame() */
6757 /* mgsl_get_raw_rx_frame()
6759 * This function attempts to return a received frame from the
6760 * receive DMA buffers when running in external loop mode. In this mode,
6761 * we will return at most one DMABUFFERSIZE frame to the application.
6762 * The USC receiver is triggering off of DCD going active to start a new
6763 * frame, and DCD going inactive to terminate the frame (similar to
6764 * processing a closing flag character).
6766 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6767 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6768 * status field and the RCC field will indicate the length of the
6769 * entire received frame. We take this RCC field and get the modulus
6770 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6771 * last Rx DMA buffer and return that last portion of the frame.
6773 * Arguments: info pointer to device extension
6774 * Return Value: 1 if frame returned, otherwise 0
6776 static int mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6778 unsigned int CurrentIndex
, NextIndex
;
6779 unsigned short status
;
6780 DMABUFFERENTRY
*pBufEntry
;
6781 unsigned int framesize
= 0;
6783 unsigned long flags
;
6784 struct tty_struct
*tty
= info
->tty
;
6787 * current_rx_buffer points to the 1st buffer of the next available
6788 * receive frame. The status field is set by the 16C32 after
6789 * completing a receive frame. If the status field of this buffer
6790 * is zero, either the USC is still filling this buffer or this
6791 * is one of a series of buffers making up a received frame.
6793 * If the count field of this buffer is zero, the USC is either
6794 * using this buffer or has used this buffer. Look at the count
6795 * field of the next buffer. If that next buffer's count is
6796 * non-zero, the USC is still actively using the current buffer.
6797 * Otherwise, if the next buffer's count field is zero, the
6798 * current buffer is complete and the USC is using the next
6801 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6803 if ( NextIndex
== info
->rx_buffer_count
)
6806 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6807 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6808 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6810 * Either the status field of this dma buffer is non-zero
6811 * (indicating the last buffer of a receive frame) or the next
6812 * buffer is marked as in use -- implying this buffer is complete
6813 * and an intermediate buffer for this received frame.
6816 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6818 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6819 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6820 if ( status
& RXSTATUS_SHORT_FRAME
)
6821 info
->icount
.rxshort
++;
6822 else if ( status
& RXSTATUS_ABORT
)
6823 info
->icount
.rxabort
++;
6824 else if ( status
& RXSTATUS_OVERRUN
)
6825 info
->icount
.rxover
++;
6827 info
->icount
.rxcrc
++;
6831 * A receive frame is available, get frame size and status.
6833 * The frame size is the starting value of the RCC (which was
6834 * set to 0xffff) minus the ending value of the RCC (decremented
6835 * once for each receive character) minus 2 or 4 for the 16-bit
6838 * If the status field is zero, this is an intermediate buffer.
6841 * If the DMA Buffer Entry's Status field is non-zero, the
6842 * receive operation completed normally (ie: DCD dropped). The
6843 * RCC field is valid and holds the received frame size.
6844 * It is possible that the RCC field will be zero on a DMA buffer
6845 * entry with a non-zero status. This can occur if the total
6846 * frame size (number of bytes between the time DCD goes active
6847 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6848 * case the 16C32 has underrun on the RCC count and appears to
6849 * stop updating this counter to let us know the actual received
6850 * frame size. If this happens (non-zero status and zero RCC),
6851 * simply return the entire RxDMA Buffer
6855 * In the event that the final RxDMA Buffer is
6856 * terminated with a non-zero status and the RCC
6857 * field is zero, we interpret this as the RCC
6858 * having underflowed (received frame > 65535 bytes).
6860 * Signal the event to the user by passing back
6861 * a status of RxStatus_CrcError returning the full
6862 * buffer and let the app figure out what data is
6865 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6866 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6868 framesize
= DMABUFFERSIZE
;
6871 framesize
= DMABUFFERSIZE
;
6874 if ( framesize
> DMABUFFERSIZE
) {
6876 * if running in raw sync mode, ISR handler for
6877 * End Of Buffer events terminates all buffers at 4K.
6878 * If this frame size is said to be >4K, get the
6879 * actual number of bytes of the frame in this buffer.
6881 framesize
= framesize
% DMABUFFERSIZE
;
6885 if ( debug_level
>= DEBUG_LEVEL_BH
)
6886 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6887 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6889 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6890 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6891 min_t(int, framesize
, DMABUFFERSIZE
),0);
6894 /* copy dma buffer(s) to contiguous intermediate buffer */
6895 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6897 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6898 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6899 info
->icount
.rxok
++;
6901 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6904 /* Free the buffers used by this frame. */
6905 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6911 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6912 /* The receiver needs to restarted because of
6913 * a receive overflow (buffer or FIFO). If the
6914 * receive buffers are now empty, then restart receiver.
6917 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6918 info
->rx_buffer_list
[CurrentIndex
].count
) {
6919 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6920 usc_start_receiver(info
);
6921 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6927 } /* end of mgsl_get_raw_rx_frame() */
6929 /* mgsl_load_tx_dma_buffer()
6931 * Load the transmit DMA buffer with the specified data.
6935 * info pointer to device extension
6936 * Buffer pointer to buffer containing frame to load
6937 * BufferSize size in bytes of frame in Buffer
6939 * Return Value: None
6941 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6942 const char *Buffer
, unsigned int BufferSize
)
6944 unsigned short Copycount
;
6946 DMABUFFERENTRY
*pBufEntry
;
6948 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6949 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6951 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6952 /* set CMR:13 to start transmit when
6953 * next GoAhead (abort) is received
6955 info
->cmr_value
|= BIT13
;
6958 /* begin loading the frame in the next available tx dma
6959 * buffer, remember it's starting location for setting
6960 * up tx dma operation
6962 i
= info
->current_tx_buffer
;
6963 info
->start_tx_dma_buffer
= i
;
6965 /* Setup the status and RCC (Frame Size) fields of the 1st */
6966 /* buffer entry in the transmit DMA buffer list. */
6968 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6969 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6970 info
->tx_buffer_list
[i
].count
= BufferSize
;
6972 /* Copy frame data from 1st source buffer to the DMA buffers. */
6973 /* The frame data may span multiple DMA buffers. */
6975 while( BufferSize
){
6976 /* Get a pointer to next DMA buffer entry. */
6977 pBufEntry
= &info
->tx_buffer_list
[i
++];
6979 if ( i
== info
->tx_buffer_count
)
6982 /* Calculate the number of bytes that can be copied from */
6983 /* the source buffer to this DMA buffer. */
6984 if ( BufferSize
> DMABUFFERSIZE
)
6985 Copycount
= DMABUFFERSIZE
;
6987 Copycount
= BufferSize
;
6989 /* Actually copy data from source buffer to DMA buffer. */
6990 /* Also set the data count for this individual DMA buffer. */
6991 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6992 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6994 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6996 pBufEntry
->count
= Copycount
;
6998 /* Advance source pointer and reduce remaining data count. */
6999 Buffer
+= Copycount
;
7000 BufferSize
-= Copycount
;
7002 ++info
->tx_dma_buffers_used
;
7005 /* remember next available tx dma buffer */
7006 info
->current_tx_buffer
= i
;
7008 } /* end of mgsl_load_tx_dma_buffer() */
7011 * mgsl_register_test()
7013 * Performs a register test of the 16C32.
7015 * Arguments: info pointer to device instance data
7016 * Return Value: TRUE if test passed, otherwise FALSE
7018 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
)
7020 static unsigned short BitPatterns
[] =
7021 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7022 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
7025 unsigned long flags
;
7027 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7030 /* Verify the reset state of some registers. */
7032 if ( (usc_InReg( info
, SICR
) != 0) ||
7033 (usc_InReg( info
, IVR
) != 0) ||
7034 (usc_InDmaReg( info
, DIVR
) != 0) ){
7039 /* Write bit patterns to various registers but do it out of */
7040 /* sync, then read back and verify values. */
7042 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7043 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
7044 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
7045 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
7046 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
7047 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
7048 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
7050 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
7051 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
7052 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
7053 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
7054 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
7055 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
7063 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7067 } /* end of mgsl_register_test() */
7069 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7071 * Arguments: info pointer to device instance data
7072 * Return Value: TRUE if test passed, otherwise FALSE
7074 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
)
7076 unsigned long EndTime
;
7077 unsigned long flags
;
7079 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7083 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7084 * The ISR sets irq_occurred to 1.
7087 info
->irq_occurred
= FALSE
;
7089 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7090 /* Enable INTEN (Port 6, Bit12) */
7091 /* This connects the IRQ request signal to the ISA bus */
7092 /* on the ISA adapter. This has no effect for the PCI adapter */
7093 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7095 usc_EnableMasterIrqBit(info
);
7096 usc_EnableInterrupts(info
, IO_PIN
);
7097 usc_ClearIrqPendingBits(info
, IO_PIN
);
7099 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7100 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7102 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7105 while( EndTime
-- && !info
->irq_occurred
) {
7106 msleep_interruptible(10);
7109 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7111 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7113 if ( !info
->irq_occurred
)
7118 } /* end of mgsl_irq_test() */
7122 * Perform a DMA test of the 16C32. A small frame is
7123 * transmitted via DMA from a transmit buffer to a receive buffer
7124 * using single buffer DMA mode.
7126 * Arguments: info pointer to device instance data
7127 * Return Value: TRUE if test passed, otherwise FALSE
7129 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
)
7131 unsigned short FifoLevel
;
7132 unsigned long phys_addr
;
7133 unsigned int FrameSize
;
7137 unsigned short status
=0;
7138 unsigned long EndTime
;
7139 unsigned long flags
;
7140 MGSL_PARAMS tmp_params
;
7142 /* save current port options */
7143 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7144 /* load default port options */
7145 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7147 #define TESTFRAMESIZE 40
7149 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7151 /* setup 16C32 for SDLC DMA transfer mode */
7154 usc_set_sdlc_mode(info
);
7155 usc_enable_loopback(info
,1);
7157 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7158 * field of the buffer entry after fetching buffer address. This
7159 * way we can detect a DMA failure for a DMA read (which should be
7160 * non-destructive to system memory) before we try and write to
7161 * memory (where a failure could corrupt system memory).
7164 /* Receive DMA mode Register (RDMR)
7166 * <15..14> 11 DMA mode = Linked List Buffer mode
7167 * <13> 1 RSBinA/L = store Rx status Block in List entry
7168 * <12> 0 1 = Clear count of List Entry after fetching
7169 * <11..10> 00 Address mode = Increment
7170 * <9> 1 Terminate Buffer on RxBound
7171 * <8> 0 Bus Width = 16bits
7172 * <7..0> ? status Bits (write as 0s)
7174 * 1110 0010 0000 0000 = 0xe200
7177 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7179 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7182 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7184 FrameSize
= TESTFRAMESIZE
;
7186 /* setup 1st transmit buffer entry: */
7187 /* with frame size and transmit control word */
7189 info
->tx_buffer_list
[0].count
= FrameSize
;
7190 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7191 info
->tx_buffer_list
[0].status
= 0x4000;
7193 /* build a transmit frame in 1st transmit DMA buffer */
7195 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7196 for (i
= 0; i
< FrameSize
; i
++ )
7199 /* setup 1st receive buffer entry: */
7200 /* clear status, set max receive buffer size */
7202 info
->rx_buffer_list
[0].status
= 0;
7203 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7205 /* zero out the 1st receive buffer */
7207 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7209 /* Set count field of next buffer entries to prevent */
7210 /* 16C32 from using buffers after the 1st one. */
7212 info
->tx_buffer_list
[1].count
= 0;
7213 info
->rx_buffer_list
[1].count
= 0;
7216 /***************************/
7217 /* Program 16C32 receiver. */
7218 /***************************/
7220 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7222 /* setup DMA transfers */
7223 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7225 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7226 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7227 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7228 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7230 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7231 usc_InDmaReg( info
, RDMR
);
7232 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7234 /* Enable Receiver (RMR <1..0> = 10) */
7235 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7237 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7240 /*************************************************************/
7241 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7242 /*************************************************************/
7244 /* Wait 100ms for interrupt. */
7245 EndTime
= jiffies
+ msecs_to_jiffies(100);
7248 if (time_after(jiffies
, EndTime
)) {
7253 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7254 status
= usc_InDmaReg( info
, RDMR
);
7255 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7257 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7258 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7259 /* BUSY (BIT 5) is active (channel still active). */
7260 /* This means the buffer entry read has completed. */
7266 /******************************/
7267 /* Program 16C32 transmitter. */
7268 /******************************/
7270 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7272 /* Program the Transmit Character Length Register (TCLR) */
7273 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7275 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7276 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7278 /* Program the address of the 1st DMA Buffer Entry in linked list */
7280 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7281 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7282 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7284 /* unlatch Tx status bits, and start transmit channel. */
7286 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7287 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7289 /* wait for DMA controller to fill transmit FIFO */
7291 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7293 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7296 /**********************************/
7297 /* WAIT FOR TRANSMIT FIFO TO FILL */
7298 /**********************************/
7301 EndTime
= jiffies
+ msecs_to_jiffies(100);
7304 if (time_after(jiffies
, EndTime
)) {
7309 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7310 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7311 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7313 if ( FifoLevel
< 16 )
7316 if ( FrameSize
< 32 ) {
7317 /* This frame is smaller than the entire transmit FIFO */
7318 /* so wait for the entire frame to be loaded. */
7319 if ( FifoLevel
<= (32 - FrameSize
) )
7327 /* Enable 16C32 transmitter. */
7329 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7331 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7332 usc_TCmd( info
, TCmd_SendFrame
);
7333 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7335 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7338 /******************************/
7339 /* WAIT FOR TRANSMIT COMPLETE */
7340 /******************************/
7343 EndTime
= jiffies
+ msecs_to_jiffies(100);
7345 /* While timer not expired wait for transmit complete */
7347 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7348 status
= usc_InReg( info
, TCSR
);
7349 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7351 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7352 if (time_after(jiffies
, EndTime
)) {
7357 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7358 status
= usc_InReg( info
, TCSR
);
7359 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7365 /* CHECK FOR TRANSMIT ERRORS */
7366 if ( status
& (BIT5
+ BIT1
) )
7371 /* WAIT FOR RECEIVE COMPLETE */
7374 EndTime
= jiffies
+ msecs_to_jiffies(100);
7376 /* Wait for 16C32 to write receive status to buffer entry. */
7377 status
=info
->rx_buffer_list
[0].status
;
7378 while ( status
== 0 ) {
7379 if (time_after(jiffies
, EndTime
)) {
7383 status
=info
->rx_buffer_list
[0].status
;
7389 /* CHECK FOR RECEIVE ERRORS */
7390 status
= info
->rx_buffer_list
[0].status
;
7392 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7393 /* receive error has occurred */
7396 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7397 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7403 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7405 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7407 /* restore current port options */
7408 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7412 } /* end of mgsl_dma_test() */
7414 /* mgsl_adapter_test()
7416 * Perform the register, IRQ, and DMA tests for the 16C32.
7418 * Arguments: info pointer to device instance data
7419 * Return Value: 0 if success, otherwise -ENODEV
7421 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7423 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7424 printk( "%s(%d):Testing device %s\n",
7425 __FILE__
,__LINE__
,info
->device_name
);
7427 if ( !mgsl_register_test( info
) ) {
7428 info
->init_error
= DiagStatus_AddressFailure
;
7429 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7430 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7434 if ( !mgsl_irq_test( info
) ) {
7435 info
->init_error
= DiagStatus_IrqFailure
;
7436 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7437 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7441 if ( !mgsl_dma_test( info
) ) {
7442 info
->init_error
= DiagStatus_DmaFailure
;
7443 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7444 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7448 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7449 printk( "%s(%d):device %s passed diagnostics\n",
7450 __FILE__
,__LINE__
,info
->device_name
);
7454 } /* end of mgsl_adapter_test() */
7456 /* mgsl_memory_test()
7458 * Test the shared memory on a PCI adapter.
7460 * Arguments: info pointer to device instance data
7461 * Return Value: TRUE if test passed, otherwise FALSE
7463 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
)
7465 static unsigned long BitPatterns
[] =
7466 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7467 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7469 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7470 unsigned long * TestAddr
;
7472 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7475 TestAddr
= (unsigned long *)info
->memory_base
;
7477 /* Test data lines with test pattern at one location. */
7479 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7480 *TestAddr
= BitPatterns
[i
];
7481 if ( *TestAddr
!= BitPatterns
[i
] )
7485 /* Test address lines with incrementing pattern over */
7486 /* entire address range. */
7488 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7493 TestAddr
= (unsigned long *)info
->memory_base
;
7495 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7496 if ( *TestAddr
!= i
* 4 )
7501 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7505 } /* End Of mgsl_memory_test() */
7508 /* mgsl_load_pci_memory()
7510 * Load a large block of data into the PCI shared memory.
7511 * Use this instead of memcpy() or memmove() to move data
7512 * into the PCI shared memory.
7516 * This function prevents the PCI9050 interface chip from hogging
7517 * the adapter local bus, which can starve the 16C32 by preventing
7518 * 16C32 bus master cycles.
7520 * The PCI9050 documentation says that the 9050 will always release
7521 * control of the local bus after completing the current read
7522 * or write operation.
7524 * It appears that as long as the PCI9050 write FIFO is full, the
7525 * PCI9050 treats all of the writes as a single burst transaction
7526 * and will not release the bus. This causes DMA latency problems
7527 * at high speeds when copying large data blocks to the shared
7530 * This function in effect, breaks the a large shared memory write
7531 * into multiple transations by interleaving a shared memory read
7532 * which will flush the write FIFO and 'complete' the write
7533 * transation. This allows any pending DMA request to gain control
7534 * of the local bus in a timely fasion.
7538 * TargetPtr pointer to target address in PCI shared memory
7539 * SourcePtr pointer to source buffer for data
7540 * count count in bytes of data to copy
7542 * Return Value: None
7544 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7545 unsigned short count
)
7547 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7548 #define PCI_LOAD_INTERVAL 64
7550 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7551 unsigned short Index
;
7552 unsigned long Dummy
;
7554 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7556 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7557 Dummy
= *((volatile unsigned long *)TargetPtr
);
7558 TargetPtr
+= PCI_LOAD_INTERVAL
;
7559 SourcePtr
+= PCI_LOAD_INTERVAL
;
7562 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7564 } /* End Of mgsl_load_pci_memory() */
7566 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7571 printk("%s tx data:\n",info
->device_name
);
7573 printk("%s rx data:\n",info
->device_name
);
7581 for(i
=0;i
<linecount
;i
++)
7582 printk("%02X ",(unsigned char)data
[i
]);
7585 for(i
=0;i
<linecount
;i
++) {
7586 if (data
[i
]>=040 && data
[i
]<=0176)
7587 printk("%c",data
[i
]);
7596 } /* end of mgsl_trace_block() */
7598 /* mgsl_tx_timeout()
7600 * called when HDLC frame times out
7601 * update stats and do tx completion processing
7603 * Arguments: context pointer to device instance data
7604 * Return Value: None
7606 static void mgsl_tx_timeout(unsigned long context
)
7608 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7609 unsigned long flags
;
7611 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7612 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7613 __FILE__
,__LINE__
,info
->device_name
);
7614 if(info
->tx_active
&&
7615 (info
->params
.mode
== MGSL_MODE_HDLC
||
7616 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7617 info
->icount
.txtimeout
++;
7619 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7620 info
->tx_active
= 0;
7621 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7623 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7624 usc_loopmode_cancel_transmit( info
);
7626 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7630 hdlcdev_tx_done(info
);
7633 mgsl_bh_transmit(info
);
7635 } /* end of mgsl_tx_timeout() */
7637 /* signal that there are no more frames to send, so that
7638 * line is 'released' by echoing RxD to TxD when current
7639 * transmission is complete (or immediately if no tx in progress).
7641 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7643 unsigned long flags
;
7645 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7646 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7647 if (info
->tx_active
)
7648 info
->loopmode_send_done_requested
= TRUE
;
7650 usc_loopmode_send_done(info
);
7652 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7657 /* release the line by echoing RxD to TxD
7658 * upon completion of a transmit frame
7660 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7662 info
->loopmode_send_done_requested
= FALSE
;
7663 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7664 info
->cmr_value
&= ~BIT13
;
7665 usc_OutReg(info
, CMR
, info
->cmr_value
);
7668 /* abort a transmit in progress while in HDLC LoopMode
7670 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7672 /* reset tx dma channel and purge TxFifo */
7673 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7674 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7675 usc_loopmode_send_done( info
);
7678 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7679 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7680 * we must clear CMR:13 to begin repeating TxData to RxData
7682 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7684 info
->loopmode_insert_requested
= TRUE
;
7686 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7687 * begin repeating TxData on RxData (complete insertion)
7689 usc_OutReg( info
, RICR
,
7690 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7692 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7693 info
->cmr_value
|= BIT13
;
7694 usc_OutReg(info
, CMR
, info
->cmr_value
);
7697 /* return 1 if station is inserted into the loop, otherwise 0
7699 static int usc_loopmode_active( struct mgsl_struct
* info
)
7701 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7707 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7708 * set encoding and frame check sequence (FCS) options
7710 * dev pointer to network device structure
7711 * encoding serial encoding setting
7712 * parity FCS setting
7714 * returns 0 if success, otherwise error code
7716 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7717 unsigned short parity
)
7719 struct mgsl_struct
*info
= dev_to_port(dev
);
7720 unsigned char new_encoding
;
7721 unsigned short new_crctype
;
7723 /* return error if TTY interface open */
7729 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7730 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7731 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7732 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7733 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7734 default: return -EINVAL
;
7739 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7740 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7741 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7742 default: return -EINVAL
;
7745 info
->params
.encoding
= new_encoding
;
7746 info
->params
.crc_type
= new_crctype
;
7748 /* if network interface up, reprogram hardware */
7750 mgsl_program_hw(info
);
7756 * called by generic HDLC layer to send frame
7758 * skb socket buffer containing HDLC frame
7759 * dev pointer to network device structure
7761 * returns 0 if success, otherwise error code
7763 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
7765 struct mgsl_struct
*info
= dev_to_port(dev
);
7766 struct net_device_stats
*stats
= hdlc_stats(dev
);
7767 unsigned long flags
;
7769 if (debug_level
>= DEBUG_LEVEL_INFO
)
7770 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7772 /* stop sending until this frame completes */
7773 netif_stop_queue(dev
);
7775 /* copy data to device buffers */
7776 info
->xmit_cnt
= skb
->len
;
7777 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7779 /* update network statistics */
7780 stats
->tx_packets
++;
7781 stats
->tx_bytes
+= skb
->len
;
7783 /* done with socket buffer, so free it */
7786 /* save start time for transmit timeout detection */
7787 dev
->trans_start
= jiffies
;
7789 /* start hardware transmitter if necessary */
7790 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7791 if (!info
->tx_active
)
7792 usc_start_transmitter(info
);
7793 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7799 * called by network layer when interface enabled
7800 * claim resources and initialize hardware
7802 * dev pointer to network device structure
7804 * returns 0 if success, otherwise error code
7806 static int hdlcdev_open(struct net_device
*dev
)
7808 struct mgsl_struct
*info
= dev_to_port(dev
);
7810 unsigned long flags
;
7812 if (debug_level
>= DEBUG_LEVEL_INFO
)
7813 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7815 /* generic HDLC layer open processing */
7816 if ((rc
= hdlc_open(dev
)))
7819 /* arbitrate between network and tty opens */
7820 spin_lock_irqsave(&info
->netlock
, flags
);
7821 if (info
->count
!= 0 || info
->netcount
!= 0) {
7822 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7823 spin_unlock_irqrestore(&info
->netlock
, flags
);
7827 spin_unlock_irqrestore(&info
->netlock
, flags
);
7829 /* claim resources and init adapter */
7830 if ((rc
= startup(info
)) != 0) {
7831 spin_lock_irqsave(&info
->netlock
, flags
);
7833 spin_unlock_irqrestore(&info
->netlock
, flags
);
7837 /* assert DTR and RTS, apply hardware settings */
7838 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7839 mgsl_program_hw(info
);
7841 /* enable network layer transmit */
7842 dev
->trans_start
= jiffies
;
7843 netif_start_queue(dev
);
7845 /* inform generic HDLC layer of current DCD status */
7846 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7847 usc_get_serial_signals(info
);
7848 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7849 if (info
->serial_signals
& SerialSignal_DCD
)
7850 netif_carrier_on(dev
);
7852 netif_carrier_off(dev
);
7857 * called by network layer when interface is disabled
7858 * shutdown hardware and release resources
7860 * dev pointer to network device structure
7862 * returns 0 if success, otherwise error code
7864 static int hdlcdev_close(struct net_device
*dev
)
7866 struct mgsl_struct
*info
= dev_to_port(dev
);
7867 unsigned long flags
;
7869 if (debug_level
>= DEBUG_LEVEL_INFO
)
7870 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7872 netif_stop_queue(dev
);
7874 /* shutdown adapter and release resources */
7879 spin_lock_irqsave(&info
->netlock
, flags
);
7881 spin_unlock_irqrestore(&info
->netlock
, flags
);
7887 * called by network layer to process IOCTL call to network device
7889 * dev pointer to network device structure
7890 * ifr pointer to network interface request structure
7891 * cmd IOCTL command code
7893 * returns 0 if success, otherwise error code
7895 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7897 const size_t size
= sizeof(sync_serial_settings
);
7898 sync_serial_settings new_line
;
7899 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7900 struct mgsl_struct
*info
= dev_to_port(dev
);
7903 if (debug_level
>= DEBUG_LEVEL_INFO
)
7904 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7906 /* return error if TTY interface open */
7910 if (cmd
!= SIOCWANDEV
)
7911 return hdlc_ioctl(dev
, ifr
, cmd
);
7913 switch(ifr
->ifr_settings
.type
) {
7914 case IF_GET_IFACE
: /* return current sync_serial_settings */
7916 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7917 if (ifr
->ifr_settings
.size
< size
) {
7918 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7922 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7923 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7924 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7925 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7928 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7929 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7930 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7931 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7932 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7935 new_line
.clock_rate
= info
->params
.clock_speed
;
7936 new_line
.loopback
= info
->params
.loopback
? 1:0;
7938 if (copy_to_user(line
, &new_line
, size
))
7942 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7944 if(!capable(CAP_NET_ADMIN
))
7946 if (copy_from_user(&new_line
, line
, size
))
7949 switch (new_line
.clock_type
)
7951 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7952 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7953 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7954 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7955 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7956 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7957 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7958 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7959 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7960 default: return -EINVAL
;
7963 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7966 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7967 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7968 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7969 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7970 info
->params
.flags
|= flags
;
7972 info
->params
.loopback
= new_line
.loopback
;
7974 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7975 info
->params
.clock_speed
= new_line
.clock_rate
;
7977 info
->params
.clock_speed
= 0;
7979 /* if network interface up, reprogram hardware */
7981 mgsl_program_hw(info
);
7985 return hdlc_ioctl(dev
, ifr
, cmd
);
7990 * called by network layer when transmit timeout is detected
7992 * dev pointer to network device structure
7994 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7996 struct mgsl_struct
*info
= dev_to_port(dev
);
7997 struct net_device_stats
*stats
= hdlc_stats(dev
);
7998 unsigned long flags
;
8000 if (debug_level
>= DEBUG_LEVEL_INFO
)
8001 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
8004 stats
->tx_aborted_errors
++;
8006 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
8007 usc_stop_transmitter(info
);
8008 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
8010 netif_wake_queue(dev
);
8014 * called by device driver when transmit completes
8015 * reenable network layer transmit if stopped
8017 * info pointer to device instance information
8019 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
8021 if (netif_queue_stopped(info
->netdev
))
8022 netif_wake_queue(info
->netdev
);
8026 * called by device driver when frame received
8027 * pass frame to network layer
8029 * info pointer to device instance information
8030 * buf pointer to buffer contianing frame data
8031 * size count of data bytes in buf
8033 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
8035 struct sk_buff
*skb
= dev_alloc_skb(size
);
8036 struct net_device
*dev
= info
->netdev
;
8037 struct net_device_stats
*stats
= hdlc_stats(dev
);
8039 if (debug_level
>= DEBUG_LEVEL_INFO
)
8040 printk("hdlcdev_rx(%s)\n",dev
->name
);
8043 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
8044 stats
->rx_dropped
++;
8048 memcpy(skb_put(skb
, size
),buf
,size
);
8050 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
8052 stats
->rx_packets
++;
8053 stats
->rx_bytes
+= size
;
8057 info
->netdev
->last_rx
= jiffies
;
8061 * called by device driver when adding device instance
8062 * do generic HDLC initialization
8064 * info pointer to device instance information
8066 * returns 0 if success, otherwise error code
8068 static int hdlcdev_init(struct mgsl_struct
*info
)
8071 struct net_device
*dev
;
8074 /* allocate and initialize network and HDLC layer objects */
8076 if (!(dev
= alloc_hdlcdev(info
))) {
8077 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8081 /* for network layer reporting purposes only */
8082 dev
->base_addr
= info
->io_base
;
8083 dev
->irq
= info
->irq_level
;
8084 dev
->dma
= info
->dma_level
;
8086 /* network layer callbacks and settings */
8087 dev
->do_ioctl
= hdlcdev_ioctl
;
8088 dev
->open
= hdlcdev_open
;
8089 dev
->stop
= hdlcdev_close
;
8090 dev
->tx_timeout
= hdlcdev_tx_timeout
;
8091 dev
->watchdog_timeo
= 10*HZ
;
8092 dev
->tx_queue_len
= 50;
8094 /* generic HDLC layer callbacks and settings */
8095 hdlc
= dev_to_hdlc(dev
);
8096 hdlc
->attach
= hdlcdev_attach
;
8097 hdlc
->xmit
= hdlcdev_xmit
;
8099 /* register objects with HDLC layer */
8100 if ((rc
= register_hdlc_device(dev
))) {
8101 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8111 * called by device driver when removing device instance
8112 * do generic HDLC cleanup
8114 * info pointer to device instance information
8116 static void hdlcdev_exit(struct mgsl_struct
*info
)
8118 unregister_hdlc_device(info
->netdev
);
8119 free_netdev(info
->netdev
);
8120 info
->netdev
= NULL
;
8123 #endif /* CONFIG_HDLC */
8126 static int __devinit
synclink_init_one (struct pci_dev
*dev
,
8127 const struct pci_device_id
*ent
)
8129 struct mgsl_struct
*info
;
8131 if (pci_enable_device(dev
)) {
8132 printk("error enabling pci device %p\n", dev
);
8136 if (!(info
= mgsl_allocate_device())) {
8137 printk("can't allocate device instance data.\n");
8141 /* Copy user configuration info to device instance data */
8143 info
->io_base
= pci_resource_start(dev
, 2);
8144 info
->irq_level
= dev
->irq
;
8145 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8147 /* Because veremap only works on page boundaries we must map
8148 * a larger area than is actually implemented for the LCR
8149 * memory range. We map a full page starting at the page boundary.
8151 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8152 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8153 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8155 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8156 info
->io_addr_size
= 8;
8157 info
->irq_flags
= IRQF_SHARED
;
8159 if (dev
->device
== 0x0210) {
8160 /* Version 1 PCI9030 based universal PCI adapter */
8161 info
->misc_ctrl_value
= 0x007c4080;
8162 info
->hw_version
= 1;
8164 /* Version 0 PCI9050 based 5V PCI adapter
8165 * A PCI9050 bug prevents reading LCR registers if
8166 * LCR base address bit 7 is set. Maintain shadow
8167 * value so we can write to LCR misc control reg.
8169 info
->misc_ctrl_value
= 0x087e4546;
8170 info
->hw_version
= 0;
8173 mgsl_add_device(info
);
8178 static void __devexit
synclink_remove_one (struct pci_dev
*dev
)