2 * $Id: synclink_gt.c,v 4.25 2006/02/06 21:20:33 paulkf Exp $
4 * Device driver for Microgate SyncLink GT serial adapters.
6 * written by Paul Fulghum for Microgate Corporation
9 * Microgate and SyncLink are trademarks of Microgate Corporation
11 * This code is released under the GNU General Public License (GPL)
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 * DEBUG OUTPUT DEFINITIONS
29 * uncomment lines below to enable specific types of debug output
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
77 #include <asm/system.h>
81 #include <asm/types.h>
82 #include <asm/uaccess.h>
84 #include "linux/synclink.h"
86 #ifdef CONFIG_HDLC_MODULE
91 * module identification
93 static char *driver_name
= "SyncLink GT";
94 static char *driver_version
= "$Revision: 4.25 $";
95 static char *tty_driver_name
= "synclink_gt";
96 static char *tty_dev_prefix
= "ttySLG";
97 MODULE_LICENSE("GPL");
98 #define MGSL_MAGIC 0x5401
99 #define MAX_DEVICES 12
101 static struct pci_device_id pci_table
[] = {
102 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_GT_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
103 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_GT2_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
104 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_GT4_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
105 {PCI_VENDOR_ID_MICROGATE
, SYNCLINK_AC_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
,},
106 {0,}, /* terminate list */
108 MODULE_DEVICE_TABLE(pci
, pci_table
);
110 static int init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
111 static void remove_one(struct pci_dev
*dev
);
112 static struct pci_driver pci_driver
= {
113 .name
= "synclink_gt",
114 .id_table
= pci_table
,
116 .remove
= __devexit_p(remove_one
),
119 static int pci_registered
;
122 * module configuration and status
124 static struct slgt_info
*slgt_device_list
;
125 static int slgt_device_count
;
128 static int debug_level
;
129 static int maxframe
[MAX_DEVICES
];
130 static int dosyncppp
[MAX_DEVICES
];
132 module_param(ttymajor
, int, 0);
133 module_param(debug_level
, int, 0);
134 module_param_array(maxframe
, int, NULL
, 0);
135 module_param_array(dosyncppp
, int, NULL
, 0);
137 MODULE_PARM_DESC(ttymajor
, "TTY major device number override: 0=auto assigned");
138 MODULE_PARM_DESC(debug_level
, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
139 MODULE_PARM_DESC(maxframe
, "Maximum frame size used by device (4096 to 65535)");
140 MODULE_PARM_DESC(dosyncppp
, "Enable synchronous net device, 0=disable 1=enable");
143 * tty support and callbacks
145 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
147 static struct tty_driver
*serial_driver
;
149 static int open(struct tty_struct
*tty
, struct file
* filp
);
150 static void close(struct tty_struct
*tty
, struct file
* filp
);
151 static void hangup(struct tty_struct
*tty
);
152 static void set_termios(struct tty_struct
*tty
, struct termios
*old_termios
);
154 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
155 static void put_char(struct tty_struct
*tty
, unsigned char ch
);
156 static void send_xchar(struct tty_struct
*tty
, char ch
);
157 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
158 static int write_room(struct tty_struct
*tty
);
159 static void flush_chars(struct tty_struct
*tty
);
160 static void flush_buffer(struct tty_struct
*tty
);
161 static void tx_hold(struct tty_struct
*tty
);
162 static void tx_release(struct tty_struct
*tty
);
164 static int ioctl(struct tty_struct
*tty
, struct file
*file
, unsigned int cmd
, unsigned long arg
);
165 static int read_proc(char *page
, char **start
, off_t off
, int count
,int *eof
, void *data
);
166 static int chars_in_buffer(struct tty_struct
*tty
);
167 static void throttle(struct tty_struct
* tty
);
168 static void unthrottle(struct tty_struct
* tty
);
169 static void set_break(struct tty_struct
*tty
, int break_state
);
172 * generic HDLC support and callbacks
175 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
176 static void hdlcdev_tx_done(struct slgt_info
*info
);
177 static void hdlcdev_rx(struct slgt_info
*info
, char *buf
, int size
);
178 static int hdlcdev_init(struct slgt_info
*info
);
179 static void hdlcdev_exit(struct slgt_info
*info
);
184 * device specific structures, macros and functions
187 #define SLGT_MAX_PORTS 4
188 #define SLGT_REG_SIZE 256
191 * conditional wait facility
194 struct cond_wait
*next
;
199 static void init_cond_wait(struct cond_wait
*w
, unsigned int data
);
200 static void add_cond_wait(struct cond_wait
**head
, struct cond_wait
*w
);
201 static void remove_cond_wait(struct cond_wait
**head
, struct cond_wait
*w
);
202 static void flush_cond_wait(struct cond_wait
**head
);
205 * DMA buffer descriptor and access macros
209 unsigned short count
;
210 unsigned short status
;
211 unsigned int pbuf
; /* physical address of data buffer */
212 unsigned int next
; /* physical address of next descriptor */
214 /* driver book keeping */
215 char *buf
; /* virtual address of data buffer */
216 unsigned int pdesc
; /* physical address of this descriptor */
217 dma_addr_t buf_dma_addr
;
220 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
221 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
222 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
223 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
224 #define desc_count(a) (le16_to_cpu((a).count))
225 #define desc_status(a) (le16_to_cpu((a).status))
226 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
227 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
228 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
229 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
230 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
232 struct _input_signal_events
{
244 * device instance data structure
247 void *if_ptr
; /* General purpose pointer (used by SPPP) */
249 struct slgt_info
*next_device
; /* device list link */
254 char device_name
[25];
255 struct pci_dev
*pdev
;
257 int port_count
; /* count of ports on adapter */
258 int adapter_num
; /* adapter instance number */
259 int port_num
; /* port instance number */
261 /* array of pointers to port contexts on this adapter */
262 struct slgt_info
*port_array
[SLGT_MAX_PORTS
];
264 int count
; /* count of opens */
265 int line
; /* tty line instance number */
266 unsigned short close_delay
;
267 unsigned short closing_wait
; /* time to wait before closing */
269 struct mgsl_icount icount
;
271 struct tty_struct
*tty
;
273 int x_char
; /* xon/xoff character */
274 int blocked_open
; /* # of blocked opens */
275 unsigned int read_status_mask
;
276 unsigned int ignore_status_mask
;
278 wait_queue_head_t open_wait
;
279 wait_queue_head_t close_wait
;
281 wait_queue_head_t status_event_wait_q
;
282 wait_queue_head_t event_wait_q
;
283 struct timer_list tx_timer
;
284 struct timer_list rx_timer
;
286 unsigned int gpio_present
;
287 struct cond_wait
*gpio_wait_q
;
289 spinlock_t lock
; /* spinlock for synchronizing with ISR */
291 struct work_struct task
;
297 int irq_requested
; /* nonzero if IRQ requested */
298 int irq_occurred
; /* for diagnostics use */
300 /* device configuration */
302 unsigned int bus_type
;
303 unsigned int irq_level
;
304 unsigned long irq_flags
;
306 unsigned char __iomem
* reg_addr
; /* memory mapped registers address */
308 int reg_addr_requested
;
310 MGSL_PARAMS params
; /* communications parameters */
312 u32 max_frame_size
; /* as set by device config */
314 unsigned int raw_rx_size
;
315 unsigned int if_mode
;
325 unsigned char signals
; /* serial signal states */
326 int init_error
; /* initialization error */
328 unsigned char *tx_buf
;
331 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
332 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
333 BOOLEAN drop_rts_on_tx_done
;
334 struct _input_signal_events input_signal_events
;
336 int dcd_chkcount
; /* check counts to prevent */
337 int cts_chkcount
; /* too many IRQs if a signal */
338 int dsr_chkcount
; /* is floating */
341 char *bufs
; /* virtual address of DMA buffer lists */
342 dma_addr_t bufs_dma_addr
; /* physical address of buffer descriptors */
344 unsigned int rbuf_count
;
345 struct slgt_desc
*rbufs
;
346 unsigned int rbuf_current
;
347 unsigned int rbuf_index
;
349 unsigned int tbuf_count
;
350 struct slgt_desc
*tbufs
;
351 unsigned int tbuf_current
;
352 unsigned int tbuf_start
;
354 unsigned char *tmp_rbuf
;
355 unsigned int tmp_rbuf_count
;
357 /* SPPP/Cisco HDLC device parts */
363 struct net_device
*netdev
;
368 static MGSL_PARAMS default_params
= {
369 .mode
= MGSL_MODE_HDLC
,
371 .flags
= HDLC_FLAG_UNDERRUN_ABORT15
,
372 .encoding
= HDLC_ENCODING_NRZI_SPACE
,
375 .crc_type
= HDLC_CRC_16_CCITT
,
376 .preamble_length
= HDLC_PREAMBLE_LENGTH_8BITS
,
377 .preamble
= HDLC_PREAMBLE_PATTERN_NONE
,
381 .parity
= ASYNC_PARITY_NONE
386 #define BH_TRANSMIT 2
388 #define IO_PIN_SHUTDOWN_LIMIT 100
390 #define DMABUFSIZE 256
391 #define DESC_LIST_SIZE 4096
393 #define MASK_PARITY BIT1
394 #define MASK_FRAMING BIT2
395 #define MASK_BREAK BIT3
396 #define MASK_OVERRUN BIT4
398 #define GSR 0x00 /* global status */
399 #define JCR 0x04 /* JTAG control */
400 #define IODR 0x08 /* GPIO direction */
401 #define IOER 0x0c /* GPIO interrupt enable */
402 #define IOVR 0x10 /* GPIO value */
403 #define IOSR 0x14 /* GPIO interrupt status */
404 #define TDR 0x80 /* tx data */
405 #define RDR 0x80 /* rx data */
406 #define TCR 0x82 /* tx control */
407 #define TIR 0x84 /* tx idle */
408 #define TPR 0x85 /* tx preamble */
409 #define RCR 0x86 /* rx control */
410 #define VCR 0x88 /* V.24 control */
411 #define CCR 0x89 /* clock control */
412 #define BDR 0x8a /* baud divisor */
413 #define SCR 0x8c /* serial control */
414 #define SSR 0x8e /* serial status */
415 #define RDCSR 0x90 /* rx DMA control/status */
416 #define TDCSR 0x94 /* tx DMA control/status */
417 #define RDDAR 0x98 /* rx DMA descriptor address */
418 #define TDDAR 0x9c /* tx DMA descriptor address */
421 #define RXBREAK BIT14
422 #define IRQ_TXDATA BIT13
423 #define IRQ_TXIDLE BIT12
424 #define IRQ_TXUNDER BIT11 /* HDLC */
425 #define IRQ_RXDATA BIT10
426 #define IRQ_RXIDLE BIT9 /* HDLC */
427 #define IRQ_RXBREAK BIT9 /* async */
428 #define IRQ_RXOVER BIT8
433 #define IRQ_ALL 0x3ff0
434 #define IRQ_MASTER BIT0
436 #define slgt_irq_on(info, mask) \
437 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
438 #define slgt_irq_off(info, mask) \
439 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
441 static __u8
rd_reg8(struct slgt_info
*info
, unsigned int addr
);
442 static void wr_reg8(struct slgt_info
*info
, unsigned int addr
, __u8 value
);
443 static __u16
rd_reg16(struct slgt_info
*info
, unsigned int addr
);
444 static void wr_reg16(struct slgt_info
*info
, unsigned int addr
, __u16 value
);
445 static __u32
rd_reg32(struct slgt_info
*info
, unsigned int addr
);
446 static void wr_reg32(struct slgt_info
*info
, unsigned int addr
, __u32 value
);
448 static void msc_set_vcr(struct slgt_info
*info
);
450 static int startup(struct slgt_info
*info
);
451 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,struct slgt_info
*info
);
452 static void shutdown(struct slgt_info
*info
);
453 static void program_hw(struct slgt_info
*info
);
454 static void change_params(struct slgt_info
*info
);
456 static int register_test(struct slgt_info
*info
);
457 static int irq_test(struct slgt_info
*info
);
458 static int loopback_test(struct slgt_info
*info
);
459 static int adapter_test(struct slgt_info
*info
);
461 static void reset_adapter(struct slgt_info
*info
);
462 static void reset_port(struct slgt_info
*info
);
463 static void async_mode(struct slgt_info
*info
);
464 static void hdlc_mode(struct slgt_info
*info
);
466 static void rx_stop(struct slgt_info
*info
);
467 static void rx_start(struct slgt_info
*info
);
468 static void reset_rbufs(struct slgt_info
*info
);
469 static void free_rbufs(struct slgt_info
*info
, unsigned int first
, unsigned int last
);
470 static void rdma_reset(struct slgt_info
*info
);
471 static int rx_get_frame(struct slgt_info
*info
);
472 static int rx_get_buf(struct slgt_info
*info
);
474 static void tx_start(struct slgt_info
*info
);
475 static void tx_stop(struct slgt_info
*info
);
476 static void tx_set_idle(struct slgt_info
*info
);
477 static unsigned int free_tbuf_count(struct slgt_info
*info
);
478 static void reset_tbufs(struct slgt_info
*info
);
479 static void tdma_reset(struct slgt_info
*info
);
480 static void tx_load(struct slgt_info
*info
, const char *buf
, unsigned int count
);
482 static void get_signals(struct slgt_info
*info
);
483 static void set_signals(struct slgt_info
*info
);
484 static void enable_loopback(struct slgt_info
*info
);
485 static void set_rate(struct slgt_info
*info
, u32 data_rate
);
487 static int bh_action(struct slgt_info
*info
);
488 static void bh_handler(void* context
);
489 static void bh_transmit(struct slgt_info
*info
);
490 static void isr_serial(struct slgt_info
*info
);
491 static void isr_rdma(struct slgt_info
*info
);
492 static void isr_txeom(struct slgt_info
*info
, unsigned short status
);
493 static void isr_tdma(struct slgt_info
*info
);
494 static irqreturn_t
slgt_interrupt(int irq
, void *dev_id
, struct pt_regs
* regs
);
496 static int alloc_dma_bufs(struct slgt_info
*info
);
497 static void free_dma_bufs(struct slgt_info
*info
);
498 static int alloc_desc(struct slgt_info
*info
);
499 static void free_desc(struct slgt_info
*info
);
500 static int alloc_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
);
501 static void free_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
);
503 static int alloc_tmp_rbuf(struct slgt_info
*info
);
504 static void free_tmp_rbuf(struct slgt_info
*info
);
506 static void tx_timeout(unsigned long context
);
507 static void rx_timeout(unsigned long context
);
512 static int get_stats(struct slgt_info
*info
, struct mgsl_icount __user
*user_icount
);
513 static int get_params(struct slgt_info
*info
, MGSL_PARAMS __user
*params
);
514 static int set_params(struct slgt_info
*info
, MGSL_PARAMS __user
*params
);
515 static int get_txidle(struct slgt_info
*info
, int __user
*idle_mode
);
516 static int set_txidle(struct slgt_info
*info
, int idle_mode
);
517 static int tx_enable(struct slgt_info
*info
, int enable
);
518 static int tx_abort(struct slgt_info
*info
);
519 static int rx_enable(struct slgt_info
*info
, int enable
);
520 static int modem_input_wait(struct slgt_info
*info
,int arg
);
521 static int wait_mgsl_event(struct slgt_info
*info
, int __user
*mask_ptr
);
522 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
523 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
524 unsigned int set
, unsigned int clear
);
525 static void set_break(struct tty_struct
*tty
, int break_state
);
526 static int get_interface(struct slgt_info
*info
, int __user
*if_mode
);
527 static int set_interface(struct slgt_info
*info
, int if_mode
);
528 static int set_gpio(struct slgt_info
*info
, struct gpio_desc __user
*gpio
);
529 static int get_gpio(struct slgt_info
*info
, struct gpio_desc __user
*gpio
);
530 static int wait_gpio(struct slgt_info
*info
, struct gpio_desc __user
*gpio
);
535 static void add_device(struct slgt_info
*info
);
536 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
537 static int claim_resources(struct slgt_info
*info
);
538 static void release_resources(struct slgt_info
*info
);
557 static void trace_block(struct slgt_info
*info
, const char *data
, int count
, const char *label
)
561 printk("%s %s data:\n",info
->device_name
, label
);
563 linecount
= (count
> 16) ? 16 : count
;
564 for(i
=0; i
< linecount
; i
++)
565 printk("%02X ",(unsigned char)data
[i
]);
568 for(i
=0;i
<linecount
;i
++) {
569 if (data
[i
]>=040 && data
[i
]<=0176)
570 printk("%c",data
[i
]);
580 #define DBGDATA(info, buf, size, label)
584 static void dump_tbufs(struct slgt_info
*info
)
587 printk("tbuf_current=%d\n", info
->tbuf_current
);
588 for (i
=0 ; i
< info
->tbuf_count
; i
++) {
589 printk("%d: count=%04X status=%04X\n",
590 i
, le16_to_cpu(info
->tbufs
[i
].count
), le16_to_cpu(info
->tbufs
[i
].status
));
594 #define DBGTBUF(info)
598 static void dump_rbufs(struct slgt_info
*info
)
601 printk("rbuf_current=%d\n", info
->rbuf_current
);
602 for (i
=0 ; i
< info
->rbuf_count
; i
++) {
603 printk("%d: count=%04X status=%04X\n",
604 i
, le16_to_cpu(info
->rbufs
[i
].count
), le16_to_cpu(info
->rbufs
[i
].status
));
608 #define DBGRBUF(info)
611 static inline int sanity_check(struct slgt_info
*info
, char *devname
, const char *name
)
615 printk("null struct slgt_info for (%s) in %s\n", devname
, name
);
618 if (info
->magic
!= MGSL_MAGIC
) {
619 printk("bad magic number struct slgt_info (%s) in %s\n", devname
, name
);
630 * line discipline callback wrappers
632 * The wrappers maintain line discipline references
633 * while calling into the line discipline.
635 * ldisc_receive_buf - pass receive data to line discipline
637 static void ldisc_receive_buf(struct tty_struct
*tty
,
638 const __u8
*data
, char *flags
, int count
)
640 struct tty_ldisc
*ld
;
643 ld
= tty_ldisc_ref(tty
);
646 ld
->receive_buf(tty
, data
, flags
, count
);
653 static int open(struct tty_struct
*tty
, struct file
*filp
)
655 struct slgt_info
*info
;
660 if ((line
< 0) || (line
>= slgt_device_count
)) {
661 DBGERR(("%s: open with invalid line #%d.\n", driver_name
, line
));
665 info
= slgt_device_list
;
666 while(info
&& info
->line
!= line
)
667 info
= info
->next_device
;
668 if (sanity_check(info
, tty
->name
, "open"))
670 if (info
->init_error
) {
671 DBGERR(("%s init error=%d\n", info
->device_name
, info
->init_error
));
675 tty
->driver_data
= info
;
678 DBGINFO(("%s open, old ref count = %d\n", info
->device_name
, info
->count
));
680 /* If port is closing, signal caller to try again */
681 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
682 if (info
->flags
& ASYNC_CLOSING
)
683 interruptible_sleep_on(&info
->close_wait
);
684 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
685 -EAGAIN
: -ERESTARTSYS
);
689 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
691 spin_lock_irqsave(&info
->netlock
, flags
);
692 if (info
->netcount
) {
694 spin_unlock_irqrestore(&info
->netlock
, flags
);
698 spin_unlock_irqrestore(&info
->netlock
, flags
);
700 if (info
->count
== 1) {
701 /* 1st open on this device, init hardware */
702 retval
= startup(info
);
707 retval
= block_til_ready(tty
, filp
, info
);
709 DBGINFO(("%s block_til_ready rc=%d\n", info
->device_name
, retval
));
718 info
->tty
= NULL
; /* tty layer will release tty struct */
723 DBGINFO(("%s open rc=%d\n", info
->device_name
, retval
));
727 static void close(struct tty_struct
*tty
, struct file
*filp
)
729 struct slgt_info
*info
= tty
->driver_data
;
731 if (sanity_check(info
, tty
->name
, "close"))
733 DBGINFO(("%s close entry, count=%d\n", info
->device_name
, info
->count
));
738 if (tty_hung_up_p(filp
))
741 if ((tty
->count
== 1) && (info
->count
!= 1)) {
743 * tty->count is 1 and the tty structure will be freed.
744 * info->count should be one in this case.
745 * if it's not, correct it so that the port is shutdown.
747 DBGERR(("%s close: bad refcount; tty->count=1, "
748 "info->count=%d\n", info
->device_name
, info
->count
));
754 /* if at least one open remaining, leave hardware active */
758 info
->flags
|= ASYNC_CLOSING
;
760 /* set tty->closing to notify line discipline to
761 * only process XON/XOFF characters. Only the N_TTY
762 * discipline appears to use this (ppp does not).
766 /* wait for transmit data to clear all layers */
768 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
769 DBGINFO(("%s call tty_wait_until_sent\n", info
->device_name
));
770 tty_wait_until_sent(tty
, info
->closing_wait
);
773 if (info
->flags
& ASYNC_INITIALIZED
)
774 wait_until_sent(tty
, info
->timeout
);
775 if (tty
->driver
->flush_buffer
)
776 tty
->driver
->flush_buffer(tty
);
777 tty_ldisc_flush(tty
);
784 if (info
->blocked_open
) {
785 if (info
->close_delay
) {
786 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
788 wake_up_interruptible(&info
->open_wait
);
791 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
793 wake_up_interruptible(&info
->close_wait
);
796 DBGINFO(("%s close exit, count=%d\n", tty
->driver
->name
, info
->count
));
799 static void hangup(struct tty_struct
*tty
)
801 struct slgt_info
*info
= tty
->driver_data
;
803 if (sanity_check(info
, tty
->name
, "hangup"))
805 DBGINFO(("%s hangup\n", info
->device_name
));
811 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
814 wake_up_interruptible(&info
->open_wait
);
817 static void set_termios(struct tty_struct
*tty
, struct termios
*old_termios
)
819 struct slgt_info
*info
= tty
->driver_data
;
822 DBGINFO(("%s set_termios\n", tty
->driver
->name
));
824 /* just return if nothing has changed */
825 if ((tty
->termios
->c_cflag
== old_termios
->c_cflag
)
826 && (RELEVANT_IFLAG(tty
->termios
->c_iflag
)
827 == RELEVANT_IFLAG(old_termios
->c_iflag
)))
832 /* Handle transition to B0 status */
833 if (old_termios
->c_cflag
& CBAUD
&&
834 !(tty
->termios
->c_cflag
& CBAUD
)) {
835 info
->signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
836 spin_lock_irqsave(&info
->lock
,flags
);
838 spin_unlock_irqrestore(&info
->lock
,flags
);
841 /* Handle transition away from B0 status */
842 if (!(old_termios
->c_cflag
& CBAUD
) &&
843 tty
->termios
->c_cflag
& CBAUD
) {
844 info
->signals
|= SerialSignal_DTR
;
845 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
846 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
847 info
->signals
|= SerialSignal_RTS
;
849 spin_lock_irqsave(&info
->lock
,flags
);
851 spin_unlock_irqrestore(&info
->lock
,flags
);
854 /* Handle turning off CRTSCTS */
855 if (old_termios
->c_cflag
& CRTSCTS
&&
856 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
862 static int write(struct tty_struct
*tty
,
863 const unsigned char *buf
, int count
)
866 struct slgt_info
*info
= tty
->driver_data
;
869 if (sanity_check(info
, tty
->name
, "write"))
871 DBGINFO(("%s write count=%d\n", info
->device_name
, count
));
876 if (count
> info
->max_frame_size
) {
884 if (info
->params
.mode
== MGSL_MODE_RAW
) {
885 unsigned int bufs_needed
= (count
/DMABUFSIZE
);
886 unsigned int bufs_free
= free_tbuf_count(info
);
887 if (count
% DMABUFSIZE
)
889 if (bufs_needed
> bufs_free
)
894 if (info
->tx_count
) {
895 /* send accumulated data from send_char() calls */
896 /* as frame and wait before accepting more data. */
897 tx_load(info
, info
->tx_buf
, info
->tx_count
);
902 ret
= info
->tx_count
= count
;
903 tx_load(info
, buf
, count
);
907 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
908 spin_lock_irqsave(&info
->lock
,flags
);
909 if (!info
->tx_active
)
911 spin_unlock_irqrestore(&info
->lock
,flags
);
915 DBGINFO(("%s write rc=%d\n", info
->device_name
, ret
));
919 static void put_char(struct tty_struct
*tty
, unsigned char ch
)
921 struct slgt_info
*info
= tty
->driver_data
;
924 if (sanity_check(info
, tty
->name
, "put_char"))
926 DBGINFO(("%s put_char(%d)\n", info
->device_name
, ch
));
929 spin_lock_irqsave(&info
->lock
,flags
);
930 if (!info
->tx_active
&& (info
->tx_count
< info
->max_frame_size
))
931 info
->tx_buf
[info
->tx_count
++] = ch
;
932 spin_unlock_irqrestore(&info
->lock
,flags
);
935 static void send_xchar(struct tty_struct
*tty
, char ch
)
937 struct slgt_info
*info
= tty
->driver_data
;
940 if (sanity_check(info
, tty
->name
, "send_xchar"))
942 DBGINFO(("%s send_xchar(%d)\n", info
->device_name
, ch
));
945 spin_lock_irqsave(&info
->lock
,flags
);
946 if (!info
->tx_enabled
)
948 spin_unlock_irqrestore(&info
->lock
,flags
);
952 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
954 struct slgt_info
*info
= tty
->driver_data
;
955 unsigned long orig_jiffies
, char_time
;
959 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
961 DBGINFO(("%s wait_until_sent entry\n", info
->device_name
));
962 if (!(info
->flags
& ASYNC_INITIALIZED
))
965 orig_jiffies
= jiffies
;
967 /* Set check interval to 1/5 of estimated time to
968 * send a character, and make it at least 1. The check
969 * interval should also be less than the timeout.
970 * Note: use tight timings here to satisfy the NIST-PCTS.
973 if (info
->params
.data_rate
) {
974 char_time
= info
->timeout
/(32 * 5);
981 char_time
= min_t(unsigned long, char_time
, timeout
);
983 while (info
->tx_active
) {
984 msleep_interruptible(jiffies_to_msecs(char_time
));
985 if (signal_pending(current
))
987 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
992 DBGINFO(("%s wait_until_sent exit\n", info
->device_name
));
995 static int write_room(struct tty_struct
*tty
)
997 struct slgt_info
*info
= tty
->driver_data
;
1000 if (sanity_check(info
, tty
->name
, "write_room"))
1002 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1003 DBGINFO(("%s write_room=%d\n", info
->device_name
, ret
));
1007 static void flush_chars(struct tty_struct
*tty
)
1009 struct slgt_info
*info
= tty
->driver_data
;
1010 unsigned long flags
;
1012 if (sanity_check(info
, tty
->name
, "flush_chars"))
1014 DBGINFO(("%s flush_chars entry tx_count=%d\n", info
->device_name
, info
->tx_count
));
1016 if (info
->tx_count
<= 0 || tty
->stopped
||
1017 tty
->hw_stopped
|| !info
->tx_buf
)
1020 DBGINFO(("%s flush_chars start transmit\n", info
->device_name
));
1022 spin_lock_irqsave(&info
->lock
,flags
);
1023 if (!info
->tx_active
&& info
->tx_count
) {
1024 tx_load(info
, info
->tx_buf
,info
->tx_count
);
1027 spin_unlock_irqrestore(&info
->lock
,flags
);
1030 static void flush_buffer(struct tty_struct
*tty
)
1032 struct slgt_info
*info
= tty
->driver_data
;
1033 unsigned long flags
;
1035 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1037 DBGINFO(("%s flush_buffer\n", info
->device_name
));
1039 spin_lock_irqsave(&info
->lock
,flags
);
1040 if (!info
->tx_active
)
1042 spin_unlock_irqrestore(&info
->lock
,flags
);
1044 wake_up_interruptible(&tty
->write_wait
);
1049 * throttle (stop) transmitter
1051 static void tx_hold(struct tty_struct
*tty
)
1053 struct slgt_info
*info
= tty
->driver_data
;
1054 unsigned long flags
;
1056 if (sanity_check(info
, tty
->name
, "tx_hold"))
1058 DBGINFO(("%s tx_hold\n", info
->device_name
));
1059 spin_lock_irqsave(&info
->lock
,flags
);
1060 if (info
->tx_enabled
&& info
->params
.mode
== MGSL_MODE_ASYNC
)
1062 spin_unlock_irqrestore(&info
->lock
,flags
);
1066 * release (start) transmitter
1068 static void tx_release(struct tty_struct
*tty
)
1070 struct slgt_info
*info
= tty
->driver_data
;
1071 unsigned long flags
;
1073 if (sanity_check(info
, tty
->name
, "tx_release"))
1075 DBGINFO(("%s tx_release\n", info
->device_name
));
1076 spin_lock_irqsave(&info
->lock
,flags
);
1077 if (!info
->tx_active
&& info
->tx_count
) {
1078 tx_load(info
, info
->tx_buf
, info
->tx_count
);
1081 spin_unlock_irqrestore(&info
->lock
,flags
);
1085 * Service an IOCTL request
1089 * tty pointer to tty instance data
1090 * file pointer to associated file object for device
1091 * cmd IOCTL command code
1092 * arg command argument/context
1094 * Return 0 if success, otherwise error code
1096 static int ioctl(struct tty_struct
*tty
, struct file
*file
,
1097 unsigned int cmd
, unsigned long arg
)
1099 struct slgt_info
*info
= tty
->driver_data
;
1100 struct mgsl_icount cnow
; /* kernel counter temps */
1101 struct serial_icounter_struct __user
*p_cuser
; /* user space */
1102 unsigned long flags
;
1103 void __user
*argp
= (void __user
*)arg
;
1105 if (sanity_check(info
, tty
->name
, "ioctl"))
1107 DBGINFO(("%s ioctl() cmd=%08X\n", info
->device_name
, cmd
));
1109 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1110 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
1111 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1116 case MGSL_IOCGPARAMS
:
1117 return get_params(info
, argp
);
1118 case MGSL_IOCSPARAMS
:
1119 return set_params(info
, argp
);
1120 case MGSL_IOCGTXIDLE
:
1121 return get_txidle(info
, argp
);
1122 case MGSL_IOCSTXIDLE
:
1123 return set_txidle(info
, (int)arg
);
1124 case MGSL_IOCTXENABLE
:
1125 return tx_enable(info
, (int)arg
);
1126 case MGSL_IOCRXENABLE
:
1127 return rx_enable(info
, (int)arg
);
1128 case MGSL_IOCTXABORT
:
1129 return tx_abort(info
);
1130 case MGSL_IOCGSTATS
:
1131 return get_stats(info
, argp
);
1132 case MGSL_IOCWAITEVENT
:
1133 return wait_mgsl_event(info
, argp
);
1135 return modem_input_wait(info
,(int)arg
);
1137 return get_interface(info
, argp
);
1139 return set_interface(info
,(int)arg
);
1141 return set_gpio(info
, argp
);
1143 return get_gpio(info
, argp
);
1144 case MGSL_IOCWAITGPIO
:
1145 return wait_gpio(info
, argp
);
1147 spin_lock_irqsave(&info
->lock
,flags
);
1148 cnow
= info
->icount
;
1149 spin_unlock_irqrestore(&info
->lock
,flags
);
1151 if (put_user(cnow
.cts
, &p_cuser
->cts
) ||
1152 put_user(cnow
.dsr
, &p_cuser
->dsr
) ||
1153 put_user(cnow
.rng
, &p_cuser
->rng
) ||
1154 put_user(cnow
.dcd
, &p_cuser
->dcd
) ||
1155 put_user(cnow
.rx
, &p_cuser
->rx
) ||
1156 put_user(cnow
.tx
, &p_cuser
->tx
) ||
1157 put_user(cnow
.frame
, &p_cuser
->frame
) ||
1158 put_user(cnow
.overrun
, &p_cuser
->overrun
) ||
1159 put_user(cnow
.parity
, &p_cuser
->parity
) ||
1160 put_user(cnow
.brk
, &p_cuser
->brk
) ||
1161 put_user(cnow
.buf_overrun
, &p_cuser
->buf_overrun
))
1165 return -ENOIOCTLCMD
;
1173 static inline int line_info(char *buf
, struct slgt_info
*info
)
1177 unsigned long flags
;
1179 ret
= sprintf(buf
, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1180 info
->device_name
, info
->phys_reg_addr
,
1181 info
->irq_level
, info
->max_frame_size
);
1183 /* output current serial signal states */
1184 spin_lock_irqsave(&info
->lock
,flags
);
1186 spin_unlock_irqrestore(&info
->lock
,flags
);
1190 if (info
->signals
& SerialSignal_RTS
)
1191 strcat(stat_buf
, "|RTS");
1192 if (info
->signals
& SerialSignal_CTS
)
1193 strcat(stat_buf
, "|CTS");
1194 if (info
->signals
& SerialSignal_DTR
)
1195 strcat(stat_buf
, "|DTR");
1196 if (info
->signals
& SerialSignal_DSR
)
1197 strcat(stat_buf
, "|DSR");
1198 if (info
->signals
& SerialSignal_DCD
)
1199 strcat(stat_buf
, "|CD");
1200 if (info
->signals
& SerialSignal_RI
)
1201 strcat(stat_buf
, "|RI");
1203 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
1204 ret
+= sprintf(buf
+ret
, "\tHDLC txok:%d rxok:%d",
1205 info
->icount
.txok
, info
->icount
.rxok
);
1206 if (info
->icount
.txunder
)
1207 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
1208 if (info
->icount
.txabort
)
1209 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
1210 if (info
->icount
.rxshort
)
1211 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
1212 if (info
->icount
.rxlong
)
1213 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
1214 if (info
->icount
.rxover
)
1215 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
1216 if (info
->icount
.rxcrc
)
1217 ret
+= sprintf(buf
+ret
, " rxcrc:%d", info
->icount
.rxcrc
);
1219 ret
+= sprintf(buf
+ret
, "\tASYNC tx:%d rx:%d",
1220 info
->icount
.tx
, info
->icount
.rx
);
1221 if (info
->icount
.frame
)
1222 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
1223 if (info
->icount
.parity
)
1224 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
1225 if (info
->icount
.brk
)
1226 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
1227 if (info
->icount
.overrun
)
1228 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
1231 /* Append serial signal status to end */
1232 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
1234 ret
+= sprintf(buf
+ret
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1235 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1241 /* Called to print information about devices
1243 static int read_proc(char *page
, char **start
, off_t off
, int count
,
1244 int *eof
, void *data
)
1248 struct slgt_info
*info
;
1250 len
+= sprintf(page
, "synclink_gt driver:%s\n", driver_version
);
1252 info
= slgt_device_list
;
1254 l
= line_info(page
+ len
, info
);
1256 if (len
+begin
> off
+count
)
1258 if (len
+begin
< off
) {
1262 info
= info
->next_device
;
1267 if (off
>= len
+begin
)
1269 *start
= page
+ (off
-begin
);
1270 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
1274 * return count of bytes in transmit buffer
1276 static int chars_in_buffer(struct tty_struct
*tty
)
1278 struct slgt_info
*info
= tty
->driver_data
;
1279 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1281 DBGINFO(("%s chars_in_buffer()=%d\n", info
->device_name
, info
->tx_count
));
1282 return info
->tx_count
;
1286 * signal remote device to throttle send data (our receive data)
1288 static void throttle(struct tty_struct
* tty
)
1290 struct slgt_info
*info
= tty
->driver_data
;
1291 unsigned long flags
;
1293 if (sanity_check(info
, tty
->name
, "throttle"))
1295 DBGINFO(("%s throttle\n", info
->device_name
));
1297 send_xchar(tty
, STOP_CHAR(tty
));
1298 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1299 spin_lock_irqsave(&info
->lock
,flags
);
1300 info
->signals
&= ~SerialSignal_RTS
;
1302 spin_unlock_irqrestore(&info
->lock
,flags
);
1307 * signal remote device to stop throttling send data (our receive data)
1309 static void unthrottle(struct tty_struct
* tty
)
1311 struct slgt_info
*info
= tty
->driver_data
;
1312 unsigned long flags
;
1314 if (sanity_check(info
, tty
->name
, "unthrottle"))
1316 DBGINFO(("%s unthrottle\n", info
->device_name
));
1321 send_xchar(tty
, START_CHAR(tty
));
1323 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1324 spin_lock_irqsave(&info
->lock
,flags
);
1325 info
->signals
|= SerialSignal_RTS
;
1327 spin_unlock_irqrestore(&info
->lock
,flags
);
1332 * set or clear transmit break condition
1333 * break_state -1=set break condition, 0=clear
1335 static void set_break(struct tty_struct
*tty
, int break_state
)
1337 struct slgt_info
*info
= tty
->driver_data
;
1338 unsigned short value
;
1339 unsigned long flags
;
1341 if (sanity_check(info
, tty
->name
, "set_break"))
1343 DBGINFO(("%s set_break(%d)\n", info
->device_name
, break_state
));
1345 spin_lock_irqsave(&info
->lock
,flags
);
1346 value
= rd_reg16(info
, TCR
);
1347 if (break_state
== -1)
1351 wr_reg16(info
, TCR
, value
);
1352 spin_unlock_irqrestore(&info
->lock
,flags
);
1358 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1359 * set encoding and frame check sequence (FCS) options
1361 * dev pointer to network device structure
1362 * encoding serial encoding setting
1363 * parity FCS setting
1365 * returns 0 if success, otherwise error code
1367 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1368 unsigned short parity
)
1370 struct slgt_info
*info
= dev_to_port(dev
);
1371 unsigned char new_encoding
;
1372 unsigned short new_crctype
;
1374 /* return error if TTY interface open */
1378 DBGINFO(("%s hdlcdev_attach\n", info
->device_name
));
1382 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1383 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1384 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1385 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1386 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1387 default: return -EINVAL
;
1392 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1393 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1394 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1395 default: return -EINVAL
;
1398 info
->params
.encoding
= new_encoding
;
1399 info
->params
.crc_type
= new_crctype
;
1401 /* if network interface up, reprogram hardware */
1409 * called by generic HDLC layer to send frame
1411 * skb socket buffer containing HDLC frame
1412 * dev pointer to network device structure
1414 * returns 0 if success, otherwise error code
1416 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1418 struct slgt_info
*info
= dev_to_port(dev
);
1419 struct net_device_stats
*stats
= hdlc_stats(dev
);
1420 unsigned long flags
;
1422 DBGINFO(("%s hdlc_xmit\n", dev
->name
));
1424 /* stop sending until this frame completes */
1425 netif_stop_queue(dev
);
1427 /* copy data to device buffers */
1428 info
->tx_count
= skb
->len
;
1429 tx_load(info
, skb
->data
, skb
->len
);
1431 /* update network statistics */
1432 stats
->tx_packets
++;
1433 stats
->tx_bytes
+= skb
->len
;
1435 /* done with socket buffer, so free it */
1438 /* save start time for transmit timeout detection */
1439 dev
->trans_start
= jiffies
;
1441 /* start hardware transmitter if necessary */
1442 spin_lock_irqsave(&info
->lock
,flags
);
1443 if (!info
->tx_active
)
1445 spin_unlock_irqrestore(&info
->lock
,flags
);
1451 * called by network layer when interface enabled
1452 * claim resources and initialize hardware
1454 * dev pointer to network device structure
1456 * returns 0 if success, otherwise error code
1458 static int hdlcdev_open(struct net_device
*dev
)
1460 struct slgt_info
*info
= dev_to_port(dev
);
1462 unsigned long flags
;
1464 DBGINFO(("%s hdlcdev_open\n", dev
->name
));
1466 /* generic HDLC layer open processing */
1467 if ((rc
= hdlc_open(dev
)))
1470 /* arbitrate between network and tty opens */
1471 spin_lock_irqsave(&info
->netlock
, flags
);
1472 if (info
->count
!= 0 || info
->netcount
!= 0) {
1473 DBGINFO(("%s hdlc_open busy\n", dev
->name
));
1474 spin_unlock_irqrestore(&info
->netlock
, flags
);
1478 spin_unlock_irqrestore(&info
->netlock
, flags
);
1480 /* claim resources and init adapter */
1481 if ((rc
= startup(info
)) != 0) {
1482 spin_lock_irqsave(&info
->netlock
, flags
);
1484 spin_unlock_irqrestore(&info
->netlock
, flags
);
1488 /* assert DTR and RTS, apply hardware settings */
1489 info
->signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1492 /* enable network layer transmit */
1493 dev
->trans_start
= jiffies
;
1494 netif_start_queue(dev
);
1496 /* inform generic HDLC layer of current DCD status */
1497 spin_lock_irqsave(&info
->lock
, flags
);
1499 spin_unlock_irqrestore(&info
->lock
, flags
);
1500 hdlc_set_carrier(info
->signals
& SerialSignal_DCD
, dev
);
1506 * called by network layer when interface is disabled
1507 * shutdown hardware and release resources
1509 * dev pointer to network device structure
1511 * returns 0 if success, otherwise error code
1513 static int hdlcdev_close(struct net_device
*dev
)
1515 struct slgt_info
*info
= dev_to_port(dev
);
1516 unsigned long flags
;
1518 DBGINFO(("%s hdlcdev_close\n", dev
->name
));
1520 netif_stop_queue(dev
);
1522 /* shutdown adapter and release resources */
1527 spin_lock_irqsave(&info
->netlock
, flags
);
1529 spin_unlock_irqrestore(&info
->netlock
, flags
);
1535 * called by network layer to process IOCTL call to network device
1537 * dev pointer to network device structure
1538 * ifr pointer to network interface request structure
1539 * cmd IOCTL command code
1541 * returns 0 if success, otherwise error code
1543 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1545 const size_t size
= sizeof(sync_serial_settings
);
1546 sync_serial_settings new_line
;
1547 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1548 struct slgt_info
*info
= dev_to_port(dev
);
1551 DBGINFO(("%s hdlcdev_ioctl\n", dev
->name
));
1553 /* return error if TTY interface open */
1557 if (cmd
!= SIOCWANDEV
)
1558 return hdlc_ioctl(dev
, ifr
, cmd
);
1560 switch(ifr
->ifr_settings
.type
) {
1561 case IF_GET_IFACE
: /* return current sync_serial_settings */
1563 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1564 if (ifr
->ifr_settings
.size
< size
) {
1565 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1569 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1570 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1571 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1572 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1575 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1576 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1577 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1578 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1579 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1582 new_line
.clock_rate
= info
->params
.clock_speed
;
1583 new_line
.loopback
= info
->params
.loopback
? 1:0;
1585 if (copy_to_user(line
, &new_line
, size
))
1589 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1591 if(!capable(CAP_NET_ADMIN
))
1593 if (copy_from_user(&new_line
, line
, size
))
1596 switch (new_line
.clock_type
)
1598 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1599 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1600 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1601 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1602 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1603 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1604 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1605 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1606 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1607 default: return -EINVAL
;
1610 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1613 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1614 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1615 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1616 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1617 info
->params
.flags
|= flags
;
1619 info
->params
.loopback
= new_line
.loopback
;
1621 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1622 info
->params
.clock_speed
= new_line
.clock_rate
;
1624 info
->params
.clock_speed
= 0;
1626 /* if network interface up, reprogram hardware */
1632 return hdlc_ioctl(dev
, ifr
, cmd
);
1637 * called by network layer when transmit timeout is detected
1639 * dev pointer to network device structure
1641 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1643 struct slgt_info
*info
= dev_to_port(dev
);
1644 struct net_device_stats
*stats
= hdlc_stats(dev
);
1645 unsigned long flags
;
1647 DBGINFO(("%s hdlcdev_tx_timeout\n", dev
->name
));
1650 stats
->tx_aborted_errors
++;
1652 spin_lock_irqsave(&info
->lock
,flags
);
1654 spin_unlock_irqrestore(&info
->lock
,flags
);
1656 netif_wake_queue(dev
);
1660 * called by device driver when transmit completes
1661 * reenable network layer transmit if stopped
1663 * info pointer to device instance information
1665 static void hdlcdev_tx_done(struct slgt_info
*info
)
1667 if (netif_queue_stopped(info
->netdev
))
1668 netif_wake_queue(info
->netdev
);
1672 * called by device driver when frame received
1673 * pass frame to network layer
1675 * info pointer to device instance information
1676 * buf pointer to buffer contianing frame data
1677 * size count of data bytes in buf
1679 static void hdlcdev_rx(struct slgt_info
*info
, char *buf
, int size
)
1681 struct sk_buff
*skb
= dev_alloc_skb(size
);
1682 struct net_device
*dev
= info
->netdev
;
1683 struct net_device_stats
*stats
= hdlc_stats(dev
);
1685 DBGINFO(("%s hdlcdev_rx\n", dev
->name
));
1688 DBGERR(("%s: can't alloc skb, drop packet\n", dev
->name
));
1689 stats
->rx_dropped
++;
1693 memcpy(skb_put(skb
, size
),buf
,size
);
1695 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
1697 stats
->rx_packets
++;
1698 stats
->rx_bytes
+= size
;
1702 info
->netdev
->last_rx
= jiffies
;
1706 * called by device driver when adding device instance
1707 * do generic HDLC initialization
1709 * info pointer to device instance information
1711 * returns 0 if success, otherwise error code
1713 static int hdlcdev_init(struct slgt_info
*info
)
1716 struct net_device
*dev
;
1719 /* allocate and initialize network and HDLC layer objects */
1721 if (!(dev
= alloc_hdlcdev(info
))) {
1722 printk(KERN_ERR
"%s hdlc device alloc failure\n", info
->device_name
);
1726 /* for network layer reporting purposes only */
1727 dev
->mem_start
= info
->phys_reg_addr
;
1728 dev
->mem_end
= info
->phys_reg_addr
+ SLGT_REG_SIZE
- 1;
1729 dev
->irq
= info
->irq_level
;
1731 /* network layer callbacks and settings */
1732 dev
->do_ioctl
= hdlcdev_ioctl
;
1733 dev
->open
= hdlcdev_open
;
1734 dev
->stop
= hdlcdev_close
;
1735 dev
->tx_timeout
= hdlcdev_tx_timeout
;
1736 dev
->watchdog_timeo
= 10*HZ
;
1737 dev
->tx_queue_len
= 50;
1739 /* generic HDLC layer callbacks and settings */
1740 hdlc
= dev_to_hdlc(dev
);
1741 hdlc
->attach
= hdlcdev_attach
;
1742 hdlc
->xmit
= hdlcdev_xmit
;
1744 /* register objects with HDLC layer */
1745 if ((rc
= register_hdlc_device(dev
))) {
1746 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
1756 * called by device driver when removing device instance
1757 * do generic HDLC cleanup
1759 * info pointer to device instance information
1761 static void hdlcdev_exit(struct slgt_info
*info
)
1763 unregister_hdlc_device(info
->netdev
);
1764 free_netdev(info
->netdev
);
1765 info
->netdev
= NULL
;
1768 #endif /* ifdef CONFIG_HDLC */
1771 * get async data from rx DMA buffers
1773 static void rx_async(struct slgt_info
*info
)
1775 struct tty_struct
*tty
= info
->tty
;
1776 struct mgsl_icount
*icount
= &info
->icount
;
1777 unsigned int start
, end
;
1779 unsigned char status
;
1780 struct slgt_desc
*bufs
= info
->rbufs
;
1786 start
= end
= info
->rbuf_current
;
1788 while(desc_complete(bufs
[end
])) {
1789 count
= desc_count(bufs
[end
]) - info
->rbuf_index
;
1790 p
= bufs
[end
].buf
+ info
->rbuf_index
;
1792 DBGISR(("%s rx_async count=%d\n", info
->device_name
, count
));
1793 DBGDATA(info
, p
, count
, "rx");
1795 for(i
=0 ; i
< count
; i
+=2, p
+=2) {
1801 if ((status
= *(p
+1) & (BIT9
+ BIT8
))) {
1804 else if (status
& BIT8
)
1806 /* discard char if tty control flags say so */
1807 if (status
& info
->ignore_status_mask
)
1811 else if (status
& BIT8
)
1815 tty_insert_flip_char(tty
, ch
, stat
);
1821 /* receive buffer not completed */
1822 info
->rbuf_index
+= i
;
1823 info
->rx_timer
.expires
= jiffies
+ 1;
1824 add_timer(&info
->rx_timer
);
1828 info
->rbuf_index
= 0;
1829 free_rbufs(info
, end
, end
);
1831 if (++end
== info
->rbuf_count
)
1834 /* if entire list searched then no frame available */
1840 tty_flip_buffer_push(tty
);
1844 * return next bottom half action to perform
1846 static int bh_action(struct slgt_info
*info
)
1848 unsigned long flags
;
1851 spin_lock_irqsave(&info
->lock
,flags
);
1853 if (info
->pending_bh
& BH_RECEIVE
) {
1854 info
->pending_bh
&= ~BH_RECEIVE
;
1856 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1857 info
->pending_bh
&= ~BH_TRANSMIT
;
1859 } else if (info
->pending_bh
& BH_STATUS
) {
1860 info
->pending_bh
&= ~BH_STATUS
;
1863 /* Mark BH routine as complete */
1864 info
->bh_running
= 0;
1865 info
->bh_requested
= 0;
1869 spin_unlock_irqrestore(&info
->lock
,flags
);
1875 * perform bottom half processing
1877 static void bh_handler(void* context
)
1879 struct slgt_info
*info
= context
;
1884 info
->bh_running
= 1;
1886 while((action
= bh_action(info
))) {
1889 DBGBH(("%s bh receive\n", info
->device_name
));
1890 switch(info
->params
.mode
) {
1891 case MGSL_MODE_ASYNC
:
1894 case MGSL_MODE_HDLC
:
1895 while(rx_get_frame(info
));
1898 while(rx_get_buf(info
));
1901 /* restart receiver if rx DMA buffers exhausted */
1902 if (info
->rx_restart
)
1909 DBGBH(("%s bh status\n", info
->device_name
));
1910 info
->ri_chkcount
= 0;
1911 info
->dsr_chkcount
= 0;
1912 info
->dcd_chkcount
= 0;
1913 info
->cts_chkcount
= 0;
1916 DBGBH(("%s unknown action\n", info
->device_name
));
1920 DBGBH(("%s bh_handler exit\n", info
->device_name
));
1923 static void bh_transmit(struct slgt_info
*info
)
1925 struct tty_struct
*tty
= info
->tty
;
1927 DBGBH(("%s bh_transmit\n", info
->device_name
));
1930 wake_up_interruptible(&tty
->write_wait
);
1934 static void dsr_change(struct slgt_info
*info
)
1937 DBGISR(("dsr_change %s signals=%04X\n", info
->device_name
, info
->signals
));
1938 if ((info
->dsr_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
1939 slgt_irq_off(info
, IRQ_DSR
);
1943 if (info
->signals
& SerialSignal_DSR
)
1944 info
->input_signal_events
.dsr_up
++;
1946 info
->input_signal_events
.dsr_down
++;
1947 wake_up_interruptible(&info
->status_event_wait_q
);
1948 wake_up_interruptible(&info
->event_wait_q
);
1949 info
->pending_bh
|= BH_STATUS
;
1952 static void cts_change(struct slgt_info
*info
)
1955 DBGISR(("cts_change %s signals=%04X\n", info
->device_name
, info
->signals
));
1956 if ((info
->cts_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
1957 slgt_irq_off(info
, IRQ_CTS
);
1961 if (info
->signals
& SerialSignal_CTS
)
1962 info
->input_signal_events
.cts_up
++;
1964 info
->input_signal_events
.cts_down
++;
1965 wake_up_interruptible(&info
->status_event_wait_q
);
1966 wake_up_interruptible(&info
->event_wait_q
);
1967 info
->pending_bh
|= BH_STATUS
;
1969 if (info
->flags
& ASYNC_CTS_FLOW
) {
1971 if (info
->tty
->hw_stopped
) {
1972 if (info
->signals
& SerialSignal_CTS
) {
1973 info
->tty
->hw_stopped
= 0;
1974 info
->pending_bh
|= BH_TRANSMIT
;
1978 if (!(info
->signals
& SerialSignal_CTS
))
1979 info
->tty
->hw_stopped
= 1;
1985 static void dcd_change(struct slgt_info
*info
)
1988 DBGISR(("dcd_change %s signals=%04X\n", info
->device_name
, info
->signals
));
1989 if ((info
->dcd_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
1990 slgt_irq_off(info
, IRQ_DCD
);
1994 if (info
->signals
& SerialSignal_DCD
) {
1995 info
->input_signal_events
.dcd_up
++;
1997 info
->input_signal_events
.dcd_down
++;
2001 hdlc_set_carrier(info
->signals
& SerialSignal_DCD
, info
->netdev
);
2003 wake_up_interruptible(&info
->status_event_wait_q
);
2004 wake_up_interruptible(&info
->event_wait_q
);
2005 info
->pending_bh
|= BH_STATUS
;
2007 if (info
->flags
& ASYNC_CHECK_CD
) {
2008 if (info
->signals
& SerialSignal_DCD
)
2009 wake_up_interruptible(&info
->open_wait
);
2012 tty_hangup(info
->tty
);
2017 static void ri_change(struct slgt_info
*info
)
2020 DBGISR(("ri_change %s signals=%04X\n", info
->device_name
, info
->signals
));
2021 if ((info
->ri_chkcount
)++ == IO_PIN_SHUTDOWN_LIMIT
) {
2022 slgt_irq_off(info
, IRQ_RI
);
2026 if (info
->signals
& SerialSignal_RI
) {
2027 info
->input_signal_events
.ri_up
++;
2029 info
->input_signal_events
.ri_down
++;
2031 wake_up_interruptible(&info
->status_event_wait_q
);
2032 wake_up_interruptible(&info
->event_wait_q
);
2033 info
->pending_bh
|= BH_STATUS
;
2036 static void isr_serial(struct slgt_info
*info
)
2038 unsigned short status
= rd_reg16(info
, SSR
);
2040 DBGISR(("%s isr_serial status=%04X\n", info
->device_name
, status
));
2042 wr_reg16(info
, SSR
, status
); /* clear pending */
2044 info
->irq_occurred
= 1;
2046 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2047 if (status
& IRQ_TXIDLE
) {
2049 isr_txeom(info
, status
);
2051 if ((status
& IRQ_RXBREAK
) && (status
& RXBREAK
)) {
2053 /* process break detection if tty control allows */
2055 if (!(status
& info
->ignore_status_mask
)) {
2056 if (info
->read_status_mask
& MASK_BREAK
) {
2057 tty_insert_flip_char(info
->tty
, 0, TTY_BREAK
);
2058 if (info
->flags
& ASYNC_SAK
)
2065 if (status
& (IRQ_TXIDLE
+ IRQ_TXUNDER
))
2066 isr_txeom(info
, status
);
2068 if (status
& IRQ_RXIDLE
) {
2069 if (status
& RXIDLE
)
2070 info
->icount
.rxidle
++;
2072 info
->icount
.exithunt
++;
2073 wake_up_interruptible(&info
->event_wait_q
);
2076 if (status
& IRQ_RXOVER
)
2080 if (status
& IRQ_DSR
)
2082 if (status
& IRQ_CTS
)
2084 if (status
& IRQ_DCD
)
2086 if (status
& IRQ_RI
)
2090 static void isr_rdma(struct slgt_info
*info
)
2092 unsigned int status
= rd_reg32(info
, RDCSR
);
2094 DBGISR(("%s isr_rdma status=%08x\n", info
->device_name
, status
));
2096 /* RDCSR (rx DMA control/status)
2099 * 06 save status byte to DMA buffer
2101 * 04 eol (end of list)
2102 * 03 eob (end of buffer)
2107 wr_reg32(info
, RDCSR
, status
); /* clear pending */
2109 if (status
& (BIT5
+ BIT4
)) {
2110 DBGISR(("%s isr_rdma rx_restart=1\n", info
->device_name
));
2111 info
->rx_restart
= 1;
2113 info
->pending_bh
|= BH_RECEIVE
;
2116 static void isr_tdma(struct slgt_info
*info
)
2118 unsigned int status
= rd_reg32(info
, TDCSR
);
2120 DBGISR(("%s isr_tdma status=%08x\n", info
->device_name
, status
));
2122 /* TDCSR (tx DMA control/status)
2126 * 04 eol (end of list)
2127 * 03 eob (end of buffer)
2132 wr_reg32(info
, TDCSR
, status
); /* clear pending */
2134 if (status
& (BIT5
+ BIT4
+ BIT3
)) {
2135 // another transmit buffer has completed
2136 // run bottom half to get more send data from user
2137 info
->pending_bh
|= BH_TRANSMIT
;
2141 static void isr_txeom(struct slgt_info
*info
, unsigned short status
)
2143 DBGISR(("%s txeom status=%04x\n", info
->device_name
, status
));
2145 slgt_irq_off(info
, IRQ_TXDATA
+ IRQ_TXIDLE
+ IRQ_TXUNDER
);
2148 if (status
& IRQ_TXUNDER
) {
2149 unsigned short val
= rd_reg16(info
, TCR
);
2150 wr_reg16(info
, TCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
2151 wr_reg16(info
, TCR
, val
); /* clear reset bit */
2154 if (info
->tx_active
) {
2155 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2156 if (status
& IRQ_TXUNDER
)
2157 info
->icount
.txunder
++;
2158 else if (status
& IRQ_TXIDLE
)
2159 info
->icount
.txok
++;
2162 info
->tx_active
= 0;
2165 del_timer(&info
->tx_timer
);
2167 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2168 info
->signals
&= ~SerialSignal_RTS
;
2169 info
->drop_rts_on_tx_done
= 0;
2175 hdlcdev_tx_done(info
);
2179 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2183 info
->pending_bh
|= BH_TRANSMIT
;
2188 static void isr_gpio(struct slgt_info
*info
, unsigned int changed
, unsigned int state
)
2190 struct cond_wait
*w
, *prev
;
2192 /* wake processes waiting for specific transitions */
2193 for (w
= info
->gpio_wait_q
, prev
= NULL
; w
!= NULL
; w
= w
->next
) {
2194 if (w
->data
& changed
) {
2196 wake_up_interruptible(&w
->q
);
2198 prev
->next
= w
->next
;
2200 info
->gpio_wait_q
= w
->next
;
2206 /* interrupt service routine
2208 * irq interrupt number
2209 * dev_id device ID supplied during interrupt registration
2210 * regs interrupted processor context
2212 static irqreturn_t
slgt_interrupt(int irq
, void *dev_id
, struct pt_regs
* regs
)
2214 struct slgt_info
*info
;
2218 DBGISR(("slgt_interrupt irq=%d entry\n", irq
));
2224 spin_lock(&info
->lock
);
2226 while((gsr
= rd_reg32(info
, GSR
) & 0xffffff00)) {
2227 DBGISR(("%s gsr=%08x\n", info
->device_name
, gsr
));
2228 info
->irq_occurred
= 1;
2229 for(i
=0; i
< info
->port_count
; i
++) {
2230 if (info
->port_array
[i
] == NULL
)
2232 if (gsr
& (BIT8
<< i
))
2233 isr_serial(info
->port_array
[i
]);
2234 if (gsr
& (BIT16
<< (i
*2)))
2235 isr_rdma(info
->port_array
[i
]);
2236 if (gsr
& (BIT17
<< (i
*2)))
2237 isr_tdma(info
->port_array
[i
]);
2241 if (info
->gpio_present
) {
2243 unsigned int changed
;
2244 while ((changed
= rd_reg32(info
, IOSR
)) != 0) {
2245 DBGISR(("%s iosr=%08x\n", info
->device_name
, changed
));
2246 /* read latched state of GPIO signals */
2247 state
= rd_reg32(info
, IOVR
);
2248 /* clear pending GPIO interrupt bits */
2249 wr_reg32(info
, IOSR
, changed
);
2250 for (i
=0 ; i
< info
->port_count
; i
++) {
2251 if (info
->port_array
[i
] != NULL
)
2252 isr_gpio(info
->port_array
[i
], changed
, state
);
2257 for(i
=0; i
< info
->port_count
; i
++) {
2258 struct slgt_info
*port
= info
->port_array
[i
];
2260 if (port
&& (port
->count
|| port
->netcount
) &&
2261 port
->pending_bh
&& !port
->bh_running
&&
2262 !port
->bh_requested
) {
2263 DBGISR(("%s bh queued\n", port
->device_name
));
2264 schedule_work(&port
->task
);
2265 port
->bh_requested
= 1;
2269 spin_unlock(&info
->lock
);
2271 DBGISR(("slgt_interrupt irq=%d exit\n", irq
));
2275 static int startup(struct slgt_info
*info
)
2277 DBGINFO(("%s startup\n", info
->device_name
));
2279 if (info
->flags
& ASYNC_INITIALIZED
)
2282 if (!info
->tx_buf
) {
2283 info
->tx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2284 if (!info
->tx_buf
) {
2285 DBGERR(("%s can't allocate tx buffer\n", info
->device_name
));
2290 info
->pending_bh
= 0;
2292 memset(&info
->icount
, 0, sizeof(info
->icount
));
2294 /* program hardware for current parameters */
2295 change_params(info
);
2298 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2300 info
->flags
|= ASYNC_INITIALIZED
;
2306 * called by close() and hangup() to shutdown hardware
2308 static void shutdown(struct slgt_info
*info
)
2310 unsigned long flags
;
2312 if (!(info
->flags
& ASYNC_INITIALIZED
))
2315 DBGINFO(("%s shutdown\n", info
->device_name
));
2317 /* clear status wait queue because status changes */
2318 /* can't happen after shutting down the hardware */
2319 wake_up_interruptible(&info
->status_event_wait_q
);
2320 wake_up_interruptible(&info
->event_wait_q
);
2322 del_timer_sync(&info
->tx_timer
);
2323 del_timer_sync(&info
->rx_timer
);
2325 kfree(info
->tx_buf
);
2326 info
->tx_buf
= NULL
;
2328 spin_lock_irqsave(&info
->lock
,flags
);
2333 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
2335 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
2336 info
->signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2340 flush_cond_wait(&info
->gpio_wait_q
);
2342 spin_unlock_irqrestore(&info
->lock
,flags
);
2345 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2347 info
->flags
&= ~ASYNC_INITIALIZED
;
2350 static void program_hw(struct slgt_info
*info
)
2352 unsigned long flags
;
2354 spin_lock_irqsave(&info
->lock
,flags
);
2359 if (info
->params
.mode
== MGSL_MODE_HDLC
||
2360 info
->params
.mode
== MGSL_MODE_RAW
||
2368 info
->dcd_chkcount
= 0;
2369 info
->cts_chkcount
= 0;
2370 info
->ri_chkcount
= 0;
2371 info
->dsr_chkcount
= 0;
2373 slgt_irq_on(info
, IRQ_DCD
| IRQ_CTS
| IRQ_DSR
);
2376 if (info
->netcount
||
2377 (info
->tty
&& info
->tty
->termios
->c_cflag
& CREAD
))
2380 spin_unlock_irqrestore(&info
->lock
,flags
);
2384 * reconfigure adapter based on new parameters
2386 static void change_params(struct slgt_info
*info
)
2391 if (!info
->tty
|| !info
->tty
->termios
)
2393 DBGINFO(("%s change_params\n", info
->device_name
));
2395 cflag
= info
->tty
->termios
->c_cflag
;
2397 /* if B0 rate (hangup) specified then negate DTR and RTS */
2398 /* otherwise assert DTR and RTS */
2400 info
->signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2402 info
->signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2404 /* byte size and parity */
2406 switch (cflag
& CSIZE
) {
2407 case CS5
: info
->params
.data_bits
= 5; break;
2408 case CS6
: info
->params
.data_bits
= 6; break;
2409 case CS7
: info
->params
.data_bits
= 7; break;
2410 case CS8
: info
->params
.data_bits
= 8; break;
2411 default: info
->params
.data_bits
= 7; break;
2414 info
->params
.stop_bits
= (cflag
& CSTOPB
) ? 2 : 1;
2417 info
->params
.parity
= (cflag
& PARODD
) ? ASYNC_PARITY_ODD
: ASYNC_PARITY_EVEN
;
2419 info
->params
.parity
= ASYNC_PARITY_NONE
;
2421 /* calculate number of jiffies to transmit a full
2422 * FIFO (32 bytes) at specified data rate
2424 bits_per_char
= info
->params
.data_bits
+
2425 info
->params
.stop_bits
+ 1;
2427 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2429 if (info
->params
.data_rate
) {
2430 info
->timeout
= (32*HZ
*bits_per_char
) /
2431 info
->params
.data_rate
;
2433 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2435 if (cflag
& CRTSCTS
)
2436 info
->flags
|= ASYNC_CTS_FLOW
;
2438 info
->flags
&= ~ASYNC_CTS_FLOW
;
2441 info
->flags
&= ~ASYNC_CHECK_CD
;
2443 info
->flags
|= ASYNC_CHECK_CD
;
2445 /* process tty input control flags */
2447 info
->read_status_mask
= IRQ_RXOVER
;
2448 if (I_INPCK(info
->tty
))
2449 info
->read_status_mask
|= MASK_PARITY
| MASK_FRAMING
;
2450 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2451 info
->read_status_mask
|= MASK_BREAK
;
2452 if (I_IGNPAR(info
->tty
))
2453 info
->ignore_status_mask
|= MASK_PARITY
| MASK_FRAMING
;
2454 if (I_IGNBRK(info
->tty
)) {
2455 info
->ignore_status_mask
|= MASK_BREAK
;
2456 /* If ignoring parity and break indicators, ignore
2457 * overruns too. (For real raw support).
2459 if (I_IGNPAR(info
->tty
))
2460 info
->ignore_status_mask
|= MASK_OVERRUN
;
2466 static int get_stats(struct slgt_info
*info
, struct mgsl_icount __user
*user_icount
)
2468 DBGINFO(("%s get_stats\n", info
->device_name
));
2470 memset(&info
->icount
, 0, sizeof(info
->icount
));
2472 if (copy_to_user(user_icount
, &info
->icount
, sizeof(struct mgsl_icount
)))
2478 static int get_params(struct slgt_info
*info
, MGSL_PARAMS __user
*user_params
)
2480 DBGINFO(("%s get_params\n", info
->device_name
));
2481 if (copy_to_user(user_params
, &info
->params
, sizeof(MGSL_PARAMS
)))
2486 static int set_params(struct slgt_info
*info
, MGSL_PARAMS __user
*new_params
)
2488 unsigned long flags
;
2489 MGSL_PARAMS tmp_params
;
2491 DBGINFO(("%s set_params\n", info
->device_name
));
2492 if (copy_from_user(&tmp_params
, new_params
, sizeof(MGSL_PARAMS
)))
2495 spin_lock_irqsave(&info
->lock
, flags
);
2496 memcpy(&info
->params
, &tmp_params
, sizeof(MGSL_PARAMS
));
2497 spin_unlock_irqrestore(&info
->lock
, flags
);
2499 change_params(info
);
2504 static int get_txidle(struct slgt_info
*info
, int __user
*idle_mode
)
2506 DBGINFO(("%s get_txidle=%d\n", info
->device_name
, info
->idle_mode
));
2507 if (put_user(info
->idle_mode
, idle_mode
))
2512 static int set_txidle(struct slgt_info
*info
, int idle_mode
)
2514 unsigned long flags
;
2515 DBGINFO(("%s set_txidle(%d)\n", info
->device_name
, idle_mode
));
2516 spin_lock_irqsave(&info
->lock
,flags
);
2517 info
->idle_mode
= idle_mode
;
2518 if (info
->params
.mode
!= MGSL_MODE_ASYNC
)
2520 spin_unlock_irqrestore(&info
->lock
,flags
);
2524 static int tx_enable(struct slgt_info
*info
, int enable
)
2526 unsigned long flags
;
2527 DBGINFO(("%s tx_enable(%d)\n", info
->device_name
, enable
));
2528 spin_lock_irqsave(&info
->lock
,flags
);
2530 if (!info
->tx_enabled
)
2533 if (info
->tx_enabled
)
2536 spin_unlock_irqrestore(&info
->lock
,flags
);
2541 * abort transmit HDLC frame
2543 static int tx_abort(struct slgt_info
*info
)
2545 unsigned long flags
;
2546 DBGINFO(("%s tx_abort\n", info
->device_name
));
2547 spin_lock_irqsave(&info
->lock
,flags
);
2549 spin_unlock_irqrestore(&info
->lock
,flags
);
2553 static int rx_enable(struct slgt_info
*info
, int enable
)
2555 unsigned long flags
;
2556 DBGINFO(("%s rx_enable(%d)\n", info
->device_name
, enable
));
2557 spin_lock_irqsave(&info
->lock
,flags
);
2559 if (!info
->rx_enabled
)
2562 if (info
->rx_enabled
)
2565 spin_unlock_irqrestore(&info
->lock
,flags
);
2570 * wait for specified event to occur
2572 static int wait_mgsl_event(struct slgt_info
*info
, int __user
*mask_ptr
)
2574 unsigned long flags
;
2577 struct mgsl_icount cprev
, cnow
;
2580 struct _input_signal_events oldsigs
, newsigs
;
2581 DECLARE_WAITQUEUE(wait
, current
);
2583 if (get_user(mask
, mask_ptr
))
2586 DBGINFO(("%s wait_mgsl_event(%d)\n", info
->device_name
, mask
));
2588 spin_lock_irqsave(&info
->lock
,flags
);
2590 /* return immediately if state matches requested events */
2595 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2596 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2597 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2598 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2600 spin_unlock_irqrestore(&info
->lock
,flags
);
2604 /* save current irq counts */
2605 cprev
= info
->icount
;
2606 oldsigs
= info
->input_signal_events
;
2608 /* enable hunt and idle irqs if needed */
2609 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
2610 unsigned short val
= rd_reg16(info
, SCR
);
2611 if (!(val
& IRQ_RXIDLE
))
2612 wr_reg16(info
, SCR
, (unsigned short)(val
| IRQ_RXIDLE
));
2615 set_current_state(TASK_INTERRUPTIBLE
);
2616 add_wait_queue(&info
->event_wait_q
, &wait
);
2618 spin_unlock_irqrestore(&info
->lock
,flags
);
2622 if (signal_pending(current
)) {
2627 /* get current irq counts */
2628 spin_lock_irqsave(&info
->lock
,flags
);
2629 cnow
= info
->icount
;
2630 newsigs
= info
->input_signal_events
;
2631 set_current_state(TASK_INTERRUPTIBLE
);
2632 spin_unlock_irqrestore(&info
->lock
,flags
);
2634 /* if no change, wait aborted for some reason */
2635 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2636 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2637 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2638 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2639 newsigs
.cts_up
== oldsigs
.cts_up
&&
2640 newsigs
.cts_down
== oldsigs
.cts_down
&&
2641 newsigs
.ri_up
== oldsigs
.ri_up
&&
2642 newsigs
.ri_down
== oldsigs
.ri_down
&&
2643 cnow
.exithunt
== cprev
.exithunt
&&
2644 cnow
.rxidle
== cprev
.rxidle
) {
2650 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2651 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2652 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2653 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2654 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2655 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2656 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2657 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2658 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2659 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2667 remove_wait_queue(&info
->event_wait_q
, &wait
);
2668 set_current_state(TASK_RUNNING
);
2671 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2672 spin_lock_irqsave(&info
->lock
,flags
);
2673 if (!waitqueue_active(&info
->event_wait_q
)) {
2674 /* disable enable exit hunt mode/idle rcvd IRQs */
2676 (unsigned short)(rd_reg16(info
, SCR
) & ~IRQ_RXIDLE
));
2678 spin_unlock_irqrestore(&info
->lock
,flags
);
2682 rc
= put_user(events
, mask_ptr
);
2686 static int get_interface(struct slgt_info
*info
, int __user
*if_mode
)
2688 DBGINFO(("%s get_interface=%x\n", info
->device_name
, info
->if_mode
));
2689 if (put_user(info
->if_mode
, if_mode
))
2694 static int set_interface(struct slgt_info
*info
, int if_mode
)
2696 unsigned long flags
;
2699 DBGINFO(("%s set_interface=%x)\n", info
->device_name
, if_mode
));
2700 spin_lock_irqsave(&info
->lock
,flags
);
2701 info
->if_mode
= if_mode
;
2705 /* TCR (tx control) 07 1=RTS driver control */
2706 val
= rd_reg16(info
, TCR
);
2707 if (info
->if_mode
& MGSL_INTERFACE_RTS_EN
)
2711 wr_reg16(info
, TCR
, val
);
2713 spin_unlock_irqrestore(&info
->lock
,flags
);
2718 * set general purpose IO pin state and direction
2721 * state each bit indicates a pin state
2722 * smask set bit indicates pin state to set
2723 * dir each bit indicates a pin direction (0=input, 1=output)
2724 * dmask set bit indicates pin direction to set
2726 static int set_gpio(struct slgt_info
*info
, struct gpio_desc __user
*user_gpio
)
2728 unsigned long flags
;
2729 struct gpio_desc gpio
;
2732 if (!info
->gpio_present
)
2734 if (copy_from_user(&gpio
, user_gpio
, sizeof(gpio
)))
2736 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2737 info
->device_name
, gpio
.state
, gpio
.smask
,
2738 gpio
.dir
, gpio
.dmask
));
2740 spin_lock_irqsave(&info
->lock
,flags
);
2742 data
= rd_reg32(info
, IODR
);
2743 data
|= gpio
.dmask
& gpio
.dir
;
2744 data
&= ~(gpio
.dmask
& ~gpio
.dir
);
2745 wr_reg32(info
, IODR
, data
);
2748 data
= rd_reg32(info
, IOVR
);
2749 data
|= gpio
.smask
& gpio
.state
;
2750 data
&= ~(gpio
.smask
& ~gpio
.state
);
2751 wr_reg32(info
, IOVR
, data
);
2753 spin_unlock_irqrestore(&info
->lock
,flags
);
2759 * get general purpose IO pin state and direction
2761 static int get_gpio(struct slgt_info
*info
, struct gpio_desc __user
*user_gpio
)
2763 struct gpio_desc gpio
;
2764 if (!info
->gpio_present
)
2766 gpio
.state
= rd_reg32(info
, IOVR
);
2767 gpio
.smask
= 0xffffffff;
2768 gpio
.dir
= rd_reg32(info
, IODR
);
2769 gpio
.dmask
= 0xffffffff;
2770 if (copy_to_user(user_gpio
, &gpio
, sizeof(gpio
)))
2772 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2773 info
->device_name
, gpio
.state
, gpio
.dir
));
2778 * conditional wait facility
2780 static void init_cond_wait(struct cond_wait
*w
, unsigned int data
)
2782 init_waitqueue_head(&w
->q
);
2783 init_waitqueue_entry(&w
->wait
, current
);
2787 static void add_cond_wait(struct cond_wait
**head
, struct cond_wait
*w
)
2789 set_current_state(TASK_INTERRUPTIBLE
);
2790 add_wait_queue(&w
->q
, &w
->wait
);
2795 static void remove_cond_wait(struct cond_wait
**head
, struct cond_wait
*cw
)
2797 struct cond_wait
*w
, *prev
;
2798 remove_wait_queue(&cw
->q
, &cw
->wait
);
2799 set_current_state(TASK_RUNNING
);
2800 for (w
= *head
, prev
= NULL
; w
!= NULL
; prev
= w
, w
= w
->next
) {
2803 prev
->next
= w
->next
;
2811 static void flush_cond_wait(struct cond_wait
**head
)
2813 while (*head
!= NULL
) {
2814 wake_up_interruptible(&(*head
)->q
);
2815 *head
= (*head
)->next
;
2820 * wait for general purpose I/O pin(s) to enter specified state
2823 * state - bit indicates target pin state
2824 * smask - set bit indicates watched pin
2826 * The wait ends when at least one watched pin enters the specified
2827 * state. When 0 (no error) is returned, user_gpio->state is set to the
2828 * state of all GPIO pins when the wait ends.
2830 * Note: Each pin may be a dedicated input, dedicated output, or
2831 * configurable input/output. The number and configuration of pins
2832 * varies with the specific adapter model. Only input pins (dedicated
2833 * or configured) can be monitored with this function.
2835 static int wait_gpio(struct slgt_info
*info
, struct gpio_desc __user
*user_gpio
)
2837 unsigned long flags
;
2839 struct gpio_desc gpio
;
2840 struct cond_wait wait
;
2843 if (!info
->gpio_present
)
2845 if (copy_from_user(&gpio
, user_gpio
, sizeof(gpio
)))
2847 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2848 info
->device_name
, gpio
.state
, gpio
.smask
));
2849 /* ignore output pins identified by set IODR bit */
2850 if ((gpio
.smask
&= ~rd_reg32(info
, IODR
)) == 0)
2852 init_cond_wait(&wait
, gpio
.smask
);
2854 spin_lock_irqsave(&info
->lock
, flags
);
2855 /* enable interrupts for watched pins */
2856 wr_reg32(info
, IOER
, rd_reg32(info
, IOER
) | gpio
.smask
);
2857 /* get current pin states */
2858 state
= rd_reg32(info
, IOVR
);
2860 if (gpio
.smask
& ~(state
^ gpio
.state
)) {
2861 /* already in target state */
2864 /* wait for target state */
2865 add_cond_wait(&info
->gpio_wait_q
, &wait
);
2866 spin_unlock_irqrestore(&info
->lock
, flags
);
2868 if (signal_pending(current
))
2871 gpio
.state
= wait
.data
;
2872 spin_lock_irqsave(&info
->lock
, flags
);
2873 remove_cond_wait(&info
->gpio_wait_q
, &wait
);
2876 /* disable all GPIO interrupts if no waiting processes */
2877 if (info
->gpio_wait_q
== NULL
)
2878 wr_reg32(info
, IOER
, 0);
2879 spin_unlock_irqrestore(&info
->lock
,flags
);
2881 if ((rc
== 0) && copy_to_user(user_gpio
, &gpio
, sizeof(gpio
)))
2886 static int modem_input_wait(struct slgt_info
*info
,int arg
)
2888 unsigned long flags
;
2890 struct mgsl_icount cprev
, cnow
;
2891 DECLARE_WAITQUEUE(wait
, current
);
2893 /* save current irq counts */
2894 spin_lock_irqsave(&info
->lock
,flags
);
2895 cprev
= info
->icount
;
2896 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2897 set_current_state(TASK_INTERRUPTIBLE
);
2898 spin_unlock_irqrestore(&info
->lock
,flags
);
2902 if (signal_pending(current
)) {
2907 /* get new irq counts */
2908 spin_lock_irqsave(&info
->lock
,flags
);
2909 cnow
= info
->icount
;
2910 set_current_state(TASK_INTERRUPTIBLE
);
2911 spin_unlock_irqrestore(&info
->lock
,flags
);
2913 /* if no change, wait aborted for some reason */
2914 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2915 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2920 /* check for change in caller specified modem input */
2921 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2922 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2923 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2924 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2931 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2932 set_current_state(TASK_RUNNING
);
2937 * return state of serial control and status signals
2939 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
2941 struct slgt_info
*info
= tty
->driver_data
;
2942 unsigned int result
;
2943 unsigned long flags
;
2945 spin_lock_irqsave(&info
->lock
,flags
);
2947 spin_unlock_irqrestore(&info
->lock
,flags
);
2949 result
= ((info
->signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2950 ((info
->signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2951 ((info
->signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2952 ((info
->signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2953 ((info
->signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2954 ((info
->signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2956 DBGINFO(("%s tiocmget value=%08X\n", info
->device_name
, result
));
2961 * set modem control signals (DTR/RTS)
2963 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2964 * TIOCMSET = set/clear signal values
2965 * value bit mask for command
2967 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
2968 unsigned int set
, unsigned int clear
)
2970 struct slgt_info
*info
= tty
->driver_data
;
2971 unsigned long flags
;
2973 DBGINFO(("%s tiocmset(%x,%x)\n", info
->device_name
, set
, clear
));
2975 if (set
& TIOCM_RTS
)
2976 info
->signals
|= SerialSignal_RTS
;
2977 if (set
& TIOCM_DTR
)
2978 info
->signals
|= SerialSignal_DTR
;
2979 if (clear
& TIOCM_RTS
)
2980 info
->signals
&= ~SerialSignal_RTS
;
2981 if (clear
& TIOCM_DTR
)
2982 info
->signals
&= ~SerialSignal_DTR
;
2984 spin_lock_irqsave(&info
->lock
,flags
);
2986 spin_unlock_irqrestore(&info
->lock
,flags
);
2991 * block current process until the device is ready to open
2993 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
2994 struct slgt_info
*info
)
2996 DECLARE_WAITQUEUE(wait
, current
);
2998 int do_clocal
= 0, extra_count
= 0;
2999 unsigned long flags
;
3001 DBGINFO(("%s block_til_ready\n", tty
->driver
->name
));
3003 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3004 /* nonblock mode is set or port is not enabled */
3005 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3009 if (tty
->termios
->c_cflag
& CLOCAL
)
3012 /* Wait for carrier detect and the line to become
3013 * free (i.e., not in use by the callout). While we are in
3014 * this loop, info->count is dropped by one, so that
3015 * close() knows when to free things. We restore it upon
3016 * exit, either normal or abnormal.
3020 add_wait_queue(&info
->open_wait
, &wait
);
3022 spin_lock_irqsave(&info
->lock
, flags
);
3023 if (!tty_hung_up_p(filp
)) {
3027 spin_unlock_irqrestore(&info
->lock
, flags
);
3028 info
->blocked_open
++;
3031 if ((tty
->termios
->c_cflag
& CBAUD
)) {
3032 spin_lock_irqsave(&info
->lock
,flags
);
3033 info
->signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3035 spin_unlock_irqrestore(&info
->lock
,flags
);
3038 set_current_state(TASK_INTERRUPTIBLE
);
3040 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3041 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3042 -EAGAIN
: -ERESTARTSYS
;
3046 spin_lock_irqsave(&info
->lock
,flags
);
3048 spin_unlock_irqrestore(&info
->lock
,flags
);
3050 if (!(info
->flags
& ASYNC_CLOSING
) &&
3051 (do_clocal
|| (info
->signals
& SerialSignal_DCD
)) ) {
3055 if (signal_pending(current
)) {
3056 retval
= -ERESTARTSYS
;
3060 DBGINFO(("%s block_til_ready wait\n", tty
->driver
->name
));
3064 set_current_state(TASK_RUNNING
);
3065 remove_wait_queue(&info
->open_wait
, &wait
);
3069 info
->blocked_open
--;
3072 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3074 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty
->driver
->name
, retval
));
3078 static int alloc_tmp_rbuf(struct slgt_info
*info
)
3080 info
->tmp_rbuf
= kmalloc(info
->max_frame_size
+ 5, GFP_KERNEL
);
3081 if (info
->tmp_rbuf
== NULL
)
3086 static void free_tmp_rbuf(struct slgt_info
*info
)
3088 kfree(info
->tmp_rbuf
);
3089 info
->tmp_rbuf
= NULL
;
3093 * allocate DMA descriptor lists.
3095 static int alloc_desc(struct slgt_info
*info
)
3100 /* allocate memory to hold descriptor lists */
3101 info
->bufs
= pci_alloc_consistent(info
->pdev
, DESC_LIST_SIZE
, &info
->bufs_dma_addr
);
3102 if (info
->bufs
== NULL
)
3105 memset(info
->bufs
, 0, DESC_LIST_SIZE
);
3107 info
->rbufs
= (struct slgt_desc
*)info
->bufs
;
3108 info
->tbufs
= ((struct slgt_desc
*)info
->bufs
) + info
->rbuf_count
;
3110 pbufs
= (unsigned int)info
->bufs_dma_addr
;
3113 * Build circular lists of descriptors
3116 for (i
=0; i
< info
->rbuf_count
; i
++) {
3117 /* physical address of this descriptor */
3118 info
->rbufs
[i
].pdesc
= pbufs
+ (i
* sizeof(struct slgt_desc
));
3120 /* physical address of next descriptor */
3121 if (i
== info
->rbuf_count
- 1)
3122 info
->rbufs
[i
].next
= cpu_to_le32(pbufs
);
3124 info
->rbufs
[i
].next
= cpu_to_le32(pbufs
+ ((i
+1) * sizeof(struct slgt_desc
)));
3125 set_desc_count(info
->rbufs
[i
], DMABUFSIZE
);
3128 for (i
=0; i
< info
->tbuf_count
; i
++) {
3129 /* physical address of this descriptor */
3130 info
->tbufs
[i
].pdesc
= pbufs
+ ((info
->rbuf_count
+ i
) * sizeof(struct slgt_desc
));
3132 /* physical address of next descriptor */
3133 if (i
== info
->tbuf_count
- 1)
3134 info
->tbufs
[i
].next
= cpu_to_le32(pbufs
+ info
->rbuf_count
* sizeof(struct slgt_desc
));
3136 info
->tbufs
[i
].next
= cpu_to_le32(pbufs
+ ((info
->rbuf_count
+ i
+ 1) * sizeof(struct slgt_desc
)));
3142 static void free_desc(struct slgt_info
*info
)
3144 if (info
->bufs
!= NULL
) {
3145 pci_free_consistent(info
->pdev
, DESC_LIST_SIZE
, info
->bufs
, info
->bufs_dma_addr
);
3152 static int alloc_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
)
3155 for (i
=0; i
< count
; i
++) {
3156 if ((bufs
[i
].buf
= pci_alloc_consistent(info
->pdev
, DMABUFSIZE
, &bufs
[i
].buf_dma_addr
)) == NULL
)
3158 bufs
[i
].pbuf
= cpu_to_le32((unsigned int)bufs
[i
].buf_dma_addr
);
3163 static void free_bufs(struct slgt_info
*info
, struct slgt_desc
*bufs
, int count
)
3166 for (i
=0; i
< count
; i
++) {
3167 if (bufs
[i
].buf
== NULL
)
3169 pci_free_consistent(info
->pdev
, DMABUFSIZE
, bufs
[i
].buf
, bufs
[i
].buf_dma_addr
);
3174 static int alloc_dma_bufs(struct slgt_info
*info
)
3176 info
->rbuf_count
= 32;
3177 info
->tbuf_count
= 32;
3179 if (alloc_desc(info
) < 0 ||
3180 alloc_bufs(info
, info
->rbufs
, info
->rbuf_count
) < 0 ||
3181 alloc_bufs(info
, info
->tbufs
, info
->tbuf_count
) < 0 ||
3182 alloc_tmp_rbuf(info
) < 0) {
3183 DBGERR(("%s DMA buffer alloc fail\n", info
->device_name
));
3190 static void free_dma_bufs(struct slgt_info
*info
)
3193 free_bufs(info
, info
->rbufs
, info
->rbuf_count
);
3194 free_bufs(info
, info
->tbufs
, info
->tbuf_count
);
3197 free_tmp_rbuf(info
);
3200 static int claim_resources(struct slgt_info
*info
)
3202 if (request_mem_region(info
->phys_reg_addr
, SLGT_REG_SIZE
, "synclink_gt") == NULL
) {
3203 DBGERR(("%s reg addr conflict, addr=%08X\n",
3204 info
->device_name
, info
->phys_reg_addr
));
3205 info
->init_error
= DiagStatus_AddressConflict
;
3209 info
->reg_addr_requested
= 1;
3211 info
->reg_addr
= ioremap(info
->phys_reg_addr
, SLGT_REG_SIZE
);
3212 if (!info
->reg_addr
) {
3213 DBGERR(("%s cant map device registers, addr=%08X\n",
3214 info
->device_name
, info
->phys_reg_addr
));
3215 info
->init_error
= DiagStatus_CantAssignPciResources
;
3221 release_resources(info
);
3225 static void release_resources(struct slgt_info
*info
)
3227 if (info
->irq_requested
) {
3228 free_irq(info
->irq_level
, info
);
3229 info
->irq_requested
= 0;
3232 if (info
->reg_addr_requested
) {
3233 release_mem_region(info
->phys_reg_addr
, SLGT_REG_SIZE
);
3234 info
->reg_addr_requested
= 0;
3237 if (info
->reg_addr
) {
3238 iounmap(info
->reg_addr
);
3239 info
->reg_addr
= NULL
;
3243 /* Add the specified device instance data structure to the
3244 * global linked list of devices and increment the device count.
3246 static void add_device(struct slgt_info
*info
)
3250 info
->next_device
= NULL
;
3251 info
->line
= slgt_device_count
;
3252 sprintf(info
->device_name
, "%s%d", tty_dev_prefix
, info
->line
);
3254 if (info
->line
< MAX_DEVICES
) {
3255 if (maxframe
[info
->line
])
3256 info
->max_frame_size
= maxframe
[info
->line
];
3257 info
->dosyncppp
= dosyncppp
[info
->line
];
3260 slgt_device_count
++;
3262 if (!slgt_device_list
)
3263 slgt_device_list
= info
;
3265 struct slgt_info
*current_dev
= slgt_device_list
;
3266 while(current_dev
->next_device
)
3267 current_dev
= current_dev
->next_device
;
3268 current_dev
->next_device
= info
;
3271 if (info
->max_frame_size
< 4096)
3272 info
->max_frame_size
= 4096;
3273 else if (info
->max_frame_size
> 65535)
3274 info
->max_frame_size
= 65535;
3276 switch(info
->pdev
->device
) {
3277 case SYNCLINK_GT_DEVICE_ID
:
3280 case SYNCLINK_GT2_DEVICE_ID
:
3283 case SYNCLINK_GT4_DEVICE_ID
:
3286 case SYNCLINK_AC_DEVICE_ID
:
3288 info
->params
.mode
= MGSL_MODE_ASYNC
;
3291 devstr
= "(unknown model)";
3293 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3294 devstr
, info
->device_name
, info
->phys_reg_addr
,
3295 info
->irq_level
, info
->max_frame_size
);
3303 * allocate device instance structure, return NULL on failure
3305 static struct slgt_info
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3307 struct slgt_info
*info
;
3309 info
= kmalloc(sizeof(struct slgt_info
), GFP_KERNEL
);
3312 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3313 driver_name
, adapter_num
, port_num
));
3315 memset(info
, 0, sizeof(struct slgt_info
));
3316 info
->magic
= MGSL_MAGIC
;
3317 INIT_WORK(&info
->task
, bh_handler
, info
);
3318 info
->max_frame_size
= 4096;
3319 info
->raw_rx_size
= DMABUFSIZE
;
3320 info
->close_delay
= 5*HZ
/10;
3321 info
->closing_wait
= 30*HZ
;
3322 init_waitqueue_head(&info
->open_wait
);
3323 init_waitqueue_head(&info
->close_wait
);
3324 init_waitqueue_head(&info
->status_event_wait_q
);
3325 init_waitqueue_head(&info
->event_wait_q
);
3326 spin_lock_init(&info
->netlock
);
3327 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3328 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3329 info
->adapter_num
= adapter_num
;
3330 info
->port_num
= port_num
;
3332 init_timer(&info
->tx_timer
);
3333 info
->tx_timer
.data
= (unsigned long)info
;
3334 info
->tx_timer
.function
= tx_timeout
;
3336 init_timer(&info
->rx_timer
);
3337 info
->rx_timer
.data
= (unsigned long)info
;
3338 info
->rx_timer
.function
= rx_timeout
;
3340 /* Copy configuration info to device instance data */
3342 info
->irq_level
= pdev
->irq
;
3343 info
->phys_reg_addr
= pci_resource_start(pdev
,0);
3345 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3346 info
->irq_flags
= SA_SHIRQ
;
3348 info
->init_error
= -1; /* assume error, set to 0 on successful init */
3354 static void device_init(int adapter_num
, struct pci_dev
*pdev
)
3356 struct slgt_info
*port_array
[SLGT_MAX_PORTS
];
3360 if (pdev
->device
== SYNCLINK_GT2_DEVICE_ID
)
3362 else if (pdev
->device
== SYNCLINK_GT4_DEVICE_ID
)
3365 /* allocate device instances for all ports */
3366 for (i
=0; i
< port_count
; ++i
) {
3367 port_array
[i
] = alloc_dev(adapter_num
, i
, pdev
);
3368 if (port_array
[i
] == NULL
) {
3369 for (--i
; i
>= 0; --i
)
3370 kfree(port_array
[i
]);
3375 /* give copy of port_array to all ports and add to device list */
3376 for (i
=0; i
< port_count
; ++i
) {
3377 memcpy(port_array
[i
]->port_array
, port_array
, sizeof(port_array
));
3378 add_device(port_array
[i
]);
3379 port_array
[i
]->port_count
= port_count
;
3380 spin_lock_init(&port_array
[i
]->lock
);
3383 /* Allocate and claim adapter resources */
3384 if (!claim_resources(port_array
[0])) {
3386 alloc_dma_bufs(port_array
[0]);
3388 /* copy resource information from first port to others */
3389 for (i
= 1; i
< port_count
; ++i
) {
3390 port_array
[i
]->lock
= port_array
[0]->lock
;
3391 port_array
[i
]->irq_level
= port_array
[0]->irq_level
;
3392 port_array
[i
]->reg_addr
= port_array
[0]->reg_addr
;
3393 alloc_dma_bufs(port_array
[i
]);
3396 if (request_irq(port_array
[0]->irq_level
,
3398 port_array
[0]->irq_flags
,
3399 port_array
[0]->device_name
,
3400 port_array
[0]) < 0) {
3401 DBGERR(("%s request_irq failed IRQ=%d\n",
3402 port_array
[0]->device_name
,
3403 port_array
[0]->irq_level
));
3405 port_array
[0]->irq_requested
= 1;
3406 adapter_test(port_array
[0]);
3407 for (i
=1 ; i
< port_count
; i
++) {
3408 port_array
[i
]->init_error
= port_array
[0]->init_error
;
3409 port_array
[i
]->gpio_present
= port_array
[0]->gpio_present
;
3415 static int __devinit
init_one(struct pci_dev
*dev
,
3416 const struct pci_device_id
*ent
)
3418 if (pci_enable_device(dev
)) {
3419 printk("error enabling pci device %p\n", dev
);
3422 pci_set_master(dev
);
3423 device_init(slgt_device_count
, dev
);
3427 static void __devexit
remove_one(struct pci_dev
*dev
)
3431 static struct tty_operations ops
= {
3435 .put_char
= put_char
,
3436 .flush_chars
= flush_chars
,
3437 .write_room
= write_room
,
3438 .chars_in_buffer
= chars_in_buffer
,
3439 .flush_buffer
= flush_buffer
,
3441 .throttle
= throttle
,
3442 .unthrottle
= unthrottle
,
3443 .send_xchar
= send_xchar
,
3444 .break_ctl
= set_break
,
3445 .wait_until_sent
= wait_until_sent
,
3446 .read_proc
= read_proc
,
3447 .set_termios
= set_termios
,
3449 .start
= tx_release
,
3451 .tiocmget
= tiocmget
,
3452 .tiocmset
= tiocmset
,
3455 static void slgt_cleanup(void)
3458 struct slgt_info
*info
;
3459 struct slgt_info
*tmp
;
3461 printk("unload %s %s\n", driver_name
, driver_version
);
3463 if (serial_driver
) {
3464 if ((rc
= tty_unregister_driver(serial_driver
)))
3465 DBGERR(("tty_unregister_driver error=%d\n", rc
));
3466 put_tty_driver(serial_driver
);
3470 info
= slgt_device_list
;
3473 info
= info
->next_device
;
3476 /* release devices */
3477 info
= slgt_device_list
;
3482 free_dma_bufs(info
);
3483 free_tmp_rbuf(info
);
3484 if (info
->port_num
== 0)
3485 release_resources(info
);
3487 info
= info
->next_device
;
3492 pci_unregister_driver(&pci_driver
);
3496 * Driver initialization entry point.
3498 static int __init
slgt_init(void)
3502 printk("%s %s\n", driver_name
, driver_version
);
3504 slgt_device_count
= 0;
3505 if ((rc
= pci_register_driver(&pci_driver
)) < 0) {
3506 printk("%s pci_register_driver error=%d\n", driver_name
, rc
);
3511 if (!slgt_device_list
) {
3512 printk("%s no devices found\n",driver_name
);
3516 serial_driver
= alloc_tty_driver(MAX_DEVICES
);
3517 if (!serial_driver
) {
3522 /* Initialize the tty_driver structure */
3524 serial_driver
->owner
= THIS_MODULE
;
3525 serial_driver
->driver_name
= tty_driver_name
;
3526 serial_driver
->name
= tty_dev_prefix
;
3527 serial_driver
->major
= ttymajor
;
3528 serial_driver
->minor_start
= 64;
3529 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
3530 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
3531 serial_driver
->init_termios
= tty_std_termios
;
3532 serial_driver
->init_termios
.c_cflag
=
3533 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
3534 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
3535 tty_set_operations(serial_driver
, &ops
);
3536 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
3537 DBGERR(("%s can't register serial driver\n", driver_name
));
3538 put_tty_driver(serial_driver
);
3539 serial_driver
= NULL
;
3543 printk("%s %s, tty major#%d\n",
3544 driver_name
, driver_version
,
3545 serial_driver
->major
);
3554 static void __exit
slgt_exit(void)
3559 module_init(slgt_init
);
3560 module_exit(slgt_exit
);
3563 * register access routines
3566 #define CALC_REGADDR() \
3567 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3569 reg_addr += (info->port_num) * 32;
3571 static __u8
rd_reg8(struct slgt_info
*info
, unsigned int addr
)
3574 return readb((void __iomem
*)reg_addr
);
3577 static void wr_reg8(struct slgt_info
*info
, unsigned int addr
, __u8 value
)
3580 writeb(value
, (void __iomem
*)reg_addr
);
3583 static __u16
rd_reg16(struct slgt_info
*info
, unsigned int addr
)
3586 return readw((void __iomem
*)reg_addr
);
3589 static void wr_reg16(struct slgt_info
*info
, unsigned int addr
, __u16 value
)
3592 writew(value
, (void __iomem
*)reg_addr
);
3595 static __u32
rd_reg32(struct slgt_info
*info
, unsigned int addr
)
3598 return readl((void __iomem
*)reg_addr
);
3601 static void wr_reg32(struct slgt_info
*info
, unsigned int addr
, __u32 value
)
3604 writel(value
, (void __iomem
*)reg_addr
);
3607 static void rdma_reset(struct slgt_info
*info
)
3612 wr_reg32(info
, RDCSR
, BIT1
);
3614 /* wait for enable bit cleared */
3615 for(i
=0 ; i
< 1000 ; i
++)
3616 if (!(rd_reg32(info
, RDCSR
) & BIT0
))
3620 static void tdma_reset(struct slgt_info
*info
)
3625 wr_reg32(info
, TDCSR
, BIT1
);
3627 /* wait for enable bit cleared */
3628 for(i
=0 ; i
< 1000 ; i
++)
3629 if (!(rd_reg32(info
, TDCSR
) & BIT0
))
3634 * enable internal loopback
3635 * TxCLK and RxCLK are generated from BRG
3636 * and TxD is looped back to RxD internally.
3638 static void enable_loopback(struct slgt_info
*info
)
3640 /* SCR (serial control) BIT2=looopback enable */
3641 wr_reg16(info
, SCR
, (unsigned short)(rd_reg16(info
, SCR
) | BIT2
));
3643 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
3644 /* CCR (clock control)
3645 * 07..05 tx clock source (010 = BRG)
3646 * 04..02 rx clock source (010 = BRG)
3647 * 01 auxclk enable (0 = disable)
3648 * 00 BRG enable (1 = enable)
3652 wr_reg8(info
, CCR
, 0x49);
3654 /* set speed if available, otherwise use default */
3655 if (info
->params
.clock_speed
)
3656 set_rate(info
, info
->params
.clock_speed
);
3658 set_rate(info
, 3686400);
3663 * set baud rate generator to specified rate
3665 static void set_rate(struct slgt_info
*info
, u32 rate
)
3668 static unsigned int osc
= 14745600;
3670 /* div = osc/rate - 1
3672 * Round div up if osc/rate is not integer to
3673 * force to next slowest rate.
3678 if (!(osc
% rate
) && div
)
3680 wr_reg16(info
, BDR
, (unsigned short)div
);
3684 static void rx_stop(struct slgt_info
*info
)
3688 /* disable and reset receiver */
3689 val
= rd_reg16(info
, RCR
) & ~BIT1
; /* clear enable bit */
3690 wr_reg16(info
, RCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
3691 wr_reg16(info
, RCR
, val
); /* clear reset bit */
3693 slgt_irq_off(info
, IRQ_RXOVER
+ IRQ_RXDATA
+ IRQ_RXIDLE
);
3695 /* clear pending rx interrupts */
3696 wr_reg16(info
, SSR
, IRQ_RXIDLE
+ IRQ_RXOVER
);
3700 info
->rx_enabled
= 0;
3701 info
->rx_restart
= 0;
3704 static void rx_start(struct slgt_info
*info
)
3708 slgt_irq_off(info
, IRQ_RXOVER
+ IRQ_RXDATA
);
3710 /* clear pending rx overrun IRQ */
3711 wr_reg16(info
, SSR
, IRQ_RXOVER
);
3713 /* reset and disable receiver */
3714 val
= rd_reg16(info
, RCR
) & ~BIT1
; /* clear enable bit */
3715 wr_reg16(info
, RCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
3716 wr_reg16(info
, RCR
, val
); /* clear reset bit */
3721 /* set 1st descriptor address */
3722 wr_reg32(info
, RDDAR
, info
->rbufs
[0].pdesc
);
3724 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
3725 /* enable rx DMA and DMA interrupt */
3726 wr_reg32(info
, RDCSR
, (BIT2
+ BIT0
));
3728 /* enable saving of rx status, rx DMA and DMA interrupt */
3729 wr_reg32(info
, RDCSR
, (BIT6
+ BIT2
+ BIT0
));
3732 slgt_irq_on(info
, IRQ_RXOVER
);
3734 /* enable receiver */
3735 wr_reg16(info
, RCR
, (unsigned short)(rd_reg16(info
, RCR
) | BIT1
));
3737 info
->rx_restart
= 0;
3738 info
->rx_enabled
= 1;
3741 static void tx_start(struct slgt_info
*info
)
3743 if (!info
->tx_enabled
) {
3745 (unsigned short)(rd_reg16(info
, TCR
) | BIT1
));
3746 info
->tx_enabled
= TRUE
;
3749 if (info
->tx_count
) {
3750 info
->drop_rts_on_tx_done
= 0;
3752 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
3753 if (info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
3755 if (!(info
->signals
& SerialSignal_RTS
)) {
3756 info
->signals
|= SerialSignal_RTS
;
3758 info
->drop_rts_on_tx_done
= 1;
3762 slgt_irq_off(info
, IRQ_TXDATA
);
3763 slgt_irq_on(info
, IRQ_TXUNDER
+ IRQ_TXIDLE
);
3764 /* clear tx idle and underrun status bits */
3765 wr_reg16(info
, SSR
, (unsigned short)(IRQ_TXIDLE
+ IRQ_TXUNDER
));
3767 if (!(rd_reg32(info
, TDCSR
) & BIT0
)) {
3768 /* tx DMA stopped, restart tx DMA */
3770 /* set 1st descriptor address */
3771 wr_reg32(info
, TDDAR
, info
->tbufs
[info
->tbuf_start
].pdesc
);
3772 if (info
->params
.mode
== MGSL_MODE_RAW
)
3773 wr_reg32(info
, TDCSR
, BIT2
+ BIT0
); /* IRQ + DMA enable */
3775 wr_reg32(info
, TDCSR
, BIT0
); /* DMA enable */
3778 if (info
->params
.mode
!= MGSL_MODE_RAW
) {
3779 info
->tx_timer
.expires
= jiffies
+ msecs_to_jiffies(5000);
3780 add_timer(&info
->tx_timer
);
3784 /* set 1st descriptor address */
3785 wr_reg32(info
, TDDAR
, info
->tbufs
[info
->tbuf_start
].pdesc
);
3787 slgt_irq_off(info
, IRQ_TXDATA
);
3788 slgt_irq_on(info
, IRQ_TXIDLE
);
3789 /* clear tx idle status bit */
3790 wr_reg16(info
, SSR
, IRQ_TXIDLE
);
3793 wr_reg32(info
, TDCSR
, BIT0
);
3796 info
->tx_active
= 1;
3800 static void tx_stop(struct slgt_info
*info
)
3804 del_timer(&info
->tx_timer
);
3808 /* reset and disable transmitter */
3809 val
= rd_reg16(info
, TCR
) & ~BIT1
; /* clear enable bit */
3810 wr_reg16(info
, TCR
, (unsigned short)(val
| BIT2
)); /* set reset bit */
3811 wr_reg16(info
, TCR
, val
); /* clear reset */
3813 slgt_irq_off(info
, IRQ_TXDATA
+ IRQ_TXIDLE
+ IRQ_TXUNDER
);
3815 /* clear tx idle and underrun status bit */
3816 wr_reg16(info
, SSR
, (unsigned short)(IRQ_TXIDLE
+ IRQ_TXUNDER
));
3820 info
->tx_enabled
= 0;
3821 info
->tx_active
= 0;
3824 static void reset_port(struct slgt_info
*info
)
3826 if (!info
->reg_addr
)
3832 info
->signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
3835 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
3838 static void reset_adapter(struct slgt_info
*info
)
3841 for (i
=0; i
< info
->port_count
; ++i
) {
3842 if (info
->port_array
[i
])
3843 reset_port(info
->port_array
[i
]);
3847 static void async_mode(struct slgt_info
*info
)
3851 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
3857 * 15..13 mode, 010=async
3858 * 12..10 encoding, 000=NRZ
3860 * 08 1=odd parity, 0=even parity
3861 * 07 1=RTS driver control
3863 * 05..04 character length
3868 * 03 0=1 stop bit, 1=2 stop bits
3871 * 00 auto-CTS enable
3875 if (info
->if_mode
& MGSL_INTERFACE_RTS_EN
)
3878 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
3880 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
3884 switch (info
->params
.data_bits
)
3886 case 6: val
|= BIT4
; break;
3887 case 7: val
|= BIT5
; break;
3888 case 8: val
|= BIT5
+ BIT4
; break;
3891 if (info
->params
.stop_bits
!= 1)
3894 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
3897 wr_reg16(info
, TCR
, val
);
3901 * 15..13 mode, 010=async
3902 * 12..10 encoding, 000=NRZ
3904 * 08 1=odd parity, 0=even parity
3905 * 07..06 reserved, must be 0
3906 * 05..04 character length
3911 * 03 reserved, must be zero
3914 * 00 auto-DCD enable
3918 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
3920 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
3924 switch (info
->params
.data_bits
)
3926 case 6: val
|= BIT4
; break;
3927 case 7: val
|= BIT5
; break;
3928 case 8: val
|= BIT5
+ BIT4
; break;
3931 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
3934 wr_reg16(info
, RCR
, val
);
3936 /* CCR (clock control)
3938 * 07..05 011 = tx clock source is BRG/16
3939 * 04..02 010 = rx clock source is BRG
3940 * 01 0 = auxclk disabled
3941 * 00 1 = BRG enabled
3945 wr_reg8(info
, CCR
, 0x69);
3949 /* SCR (serial control)
3951 * 15 1=tx req on FIFO half empty
3952 * 14 1=rx req on FIFO half full
3953 * 13 tx data IRQ enable
3954 * 12 tx idle IRQ enable
3955 * 11 rx break on IRQ enable
3956 * 10 rx data IRQ enable
3957 * 09 rx break off IRQ enable
3958 * 08 overrun IRQ enable
3963 * 03 reserved, must be zero
3964 * 02 1=txd->rxd internal loopback enable
3965 * 01 reserved, must be zero
3966 * 00 1=master IRQ enable
3968 val
= BIT15
+ BIT14
+ BIT0
;
3969 wr_reg16(info
, SCR
, val
);
3971 slgt_irq_on(info
, IRQ_RXBREAK
| IRQ_RXOVER
);
3973 set_rate(info
, info
->params
.data_rate
* 16);
3975 if (info
->params
.loopback
)
3976 enable_loopback(info
);
3979 static void hdlc_mode(struct slgt_info
*info
)
3983 slgt_irq_off(info
, IRQ_ALL
| IRQ_MASTER
);
3989 * 15..13 mode, 000=HDLC 001=raw sync
3993 * 07 1=RTS driver control
3994 * 06 preamble enable
3995 * 05..04 preamble length
3996 * 03 share open/close flag
3999 * 00 auto-CTS enable
4003 if (info
->params
.mode
== MGSL_MODE_RAW
)
4005 if (info
->if_mode
& MGSL_INTERFACE_RTS_EN
)
4008 switch(info
->params
.encoding
)
4010 case HDLC_ENCODING_NRZB
: val
|= BIT10
; break;
4011 case HDLC_ENCODING_NRZI_MARK
: val
|= BIT11
; break;
4012 case HDLC_ENCODING_NRZI
: val
|= BIT11
+ BIT10
; break;
4013 case HDLC_ENCODING_BIPHASE_MARK
: val
|= BIT12
; break;
4014 case HDLC_ENCODING_BIPHASE_SPACE
: val
|= BIT12
+ BIT10
; break;
4015 case HDLC_ENCODING_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
; break;
4016 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
+ BIT10
; break;
4019 switch (info
->params
.crc_type
& HDLC_CRC_MASK
)
4021 case HDLC_CRC_16_CCITT
: val
|= BIT9
; break;
4022 case HDLC_CRC_32_CCITT
: val
|= BIT9
+ BIT8
; break;
4025 if (info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4028 switch (info
->params
.preamble_length
)
4030 case HDLC_PREAMBLE_LENGTH_16BITS
: val
|= BIT5
; break;
4031 case HDLC_PREAMBLE_LENGTH_32BITS
: val
|= BIT4
; break;
4032 case HDLC_PREAMBLE_LENGTH_64BITS
: val
|= BIT5
+ BIT4
; break;
4035 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4038 wr_reg16(info
, TCR
, val
);
4040 /* TPR (transmit preamble) */
4042 switch (info
->params
.preamble
)
4044 case HDLC_PREAMBLE_PATTERN_FLAGS
: val
= 0x7e; break;
4045 case HDLC_PREAMBLE_PATTERN_ONES
: val
= 0xff; break;
4046 case HDLC_PREAMBLE_PATTERN_ZEROS
: val
= 0x00; break;
4047 case HDLC_PREAMBLE_PATTERN_10
: val
= 0x55; break;
4048 case HDLC_PREAMBLE_PATTERN_01
: val
= 0xaa; break;
4049 default: val
= 0x7e; break;
4051 wr_reg8(info
, TPR
, (unsigned char)val
);
4055 * 15..13 mode, 000=HDLC 001=raw sync
4059 * 07..03 reserved, must be 0
4062 * 00 auto-DCD enable
4066 if (info
->params
.mode
== MGSL_MODE_RAW
)
4069 switch(info
->params
.encoding
)
4071 case HDLC_ENCODING_NRZB
: val
|= BIT10
; break;
4072 case HDLC_ENCODING_NRZI_MARK
: val
|= BIT11
; break;
4073 case HDLC_ENCODING_NRZI
: val
|= BIT11
+ BIT10
; break;
4074 case HDLC_ENCODING_BIPHASE_MARK
: val
|= BIT12
; break;
4075 case HDLC_ENCODING_BIPHASE_SPACE
: val
|= BIT12
+ BIT10
; break;
4076 case HDLC_ENCODING_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
; break;
4077 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: val
|= BIT12
+ BIT11
+ BIT10
; break;
4080 switch (info
->params
.crc_type
& HDLC_CRC_MASK
)
4082 case HDLC_CRC_16_CCITT
: val
|= BIT9
; break;
4083 case HDLC_CRC_32_CCITT
: val
|= BIT9
+ BIT8
; break;
4086 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4089 wr_reg16(info
, RCR
, val
);
4091 /* CCR (clock control)
4093 * 07..05 tx clock source
4094 * 04..02 rx clock source
4100 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4102 // when RxC source is DPLL, BRG generates 16X DPLL
4103 // reference clock, so take TxC from BRG/16 to get
4104 // transmit clock at actual data rate
4105 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4106 val
|= BIT6
+ BIT5
; /* 011, txclk = BRG/16 */
4108 val
|= BIT6
; /* 010, txclk = BRG */
4110 else if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4111 val
|= BIT7
; /* 100, txclk = DPLL Input */
4112 else if (info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4113 val
|= BIT5
; /* 001, txclk = RXC Input */
4115 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4116 val
|= BIT3
; /* 010, rxclk = BRG */
4117 else if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4118 val
|= BIT4
; /* 100, rxclk = DPLL */
4119 else if (info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4120 val
|= BIT2
; /* 001, rxclk = TXC Input */
4122 if (info
->params
.clock_speed
)
4125 wr_reg8(info
, CCR
, (unsigned char)val
);
4127 if (info
->params
.flags
& (HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
))
4129 // program DPLL mode
4130 switch(info
->params
.encoding
)
4132 case HDLC_ENCODING_BIPHASE_MARK
:
4133 case HDLC_ENCODING_BIPHASE_SPACE
:
4135 case HDLC_ENCODING_BIPHASE_LEVEL
:
4136 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
:
4137 val
= BIT7
+ BIT6
; break;
4138 default: val
= BIT6
; // NRZ encodings
4140 wr_reg16(info
, RCR
, (unsigned short)(rd_reg16(info
, RCR
) | val
));
4142 // DPLL requires a 16X reference clock from BRG
4143 set_rate(info
, info
->params
.clock_speed
* 16);
4146 set_rate(info
, info
->params
.clock_speed
);
4152 /* SCR (serial control)
4154 * 15 1=tx req on FIFO half empty
4155 * 14 1=rx req on FIFO half full
4156 * 13 tx data IRQ enable
4157 * 12 tx idle IRQ enable
4158 * 11 underrun IRQ enable
4159 * 10 rx data IRQ enable
4160 * 09 rx idle IRQ enable
4161 * 08 overrun IRQ enable
4166 * 03 reserved, must be zero
4167 * 02 1=txd->rxd internal loopback enable
4168 * 01 reserved, must be zero
4169 * 00 1=master IRQ enable
4171 wr_reg16(info
, SCR
, BIT15
+ BIT14
+ BIT0
);
4173 if (info
->params
.loopback
)
4174 enable_loopback(info
);
4178 * set transmit idle mode
4180 static void tx_set_idle(struct slgt_info
*info
)
4185 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4186 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4188 tcr
= rd_reg16(info
, TCR
);
4189 if (info
->idle_mode
& HDLC_TXIDLE_CUSTOM_16
) {
4190 /* disable preamble, set idle size to 16 bits */
4191 tcr
= (tcr
& ~(BIT6
+ BIT5
)) | BIT4
;
4192 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4193 wr_reg8(info
, TPR
, (unsigned char)((info
->idle_mode
>> 8) & 0xff));
4194 } else if (!(tcr
& BIT6
)) {
4195 /* preamble is disabled, set idle size to 8 bits */
4196 tcr
&= ~(BIT5
+ BIT4
);
4198 wr_reg16(info
, TCR
, tcr
);
4200 if (info
->idle_mode
& (HDLC_TXIDLE_CUSTOM_8
| HDLC_TXIDLE_CUSTOM_16
)) {
4201 /* LSB of custom tx idle specified in tx idle register */
4202 val
= (unsigned char)(info
->idle_mode
& 0xff);
4204 /* standard 8 bit idle patterns */
4205 switch(info
->idle_mode
)
4207 case HDLC_TXIDLE_FLAGS
: val
= 0x7e; break;
4208 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
4209 case HDLC_TXIDLE_ALT_MARK_SPACE
: val
= 0xaa; break;
4210 case HDLC_TXIDLE_ZEROS
:
4211 case HDLC_TXIDLE_SPACE
: val
= 0x00; break;
4212 default: val
= 0xff;
4216 wr_reg8(info
, TIR
, val
);
4220 * get state of V24 status (input) signals
4222 static void get_signals(struct slgt_info
*info
)
4224 unsigned short status
= rd_reg16(info
, SSR
);
4226 /* clear all serial signals except DTR and RTS */
4227 info
->signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4230 info
->signals
|= SerialSignal_DSR
;
4232 info
->signals
|= SerialSignal_CTS
;
4234 info
->signals
|= SerialSignal_DCD
;
4236 info
->signals
|= SerialSignal_RI
;
4240 * set V.24 Control Register based on current configuration
4242 static void msc_set_vcr(struct slgt_info
*info
)
4244 unsigned char val
= 0;
4246 /* VCR (V.24 control)
4248 * 07..04 serial IF select
4255 switch(info
->if_mode
& MGSL_INTERFACE_MASK
)
4257 case MGSL_INTERFACE_RS232
:
4258 val
|= BIT5
; /* 0010 */
4260 case MGSL_INTERFACE_V35
:
4261 val
|= BIT7
+ BIT6
+ BIT5
; /* 1110 */
4263 case MGSL_INTERFACE_RS422
:
4264 val
|= BIT6
; /* 0100 */
4268 if (info
->signals
& SerialSignal_DTR
)
4270 if (info
->signals
& SerialSignal_RTS
)
4272 if (info
->if_mode
& MGSL_INTERFACE_LL
)
4274 if (info
->if_mode
& MGSL_INTERFACE_RL
)
4276 wr_reg8(info
, VCR
, val
);
4280 * set state of V24 control (output) signals
4282 static void set_signals(struct slgt_info
*info
)
4284 unsigned char val
= rd_reg8(info
, VCR
);
4285 if (info
->signals
& SerialSignal_DTR
)
4289 if (info
->signals
& SerialSignal_RTS
)
4293 wr_reg8(info
, VCR
, val
);
4297 * free range of receive DMA buffers (i to last)
4299 static void free_rbufs(struct slgt_info
*info
, unsigned int i
, unsigned int last
)
4304 /* reset current buffer for reuse */
4305 info
->rbufs
[i
].status
= 0;
4306 if (info
->params
.mode
== MGSL_MODE_RAW
)
4307 set_desc_count(info
->rbufs
[i
], info
->raw_rx_size
);
4309 set_desc_count(info
->rbufs
[i
], DMABUFSIZE
);
4313 if (++i
== info
->rbuf_count
)
4316 info
->rbuf_current
= i
;
4320 * mark all receive DMA buffers as free
4322 static void reset_rbufs(struct slgt_info
*info
)
4324 free_rbufs(info
, 0, info
->rbuf_count
- 1);
4328 * pass receive HDLC frame to upper layer
4330 * return 1 if frame available, otherwise 0
4332 static int rx_get_frame(struct slgt_info
*info
)
4334 unsigned int start
, end
;
4335 unsigned short status
;
4336 unsigned int framesize
= 0;
4338 unsigned long flags
;
4339 struct tty_struct
*tty
= info
->tty
;
4340 unsigned char addr_field
= 0xff;
4341 unsigned int crc_size
= 0;
4343 switch (info
->params
.crc_type
& HDLC_CRC_MASK
) {
4344 case HDLC_CRC_16_CCITT
: crc_size
= 2; break;
4345 case HDLC_CRC_32_CCITT
: crc_size
= 4; break;
4352 start
= end
= info
->rbuf_current
;
4355 if (!desc_complete(info
->rbufs
[end
]))
4358 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4359 addr_field
= info
->rbufs
[end
].buf
[0];
4361 framesize
+= desc_count(info
->rbufs
[end
]);
4363 if (desc_eof(info
->rbufs
[end
]))
4366 if (++end
== info
->rbuf_count
)
4369 if (end
== info
->rbuf_current
) {
4370 if (info
->rx_enabled
){
4371 spin_lock_irqsave(&info
->lock
,flags
);
4373 spin_unlock_irqrestore(&info
->lock
,flags
);
4381 * 15 buffer complete
4384 * 02 eof (end of frame)
4388 status
= desc_status(info
->rbufs
[end
]);
4390 /* ignore CRC bit if not using CRC (bit is undefined) */
4391 if ((info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_NONE
)
4394 if (framesize
== 0 ||
4395 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4396 free_rbufs(info
, start
, end
);
4400 if (framesize
< (2 + crc_size
) || status
& BIT0
) {
4401 info
->icount
.rxshort
++;
4403 } else if (status
& BIT1
) {
4404 info
->icount
.rxcrc
++;
4405 if (!(info
->params
.crc_type
& HDLC_CRC_RETURN_EX
))
4410 if (framesize
== 0) {
4411 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
4413 stats
->rx_frame_errors
++;
4417 DBGBH(("%s rx frame status=%04X size=%d\n",
4418 info
->device_name
, status
, framesize
));
4419 DBGDATA(info
, info
->rbufs
[start
].buf
, min_t(int, framesize
, DMABUFSIZE
), "rx");
4422 if (!(info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)) {
4423 framesize
-= crc_size
;
4427 if (framesize
> info
->max_frame_size
+ crc_size
)
4428 info
->icount
.rxlong
++;
4430 /* copy dma buffer(s) to contiguous temp buffer */
4431 int copy_count
= framesize
;
4433 unsigned char *p
= info
->tmp_rbuf
;
4434 info
->tmp_rbuf_count
= framesize
;
4436 info
->icount
.rxok
++;
4439 int partial_count
= min(copy_count
, DMABUFSIZE
);
4440 memcpy(p
, info
->rbufs
[i
].buf
, partial_count
);
4442 copy_count
-= partial_count
;
4443 if (++i
== info
->rbuf_count
)
4447 if (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
4448 *p
= (status
& BIT1
) ? RX_CRC_ERROR
: RX_OK
;
4454 hdlcdev_rx(info
,info
->tmp_rbuf
, framesize
);
4457 ldisc_receive_buf(tty
, info
->tmp_rbuf
, info
->flag_buf
, framesize
);
4460 free_rbufs(info
, start
, end
);
4468 * pass receive buffer (RAW synchronous mode) to tty layer
4469 * return 1 if buffer available, otherwise 0
4471 static int rx_get_buf(struct slgt_info
*info
)
4473 unsigned int i
= info
->rbuf_current
;
4475 if (!desc_complete(info
->rbufs
[i
]))
4477 DBGDATA(info
, info
->rbufs
[i
].buf
, desc_count(info
->rbufs
[i
]), "rx");
4478 DBGINFO(("rx_get_buf size=%d\n", desc_count(info
->rbufs
[i
])));
4479 ldisc_receive_buf(info
->tty
, info
->rbufs
[i
].buf
,
4480 info
->flag_buf
, desc_count(info
->rbufs
[i
]));
4481 free_rbufs(info
, i
, i
);
4485 static void reset_tbufs(struct slgt_info
*info
)
4488 info
->tbuf_current
= 0;
4489 for (i
=0 ; i
< info
->tbuf_count
; i
++) {
4490 info
->tbufs
[i
].status
= 0;
4491 info
->tbufs
[i
].count
= 0;
4496 * return number of free transmit DMA buffers
4498 static unsigned int free_tbuf_count(struct slgt_info
*info
)
4500 unsigned int count
= 0;
4501 unsigned int i
= info
->tbuf_current
;
4505 if (desc_count(info
->tbufs
[i
]))
4506 break; /* buffer in use */
4508 if (++i
== info
->tbuf_count
)
4510 } while (i
!= info
->tbuf_current
);
4512 /* last buffer with zero count may be in use, assume it is */
4520 * load transmit DMA buffer(s) with data
4522 static void tx_load(struct slgt_info
*info
, const char *buf
, unsigned int size
)
4524 unsigned short count
;
4526 struct slgt_desc
*d
;
4531 DBGDATA(info
, buf
, size
, "tx");
4533 info
->tbuf_start
= i
= info
->tbuf_current
;
4536 d
= &info
->tbufs
[i
];
4537 if (++i
== info
->tbuf_count
)
4540 count
= (unsigned short)((size
> DMABUFSIZE
) ? DMABUFSIZE
: size
);
4541 memcpy(d
->buf
, buf
, count
);
4546 if (!size
&& info
->params
.mode
!= MGSL_MODE_RAW
)
4547 set_desc_eof(*d
, 1); /* HDLC: set EOF of last desc */
4549 set_desc_eof(*d
, 0);
4551 set_desc_count(*d
, count
);
4554 info
->tbuf_current
= i
;
4557 static int register_test(struct slgt_info
*info
)
4559 static unsigned short patterns
[] =
4560 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4561 static unsigned int count
= sizeof(patterns
)/sizeof(patterns
[0]);
4565 for (i
=0 ; i
< count
; i
++) {
4566 wr_reg16(info
, TIR
, patterns
[i
]);
4567 wr_reg16(info
, BDR
, patterns
[(i
+1)%count
]);
4568 if ((rd_reg16(info
, TIR
) != patterns
[i
]) ||
4569 (rd_reg16(info
, BDR
) != patterns
[(i
+1)%count
])) {
4574 info
->gpio_present
= (rd_reg32(info
, JCR
) & BIT5
) ? 1 : 0;
4575 info
->init_error
= rc
? 0 : DiagStatus_AddressFailure
;
4579 static int irq_test(struct slgt_info
*info
)
4581 unsigned long timeout
;
4582 unsigned long flags
;
4583 struct tty_struct
*oldtty
= info
->tty
;
4584 u32 speed
= info
->params
.data_rate
;
4586 info
->params
.data_rate
= 921600;
4589 spin_lock_irqsave(&info
->lock
, flags
);
4591 slgt_irq_on(info
, IRQ_TXIDLE
);
4593 /* enable transmitter */
4595 (unsigned short)(rd_reg16(info
, TCR
) | BIT1
));
4597 /* write one byte and wait for tx idle */
4598 wr_reg16(info
, TDR
, 0);
4600 /* assume failure */
4601 info
->init_error
= DiagStatus_IrqFailure
;
4602 info
->irq_occurred
= FALSE
;
4604 spin_unlock_irqrestore(&info
->lock
, flags
);
4607 while(timeout
-- && !info
->irq_occurred
)
4608 msleep_interruptible(10);
4610 spin_lock_irqsave(&info
->lock
,flags
);
4612 spin_unlock_irqrestore(&info
->lock
,flags
);
4614 info
->params
.data_rate
= speed
;
4617 info
->init_error
= info
->irq_occurred
? 0 : DiagStatus_IrqFailure
;
4618 return info
->irq_occurred
? 0 : -ENODEV
;
4621 static int loopback_test_rx(struct slgt_info
*info
)
4623 unsigned char *src
, *dest
;
4626 if (desc_complete(info
->rbufs
[0])) {
4627 count
= desc_count(info
->rbufs
[0]);
4628 src
= info
->rbufs
[0].buf
;
4629 dest
= info
->tmp_rbuf
;
4631 for( ; count
; count
-=2, src
+=2) {
4632 /* src=data byte (src+1)=status byte */
4633 if (!(*(src
+1) & (BIT9
+ BIT8
))) {
4636 info
->tmp_rbuf_count
++;
4639 DBGDATA(info
, info
->tmp_rbuf
, info
->tmp_rbuf_count
, "rx");
4645 static int loopback_test(struct slgt_info
*info
)
4647 #define TESTFRAMESIZE 20
4649 unsigned long timeout
;
4650 u16 count
= TESTFRAMESIZE
;
4651 unsigned char buf
[TESTFRAMESIZE
];
4653 unsigned long flags
;
4655 struct tty_struct
*oldtty
= info
->tty
;
4658 memcpy(¶ms
, &info
->params
, sizeof(params
));
4660 info
->params
.mode
= MGSL_MODE_ASYNC
;
4661 info
->params
.data_rate
= 921600;
4662 info
->params
.loopback
= 1;
4665 /* build and send transmit frame */
4666 for (count
= 0; count
< TESTFRAMESIZE
; ++count
)
4667 buf
[count
] = (unsigned char)count
;
4669 info
->tmp_rbuf_count
= 0;
4670 memset(info
->tmp_rbuf
, 0, TESTFRAMESIZE
);
4672 /* program hardware for HDLC and enabled receiver */
4673 spin_lock_irqsave(&info
->lock
,flags
);
4676 info
->tx_count
= count
;
4677 tx_load(info
, buf
, count
);
4679 spin_unlock_irqrestore(&info
->lock
, flags
);
4681 /* wait for receive complete */
4682 for (timeout
= 100; timeout
; --timeout
) {
4683 msleep_interruptible(10);
4684 if (loopback_test_rx(info
)) {
4690 /* verify received frame length and contents */
4691 if (!rc
&& (info
->tmp_rbuf_count
!= count
||
4692 memcmp(buf
, info
->tmp_rbuf
, count
))) {
4696 spin_lock_irqsave(&info
->lock
,flags
);
4697 reset_adapter(info
);
4698 spin_unlock_irqrestore(&info
->lock
,flags
);
4700 memcpy(&info
->params
, ¶ms
, sizeof(info
->params
));
4703 info
->init_error
= rc
? DiagStatus_DmaFailure
: 0;
4707 static int adapter_test(struct slgt_info
*info
)
4709 DBGINFO(("testing %s\n", info
->device_name
));
4710 if (register_test(info
) < 0) {
4711 printk("register test failure %s addr=%08X\n",
4712 info
->device_name
, info
->phys_reg_addr
);
4713 } else if (irq_test(info
) < 0) {
4714 printk("IRQ test failure %s IRQ=%d\n",
4715 info
->device_name
, info
->irq_level
);
4716 } else if (loopback_test(info
) < 0) {
4717 printk("loopback test failure %s\n", info
->device_name
);
4719 return info
->init_error
;
4723 * transmit timeout handler
4725 static void tx_timeout(unsigned long context
)
4727 struct slgt_info
*info
= (struct slgt_info
*)context
;
4728 unsigned long flags
;
4730 DBGINFO(("%s tx_timeout\n", info
->device_name
));
4731 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
4732 info
->icount
.txtimeout
++;
4734 spin_lock_irqsave(&info
->lock
,flags
);
4735 info
->tx_active
= 0;
4737 spin_unlock_irqrestore(&info
->lock
,flags
);
4741 hdlcdev_tx_done(info
);
4748 * receive buffer polling timer
4750 static void rx_timeout(unsigned long context
)
4752 struct slgt_info
*info
= (struct slgt_info
*)context
;
4753 unsigned long flags
;
4755 DBGINFO(("%s rx_timeout\n", info
->device_name
));
4756 spin_lock_irqsave(&info
->lock
, flags
);
4757 info
->pending_bh
|= BH_RECEIVE
;
4758 spin_unlock_irqrestore(&info
->lock
, flags
);