2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
60 #include <asm/system.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
74 #define SYNCLINK_GENERIC_HDLC 0
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82 #include <asm/uaccess.h>
84 static MGSL_PARAMS default_params
= {
85 MGSL_MODE_HDLC
, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE
/* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next
; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr
; /* lower 16 bits of buffer addr */
115 u8 buf_base
; /* upper 8 bits of buffer addr */
117 u16 length
; /* length of buffer */
118 u8 status
; /* status of buffer */
120 } SCADESC
, *PSCADESC
;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr
; /* virtual address of data buffer */
126 u16 phys_entry
; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX
, *PSCADESC_EX
;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 struct _input_signal_events
{
149 * Device instance data structure
151 typedef struct _synclinkmp_info
{
152 void *if_ptr
; /* General purpose pointer (used by SPPP) */
155 int count
; /* count of opens */
157 unsigned short close_delay
;
158 unsigned short closing_wait
; /* time to wait before closing */
160 struct mgsl_icount icount
;
162 struct tty_struct
*tty
;
164 int x_char
; /* xon/xoff character */
165 int blocked_open
; /* # of blocked opens */
166 u16 read_status_mask1
; /* break detection (SR1 indications) */
167 u16 read_status_mask2
; /* parity/framing/overun (SR2 indications) */
168 unsigned char ignore_status_mask1
; /* break detection (SR1 indications) */
169 unsigned char ignore_status_mask2
; /* parity/framing/overun (SR2 indications) */
170 unsigned char *tx_buf
;
175 wait_queue_head_t open_wait
;
176 wait_queue_head_t close_wait
;
178 wait_queue_head_t status_event_wait_q
;
179 wait_queue_head_t event_wait_q
;
180 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
181 struct _synclinkmp_info
*next_device
; /* device list link */
182 struct timer_list status_timer
; /* input signal status check timer */
184 spinlock_t lock
; /* spinlock for synchronizing with ISR */
185 struct work_struct task
; /* task structure for scheduling bh */
187 u32 max_frame_size
; /* as set by device config */
191 bool bh_running
; /* Protection from multiple */
195 int dcd_chkcount
; /* check counts to prevent */
196 int cts_chkcount
; /* too many IRQs if a signal */
197 int dsr_chkcount
; /* is floating */
200 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
201 unsigned long buffer_list_phys
;
203 unsigned int rx_buf_count
; /* count of total allocated Rx buffers */
204 SCADESC
*rx_buf_list
; /* list of receive buffer entries */
205 SCADESC_EX rx_buf_list_ex
[SCAMAXDESC
]; /* list of receive buffer entries */
206 unsigned int current_rx_buf
;
208 unsigned int tx_buf_count
; /* count of total allocated Tx buffers */
209 SCADESC
*tx_buf_list
; /* list of transmit buffer entries */
210 SCADESC_EX tx_buf_list_ex
[SCAMAXDESC
]; /* list of transmit buffer entries */
211 unsigned int last_tx_buf
;
213 unsigned char *tmp_rx_buf
;
214 unsigned int tmp_rx_buf_count
;
223 unsigned char ie0_value
;
224 unsigned char ie1_value
;
225 unsigned char ie2_value
;
226 unsigned char ctrlreg_value
;
227 unsigned char old_signals
;
229 char device_name
[25]; /* device instance name */
235 struct _synclinkmp_info
*port_array
[SCA_MAX_PORTS
];
237 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
239 unsigned int irq_level
; /* interrupt level */
240 unsigned long irq_flags
;
241 bool irq_requested
; /* true if IRQ requested */
243 MGSL_PARAMS params
; /* communications parameters */
245 unsigned char serial_signals
; /* current serial signal states */
247 bool irq_occurred
; /* for diagnostics use */
248 unsigned int init_error
; /* Initialization startup error */
251 unsigned char* memory_base
; /* shared memory address (PCI only) */
252 u32 phys_memory_base
;
253 int shared_mem_requested
;
255 unsigned char* sca_base
; /* HD64570 SCA Memory address */
258 bool sca_base_requested
;
260 unsigned char* lcr_base
; /* local config registers (PCI only) */
263 int lcr_mem_requested
;
265 unsigned char* statctrl_base
; /* status/control register memory */
266 u32 phys_statctrl_base
;
268 bool sca_statctrl_requested
;
271 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
272 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
273 bool drop_rts_on_tx_done
;
275 struct _input_signal_events input_signal_events
;
277 /* SPPP/Cisco HDLC device parts */
282 #if SYNCLINK_GENERIC_HDLC
283 struct net_device
*netdev
;
288 #define MGSL_MAGIC 0x5401
291 * define serial signal status change macros
293 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
294 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
295 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
296 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
298 /* Common Register macros */
317 /* MSCI Register macros */
347 /* Timer Register Macros */
357 /* DMA Controller Register macros */
388 /* combine with timer or DMA register address */
396 /* SCA Command Codes */
399 #define TXENABLE 0x02
400 #define TXDISABLE 0x03
401 #define TXCRCINIT 0x04
402 #define TXCRCEXCL 0x05
406 #define TXBUFCLR 0x09
408 #define RXENABLE 0x12
409 #define RXDISABLE 0x13
410 #define RXCRCINIT 0x14
411 #define RXREJECT 0x15
412 #define SEARCHMP 0x16
413 #define RXCRCEXCL 0x17
414 #define RXCRCCALC 0x18
418 /* DMA command codes */
420 #define FEICLEAR 0x02
454 * Global linked list of SyncLink devices
456 static SLMP_INFO
*synclinkmp_device_list
= NULL
;
457 static int synclinkmp_adapter_count
= -1;
458 static int synclinkmp_device_count
= 0;
461 * Set this param to non-zero to load eax with the
462 * .text section address and breakpoint on module load.
463 * This is useful for use with gdb and add-symbol-file command.
465 static int break_on_load
=0;
468 * Driver major number, defaults to zero to get auto
469 * assigned major number. May be forced as module parameter.
471 static int ttymajor
=0;
474 * Array of user specified options for ISA adapters.
476 static int debug_level
= 0;
477 static int maxframe
[MAX_DEVICES
] = {0,};
478 static int dosyncppp
[MAX_DEVICES
] = {0,};
480 module_param(break_on_load
, bool, 0);
481 module_param(ttymajor
, int, 0);
482 module_param(debug_level
, int, 0);
483 module_param_array(maxframe
, int, NULL
, 0);
484 module_param_array(dosyncppp
, int, NULL
, 0);
486 static char *driver_name
= "SyncLink MultiPort driver";
487 static char *driver_version
= "$Revision: 4.38 $";
489 static int synclinkmp_init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
490 static void synclinkmp_remove_one(struct pci_dev
*dev
);
492 static struct pci_device_id synclinkmp_pci_tbl
[] = {
493 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_SCA
, PCI_ANY_ID
, PCI_ANY_ID
, },
494 { 0, }, /* terminate list */
496 MODULE_DEVICE_TABLE(pci
, synclinkmp_pci_tbl
);
498 MODULE_LICENSE("GPL");
500 static struct pci_driver synclinkmp_pci_driver
= {
501 .name
= "synclinkmp",
502 .id_table
= synclinkmp_pci_tbl
,
503 .probe
= synclinkmp_init_one
,
504 .remove
= __devexit_p(synclinkmp_remove_one
),
508 static struct tty_driver
*serial_driver
;
510 /* number of characters left in xmit buffer before we ask for more */
511 #define WAKEUP_CHARS 256
516 static int open(struct tty_struct
*tty
, struct file
* filp
);
517 static void close(struct tty_struct
*tty
, struct file
* filp
);
518 static void hangup(struct tty_struct
*tty
);
519 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
);
521 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
522 static void put_char(struct tty_struct
*tty
, unsigned char ch
);
523 static void send_xchar(struct tty_struct
*tty
, char ch
);
524 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
525 static int write_room(struct tty_struct
*tty
);
526 static void flush_chars(struct tty_struct
*tty
);
527 static void flush_buffer(struct tty_struct
*tty
);
528 static void tx_hold(struct tty_struct
*tty
);
529 static void tx_release(struct tty_struct
*tty
);
531 static int ioctl(struct tty_struct
*tty
, struct file
*file
, unsigned int cmd
, unsigned long arg
);
532 static int read_proc(char *page
, char **start
, off_t off
, int count
,int *eof
, void *data
);
533 static int chars_in_buffer(struct tty_struct
*tty
);
534 static void throttle(struct tty_struct
* tty
);
535 static void unthrottle(struct tty_struct
* tty
);
536 static void set_break(struct tty_struct
*tty
, int break_state
);
538 #if SYNCLINK_GENERIC_HDLC
539 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
540 static void hdlcdev_tx_done(SLMP_INFO
*info
);
541 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
);
542 static int hdlcdev_init(SLMP_INFO
*info
);
543 static void hdlcdev_exit(SLMP_INFO
*info
);
548 static int get_stats(SLMP_INFO
*info
, struct mgsl_icount __user
*user_icount
);
549 static int get_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
550 static int set_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
551 static int get_txidle(SLMP_INFO
*info
, int __user
*idle_mode
);
552 static int set_txidle(SLMP_INFO
*info
, int idle_mode
);
553 static int tx_enable(SLMP_INFO
*info
, int enable
);
554 static int tx_abort(SLMP_INFO
*info
);
555 static int rx_enable(SLMP_INFO
*info
, int enable
);
556 static int modem_input_wait(SLMP_INFO
*info
,int arg
);
557 static int wait_mgsl_event(SLMP_INFO
*info
, int __user
*mask_ptr
);
558 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
559 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
560 unsigned int set
, unsigned int clear
);
561 static void set_break(struct tty_struct
*tty
, int break_state
);
563 static void add_device(SLMP_INFO
*info
);
564 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
565 static int claim_resources(SLMP_INFO
*info
);
566 static void release_resources(SLMP_INFO
*info
);
568 static int startup(SLMP_INFO
*info
);
569 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,SLMP_INFO
*info
);
570 static void shutdown(SLMP_INFO
*info
);
571 static void program_hw(SLMP_INFO
*info
);
572 static void change_params(SLMP_INFO
*info
);
574 static bool init_adapter(SLMP_INFO
*info
);
575 static bool register_test(SLMP_INFO
*info
);
576 static bool irq_test(SLMP_INFO
*info
);
577 static bool loopback_test(SLMP_INFO
*info
);
578 static int adapter_test(SLMP_INFO
*info
);
579 static bool memory_test(SLMP_INFO
*info
);
581 static void reset_adapter(SLMP_INFO
*info
);
582 static void reset_port(SLMP_INFO
*info
);
583 static void async_mode(SLMP_INFO
*info
);
584 static void hdlc_mode(SLMP_INFO
*info
);
586 static void rx_stop(SLMP_INFO
*info
);
587 static void rx_start(SLMP_INFO
*info
);
588 static void rx_reset_buffers(SLMP_INFO
*info
);
589 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
);
590 static bool rx_get_frame(SLMP_INFO
*info
);
592 static void tx_start(SLMP_INFO
*info
);
593 static void tx_stop(SLMP_INFO
*info
);
594 static void tx_load_fifo(SLMP_INFO
*info
);
595 static void tx_set_idle(SLMP_INFO
*info
);
596 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
);
598 static void get_signals(SLMP_INFO
*info
);
599 static void set_signals(SLMP_INFO
*info
);
600 static void enable_loopback(SLMP_INFO
*info
, int enable
);
601 static void set_rate(SLMP_INFO
*info
, u32 data_rate
);
603 static int bh_action(SLMP_INFO
*info
);
604 static void bh_handler(struct work_struct
*work
);
605 static void bh_receive(SLMP_INFO
*info
);
606 static void bh_transmit(SLMP_INFO
*info
);
607 static void bh_status(SLMP_INFO
*info
);
608 static void isr_timer(SLMP_INFO
*info
);
609 static void isr_rxint(SLMP_INFO
*info
);
610 static void isr_rxrdy(SLMP_INFO
*info
);
611 static void isr_txint(SLMP_INFO
*info
);
612 static void isr_txrdy(SLMP_INFO
*info
);
613 static void isr_rxdmaok(SLMP_INFO
*info
);
614 static void isr_rxdmaerror(SLMP_INFO
*info
);
615 static void isr_txdmaok(SLMP_INFO
*info
);
616 static void isr_txdmaerror(SLMP_INFO
*info
);
617 static void isr_io_pin(SLMP_INFO
*info
, u16 status
);
619 static int alloc_dma_bufs(SLMP_INFO
*info
);
620 static void free_dma_bufs(SLMP_INFO
*info
);
621 static int alloc_buf_list(SLMP_INFO
*info
);
622 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*list
, SCADESC_EX
*list_ex
,int count
);
623 static int alloc_tmp_rx_buf(SLMP_INFO
*info
);
624 static void free_tmp_rx_buf(SLMP_INFO
*info
);
626 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
);
627 static void trace_block(SLMP_INFO
*info
, const char* data
, int count
, int xmit
);
628 static void tx_timeout(unsigned long context
);
629 static void status_timeout(unsigned long context
);
631 static unsigned char read_reg(SLMP_INFO
*info
, unsigned char addr
);
632 static void write_reg(SLMP_INFO
*info
, unsigned char addr
, unsigned char val
);
633 static u16
read_reg16(SLMP_INFO
*info
, unsigned char addr
);
634 static void write_reg16(SLMP_INFO
*info
, unsigned char addr
, u16 val
);
635 static unsigned char read_status_reg(SLMP_INFO
* info
);
636 static void write_control_reg(SLMP_INFO
* info
);
639 static unsigned char rx_active_fifo_level
= 16; // rx request FIFO activation level in bytes
640 static unsigned char tx_active_fifo_level
= 16; // tx request FIFO activation level in bytes
641 static unsigned char tx_negate_fifo_level
= 32; // tx request FIFO negation level in bytes
643 static u32 misc_ctrl_value
= 0x007e4040;
644 static u32 lcr1_brdr_value
= 0x00800028;
646 static u32 read_ahead_count
= 8;
648 /* DPCR, DMA Priority Control
650 * 07..05 Not used, must be 0
651 * 04 BRC, bus release condition: 0=all transfers complete
652 * 1=release after 1 xfer on all channels
653 * 03 CCC, channel change condition: 0=every cycle
654 * 1=after each channel completes all xfers
655 * 02..00 PR<2..0>, priority 100=round robin
659 static unsigned char dma_priority
= 0x04;
661 // Number of bytes that can be written to shared RAM
662 // in a single write operation
663 static u32 sca_pci_load_interval
= 64;
666 * 1st function defined in .text section. Calling this function in
667 * init_module() followed by a breakpoint allows a remote debugger
668 * (gdb) to get the .text address for the add-symbol-file command.
669 * This allows remote debugging of dynamically loadable modules.
671 static void* synclinkmp_get_text_ptr(void);
672 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr
;}
674 static inline int sanity_check(SLMP_INFO
*info
,
675 char *name
, const char *routine
)
678 static const char *badmagic
=
679 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
680 static const char *badinfo
=
681 "Warning: null synclinkmp_struct for (%s) in %s\n";
684 printk(badinfo
, name
, routine
);
687 if (info
->magic
!= MGSL_MAGIC
) {
688 printk(badmagic
, name
, routine
);
699 * line discipline callback wrappers
701 * The wrappers maintain line discipline references
702 * while calling into the line discipline.
704 * ldisc_receive_buf - pass receive data to line discipline
707 static void ldisc_receive_buf(struct tty_struct
*tty
,
708 const __u8
*data
, char *flags
, int count
)
710 struct tty_ldisc
*ld
;
713 ld
= tty_ldisc_ref(tty
);
716 ld
->receive_buf(tty
, data
, flags
, count
);
723 /* Called when a port is opened. Init and enable port.
725 static int open(struct tty_struct
*tty
, struct file
*filp
)
732 if ((line
< 0) || (line
>= synclinkmp_device_count
)) {
733 printk("%s(%d): open with invalid line #%d.\n",
734 __FILE__
,__LINE__
,line
);
738 info
= synclinkmp_device_list
;
739 while(info
&& info
->line
!= line
)
740 info
= info
->next_device
;
741 if (sanity_check(info
, tty
->name
, "open"))
743 if ( info
->init_error
) {
744 printk("%s(%d):%s device is not allocated, init error=%d\n",
745 __FILE__
,__LINE__
,info
->device_name
,info
->init_error
);
749 tty
->driver_data
= info
;
752 if (debug_level
>= DEBUG_LEVEL_INFO
)
753 printk("%s(%d):%s open(), old ref count = %d\n",
754 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
756 /* If port is closing, signal caller to try again */
757 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
758 if (info
->flags
& ASYNC_CLOSING
)
759 interruptible_sleep_on(&info
->close_wait
);
760 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
761 -EAGAIN
: -ERESTARTSYS
);
765 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
767 spin_lock_irqsave(&info
->netlock
, flags
);
768 if (info
->netcount
) {
770 spin_unlock_irqrestore(&info
->netlock
, flags
);
774 spin_unlock_irqrestore(&info
->netlock
, flags
);
776 if (info
->count
== 1) {
777 /* 1st open on this device, init hardware */
778 retval
= startup(info
);
783 retval
= block_til_ready(tty
, filp
, info
);
785 if (debug_level
>= DEBUG_LEVEL_INFO
)
786 printk("%s(%d):%s block_til_ready() returned %d\n",
787 __FILE__
,__LINE__
, info
->device_name
, retval
);
791 if (debug_level
>= DEBUG_LEVEL_INFO
)
792 printk("%s(%d):%s open() success\n",
793 __FILE__
,__LINE__
, info
->device_name
);
799 info
->tty
= NULL
; /* tty layer will release tty struct */
807 /* Called when port is closed. Wait for remaining data to be
808 * sent. Disable port and free resources.
810 static void close(struct tty_struct
*tty
, struct file
*filp
)
812 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
814 if (sanity_check(info
, tty
->name
, "close"))
817 if (debug_level
>= DEBUG_LEVEL_INFO
)
818 printk("%s(%d):%s close() entry, count=%d\n",
819 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
824 if (tty_hung_up_p(filp
))
827 if ((tty
->count
== 1) && (info
->count
!= 1)) {
829 * tty->count is 1 and the tty structure will be freed.
830 * info->count should be one in this case.
831 * if it's not, correct it so that the port is shutdown.
833 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
834 "info->count is %d\n",
835 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
841 /* if at least one open remaining, leave hardware active */
845 info
->flags
|= ASYNC_CLOSING
;
847 /* set tty->closing to notify line discipline to
848 * only process XON/XOFF characters. Only the N_TTY
849 * discipline appears to use this (ppp does not).
853 /* wait for transmit data to clear all layers */
855 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
856 if (debug_level
>= DEBUG_LEVEL_INFO
)
857 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
858 __FILE__
,__LINE__
, info
->device_name
);
859 tty_wait_until_sent(tty
, info
->closing_wait
);
862 if (info
->flags
& ASYNC_INITIALIZED
)
863 wait_until_sent(tty
, info
->timeout
);
865 if (tty
->driver
->flush_buffer
)
866 tty
->driver
->flush_buffer(tty
);
868 tty_ldisc_flush(tty
);
875 if (info
->blocked_open
) {
876 if (info
->close_delay
) {
877 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
879 wake_up_interruptible(&info
->open_wait
);
882 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
884 wake_up_interruptible(&info
->close_wait
);
887 if (debug_level
>= DEBUG_LEVEL_INFO
)
888 printk("%s(%d):%s close() exit, count=%d\n", __FILE__
,__LINE__
,
889 tty
->driver
->name
, info
->count
);
892 /* Called by tty_hangup() when a hangup is signaled.
893 * This is the same as closing all open descriptors for the port.
895 static void hangup(struct tty_struct
*tty
)
897 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
899 if (debug_level
>= DEBUG_LEVEL_INFO
)
900 printk("%s(%d):%s hangup()\n",
901 __FILE__
,__LINE__
, info
->device_name
);
903 if (sanity_check(info
, tty
->name
, "hangup"))
910 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
913 wake_up_interruptible(&info
->open_wait
);
916 /* Set new termios settings
918 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
920 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
923 if (debug_level
>= DEBUG_LEVEL_INFO
)
924 printk("%s(%d):%s set_termios()\n", __FILE__
,__LINE__
,
929 /* Handle transition to B0 status */
930 if (old_termios
->c_cflag
& CBAUD
&&
931 !(tty
->termios
->c_cflag
& CBAUD
)) {
932 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
933 spin_lock_irqsave(&info
->lock
,flags
);
935 spin_unlock_irqrestore(&info
->lock
,flags
);
938 /* Handle transition away from B0 status */
939 if (!(old_termios
->c_cflag
& CBAUD
) &&
940 tty
->termios
->c_cflag
& CBAUD
) {
941 info
->serial_signals
|= SerialSignal_DTR
;
942 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
943 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
944 info
->serial_signals
|= SerialSignal_RTS
;
946 spin_lock_irqsave(&info
->lock
,flags
);
948 spin_unlock_irqrestore(&info
->lock
,flags
);
951 /* Handle turning off CRTSCTS */
952 if (old_termios
->c_cflag
& CRTSCTS
&&
953 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
959 /* Send a block of data
963 * tty pointer to tty information structure
964 * buf pointer to buffer containing send data
965 * count size of send data in bytes
967 * Return Value: number of characters written
969 static int write(struct tty_struct
*tty
,
970 const unsigned char *buf
, int count
)
973 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
976 if (debug_level
>= DEBUG_LEVEL_INFO
)
977 printk("%s(%d):%s write() count=%d\n",
978 __FILE__
,__LINE__
,info
->device_name
,count
);
980 if (sanity_check(info
, tty
->name
, "write"))
986 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
987 if (count
> info
->max_frame_size
) {
993 if (info
->tx_count
) {
994 /* send accumulated data from send_char() calls */
995 /* as frame and wait before accepting more data. */
996 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
999 ret
= info
->tx_count
= count
;
1000 tx_load_dma_buffer(info
, buf
, count
);
1005 c
= min_t(int, count
,
1006 min(info
->max_frame_size
- info
->tx_count
- 1,
1007 info
->max_frame_size
- info
->tx_put
));
1011 memcpy(info
->tx_buf
+ info
->tx_put
, buf
, c
);
1013 spin_lock_irqsave(&info
->lock
,flags
);
1015 if (info
->tx_put
>= info
->max_frame_size
)
1016 info
->tx_put
-= info
->max_frame_size
;
1017 info
->tx_count
+= c
;
1018 spin_unlock_irqrestore(&info
->lock
,flags
);
1025 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1027 ret
= info
->tx_count
= 0;
1030 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
1033 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
1034 spin_lock_irqsave(&info
->lock
,flags
);
1035 if (!info
->tx_active
)
1037 spin_unlock_irqrestore(&info
->lock
,flags
);
1041 if (debug_level
>= DEBUG_LEVEL_INFO
)
1042 printk( "%s(%d):%s write() returning=%d\n",
1043 __FILE__
,__LINE__
,info
->device_name
,ret
);
1047 /* Add a character to the transmit buffer.
1049 static void put_char(struct tty_struct
*tty
, unsigned char ch
)
1051 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1052 unsigned long flags
;
1054 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
1055 printk( "%s(%d):%s put_char(%d)\n",
1056 __FILE__
,__LINE__
,info
->device_name
,ch
);
1059 if (sanity_check(info
, tty
->name
, "put_char"))
1065 spin_lock_irqsave(&info
->lock
,flags
);
1067 if ( (info
->params
.mode
!= MGSL_MODE_HDLC
) ||
1068 !info
->tx_active
) {
1070 if (info
->tx_count
< info
->max_frame_size
- 1) {
1071 info
->tx_buf
[info
->tx_put
++] = ch
;
1072 if (info
->tx_put
>= info
->max_frame_size
)
1073 info
->tx_put
-= info
->max_frame_size
;
1078 spin_unlock_irqrestore(&info
->lock
,flags
);
1081 /* Send a high-priority XON/XOFF character
1083 static void send_xchar(struct tty_struct
*tty
, char ch
)
1085 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1086 unsigned long flags
;
1088 if (debug_level
>= DEBUG_LEVEL_INFO
)
1089 printk("%s(%d):%s send_xchar(%d)\n",
1090 __FILE__
,__LINE__
, info
->device_name
, ch
);
1092 if (sanity_check(info
, tty
->name
, "send_xchar"))
1097 /* Make sure transmit interrupts are on */
1098 spin_lock_irqsave(&info
->lock
,flags
);
1099 if (!info
->tx_enabled
)
1101 spin_unlock_irqrestore(&info
->lock
,flags
);
1105 /* Wait until the transmitter is empty.
1107 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
1109 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1110 unsigned long orig_jiffies
, char_time
;
1115 if (debug_level
>= DEBUG_LEVEL_INFO
)
1116 printk("%s(%d):%s wait_until_sent() entry\n",
1117 __FILE__
,__LINE__
, info
->device_name
);
1119 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
1122 if (!(info
->flags
& ASYNC_INITIALIZED
))
1125 orig_jiffies
= jiffies
;
1127 /* Set check interval to 1/5 of estimated time to
1128 * send a character, and make it at least 1. The check
1129 * interval should also be less than the timeout.
1130 * Note: use tight timings here to satisfy the NIST-PCTS.
1133 if ( info
->params
.data_rate
) {
1134 char_time
= info
->timeout
/(32 * 5);
1141 char_time
= min_t(unsigned long, char_time
, timeout
);
1143 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
1144 while (info
->tx_active
) {
1145 msleep_interruptible(jiffies_to_msecs(char_time
));
1146 if (signal_pending(current
))
1148 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1152 //TODO: determine if there is something similar to USC16C32
1153 // TXSTATUS_ALL_SENT status
1154 while ( info
->tx_active
&& info
->tx_enabled
) {
1155 msleep_interruptible(jiffies_to_msecs(char_time
));
1156 if (signal_pending(current
))
1158 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1164 if (debug_level
>= DEBUG_LEVEL_INFO
)
1165 printk("%s(%d):%s wait_until_sent() exit\n",
1166 __FILE__
,__LINE__
, info
->device_name
);
1169 /* Return the count of free bytes in transmit buffer
1171 static int write_room(struct tty_struct
*tty
)
1173 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1176 if (sanity_check(info
, tty
->name
, "write_room"))
1179 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1180 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1182 ret
= info
->max_frame_size
- info
->tx_count
- 1;
1187 if (debug_level
>= DEBUG_LEVEL_INFO
)
1188 printk("%s(%d):%s write_room()=%d\n",
1189 __FILE__
, __LINE__
, info
->device_name
, ret
);
1194 /* enable transmitter and send remaining buffered characters
1196 static void flush_chars(struct tty_struct
*tty
)
1198 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1199 unsigned long flags
;
1201 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1202 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1203 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
1205 if (sanity_check(info
, tty
->name
, "flush_chars"))
1208 if (info
->tx_count
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
1212 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1213 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1214 __FILE__
,__LINE__
,info
->device_name
);
1216 spin_lock_irqsave(&info
->lock
,flags
);
1218 if (!info
->tx_active
) {
1219 if ( (info
->params
.mode
== MGSL_MODE_HDLC
) &&
1221 /* operating in synchronous (frame oriented) mode */
1222 /* copy data from circular tx_buf to */
1223 /* transmit DMA buffer. */
1224 tx_load_dma_buffer(info
,
1225 info
->tx_buf
,info
->tx_count
);
1230 spin_unlock_irqrestore(&info
->lock
,flags
);
1233 /* Discard all data in the send buffer
1235 static void flush_buffer(struct tty_struct
*tty
)
1237 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1238 unsigned long flags
;
1240 if (debug_level
>= DEBUG_LEVEL_INFO
)
1241 printk("%s(%d):%s flush_buffer() entry\n",
1242 __FILE__
,__LINE__
, info
->device_name
);
1244 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1247 spin_lock_irqsave(&info
->lock
,flags
);
1248 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
1249 del_timer(&info
->tx_timer
);
1250 spin_unlock_irqrestore(&info
->lock
,flags
);
1255 /* throttle (stop) transmitter
1257 static void tx_hold(struct tty_struct
*tty
)
1259 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1260 unsigned long flags
;
1262 if (sanity_check(info
, tty
->name
, "tx_hold"))
1265 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1266 printk("%s(%d):%s tx_hold()\n",
1267 __FILE__
,__LINE__
,info
->device_name
);
1269 spin_lock_irqsave(&info
->lock
,flags
);
1270 if (info
->tx_enabled
)
1272 spin_unlock_irqrestore(&info
->lock
,flags
);
1275 /* release (start) transmitter
1277 static void tx_release(struct tty_struct
*tty
)
1279 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1280 unsigned long flags
;
1282 if (sanity_check(info
, tty
->name
, "tx_release"))
1285 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1286 printk("%s(%d):%s tx_release()\n",
1287 __FILE__
,__LINE__
,info
->device_name
);
1289 spin_lock_irqsave(&info
->lock
,flags
);
1290 if (!info
->tx_enabled
)
1292 spin_unlock_irqrestore(&info
->lock
,flags
);
1295 /* Service an IOCTL request
1299 * tty pointer to tty instance data
1300 * file pointer to associated file object for device
1301 * cmd IOCTL command code
1302 * arg command argument/context
1304 * Return Value: 0 if success, otherwise error code
1306 static int do_ioctl(struct tty_struct
*tty
, struct file
*file
,
1307 unsigned int cmd
, unsigned long arg
)
1309 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1311 struct mgsl_icount cnow
; /* kernel counter temps */
1312 struct serial_icounter_struct __user
*p_cuser
; /* user space */
1313 unsigned long flags
;
1314 void __user
*argp
= (void __user
*)arg
;
1316 if (debug_level
>= DEBUG_LEVEL_INFO
)
1317 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__
,__LINE__
,
1318 info
->device_name
, cmd
);
1320 if (sanity_check(info
, tty
->name
, "ioctl"))
1323 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1324 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
1325 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1330 case MGSL_IOCGPARAMS
:
1331 return get_params(info
, argp
);
1332 case MGSL_IOCSPARAMS
:
1333 return set_params(info
, argp
);
1334 case MGSL_IOCGTXIDLE
:
1335 return get_txidle(info
, argp
);
1336 case MGSL_IOCSTXIDLE
:
1337 return set_txidle(info
, (int)arg
);
1338 case MGSL_IOCTXENABLE
:
1339 return tx_enable(info
, (int)arg
);
1340 case MGSL_IOCRXENABLE
:
1341 return rx_enable(info
, (int)arg
);
1342 case MGSL_IOCTXABORT
:
1343 return tx_abort(info
);
1344 case MGSL_IOCGSTATS
:
1345 return get_stats(info
, argp
);
1346 case MGSL_IOCWAITEVENT
:
1347 return wait_mgsl_event(info
, argp
);
1348 case MGSL_IOCLOOPTXDONE
:
1349 return 0; // TODO: Not supported, need to document
1350 /* Wait for modem input (DCD,RI,DSR,CTS) change
1351 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1354 return modem_input_wait(info
,(int)arg
);
1357 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1358 * Return: write counters to the user passed counter struct
1359 * NB: both 1->0 and 0->1 transitions are counted except for
1360 * RI where only 0->1 is counted.
1363 spin_lock_irqsave(&info
->lock
,flags
);
1364 cnow
= info
->icount
;
1365 spin_unlock_irqrestore(&info
->lock
,flags
);
1367 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
1368 if (error
) return error
;
1369 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
1370 if (error
) return error
;
1371 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
1372 if (error
) return error
;
1373 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
1374 if (error
) return error
;
1375 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
1376 if (error
) return error
;
1377 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
1378 if (error
) return error
;
1379 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
1380 if (error
) return error
;
1381 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
1382 if (error
) return error
;
1383 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
1384 if (error
) return error
;
1385 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
1386 if (error
) return error
;
1387 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
1388 if (error
) return error
;
1391 return -ENOIOCTLCMD
;
1396 static int ioctl(struct tty_struct
*tty
, struct file
*file
,
1397 unsigned int cmd
, unsigned long arg
)
1401 ret
= do_ioctl(tty
, file
, cmd
, arg
);
1407 * /proc fs routines....
1410 static inline int line_info(char *buf
, SLMP_INFO
*info
)
1414 unsigned long flags
;
1416 ret
= sprintf(buf
, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1417 "\tIRQ=%d MaxFrameSize=%u\n",
1419 info
->phys_sca_base
,
1420 info
->phys_memory_base
,
1421 info
->phys_statctrl_base
,
1422 info
->phys_lcr_base
,
1424 info
->max_frame_size
);
1426 /* output current serial signal states */
1427 spin_lock_irqsave(&info
->lock
,flags
);
1429 spin_unlock_irqrestore(&info
->lock
,flags
);
1433 if (info
->serial_signals
& SerialSignal_RTS
)
1434 strcat(stat_buf
, "|RTS");
1435 if (info
->serial_signals
& SerialSignal_CTS
)
1436 strcat(stat_buf
, "|CTS");
1437 if (info
->serial_signals
& SerialSignal_DTR
)
1438 strcat(stat_buf
, "|DTR");
1439 if (info
->serial_signals
& SerialSignal_DSR
)
1440 strcat(stat_buf
, "|DSR");
1441 if (info
->serial_signals
& SerialSignal_DCD
)
1442 strcat(stat_buf
, "|CD");
1443 if (info
->serial_signals
& SerialSignal_RI
)
1444 strcat(stat_buf
, "|RI");
1446 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1447 ret
+= sprintf(buf
+ret
, "\tHDLC txok:%d rxok:%d",
1448 info
->icount
.txok
, info
->icount
.rxok
);
1449 if (info
->icount
.txunder
)
1450 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
1451 if (info
->icount
.txabort
)
1452 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
1453 if (info
->icount
.rxshort
)
1454 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
1455 if (info
->icount
.rxlong
)
1456 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
1457 if (info
->icount
.rxover
)
1458 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
1459 if (info
->icount
.rxcrc
)
1460 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxcrc
);
1462 ret
+= sprintf(buf
+ret
, "\tASYNC tx:%d rx:%d",
1463 info
->icount
.tx
, info
->icount
.rx
);
1464 if (info
->icount
.frame
)
1465 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
1466 if (info
->icount
.parity
)
1467 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
1468 if (info
->icount
.brk
)
1469 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
1470 if (info
->icount
.overrun
)
1471 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
1474 /* Append serial signal status to end */
1475 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
1477 ret
+= sprintf(buf
+ret
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1478 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1484 /* Called to print information about devices
1486 static int read_proc(char *page
, char **start
, off_t off
, int count
,
1487 int *eof
, void *data
)
1493 len
+= sprintf(page
, "synclinkmp driver:%s\n", driver_version
);
1495 info
= synclinkmp_device_list
;
1497 l
= line_info(page
+ len
, info
);
1499 if (len
+begin
> off
+count
)
1501 if (len
+begin
< off
) {
1505 info
= info
->next_device
;
1510 if (off
>= len
+begin
)
1512 *start
= page
+ (off
-begin
);
1513 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
1516 /* Return the count of bytes in transmit buffer
1518 static int chars_in_buffer(struct tty_struct
*tty
)
1520 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1522 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1525 if (debug_level
>= DEBUG_LEVEL_INFO
)
1526 printk("%s(%d):%s chars_in_buffer()=%d\n",
1527 __FILE__
, __LINE__
, info
->device_name
, info
->tx_count
);
1529 return info
->tx_count
;
1532 /* Signal remote device to throttle send data (our receive data)
1534 static void throttle(struct tty_struct
* tty
)
1536 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1537 unsigned long flags
;
1539 if (debug_level
>= DEBUG_LEVEL_INFO
)
1540 printk("%s(%d):%s throttle() entry\n",
1541 __FILE__
,__LINE__
, info
->device_name
);
1543 if (sanity_check(info
, tty
->name
, "throttle"))
1547 send_xchar(tty
, STOP_CHAR(tty
));
1549 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1550 spin_lock_irqsave(&info
->lock
,flags
);
1551 info
->serial_signals
&= ~SerialSignal_RTS
;
1553 spin_unlock_irqrestore(&info
->lock
,flags
);
1557 /* Signal remote device to stop throttling send data (our receive data)
1559 static void unthrottle(struct tty_struct
* tty
)
1561 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1562 unsigned long flags
;
1564 if (debug_level
>= DEBUG_LEVEL_INFO
)
1565 printk("%s(%d):%s unthrottle() entry\n",
1566 __FILE__
,__LINE__
, info
->device_name
);
1568 if (sanity_check(info
, tty
->name
, "unthrottle"))
1575 send_xchar(tty
, START_CHAR(tty
));
1578 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1579 spin_lock_irqsave(&info
->lock
,flags
);
1580 info
->serial_signals
|= SerialSignal_RTS
;
1582 spin_unlock_irqrestore(&info
->lock
,flags
);
1586 /* set or clear transmit break condition
1587 * break_state -1=set break condition, 0=clear
1589 static void set_break(struct tty_struct
*tty
, int break_state
)
1591 unsigned char RegValue
;
1592 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1593 unsigned long flags
;
1595 if (debug_level
>= DEBUG_LEVEL_INFO
)
1596 printk("%s(%d):%s set_break(%d)\n",
1597 __FILE__
,__LINE__
, info
->device_name
, break_state
);
1599 if (sanity_check(info
, tty
->name
, "set_break"))
1602 spin_lock_irqsave(&info
->lock
,flags
);
1603 RegValue
= read_reg(info
, CTL
);
1604 if (break_state
== -1)
1608 write_reg(info
, CTL
, RegValue
);
1609 spin_unlock_irqrestore(&info
->lock
,flags
);
1612 #if SYNCLINK_GENERIC_HDLC
1615 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1616 * set encoding and frame check sequence (FCS) options
1618 * dev pointer to network device structure
1619 * encoding serial encoding setting
1620 * parity FCS setting
1622 * returns 0 if success, otherwise error code
1624 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1625 unsigned short parity
)
1627 SLMP_INFO
*info
= dev_to_port(dev
);
1628 unsigned char new_encoding
;
1629 unsigned short new_crctype
;
1631 /* return error if TTY interface open */
1637 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1638 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1639 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1640 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1641 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1642 default: return -EINVAL
;
1647 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1648 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1649 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1650 default: return -EINVAL
;
1653 info
->params
.encoding
= new_encoding
;
1654 info
->params
.crc_type
= new_crctype
;
1656 /* if network interface up, reprogram hardware */
1664 * called by generic HDLC layer to send frame
1666 * skb socket buffer containing HDLC frame
1667 * dev pointer to network device structure
1669 * returns 0 if success, otherwise error code
1671 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1673 SLMP_INFO
*info
= dev_to_port(dev
);
1674 struct net_device_stats
*stats
= hdlc_stats(dev
);
1675 unsigned long flags
;
1677 if (debug_level
>= DEBUG_LEVEL_INFO
)
1678 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
1680 /* stop sending until this frame completes */
1681 netif_stop_queue(dev
);
1683 /* copy data to device buffers */
1684 info
->tx_count
= skb
->len
;
1685 tx_load_dma_buffer(info
, skb
->data
, skb
->len
);
1687 /* update network statistics */
1688 stats
->tx_packets
++;
1689 stats
->tx_bytes
+= skb
->len
;
1691 /* done with socket buffer, so free it */
1694 /* save start time for transmit timeout detection */
1695 dev
->trans_start
= jiffies
;
1697 /* start hardware transmitter if necessary */
1698 spin_lock_irqsave(&info
->lock
,flags
);
1699 if (!info
->tx_active
)
1701 spin_unlock_irqrestore(&info
->lock
,flags
);
1707 * called by network layer when interface enabled
1708 * claim resources and initialize hardware
1710 * dev pointer to network device structure
1712 * returns 0 if success, otherwise error code
1714 static int hdlcdev_open(struct net_device
*dev
)
1716 SLMP_INFO
*info
= dev_to_port(dev
);
1718 unsigned long flags
;
1720 if (debug_level
>= DEBUG_LEVEL_INFO
)
1721 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
1723 /* generic HDLC layer open processing */
1724 if ((rc
= hdlc_open(dev
)))
1727 /* arbitrate between network and tty opens */
1728 spin_lock_irqsave(&info
->netlock
, flags
);
1729 if (info
->count
!= 0 || info
->netcount
!= 0) {
1730 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
1731 spin_unlock_irqrestore(&info
->netlock
, flags
);
1735 spin_unlock_irqrestore(&info
->netlock
, flags
);
1737 /* claim resources and init adapter */
1738 if ((rc
= startup(info
)) != 0) {
1739 spin_lock_irqsave(&info
->netlock
, flags
);
1741 spin_unlock_irqrestore(&info
->netlock
, flags
);
1745 /* assert DTR and RTS, apply hardware settings */
1746 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1749 /* enable network layer transmit */
1750 dev
->trans_start
= jiffies
;
1751 netif_start_queue(dev
);
1753 /* inform generic HDLC layer of current DCD status */
1754 spin_lock_irqsave(&info
->lock
, flags
);
1756 spin_unlock_irqrestore(&info
->lock
, flags
);
1757 if (info
->serial_signals
& SerialSignal_DCD
)
1758 netif_carrier_on(dev
);
1760 netif_carrier_off(dev
);
1765 * called by network layer when interface is disabled
1766 * shutdown hardware and release resources
1768 * dev pointer to network device structure
1770 * returns 0 if success, otherwise error code
1772 static int hdlcdev_close(struct net_device
*dev
)
1774 SLMP_INFO
*info
= dev_to_port(dev
);
1775 unsigned long flags
;
1777 if (debug_level
>= DEBUG_LEVEL_INFO
)
1778 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
1780 netif_stop_queue(dev
);
1782 /* shutdown adapter and release resources */
1787 spin_lock_irqsave(&info
->netlock
, flags
);
1789 spin_unlock_irqrestore(&info
->netlock
, flags
);
1795 * called by network layer to process IOCTL call to network device
1797 * dev pointer to network device structure
1798 * ifr pointer to network interface request structure
1799 * cmd IOCTL command code
1801 * returns 0 if success, otherwise error code
1803 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1805 const size_t size
= sizeof(sync_serial_settings
);
1806 sync_serial_settings new_line
;
1807 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1808 SLMP_INFO
*info
= dev_to_port(dev
);
1811 if (debug_level
>= DEBUG_LEVEL_INFO
)
1812 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
1814 /* return error if TTY interface open */
1818 if (cmd
!= SIOCWANDEV
)
1819 return hdlc_ioctl(dev
, ifr
, cmd
);
1821 switch(ifr
->ifr_settings
.type
) {
1822 case IF_GET_IFACE
: /* return current sync_serial_settings */
1824 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1825 if (ifr
->ifr_settings
.size
< size
) {
1826 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1830 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1831 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1832 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1833 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1836 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1837 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1838 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1839 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1840 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1843 new_line
.clock_rate
= info
->params
.clock_speed
;
1844 new_line
.loopback
= info
->params
.loopback
? 1:0;
1846 if (copy_to_user(line
, &new_line
, size
))
1850 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1852 if(!capable(CAP_NET_ADMIN
))
1854 if (copy_from_user(&new_line
, line
, size
))
1857 switch (new_line
.clock_type
)
1859 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1860 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1861 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1862 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1863 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1864 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1865 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1866 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1867 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1868 default: return -EINVAL
;
1871 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1874 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1875 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1876 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1877 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1878 info
->params
.flags
|= flags
;
1880 info
->params
.loopback
= new_line
.loopback
;
1882 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1883 info
->params
.clock_speed
= new_line
.clock_rate
;
1885 info
->params
.clock_speed
= 0;
1887 /* if network interface up, reprogram hardware */
1893 return hdlc_ioctl(dev
, ifr
, cmd
);
1898 * called by network layer when transmit timeout is detected
1900 * dev pointer to network device structure
1902 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1904 SLMP_INFO
*info
= dev_to_port(dev
);
1905 struct net_device_stats
*stats
= hdlc_stats(dev
);
1906 unsigned long flags
;
1908 if (debug_level
>= DEBUG_LEVEL_INFO
)
1909 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
1912 stats
->tx_aborted_errors
++;
1914 spin_lock_irqsave(&info
->lock
,flags
);
1916 spin_unlock_irqrestore(&info
->lock
,flags
);
1918 netif_wake_queue(dev
);
1922 * called by device driver when transmit completes
1923 * reenable network layer transmit if stopped
1925 * info pointer to device instance information
1927 static void hdlcdev_tx_done(SLMP_INFO
*info
)
1929 if (netif_queue_stopped(info
->netdev
))
1930 netif_wake_queue(info
->netdev
);
1934 * called by device driver when frame received
1935 * pass frame to network layer
1937 * info pointer to device instance information
1938 * buf pointer to buffer contianing frame data
1939 * size count of data bytes in buf
1941 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
)
1943 struct sk_buff
*skb
= dev_alloc_skb(size
);
1944 struct net_device
*dev
= info
->netdev
;
1945 struct net_device_stats
*stats
= hdlc_stats(dev
);
1947 if (debug_level
>= DEBUG_LEVEL_INFO
)
1948 printk("hdlcdev_rx(%s)\n",dev
->name
);
1951 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
1952 stats
->rx_dropped
++;
1956 memcpy(skb_put(skb
, size
),buf
,size
);
1958 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
1960 stats
->rx_packets
++;
1961 stats
->rx_bytes
+= size
;
1965 info
->netdev
->last_rx
= jiffies
;
1969 * called by device driver when adding device instance
1970 * do generic HDLC initialization
1972 * info pointer to device instance information
1974 * returns 0 if success, otherwise error code
1976 static int hdlcdev_init(SLMP_INFO
*info
)
1979 struct net_device
*dev
;
1982 /* allocate and initialize network and HDLC layer objects */
1984 if (!(dev
= alloc_hdlcdev(info
))) {
1985 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
1989 /* for network layer reporting purposes only */
1990 dev
->mem_start
= info
->phys_sca_base
;
1991 dev
->mem_end
= info
->phys_sca_base
+ SCA_BASE_SIZE
- 1;
1992 dev
->irq
= info
->irq_level
;
1994 /* network layer callbacks and settings */
1995 dev
->do_ioctl
= hdlcdev_ioctl
;
1996 dev
->open
= hdlcdev_open
;
1997 dev
->stop
= hdlcdev_close
;
1998 dev
->tx_timeout
= hdlcdev_tx_timeout
;
1999 dev
->watchdog_timeo
= 10*HZ
;
2000 dev
->tx_queue_len
= 50;
2002 /* generic HDLC layer callbacks and settings */
2003 hdlc
= dev_to_hdlc(dev
);
2004 hdlc
->attach
= hdlcdev_attach
;
2005 hdlc
->xmit
= hdlcdev_xmit
;
2007 /* register objects with HDLC layer */
2008 if ((rc
= register_hdlc_device(dev
))) {
2009 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
2019 * called by device driver when removing device instance
2020 * do generic HDLC cleanup
2022 * info pointer to device instance information
2024 static void hdlcdev_exit(SLMP_INFO
*info
)
2026 unregister_hdlc_device(info
->netdev
);
2027 free_netdev(info
->netdev
);
2028 info
->netdev
= NULL
;
2031 #endif /* CONFIG_HDLC */
2034 /* Return next bottom half action to perform.
2035 * Return Value: BH action code or 0 if nothing to do.
2037 static int bh_action(SLMP_INFO
*info
)
2039 unsigned long flags
;
2042 spin_lock_irqsave(&info
->lock
,flags
);
2044 if (info
->pending_bh
& BH_RECEIVE
) {
2045 info
->pending_bh
&= ~BH_RECEIVE
;
2047 } else if (info
->pending_bh
& BH_TRANSMIT
) {
2048 info
->pending_bh
&= ~BH_TRANSMIT
;
2050 } else if (info
->pending_bh
& BH_STATUS
) {
2051 info
->pending_bh
&= ~BH_STATUS
;
2056 /* Mark BH routine as complete */
2057 info
->bh_running
= false;
2058 info
->bh_requested
= false;
2061 spin_unlock_irqrestore(&info
->lock
,flags
);
2066 /* Perform bottom half processing of work items queued by ISR.
2068 static void bh_handler(struct work_struct
*work
)
2070 SLMP_INFO
*info
= container_of(work
, SLMP_INFO
, task
);
2076 if ( debug_level
>= DEBUG_LEVEL_BH
)
2077 printk( "%s(%d):%s bh_handler() entry\n",
2078 __FILE__
,__LINE__
,info
->device_name
);
2080 info
->bh_running
= true;
2082 while((action
= bh_action(info
)) != 0) {
2084 /* Process work item */
2085 if ( debug_level
>= DEBUG_LEVEL_BH
)
2086 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2087 __FILE__
,__LINE__
,info
->device_name
, action
);
2101 /* unknown work item ID */
2102 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2103 __FILE__
,__LINE__
,info
->device_name
,action
);
2108 if ( debug_level
>= DEBUG_LEVEL_BH
)
2109 printk( "%s(%d):%s bh_handler() exit\n",
2110 __FILE__
,__LINE__
,info
->device_name
);
2113 static void bh_receive(SLMP_INFO
*info
)
2115 if ( debug_level
>= DEBUG_LEVEL_BH
)
2116 printk( "%s(%d):%s bh_receive()\n",
2117 __FILE__
,__LINE__
,info
->device_name
);
2119 while( rx_get_frame(info
) );
2122 static void bh_transmit(SLMP_INFO
*info
)
2124 struct tty_struct
*tty
= info
->tty
;
2126 if ( debug_level
>= DEBUG_LEVEL_BH
)
2127 printk( "%s(%d):%s bh_transmit() entry\n",
2128 __FILE__
,__LINE__
,info
->device_name
);
2134 static void bh_status(SLMP_INFO
*info
)
2136 if ( debug_level
>= DEBUG_LEVEL_BH
)
2137 printk( "%s(%d):%s bh_status() entry\n",
2138 __FILE__
,__LINE__
,info
->device_name
);
2140 info
->ri_chkcount
= 0;
2141 info
->dsr_chkcount
= 0;
2142 info
->dcd_chkcount
= 0;
2143 info
->cts_chkcount
= 0;
2146 static void isr_timer(SLMP_INFO
* info
)
2148 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
2150 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2151 write_reg(info
, IER2
, 0);
2153 /* TMCS, Timer Control/Status Register
2155 * 07 CMF, Compare match flag (read only) 1=match
2156 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2157 * 05 Reserved, must be 0
2158 * 04 TME, Timer Enable
2159 * 03..00 Reserved, must be 0
2163 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0);
2165 info
->irq_occurred
= true;
2167 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2168 printk("%s(%d):%s isr_timer()\n",
2169 __FILE__
,__LINE__
,info
->device_name
);
2172 static void isr_rxint(SLMP_INFO
* info
)
2174 struct tty_struct
*tty
= info
->tty
;
2175 struct mgsl_icount
*icount
= &info
->icount
;
2176 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (FLGD
+ IDLD
+ CDCD
+ BRKD
);
2177 unsigned char status2
= read_reg(info
, SR2
) & info
->ie2_value
& OVRN
;
2179 /* clear status bits */
2181 write_reg(info
, SR1
, status
);
2184 write_reg(info
, SR2
, status2
);
2186 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2187 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2188 __FILE__
,__LINE__
,info
->device_name
,status
,status2
);
2190 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2191 if (status
& BRKD
) {
2194 /* process break detection if tty control
2195 * is not set to ignore it
2198 if (!(status
& info
->ignore_status_mask1
)) {
2199 if (info
->read_status_mask1
& BRKD
) {
2200 tty_insert_flip_char(tty
, 0, TTY_BREAK
);
2201 if (info
->flags
& ASYNC_SAK
)
2209 if (status
& (FLGD
|IDLD
)) {
2211 info
->icount
.exithunt
++;
2212 else if (status
& IDLD
)
2213 info
->icount
.rxidle
++;
2214 wake_up_interruptible(&info
->event_wait_q
);
2218 if (status
& CDCD
) {
2219 /* simulate a common modem status change interrupt
2222 get_signals( info
);
2224 MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
));
2229 * handle async rx data interrupts
2231 static void isr_rxrdy(SLMP_INFO
* info
)
2234 unsigned char DataByte
;
2235 struct tty_struct
*tty
= info
->tty
;
2236 struct mgsl_icount
*icount
= &info
->icount
;
2238 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2239 printk("%s(%d):%s isr_rxrdy\n",
2240 __FILE__
,__LINE__
,info
->device_name
);
2242 while((status
= read_reg(info
,CST0
)) & BIT0
)
2246 DataByte
= read_reg(info
,TRB
);
2250 if ( status
& (PE
+ FRME
+ OVRN
) ) {
2251 printk("%s(%d):%s rxerr=%04X\n",
2252 __FILE__
,__LINE__
,info
->device_name
,status
);
2254 /* update error statistics */
2257 else if (status
& FRME
)
2259 else if (status
& OVRN
)
2262 /* discard char if tty control flags say so */
2263 if (status
& info
->ignore_status_mask2
)
2266 status
&= info
->read_status_mask2
;
2271 else if (status
& FRME
)
2273 if (status
& OVRN
) {
2274 /* Overrun is special, since it's
2275 * reported immediately, and doesn't
2276 * affect the current character
2281 } /* end of if (error) */
2284 tty_insert_flip_char(tty
, DataByte
, flag
);
2286 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
2290 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
2291 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2292 __FILE__
,__LINE__
,info
->device_name
,
2293 icount
->rx
,icount
->brk
,icount
->parity
,
2294 icount
->frame
,icount
->overrun
);
2298 tty_flip_buffer_push(tty
);
2301 static void isr_txeom(SLMP_INFO
* info
, unsigned char status
)
2303 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2304 printk("%s(%d):%s isr_txeom status=%02x\n",
2305 __FILE__
,__LINE__
,info
->device_name
,status
);
2307 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2308 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2309 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2311 if (status
& UDRN
) {
2312 write_reg(info
, CMD
, TXRESET
);
2313 write_reg(info
, CMD
, TXENABLE
);
2315 write_reg(info
, CMD
, TXBUFCLR
);
2317 /* disable and clear tx interrupts */
2318 info
->ie0_value
&= ~TXRDYE
;
2319 info
->ie1_value
&= ~(IDLE
+ UDRN
);
2320 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2321 write_reg(info
, SR1
, (unsigned char)(UDRN
+ IDLE
));
2323 if ( info
->tx_active
) {
2324 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2326 info
->icount
.txunder
++;
2327 else if (status
& IDLE
)
2328 info
->icount
.txok
++;
2331 info
->tx_active
= false;
2332 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2334 del_timer(&info
->tx_timer
);
2336 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2337 info
->serial_signals
&= ~SerialSignal_RTS
;
2338 info
->drop_rts_on_tx_done
= false;
2342 #if SYNCLINK_GENERIC_HDLC
2344 hdlcdev_tx_done(info
);
2348 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2352 info
->pending_bh
|= BH_TRANSMIT
;
2359 * handle tx status interrupts
2361 static void isr_txint(SLMP_INFO
* info
)
2363 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (UDRN
+ IDLE
+ CCTS
);
2365 /* clear status bits */
2366 write_reg(info
, SR1
, status
);
2368 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2369 printk("%s(%d):%s isr_txint status=%02x\n",
2370 __FILE__
,__LINE__
,info
->device_name
,status
);
2372 if (status
& (UDRN
+ IDLE
))
2373 isr_txeom(info
, status
);
2375 if (status
& CCTS
) {
2376 /* simulate a common modem status change interrupt
2379 get_signals( info
);
2381 MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
));
2387 * handle async tx data interrupts
2389 static void isr_txrdy(SLMP_INFO
* info
)
2391 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2392 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2393 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
2395 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2396 /* disable TXRDY IRQ, enable IDLE IRQ */
2397 info
->ie0_value
&= ~TXRDYE
;
2398 info
->ie1_value
|= IDLE
;
2399 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2403 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2408 if ( info
->tx_count
)
2409 tx_load_fifo( info
);
2411 info
->tx_active
= false;
2412 info
->ie0_value
&= ~TXRDYE
;
2413 write_reg(info
, IE0
, info
->ie0_value
);
2416 if (info
->tx_count
< WAKEUP_CHARS
)
2417 info
->pending_bh
|= BH_TRANSMIT
;
2420 static void isr_rxdmaok(SLMP_INFO
* info
)
2422 /* BIT7 = EOT (end of transfer)
2423 * BIT6 = EOM (end of message/frame)
2425 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0xc0;
2427 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2428 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2430 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2431 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2432 __FILE__
,__LINE__
,info
->device_name
,status
);
2434 info
->pending_bh
|= BH_RECEIVE
;
2437 static void isr_rxdmaerror(SLMP_INFO
* info
)
2439 /* BIT5 = BOF (buffer overflow)
2440 * BIT4 = COF (counter overflow)
2442 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0x30;
2444 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2445 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2447 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2448 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2449 __FILE__
,__LINE__
,info
->device_name
,status
);
2451 info
->rx_overflow
= true;
2452 info
->pending_bh
|= BH_RECEIVE
;
2455 static void isr_txdmaok(SLMP_INFO
* info
)
2457 unsigned char status_reg1
= read_reg(info
, SR1
);
2459 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2460 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2461 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2463 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2464 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2465 __FILE__
,__LINE__
,info
->device_name
,status_reg1
);
2467 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2468 write_reg16(info
, TRC0
, 0);
2469 info
->ie0_value
|= TXRDYE
;
2470 write_reg(info
, IE0
, info
->ie0_value
);
2473 static void isr_txdmaerror(SLMP_INFO
* info
)
2475 /* BIT5 = BOF (buffer overflow)
2476 * BIT4 = COF (counter overflow)
2478 unsigned char status
= read_reg(info
,TXDMA
+ DSR
) & 0x30;
2480 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2481 write_reg(info
, TXDMA
+ DSR
, (unsigned char)(status
| 1));
2483 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2484 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2485 __FILE__
,__LINE__
,info
->device_name
,status
);
2488 /* handle input serial signal changes
2490 static void isr_io_pin( SLMP_INFO
*info
, u16 status
)
2492 struct mgsl_icount
*icount
;
2494 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2495 printk("%s(%d):isr_io_pin status=%04X\n",
2496 __FILE__
,__LINE__
,status
);
2498 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
2499 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
2500 icount
= &info
->icount
;
2501 /* update input line counters */
2502 if (status
& MISCSTATUS_RI_LATCHED
) {
2504 if ( status
& SerialSignal_RI
)
2505 info
->input_signal_events
.ri_up
++;
2507 info
->input_signal_events
.ri_down
++;
2509 if (status
& MISCSTATUS_DSR_LATCHED
) {
2511 if ( status
& SerialSignal_DSR
)
2512 info
->input_signal_events
.dsr_up
++;
2514 info
->input_signal_events
.dsr_down
++;
2516 if (status
& MISCSTATUS_DCD_LATCHED
) {
2517 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2518 info
->ie1_value
&= ~CDCD
;
2519 write_reg(info
, IE1
, info
->ie1_value
);
2522 if (status
& SerialSignal_DCD
) {
2523 info
->input_signal_events
.dcd_up
++;
2525 info
->input_signal_events
.dcd_down
++;
2526 #if SYNCLINK_GENERIC_HDLC
2527 if (info
->netcount
) {
2528 if (status
& SerialSignal_DCD
)
2529 netif_carrier_on(info
->netdev
);
2531 netif_carrier_off(info
->netdev
);
2535 if (status
& MISCSTATUS_CTS_LATCHED
)
2537 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2538 info
->ie1_value
&= ~CCTS
;
2539 write_reg(info
, IE1
, info
->ie1_value
);
2542 if ( status
& SerialSignal_CTS
)
2543 info
->input_signal_events
.cts_up
++;
2545 info
->input_signal_events
.cts_down
++;
2547 wake_up_interruptible(&info
->status_event_wait_q
);
2548 wake_up_interruptible(&info
->event_wait_q
);
2550 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
2551 (status
& MISCSTATUS_DCD_LATCHED
) ) {
2552 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2553 printk("%s CD now %s...", info
->device_name
,
2554 (status
& SerialSignal_DCD
) ? "on" : "off");
2555 if (status
& SerialSignal_DCD
)
2556 wake_up_interruptible(&info
->open_wait
);
2558 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2559 printk("doing serial hangup...");
2561 tty_hangup(info
->tty
);
2565 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
2566 (status
& MISCSTATUS_CTS_LATCHED
) ) {
2568 if (info
->tty
->hw_stopped
) {
2569 if (status
& SerialSignal_CTS
) {
2570 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2571 printk("CTS tx start...");
2572 info
->tty
->hw_stopped
= 0;
2574 info
->pending_bh
|= BH_TRANSMIT
;
2578 if (!(status
& SerialSignal_CTS
)) {
2579 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2580 printk("CTS tx stop...");
2581 info
->tty
->hw_stopped
= 1;
2589 info
->pending_bh
|= BH_STATUS
;
2592 /* Interrupt service routine entry point.
2595 * irq interrupt number that caused interrupt
2596 * dev_id device ID supplied during interrupt registration
2597 * regs interrupted processor context
2599 static irqreturn_t
synclinkmp_interrupt(int dummy
, void *dev_id
)
2601 SLMP_INFO
*info
= dev_id
;
2602 unsigned char status
, status0
, status1
=0;
2603 unsigned char dmastatus
, dmastatus0
, dmastatus1
=0;
2604 unsigned char timerstatus0
, timerstatus1
=0;
2605 unsigned char shift
;
2609 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2610 printk(KERN_DEBUG
"%s(%d): synclinkmp_interrupt(%d)entry.\n",
2611 __FILE__
, __LINE__
, info
->irq_level
);
2613 spin_lock(&info
->lock
);
2617 /* get status for SCA0 (ports 0-1) */
2618 tmp
= read_reg16(info
, ISR0
); /* get ISR0 and ISR1 in one read */
2619 status0
= (unsigned char)tmp
;
2620 dmastatus0
= (unsigned char)(tmp
>>8);
2621 timerstatus0
= read_reg(info
, ISR2
);
2623 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2624 printk(KERN_DEBUG
"%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2625 __FILE__
, __LINE__
, info
->device_name
,
2626 status0
, dmastatus0
, timerstatus0
);
2628 if (info
->port_count
== 4) {
2629 /* get status for SCA1 (ports 2-3) */
2630 tmp
= read_reg16(info
->port_array
[2], ISR0
);
2631 status1
= (unsigned char)tmp
;
2632 dmastatus1
= (unsigned char)(tmp
>>8);
2633 timerstatus1
= read_reg(info
->port_array
[2], ISR2
);
2635 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2636 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2637 __FILE__
,__LINE__
,info
->device_name
,
2638 status1
,dmastatus1
,timerstatus1
);
2641 if (!status0
&& !dmastatus0
&& !timerstatus0
&&
2642 !status1
&& !dmastatus1
&& !timerstatus1
)
2645 for(i
=0; i
< info
->port_count
; i
++) {
2646 if (info
->port_array
[i
] == NULL
)
2650 dmastatus
= dmastatus0
;
2653 dmastatus
= dmastatus1
;
2656 shift
= i
& 1 ? 4 :0;
2658 if (status
& BIT0
<< shift
)
2659 isr_rxrdy(info
->port_array
[i
]);
2660 if (status
& BIT1
<< shift
)
2661 isr_txrdy(info
->port_array
[i
]);
2662 if (status
& BIT2
<< shift
)
2663 isr_rxint(info
->port_array
[i
]);
2664 if (status
& BIT3
<< shift
)
2665 isr_txint(info
->port_array
[i
]);
2667 if (dmastatus
& BIT0
<< shift
)
2668 isr_rxdmaerror(info
->port_array
[i
]);
2669 if (dmastatus
& BIT1
<< shift
)
2670 isr_rxdmaok(info
->port_array
[i
]);
2671 if (dmastatus
& BIT2
<< shift
)
2672 isr_txdmaerror(info
->port_array
[i
]);
2673 if (dmastatus
& BIT3
<< shift
)
2674 isr_txdmaok(info
->port_array
[i
]);
2677 if (timerstatus0
& (BIT5
| BIT4
))
2678 isr_timer(info
->port_array
[0]);
2679 if (timerstatus0
& (BIT7
| BIT6
))
2680 isr_timer(info
->port_array
[1]);
2681 if (timerstatus1
& (BIT5
| BIT4
))
2682 isr_timer(info
->port_array
[2]);
2683 if (timerstatus1
& (BIT7
| BIT6
))
2684 isr_timer(info
->port_array
[3]);
2687 for(i
=0; i
< info
->port_count
; i
++) {
2688 SLMP_INFO
* port
= info
->port_array
[i
];
2690 /* Request bottom half processing if there's something
2691 * for it to do and the bh is not already running.
2693 * Note: startup adapter diags require interrupts.
2694 * do not request bottom half processing if the
2695 * device is not open in a normal mode.
2697 if ( port
&& (port
->count
|| port
->netcount
) &&
2698 port
->pending_bh
&& !port
->bh_running
&&
2699 !port
->bh_requested
) {
2700 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2701 printk("%s(%d):%s queueing bh task.\n",
2702 __FILE__
,__LINE__
,port
->device_name
);
2703 schedule_work(&port
->task
);
2704 port
->bh_requested
= true;
2708 spin_unlock(&info
->lock
);
2710 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2711 printk(KERN_DEBUG
"%s(%d):synclinkmp_interrupt(%d)exit.\n",
2712 __FILE__
, __LINE__
, info
->irq_level
);
2716 /* Initialize and start device.
2718 static int startup(SLMP_INFO
* info
)
2720 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2721 printk("%s(%d):%s tx_releaseup()\n",__FILE__
,__LINE__
,info
->device_name
);
2723 if (info
->flags
& ASYNC_INITIALIZED
)
2726 if (!info
->tx_buf
) {
2727 info
->tx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2728 if (!info
->tx_buf
) {
2729 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
2730 __FILE__
,__LINE__
,info
->device_name
);
2735 info
->pending_bh
= 0;
2737 memset(&info
->icount
, 0, sizeof(info
->icount
));
2739 /* program hardware for current parameters */
2742 change_params(info
);
2744 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
2747 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2749 info
->flags
|= ASYNC_INITIALIZED
;
2754 /* Called by close() and hangup() to shutdown hardware
2756 static void shutdown(SLMP_INFO
* info
)
2758 unsigned long flags
;
2760 if (!(info
->flags
& ASYNC_INITIALIZED
))
2763 if (debug_level
>= DEBUG_LEVEL_INFO
)
2764 printk("%s(%d):%s synclinkmp_shutdown()\n",
2765 __FILE__
,__LINE__
, info
->device_name
);
2767 /* clear status wait queue because status changes */
2768 /* can't happen after shutting down the hardware */
2769 wake_up_interruptible(&info
->status_event_wait_q
);
2770 wake_up_interruptible(&info
->event_wait_q
);
2772 del_timer(&info
->tx_timer
);
2773 del_timer(&info
->status_timer
);
2775 kfree(info
->tx_buf
);
2776 info
->tx_buf
= NULL
;
2778 spin_lock_irqsave(&info
->lock
,flags
);
2782 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
2783 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2787 spin_unlock_irqrestore(&info
->lock
,flags
);
2790 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2792 info
->flags
&= ~ASYNC_INITIALIZED
;
2795 static void program_hw(SLMP_INFO
*info
)
2797 unsigned long flags
;
2799 spin_lock_irqsave(&info
->lock
,flags
);
2804 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2806 if (info
->params
.mode
== MGSL_MODE_HDLC
|| info
->netcount
)
2813 info
->dcd_chkcount
= 0;
2814 info
->cts_chkcount
= 0;
2815 info
->ri_chkcount
= 0;
2816 info
->dsr_chkcount
= 0;
2818 info
->ie1_value
|= (CDCD
|CCTS
);
2819 write_reg(info
, IE1
, info
->ie1_value
);
2823 if (info
->netcount
|| (info
->tty
&& info
->tty
->termios
->c_cflag
& CREAD
) )
2826 spin_unlock_irqrestore(&info
->lock
,flags
);
2829 /* Reconfigure adapter based on new parameters
2831 static void change_params(SLMP_INFO
*info
)
2836 if (!info
->tty
|| !info
->tty
->termios
)
2839 if (debug_level
>= DEBUG_LEVEL_INFO
)
2840 printk("%s(%d):%s change_params()\n",
2841 __FILE__
,__LINE__
, info
->device_name
);
2843 cflag
= info
->tty
->termios
->c_cflag
;
2845 /* if B0 rate (hangup) specified then negate DTR and RTS */
2846 /* otherwise assert DTR and RTS */
2848 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2850 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2852 /* byte size and parity */
2854 switch (cflag
& CSIZE
) {
2855 case CS5
: info
->params
.data_bits
= 5; break;
2856 case CS6
: info
->params
.data_bits
= 6; break;
2857 case CS7
: info
->params
.data_bits
= 7; break;
2858 case CS8
: info
->params
.data_bits
= 8; break;
2859 /* Never happens, but GCC is too dumb to figure it out */
2860 default: info
->params
.data_bits
= 7; break;
2864 info
->params
.stop_bits
= 2;
2866 info
->params
.stop_bits
= 1;
2868 info
->params
.parity
= ASYNC_PARITY_NONE
;
2869 if (cflag
& PARENB
) {
2871 info
->params
.parity
= ASYNC_PARITY_ODD
;
2873 info
->params
.parity
= ASYNC_PARITY_EVEN
;
2876 info
->params
.parity
= ASYNC_PARITY_SPACE
;
2880 /* calculate number of jiffies to transmit a full
2881 * FIFO (32 bytes) at specified data rate
2883 bits_per_char
= info
->params
.data_bits
+
2884 info
->params
.stop_bits
+ 1;
2886 /* if port data rate is set to 460800 or less then
2887 * allow tty settings to override, otherwise keep the
2888 * current data rate.
2890 if (info
->params
.data_rate
<= 460800) {
2891 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2894 if ( info
->params
.data_rate
) {
2895 info
->timeout
= (32*HZ
*bits_per_char
) /
2896 info
->params
.data_rate
;
2898 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2900 if (cflag
& CRTSCTS
)
2901 info
->flags
|= ASYNC_CTS_FLOW
;
2903 info
->flags
&= ~ASYNC_CTS_FLOW
;
2906 info
->flags
&= ~ASYNC_CHECK_CD
;
2908 info
->flags
|= ASYNC_CHECK_CD
;
2910 /* process tty input control flags */
2912 info
->read_status_mask2
= OVRN
;
2913 if (I_INPCK(info
->tty
))
2914 info
->read_status_mask2
|= PE
| FRME
;
2915 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2916 info
->read_status_mask1
|= BRKD
;
2917 if (I_IGNPAR(info
->tty
))
2918 info
->ignore_status_mask2
|= PE
| FRME
;
2919 if (I_IGNBRK(info
->tty
)) {
2920 info
->ignore_status_mask1
|= BRKD
;
2921 /* If ignoring parity and break indicators, ignore
2922 * overruns too. (For real raw support).
2924 if (I_IGNPAR(info
->tty
))
2925 info
->ignore_status_mask2
|= OVRN
;
2931 static int get_stats(SLMP_INFO
* info
, struct mgsl_icount __user
*user_icount
)
2935 if (debug_level
>= DEBUG_LEVEL_INFO
)
2936 printk("%s(%d):%s get_params()\n",
2937 __FILE__
,__LINE__
, info
->device_name
);
2940 memset(&info
->icount
, 0, sizeof(info
->icount
));
2942 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2950 static int get_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*user_params
)
2953 if (debug_level
>= DEBUG_LEVEL_INFO
)
2954 printk("%s(%d):%s get_params()\n",
2955 __FILE__
,__LINE__
, info
->device_name
);
2957 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2959 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2960 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2961 __FILE__
,__LINE__
,info
->device_name
);
2968 static int set_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*new_params
)
2970 unsigned long flags
;
2971 MGSL_PARAMS tmp_params
;
2974 if (debug_level
>= DEBUG_LEVEL_INFO
)
2975 printk("%s(%d):%s set_params\n",
2976 __FILE__
,__LINE__
,info
->device_name
);
2977 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2979 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2980 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2981 __FILE__
,__LINE__
,info
->device_name
);
2985 spin_lock_irqsave(&info
->lock
,flags
);
2986 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2987 spin_unlock_irqrestore(&info
->lock
,flags
);
2989 change_params(info
);
2994 static int get_txidle(SLMP_INFO
* info
, int __user
*idle_mode
)
2998 if (debug_level
>= DEBUG_LEVEL_INFO
)
2999 printk("%s(%d):%s get_txidle()=%d\n",
3000 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
3002 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
3004 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3005 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3006 __FILE__
,__LINE__
,info
->device_name
);
3013 static int set_txidle(SLMP_INFO
* info
, int idle_mode
)
3015 unsigned long flags
;
3017 if (debug_level
>= DEBUG_LEVEL_INFO
)
3018 printk("%s(%d):%s set_txidle(%d)\n",
3019 __FILE__
,__LINE__
,info
->device_name
, idle_mode
);
3021 spin_lock_irqsave(&info
->lock
,flags
);
3022 info
->idle_mode
= idle_mode
;
3023 tx_set_idle( info
);
3024 spin_unlock_irqrestore(&info
->lock
,flags
);
3028 static int tx_enable(SLMP_INFO
* info
, int enable
)
3030 unsigned long flags
;
3032 if (debug_level
>= DEBUG_LEVEL_INFO
)
3033 printk("%s(%d):%s tx_enable(%d)\n",
3034 __FILE__
,__LINE__
,info
->device_name
, enable
);
3036 spin_lock_irqsave(&info
->lock
,flags
);
3038 if ( !info
->tx_enabled
) {
3042 if ( info
->tx_enabled
)
3045 spin_unlock_irqrestore(&info
->lock
,flags
);
3049 /* abort send HDLC frame
3051 static int tx_abort(SLMP_INFO
* info
)
3053 unsigned long flags
;
3055 if (debug_level
>= DEBUG_LEVEL_INFO
)
3056 printk("%s(%d):%s tx_abort()\n",
3057 __FILE__
,__LINE__
,info
->device_name
);
3059 spin_lock_irqsave(&info
->lock
,flags
);
3060 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
3061 info
->ie1_value
&= ~UDRN
;
3062 info
->ie1_value
|= IDLE
;
3063 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
3064 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
3066 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
3067 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
3069 write_reg(info
, CMD
, TXABORT
);
3071 spin_unlock_irqrestore(&info
->lock
,flags
);
3075 static int rx_enable(SLMP_INFO
* info
, int enable
)
3077 unsigned long flags
;
3079 if (debug_level
>= DEBUG_LEVEL_INFO
)
3080 printk("%s(%d):%s rx_enable(%d)\n",
3081 __FILE__
,__LINE__
,info
->device_name
,enable
);
3083 spin_lock_irqsave(&info
->lock
,flags
);
3085 if ( !info
->rx_enabled
)
3088 if ( info
->rx_enabled
)
3091 spin_unlock_irqrestore(&info
->lock
,flags
);
3095 /* wait for specified event to occur
3097 static int wait_mgsl_event(SLMP_INFO
* info
, int __user
*mask_ptr
)
3099 unsigned long flags
;
3102 struct mgsl_icount cprev
, cnow
;
3105 struct _input_signal_events oldsigs
, newsigs
;
3106 DECLARE_WAITQUEUE(wait
, current
);
3108 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
3113 if (debug_level
>= DEBUG_LEVEL_INFO
)
3114 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3115 __FILE__
,__LINE__
,info
->device_name
,mask
);
3117 spin_lock_irqsave(&info
->lock
,flags
);
3119 /* return immediately if state matches requested events */
3121 s
= info
->serial_signals
;
3124 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
3125 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
3126 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
3127 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
3129 spin_unlock_irqrestore(&info
->lock
,flags
);
3133 /* save current irq counts */
3134 cprev
= info
->icount
;
3135 oldsigs
= info
->input_signal_events
;
3137 /* enable hunt and idle irqs if needed */
3138 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
3139 unsigned char oldval
= info
->ie1_value
;
3140 unsigned char newval
= oldval
+
3141 (mask
& MgslEvent_ExitHuntMode
? FLGD
:0) +
3142 (mask
& MgslEvent_IdleReceived
? IDLD
:0);
3143 if ( oldval
!= newval
) {
3144 info
->ie1_value
= newval
;
3145 write_reg(info
, IE1
, info
->ie1_value
);
3149 set_current_state(TASK_INTERRUPTIBLE
);
3150 add_wait_queue(&info
->event_wait_q
, &wait
);
3152 spin_unlock_irqrestore(&info
->lock
,flags
);
3156 if (signal_pending(current
)) {
3161 /* get current irq counts */
3162 spin_lock_irqsave(&info
->lock
,flags
);
3163 cnow
= info
->icount
;
3164 newsigs
= info
->input_signal_events
;
3165 set_current_state(TASK_INTERRUPTIBLE
);
3166 spin_unlock_irqrestore(&info
->lock
,flags
);
3168 /* if no change, wait aborted for some reason */
3169 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
3170 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
3171 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
3172 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
3173 newsigs
.cts_up
== oldsigs
.cts_up
&&
3174 newsigs
.cts_down
== oldsigs
.cts_down
&&
3175 newsigs
.ri_up
== oldsigs
.ri_up
&&
3176 newsigs
.ri_down
== oldsigs
.ri_down
&&
3177 cnow
.exithunt
== cprev
.exithunt
&&
3178 cnow
.rxidle
== cprev
.rxidle
) {
3184 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
3185 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
3186 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
3187 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
3188 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
3189 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
3190 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
3191 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
3192 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
3193 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
3201 remove_wait_queue(&info
->event_wait_q
, &wait
);
3202 set_current_state(TASK_RUNNING
);
3205 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
3206 spin_lock_irqsave(&info
->lock
,flags
);
3207 if (!waitqueue_active(&info
->event_wait_q
)) {
3208 /* disable enable exit hunt mode/idle rcvd IRQs */
3209 info
->ie1_value
&= ~(FLGD
|IDLD
);
3210 write_reg(info
, IE1
, info
->ie1_value
);
3212 spin_unlock_irqrestore(&info
->lock
,flags
);
3216 PUT_USER(rc
, events
, mask_ptr
);
3221 static int modem_input_wait(SLMP_INFO
*info
,int arg
)
3223 unsigned long flags
;
3225 struct mgsl_icount cprev
, cnow
;
3226 DECLARE_WAITQUEUE(wait
, current
);
3228 /* save current irq counts */
3229 spin_lock_irqsave(&info
->lock
,flags
);
3230 cprev
= info
->icount
;
3231 add_wait_queue(&info
->status_event_wait_q
, &wait
);
3232 set_current_state(TASK_INTERRUPTIBLE
);
3233 spin_unlock_irqrestore(&info
->lock
,flags
);
3237 if (signal_pending(current
)) {
3242 /* get new irq counts */
3243 spin_lock_irqsave(&info
->lock
,flags
);
3244 cnow
= info
->icount
;
3245 set_current_state(TASK_INTERRUPTIBLE
);
3246 spin_unlock_irqrestore(&info
->lock
,flags
);
3248 /* if no change, wait aborted for some reason */
3249 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
3250 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
3255 /* check for change in caller specified modem input */
3256 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
3257 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
3258 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
3259 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
3266 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
3267 set_current_state(TASK_RUNNING
);
3271 /* return the state of the serial control and status signals
3273 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
3275 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3276 unsigned int result
;
3277 unsigned long flags
;
3279 spin_lock_irqsave(&info
->lock
,flags
);
3281 spin_unlock_irqrestore(&info
->lock
,flags
);
3283 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
3284 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
3285 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
3286 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
3287 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
3288 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
3290 if (debug_level
>= DEBUG_LEVEL_INFO
)
3291 printk("%s(%d):%s tiocmget() value=%08X\n",
3292 __FILE__
,__LINE__
, info
->device_name
, result
);
3296 /* set modem control signals (DTR/RTS)
3298 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
3299 unsigned int set
, unsigned int clear
)
3301 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3302 unsigned long flags
;
3304 if (debug_level
>= DEBUG_LEVEL_INFO
)
3305 printk("%s(%d):%s tiocmset(%x,%x)\n",
3306 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
3308 if (set
& TIOCM_RTS
)
3309 info
->serial_signals
|= SerialSignal_RTS
;
3310 if (set
& TIOCM_DTR
)
3311 info
->serial_signals
|= SerialSignal_DTR
;
3312 if (clear
& TIOCM_RTS
)
3313 info
->serial_signals
&= ~SerialSignal_RTS
;
3314 if (clear
& TIOCM_DTR
)
3315 info
->serial_signals
&= ~SerialSignal_DTR
;
3317 spin_lock_irqsave(&info
->lock
,flags
);
3319 spin_unlock_irqrestore(&info
->lock
,flags
);
3326 /* Block the current process until the specified port is ready to open.
3328 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
3331 DECLARE_WAITQUEUE(wait
, current
);
3333 bool do_clocal
= false;
3334 bool extra_count
= false;
3335 unsigned long flags
;
3337 if (debug_level
>= DEBUG_LEVEL_INFO
)
3338 printk("%s(%d):%s block_til_ready()\n",
3339 __FILE__
,__LINE__
, tty
->driver
->name
);
3341 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3342 /* nonblock mode is set or port is not enabled */
3343 /* just verify that callout device is not active */
3344 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3348 if (tty
->termios
->c_cflag
& CLOCAL
)
3351 /* Wait for carrier detect and the line to become
3352 * free (i.e., not in use by the callout). While we are in
3353 * this loop, info->count is dropped by one, so that
3354 * close() knows when to free things. We restore it upon
3355 * exit, either normal or abnormal.
3359 add_wait_queue(&info
->open_wait
, &wait
);
3361 if (debug_level
>= DEBUG_LEVEL_INFO
)
3362 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3363 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3365 spin_lock_irqsave(&info
->lock
, flags
);
3366 if (!tty_hung_up_p(filp
)) {
3370 spin_unlock_irqrestore(&info
->lock
, flags
);
3371 info
->blocked_open
++;
3374 if ((tty
->termios
->c_cflag
& CBAUD
)) {
3375 spin_lock_irqsave(&info
->lock
,flags
);
3376 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3378 spin_unlock_irqrestore(&info
->lock
,flags
);
3381 set_current_state(TASK_INTERRUPTIBLE
);
3383 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3384 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3385 -EAGAIN
: -ERESTARTSYS
;
3389 spin_lock_irqsave(&info
->lock
,flags
);
3391 spin_unlock_irqrestore(&info
->lock
,flags
);
3393 if (!(info
->flags
& ASYNC_CLOSING
) &&
3394 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3398 if (signal_pending(current
)) {
3399 retval
= -ERESTARTSYS
;
3403 if (debug_level
>= DEBUG_LEVEL_INFO
)
3404 printk("%s(%d):%s block_til_ready() count=%d\n",
3405 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3410 set_current_state(TASK_RUNNING
);
3411 remove_wait_queue(&info
->open_wait
, &wait
);
3415 info
->blocked_open
--;
3417 if (debug_level
>= DEBUG_LEVEL_INFO
)
3418 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3419 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3422 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3427 static int alloc_dma_bufs(SLMP_INFO
*info
)
3429 unsigned short BuffersPerFrame
;
3430 unsigned short BufferCount
;
3432 // Force allocation to start at 64K boundary for each port.
3433 // This is necessary because *all* buffer descriptors for a port
3434 // *must* be in the same 64K block. All descriptors on a port
3435 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3436 // into the CBP register.
3437 info
->port_array
[0]->last_mem_alloc
= (SCA_MEM_SIZE
/4) * info
->port_num
;
3439 /* Calculate the number of DMA buffers necessary to hold the */
3440 /* largest allowable frame size. Note: If the max frame size is */
3441 /* not an even multiple of the DMA buffer size then we need to */
3442 /* round the buffer count per frame up one. */
3444 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/SCABUFSIZE
);
3445 if ( info
->max_frame_size
% SCABUFSIZE
)
3448 /* calculate total number of data buffers (SCABUFSIZE) possible
3449 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3450 * for the descriptor list (BUFFERLISTSIZE).
3452 BufferCount
= (SCA_MEM_SIZE
/4 - BUFFERLISTSIZE
)/SCABUFSIZE
;
3454 /* limit number of buffers to maximum amount of descriptors */
3455 if (BufferCount
> BUFFERLISTSIZE
/sizeof(SCADESC
))
3456 BufferCount
= BUFFERLISTSIZE
/sizeof(SCADESC
);
3458 /* use enough buffers to transmit one max size frame */
3459 info
->tx_buf_count
= BuffersPerFrame
+ 1;
3461 /* never use more than half the available buffers for transmit */
3462 if (info
->tx_buf_count
> (BufferCount
/2))
3463 info
->tx_buf_count
= BufferCount
/2;
3465 if (info
->tx_buf_count
> SCAMAXDESC
)
3466 info
->tx_buf_count
= SCAMAXDESC
;
3468 /* use remaining buffers for receive */
3469 info
->rx_buf_count
= BufferCount
- info
->tx_buf_count
;
3471 if (info
->rx_buf_count
> SCAMAXDESC
)
3472 info
->rx_buf_count
= SCAMAXDESC
;
3474 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3475 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3476 __FILE__
,__LINE__
, info
->device_name
,
3477 info
->tx_buf_count
,info
->rx_buf_count
);
3479 if ( alloc_buf_list( info
) < 0 ||
3480 alloc_frame_bufs(info
,
3482 info
->rx_buf_list_ex
,
3483 info
->rx_buf_count
) < 0 ||
3484 alloc_frame_bufs(info
,
3486 info
->tx_buf_list_ex
,
3487 info
->tx_buf_count
) < 0 ||
3488 alloc_tmp_rx_buf(info
) < 0 ) {
3489 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3490 __FILE__
,__LINE__
, info
->device_name
);
3494 rx_reset_buffers( info
);
3499 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3501 static int alloc_buf_list(SLMP_INFO
*info
)
3505 /* build list in adapter shared memory */
3506 info
->buffer_list
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3507 info
->buffer_list_phys
= info
->port_array
[0]->last_mem_alloc
;
3508 info
->port_array
[0]->last_mem_alloc
+= BUFFERLISTSIZE
;
3510 memset(info
->buffer_list
, 0, BUFFERLISTSIZE
);
3512 /* Save virtual address pointers to the receive and */
3513 /* transmit buffer lists. (Receive 1st). These pointers will */
3514 /* be used by the processor to access the lists. */
3515 info
->rx_buf_list
= (SCADESC
*)info
->buffer_list
;
3517 info
->tx_buf_list
= (SCADESC
*)info
->buffer_list
;
3518 info
->tx_buf_list
+= info
->rx_buf_count
;
3520 /* Build links for circular buffer entry lists (tx and rx)
3522 * Note: links are physical addresses read by the SCA device
3523 * to determine the next buffer entry to use.
3526 for ( i
= 0; i
< info
->rx_buf_count
; i
++ ) {
3527 /* calculate and store physical address of this buffer entry */
3528 info
->rx_buf_list_ex
[i
].phys_entry
=
3529 info
->buffer_list_phys
+ (i
* sizeof(SCABUFSIZE
));
3531 /* calculate and store physical address of */
3532 /* next entry in cirular list of entries */
3533 info
->rx_buf_list
[i
].next
= info
->buffer_list_phys
;
3534 if ( i
< info
->rx_buf_count
- 1 )
3535 info
->rx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3537 info
->rx_buf_list
[i
].length
= SCABUFSIZE
;
3540 for ( i
= 0; i
< info
->tx_buf_count
; i
++ ) {
3541 /* calculate and store physical address of this buffer entry */
3542 info
->tx_buf_list_ex
[i
].phys_entry
= info
->buffer_list_phys
+
3543 ((info
->rx_buf_count
+ i
) * sizeof(SCADESC
));
3545 /* calculate and store physical address of */
3546 /* next entry in cirular list of entries */
3548 info
->tx_buf_list
[i
].next
= info
->buffer_list_phys
+
3549 info
->rx_buf_count
* sizeof(SCADESC
);
3551 if ( i
< info
->tx_buf_count
- 1 )
3552 info
->tx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3558 /* Allocate the frame DMA buffers used by the specified buffer list.
3560 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*buf_list
,SCADESC_EX
*buf_list_ex
,int count
)
3563 unsigned long phys_addr
;
3565 for ( i
= 0; i
< count
; i
++ ) {
3566 buf_list_ex
[i
].virt_addr
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3567 phys_addr
= info
->port_array
[0]->last_mem_alloc
;
3568 info
->port_array
[0]->last_mem_alloc
+= SCABUFSIZE
;
3570 buf_list
[i
].buf_ptr
= (unsigned short)phys_addr
;
3571 buf_list
[i
].buf_base
= (unsigned char)(phys_addr
>> 16);
3577 static void free_dma_bufs(SLMP_INFO
*info
)
3579 info
->buffer_list
= NULL
;
3580 info
->rx_buf_list
= NULL
;
3581 info
->tx_buf_list
= NULL
;
3584 /* allocate buffer large enough to hold max_frame_size.
3585 * This buffer is used to pass an assembled frame to the line discipline.
3587 static int alloc_tmp_rx_buf(SLMP_INFO
*info
)
3589 info
->tmp_rx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3590 if (info
->tmp_rx_buf
== NULL
)
3595 static void free_tmp_rx_buf(SLMP_INFO
*info
)
3597 kfree(info
->tmp_rx_buf
);
3598 info
->tmp_rx_buf
= NULL
;
3601 static int claim_resources(SLMP_INFO
*info
)
3603 if (request_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
,"synclinkmp") == NULL
) {
3604 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3605 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3606 info
->init_error
= DiagStatus_AddressConflict
;
3610 info
->shared_mem_requested
= true;
3612 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclinkmp") == NULL
) {
3613 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3614 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3615 info
->init_error
= DiagStatus_AddressConflict
;
3619 info
->lcr_mem_requested
= true;
3621 if (request_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
,"synclinkmp") == NULL
) {
3622 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3623 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3624 info
->init_error
= DiagStatus_AddressConflict
;
3628 info
->sca_base_requested
= true;
3630 if (request_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
,"synclinkmp") == NULL
) {
3631 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3632 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3633 info
->init_error
= DiagStatus_AddressConflict
;
3637 info
->sca_statctrl_requested
= true;
3639 info
->memory_base
= ioremap(info
->phys_memory_base
,SCA_MEM_SIZE
);
3640 if (!info
->memory_base
) {
3641 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3642 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3643 info
->init_error
= DiagStatus_CantAssignPciResources
;
3647 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
);
3648 if (!info
->lcr_base
) {
3649 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3650 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3651 info
->init_error
= DiagStatus_CantAssignPciResources
;
3654 info
->lcr_base
+= info
->lcr_offset
;
3656 info
->sca_base
= ioremap(info
->phys_sca_base
,PAGE_SIZE
);
3657 if (!info
->sca_base
) {
3658 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3659 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3660 info
->init_error
= DiagStatus_CantAssignPciResources
;
3663 info
->sca_base
+= info
->sca_offset
;
3665 info
->statctrl_base
= ioremap(info
->phys_statctrl_base
,PAGE_SIZE
);
3666 if (!info
->statctrl_base
) {
3667 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3668 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3669 info
->init_error
= DiagStatus_CantAssignPciResources
;
3672 info
->statctrl_base
+= info
->statctrl_offset
;
3674 if ( !memory_test(info
) ) {
3675 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3676 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3677 info
->init_error
= DiagStatus_MemoryError
;
3684 release_resources( info
);
3688 static void release_resources(SLMP_INFO
*info
)
3690 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3691 printk( "%s(%d):%s release_resources() entry\n",
3692 __FILE__
,__LINE__
,info
->device_name
);
3694 if ( info
->irq_requested
) {
3695 free_irq(info
->irq_level
, info
);
3696 info
->irq_requested
= false;
3699 if ( info
->shared_mem_requested
) {
3700 release_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
);
3701 info
->shared_mem_requested
= false;
3703 if ( info
->lcr_mem_requested
) {
3704 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
3705 info
->lcr_mem_requested
= false;
3707 if ( info
->sca_base_requested
) {
3708 release_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
);
3709 info
->sca_base_requested
= false;
3711 if ( info
->sca_statctrl_requested
) {
3712 release_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
);
3713 info
->sca_statctrl_requested
= false;
3716 if (info
->memory_base
){
3717 iounmap(info
->memory_base
);
3718 info
->memory_base
= NULL
;
3721 if (info
->sca_base
) {
3722 iounmap(info
->sca_base
- info
->sca_offset
);
3723 info
->sca_base
=NULL
;
3726 if (info
->statctrl_base
) {
3727 iounmap(info
->statctrl_base
- info
->statctrl_offset
);
3728 info
->statctrl_base
=NULL
;
3731 if (info
->lcr_base
){
3732 iounmap(info
->lcr_base
- info
->lcr_offset
);
3733 info
->lcr_base
= NULL
;
3736 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3737 printk( "%s(%d):%s release_resources() exit\n",
3738 __FILE__
,__LINE__
,info
->device_name
);
3741 /* Add the specified device instance data structure to the
3742 * global linked list of devices and increment the device count.
3744 static void add_device(SLMP_INFO
*info
)
3746 info
->next_device
= NULL
;
3747 info
->line
= synclinkmp_device_count
;
3748 sprintf(info
->device_name
,"ttySLM%dp%d",info
->adapter_num
,info
->port_num
);
3750 if (info
->line
< MAX_DEVICES
) {
3751 if (maxframe
[info
->line
])
3752 info
->max_frame_size
= maxframe
[info
->line
];
3753 info
->dosyncppp
= dosyncppp
[info
->line
];
3756 synclinkmp_device_count
++;
3758 if ( !synclinkmp_device_list
)
3759 synclinkmp_device_list
= info
;
3761 SLMP_INFO
*current_dev
= synclinkmp_device_list
;
3762 while( current_dev
->next_device
)
3763 current_dev
= current_dev
->next_device
;
3764 current_dev
->next_device
= info
;
3767 if ( info
->max_frame_size
< 4096 )
3768 info
->max_frame_size
= 4096;
3769 else if ( info
->max_frame_size
> 65535 )
3770 info
->max_frame_size
= 65535;
3772 printk( "SyncLink MultiPort %s: "
3773 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3775 info
->phys_sca_base
,
3776 info
->phys_memory_base
,
3777 info
->phys_statctrl_base
,
3778 info
->phys_lcr_base
,
3780 info
->max_frame_size
);
3782 #if SYNCLINK_GENERIC_HDLC
3787 /* Allocate and initialize a device instance structure
3789 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3791 static SLMP_INFO
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3795 info
= kzalloc(sizeof(SLMP_INFO
),
3799 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3800 __FILE__
,__LINE__
, adapter_num
, port_num
);
3802 info
->magic
= MGSL_MAGIC
;
3803 INIT_WORK(&info
->task
, bh_handler
);
3804 info
->max_frame_size
= 4096;
3805 info
->close_delay
= 5*HZ
/10;
3806 info
->closing_wait
= 30*HZ
;
3807 init_waitqueue_head(&info
->open_wait
);
3808 init_waitqueue_head(&info
->close_wait
);
3809 init_waitqueue_head(&info
->status_event_wait_q
);
3810 init_waitqueue_head(&info
->event_wait_q
);
3811 spin_lock_init(&info
->netlock
);
3812 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3813 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3814 info
->adapter_num
= adapter_num
;
3815 info
->port_num
= port_num
;
3817 /* Copy configuration info to device instance data */
3818 info
->irq_level
= pdev
->irq
;
3819 info
->phys_lcr_base
= pci_resource_start(pdev
,0);
3820 info
->phys_sca_base
= pci_resource_start(pdev
,2);
3821 info
->phys_memory_base
= pci_resource_start(pdev
,3);
3822 info
->phys_statctrl_base
= pci_resource_start(pdev
,4);
3824 /* Because veremap only works on page boundaries we must map
3825 * a larger area than is actually implemented for the LCR
3826 * memory range. We map a full page starting at the page boundary.
3828 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
3829 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
3831 info
->sca_offset
= info
->phys_sca_base
& (PAGE_SIZE
-1);
3832 info
->phys_sca_base
&= ~(PAGE_SIZE
-1);
3834 info
->statctrl_offset
= info
->phys_statctrl_base
& (PAGE_SIZE
-1);
3835 info
->phys_statctrl_base
&= ~(PAGE_SIZE
-1);
3837 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3838 info
->irq_flags
= IRQF_SHARED
;
3840 setup_timer(&info
->tx_timer
, tx_timeout
, (unsigned long)info
);
3841 setup_timer(&info
->status_timer
, status_timeout
,
3842 (unsigned long)info
);
3844 /* Store the PCI9050 misc control register value because a flaw
3845 * in the PCI9050 prevents LCR registers from being read if
3846 * BIOS assigns an LCR base address with bit 7 set.
3848 * Only the misc control register is accessed for which only
3849 * write access is needed, so set an initial value and change
3850 * bits to the device instance data as we write the value
3851 * to the actual misc control register.
3853 info
->misc_ctrl_value
= 0x087e4546;
3855 /* initial port state is unknown - if startup errors
3856 * occur, init_error will be set to indicate the
3857 * problem. Once the port is fully initialized,
3858 * this value will be set to 0 to indicate the
3859 * port is available.
3861 info
->init_error
= -1;
3867 static void device_init(int adapter_num
, struct pci_dev
*pdev
)
3869 SLMP_INFO
*port_array
[SCA_MAX_PORTS
];
3872 /* allocate device instances for up to SCA_MAX_PORTS devices */
3873 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3874 port_array
[port
] = alloc_dev(adapter_num
,port
,pdev
);
3875 if( port_array
[port
] == NULL
) {
3876 for ( --port
; port
>= 0; --port
)
3877 kfree(port_array
[port
]);
3882 /* give copy of port_array to all ports and add to device list */
3883 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3884 memcpy(port_array
[port
]->port_array
,port_array
,sizeof(port_array
));
3885 add_device( port_array
[port
] );
3886 spin_lock_init(&port_array
[port
]->lock
);
3889 /* Allocate and claim adapter resources */
3890 if ( !claim_resources(port_array
[0]) ) {
3892 alloc_dma_bufs(port_array
[0]);
3894 /* copy resource information from first port to others */
3895 for ( port
= 1; port
< SCA_MAX_PORTS
; ++port
) {
3896 port_array
[port
]->lock
= port_array
[0]->lock
;
3897 port_array
[port
]->irq_level
= port_array
[0]->irq_level
;
3898 port_array
[port
]->memory_base
= port_array
[0]->memory_base
;
3899 port_array
[port
]->sca_base
= port_array
[0]->sca_base
;
3900 port_array
[port
]->statctrl_base
= port_array
[0]->statctrl_base
;
3901 port_array
[port
]->lcr_base
= port_array
[0]->lcr_base
;
3902 alloc_dma_bufs(port_array
[port
]);
3905 if ( request_irq(port_array
[0]->irq_level
,
3906 synclinkmp_interrupt
,
3907 port_array
[0]->irq_flags
,
3908 port_array
[0]->device_name
,
3909 port_array
[0]) < 0 ) {
3910 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3912 port_array
[0]->device_name
,
3913 port_array
[0]->irq_level
);
3916 port_array
[0]->irq_requested
= true;
3917 adapter_test(port_array
[0]);
3922 static const struct tty_operations ops
= {
3926 .put_char
= put_char
,
3927 .flush_chars
= flush_chars
,
3928 .write_room
= write_room
,
3929 .chars_in_buffer
= chars_in_buffer
,
3930 .flush_buffer
= flush_buffer
,
3932 .throttle
= throttle
,
3933 .unthrottle
= unthrottle
,
3934 .send_xchar
= send_xchar
,
3935 .break_ctl
= set_break
,
3936 .wait_until_sent
= wait_until_sent
,
3937 .read_proc
= read_proc
,
3938 .set_termios
= set_termios
,
3940 .start
= tx_release
,
3942 .tiocmget
= tiocmget
,
3943 .tiocmset
= tiocmset
,
3946 static void synclinkmp_cleanup(void)
3952 printk("Unloading %s %s\n", driver_name
, driver_version
);
3954 if (serial_driver
) {
3955 if ((rc
= tty_unregister_driver(serial_driver
)))
3956 printk("%s(%d) failed to unregister tty driver err=%d\n",
3957 __FILE__
,__LINE__
,rc
);
3958 put_tty_driver(serial_driver
);
3962 info
= synclinkmp_device_list
;
3965 info
= info
->next_device
;
3968 /* release devices */
3969 info
= synclinkmp_device_list
;
3971 #if SYNCLINK_GENERIC_HDLC
3974 free_dma_bufs(info
);
3975 free_tmp_rx_buf(info
);
3976 if ( info
->port_num
== 0 ) {
3978 write_reg(info
, LPR
, 1); /* set low power mode */
3979 release_resources(info
);
3982 info
= info
->next_device
;
3986 pci_unregister_driver(&synclinkmp_pci_driver
);
3989 /* Driver initialization entry point.
3992 static int __init
synclinkmp_init(void)
3996 if (break_on_load
) {
3997 synclinkmp_get_text_ptr();
4001 printk("%s %s\n", driver_name
, driver_version
);
4003 if ((rc
= pci_register_driver(&synclinkmp_pci_driver
)) < 0) {
4004 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4008 serial_driver
= alloc_tty_driver(128);
4009 if (!serial_driver
) {
4014 /* Initialize the tty_driver structure */
4016 serial_driver
->owner
= THIS_MODULE
;
4017 serial_driver
->driver_name
= "synclinkmp";
4018 serial_driver
->name
= "ttySLM";
4019 serial_driver
->major
= ttymajor
;
4020 serial_driver
->minor_start
= 64;
4021 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4022 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4023 serial_driver
->init_termios
= tty_std_termios
;
4024 serial_driver
->init_termios
.c_cflag
=
4025 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4026 serial_driver
->init_termios
.c_ispeed
= 9600;
4027 serial_driver
->init_termios
.c_ospeed
= 9600;
4028 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4029 tty_set_operations(serial_driver
, &ops
);
4030 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4031 printk("%s(%d):Couldn't register serial driver\n",
4033 put_tty_driver(serial_driver
);
4034 serial_driver
= NULL
;
4038 printk("%s %s, tty major#%d\n",
4039 driver_name
, driver_version
,
4040 serial_driver
->major
);
4045 synclinkmp_cleanup();
4049 static void __exit
synclinkmp_exit(void)
4051 synclinkmp_cleanup();
4054 module_init(synclinkmp_init
);
4055 module_exit(synclinkmp_exit
);
4057 /* Set the port for internal loopback mode.
4058 * The TxCLK and RxCLK signals are generated from the BRG and
4059 * the TxD is looped back to the RxD internally.
4061 static void enable_loopback(SLMP_INFO
*info
, int enable
)
4064 /* MD2 (Mode Register 2)
4065 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4067 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) | (BIT1
+ BIT0
)));
4069 /* degate external TxC clock source */
4070 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4071 write_control_reg(info
);
4073 /* RXS/TXS (Rx/Tx clock source)
4074 * 07 Reserved, must be 0
4075 * 06..04 Clock Source, 100=BRG
4076 * 03..00 Clock Divisor, 0000=1
4078 write_reg(info
, RXS
, 0x40);
4079 write_reg(info
, TXS
, 0x40);
4082 /* MD2 (Mode Register 2)
4083 * 01..00 CNCT<1..0> Channel connection, 0=normal
4085 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) & ~(BIT1
+ BIT0
)));
4087 /* RXS/TXS (Rx/Tx clock source)
4088 * 07 Reserved, must be 0
4089 * 06..04 Clock Source, 000=RxC/TxC Pin
4090 * 03..00 Clock Divisor, 0000=1
4092 write_reg(info
, RXS
, 0x00);
4093 write_reg(info
, TXS
, 0x00);
4096 /* set LinkSpeed if available, otherwise default to 2Mbps */
4097 if (info
->params
.clock_speed
)
4098 set_rate(info
, info
->params
.clock_speed
);
4100 set_rate(info
, 3686400);
4103 /* Set the baud rate register to the desired speed
4105 * data_rate data rate of clock in bits per second
4106 * A data rate of 0 disables the AUX clock.
4108 static void set_rate( SLMP_INFO
*info
, u32 data_rate
)
4111 unsigned char BRValue
;
4114 /* fBRG = fCLK/(TMC * 2^BR)
4116 if (data_rate
!= 0) {
4117 Divisor
= 14745600/data_rate
;
4124 if (TMCValue
!= 1 && TMCValue
!= 2) {
4125 /* BRValue of 0 provides 50/50 duty cycle *only* when
4126 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4133 /* while TMCValue is too big for TMC register, divide
4134 * by 2 and increment BR exponent.
4136 for(; TMCValue
> 256 && BRValue
< 10; BRValue
++)
4139 write_reg(info
, TXS
,
4140 (unsigned char)((read_reg(info
, TXS
) & 0xf0) | BRValue
));
4141 write_reg(info
, RXS
,
4142 (unsigned char)((read_reg(info
, RXS
) & 0xf0) | BRValue
));
4143 write_reg(info
, TMC
, (unsigned char)TMCValue
);
4146 write_reg(info
, TXS
,0);
4147 write_reg(info
, RXS
,0);
4148 write_reg(info
, TMC
, 0);
4154 static void rx_stop(SLMP_INFO
*info
)
4156 if (debug_level
>= DEBUG_LEVEL_ISR
)
4157 printk("%s(%d):%s rx_stop()\n",
4158 __FILE__
,__LINE__
, info
->device_name
);
4160 write_reg(info
, CMD
, RXRESET
);
4162 info
->ie0_value
&= ~RXRDYE
;
4163 write_reg(info
, IE0
, info
->ie0_value
); /* disable Rx data interrupts */
4165 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4166 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4167 write_reg(info
, RXDMA
+ DIR, 0); /* disable Rx DMA interrupts */
4169 info
->rx_enabled
= false;
4170 info
->rx_overflow
= false;
4173 /* enable the receiver
4175 static void rx_start(SLMP_INFO
*info
)
4179 if (debug_level
>= DEBUG_LEVEL_ISR
)
4180 printk("%s(%d):%s rx_start()\n",
4181 __FILE__
,__LINE__
, info
->device_name
);
4183 write_reg(info
, CMD
, RXRESET
);
4185 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
4186 /* HDLC, disabe IRQ on rxdata */
4187 info
->ie0_value
&= ~RXRDYE
;
4188 write_reg(info
, IE0
, info
->ie0_value
);
4190 /* Reset all Rx DMA buffers and program rx dma */
4191 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4192 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4194 for (i
= 0; i
< info
->rx_buf_count
; i
++) {
4195 info
->rx_buf_list
[i
].status
= 0xff;
4197 // throttle to 4 shared memory writes at a time to prevent
4198 // hogging local bus (keep latency time for DMA requests low).
4200 read_status_reg(info
);
4202 info
->current_rx_buf
= 0;
4204 /* set current/1st descriptor address */
4205 write_reg16(info
, RXDMA
+ CDA
,
4206 info
->rx_buf_list_ex
[0].phys_entry
);
4208 /* set new last rx descriptor address */
4209 write_reg16(info
, RXDMA
+ EDA
,
4210 info
->rx_buf_list_ex
[info
->rx_buf_count
- 1].phys_entry
);
4212 /* set buffer length (shared by all rx dma data buffers) */
4213 write_reg16(info
, RXDMA
+ BFL
, SCABUFSIZE
);
4215 write_reg(info
, RXDMA
+ DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4216 write_reg(info
, RXDMA
+ DSR
, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4218 /* async, enable IRQ on rxdata */
4219 info
->ie0_value
|= RXRDYE
;
4220 write_reg(info
, IE0
, info
->ie0_value
);
4223 write_reg(info
, CMD
, RXENABLE
);
4225 info
->rx_overflow
= false;
4226 info
->rx_enabled
= true;
4229 /* Enable the transmitter and send a transmit frame if
4230 * one is loaded in the DMA buffers.
4232 static void tx_start(SLMP_INFO
*info
)
4234 if (debug_level
>= DEBUG_LEVEL_ISR
)
4235 printk("%s(%d):%s tx_start() tx_count=%d\n",
4236 __FILE__
,__LINE__
, info
->device_name
,info
->tx_count
);
4238 if (!info
->tx_enabled
) {
4239 write_reg(info
, CMD
, TXRESET
);
4240 write_reg(info
, CMD
, TXENABLE
);
4241 info
->tx_enabled
= true;
4244 if ( info
->tx_count
) {
4246 /* If auto RTS enabled and RTS is inactive, then assert */
4247 /* RTS and set a flag indicating that the driver should */
4248 /* negate RTS when the transmission completes. */
4250 info
->drop_rts_on_tx_done
= false;
4252 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
4254 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
4255 get_signals( info
);
4256 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
4257 info
->serial_signals
|= SerialSignal_RTS
;
4258 set_signals( info
);
4259 info
->drop_rts_on_tx_done
= true;
4263 write_reg16(info
, TRC0
,
4264 (unsigned short)(((tx_negate_fifo_level
-1)<<8) + tx_active_fifo_level
));
4266 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4267 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4269 /* set TX CDA (current descriptor address) */
4270 write_reg16(info
, TXDMA
+ CDA
,
4271 info
->tx_buf_list_ex
[0].phys_entry
);
4273 /* set TX EDA (last descriptor address) */
4274 write_reg16(info
, TXDMA
+ EDA
,
4275 info
->tx_buf_list_ex
[info
->last_tx_buf
].phys_entry
);
4277 /* enable underrun IRQ */
4278 info
->ie1_value
&= ~IDLE
;
4279 info
->ie1_value
|= UDRN
;
4280 write_reg(info
, IE1
, info
->ie1_value
);
4281 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
));
4283 write_reg(info
, TXDMA
+ DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4284 write_reg(info
, TXDMA
+ DSR
, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4286 mod_timer(&info
->tx_timer
, jiffies
+
4287 msecs_to_jiffies(5000));
4291 /* async, enable IRQ on txdata */
4292 info
->ie0_value
|= TXRDYE
;
4293 write_reg(info
, IE0
, info
->ie0_value
);
4296 info
->tx_active
= true;
4300 /* stop the transmitter and DMA
4302 static void tx_stop( SLMP_INFO
*info
)
4304 if (debug_level
>= DEBUG_LEVEL_ISR
)
4305 printk("%s(%d):%s tx_stop()\n",
4306 __FILE__
,__LINE__
, info
->device_name
);
4308 del_timer(&info
->tx_timer
);
4310 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4311 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4313 write_reg(info
, CMD
, TXRESET
);
4315 info
->ie1_value
&= ~(UDRN
+ IDLE
);
4316 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
4317 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
4319 info
->ie0_value
&= ~TXRDYE
;
4320 write_reg(info
, IE0
, info
->ie0_value
); /* disable tx data interrupts */
4322 info
->tx_enabled
= false;
4323 info
->tx_active
= false;
4326 /* Fill the transmit FIFO until the FIFO is full or
4327 * there is no more data to load.
4329 static void tx_load_fifo(SLMP_INFO
*info
)
4333 /* do nothing is now tx data available and no XON/XOFF pending */
4335 if ( !info
->tx_count
&& !info
->x_char
)
4338 /* load the Transmit FIFO until FIFOs full or all data sent */
4340 while( info
->tx_count
&& (read_reg(info
,SR0
) & BIT1
) ) {
4342 /* there is more space in the transmit FIFO and */
4343 /* there is more data in transmit buffer */
4345 if ( (info
->tx_count
> 1) && !info
->x_char
) {
4347 TwoBytes
[0] = info
->tx_buf
[info
->tx_get
++];
4348 if (info
->tx_get
>= info
->max_frame_size
)
4349 info
->tx_get
-= info
->max_frame_size
;
4350 TwoBytes
[1] = info
->tx_buf
[info
->tx_get
++];
4351 if (info
->tx_get
>= info
->max_frame_size
)
4352 info
->tx_get
-= info
->max_frame_size
;
4354 write_reg16(info
, TRB
, *((u16
*)TwoBytes
));
4356 info
->tx_count
-= 2;
4357 info
->icount
.tx
+= 2;
4359 /* only 1 byte left to transmit or 1 FIFO slot left */
4362 /* transmit pending high priority char */
4363 write_reg(info
, TRB
, info
->x_char
);
4366 write_reg(info
, TRB
, info
->tx_buf
[info
->tx_get
++]);
4367 if (info
->tx_get
>= info
->max_frame_size
)
4368 info
->tx_get
-= info
->max_frame_size
;
4376 /* Reset a port to a known state
4378 static void reset_port(SLMP_INFO
*info
)
4380 if (info
->sca_base
) {
4385 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
4388 /* disable all port interrupts */
4389 info
->ie0_value
= 0;
4390 info
->ie1_value
= 0;
4391 info
->ie2_value
= 0;
4392 write_reg(info
, IE0
, info
->ie0_value
);
4393 write_reg(info
, IE1
, info
->ie1_value
);
4394 write_reg(info
, IE2
, info
->ie2_value
);
4396 write_reg(info
, CMD
, CHRESET
);
4400 /* Reset all the ports to a known state.
4402 static void reset_adapter(SLMP_INFO
*info
)
4406 for ( i
=0; i
< SCA_MAX_PORTS
; ++i
) {
4407 if (info
->port_array
[i
])
4408 reset_port(info
->port_array
[i
]);
4412 /* Program port for asynchronous communications.
4414 static void async_mode(SLMP_INFO
*info
)
4417 unsigned char RegValue
;
4422 /* MD0, Mode Register 0
4424 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4425 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4426 * 03 Reserved, must be 0
4427 * 02 CRCCC, CRC Calculation, 0=disabled
4428 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4433 if (info
->params
.stop_bits
!= 1)
4435 write_reg(info
, MD0
, RegValue
);
4437 /* MD1, Mode Register 1
4439 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4440 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4441 * 03..02 RXCHR<1..0>, rx char size
4442 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4447 switch (info
->params
.data_bits
) {
4448 case 7: RegValue
|= BIT4
+ BIT2
; break;
4449 case 6: RegValue
|= BIT5
+ BIT3
; break;
4450 case 5: RegValue
|= BIT5
+ BIT4
+ BIT3
+ BIT2
; break;
4452 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4454 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4457 write_reg(info
, MD1
, RegValue
);
4459 /* MD2, Mode Register 2
4461 * 07..02 Reserved, must be 0
4462 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4467 if (info
->params
.loopback
)
4468 RegValue
|= (BIT1
+ BIT0
);
4469 write_reg(info
, MD2
, RegValue
);
4471 /* RXS, Receive clock source
4473 * 07 Reserved, must be 0
4474 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4475 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4478 write_reg(info
, RXS
, RegValue
);
4480 /* TXS, Transmit clock source
4482 * 07 Reserved, must be 0
4483 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4484 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4487 write_reg(info
, TXS
, RegValue
);
4491 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4493 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4494 write_control_reg(info
);
4498 /* RRC Receive Ready Control 0
4500 * 07..05 Reserved, must be 0
4501 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4503 write_reg(info
, RRC
, 0x00);
4505 /* TRC0 Transmit Ready Control 0
4507 * 07..05 Reserved, must be 0
4508 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4510 write_reg(info
, TRC0
, 0x10);
4512 /* TRC1 Transmit Ready Control 1
4514 * 07..05 Reserved, must be 0
4515 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4517 write_reg(info
, TRC1
, 0x1e);
4519 /* CTL, MSCI control register
4521 * 07..06 Reserved, set to 0
4522 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4523 * 04 IDLC, idle control, 0=mark 1=idle register
4524 * 03 BRK, break, 0=off 1 =on (async)
4525 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4526 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4527 * 00 RTS, RTS output control, 0=active 1=inactive
4532 if (!(info
->serial_signals
& SerialSignal_RTS
))
4534 write_reg(info
, CTL
, RegValue
);
4536 /* enable status interrupts */
4537 info
->ie0_value
|= TXINTE
+ RXINTE
;
4538 write_reg(info
, IE0
, info
->ie0_value
);
4540 /* enable break detect interrupt */
4541 info
->ie1_value
= BRKD
;
4542 write_reg(info
, IE1
, info
->ie1_value
);
4544 /* enable rx overrun interrupt */
4545 info
->ie2_value
= OVRN
;
4546 write_reg(info
, IE2
, info
->ie2_value
);
4548 set_rate( info
, info
->params
.data_rate
* 16 );
4551 /* Program the SCA for HDLC communications.
4553 static void hdlc_mode(SLMP_INFO
*info
)
4555 unsigned char RegValue
;
4558 // Can't use DPLL because SCA outputs recovered clock on RxC when
4559 // DPLL mode selected. This causes output contention with RxC receiver.
4560 // Use of DPLL would require external hardware to disable RxC receiver
4561 // when DPLL mode selected.
4562 info
->params
.flags
&= ~(HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
);
4564 /* disable DMA interrupts */
4565 write_reg(info
, TXDMA
+ DIR, 0);
4566 write_reg(info
, RXDMA
+ DIR, 0);
4568 /* MD0, Mode Register 0
4570 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4571 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4572 * 03 Reserved, must be 0
4573 * 02 CRCCC, CRC Calculation, 1=enabled
4574 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4575 * 00 CRC0, CRC initial value, 1 = all 1s
4580 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4582 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4584 if (info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4585 RegValue
|= BIT2
+ BIT1
;
4586 write_reg(info
, MD0
, RegValue
);
4588 /* MD1, Mode Register 1
4590 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4591 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4592 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4593 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4598 write_reg(info
, MD1
, RegValue
);
4600 /* MD2, Mode Register 2
4602 * 07 NRZFM, 0=NRZ, 1=FM
4603 * 06..05 CODE<1..0> Encoding, 00=NRZ
4604 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4605 * 02 Reserved, must be 0
4606 * 01..00 CNCT<1..0> Channel connection, 0=normal
4611 switch(info
->params
.encoding
) {
4612 case HDLC_ENCODING_NRZI
: RegValue
|= BIT5
; break;
4613 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT7
+ BIT5
; break; /* aka FM1 */
4614 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT7
+ BIT6
; break; /* aka FM0 */
4615 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT7
; break; /* aka Manchester */
4617 case HDLC_ENCODING_NRZB
: /* not supported */
4618 case HDLC_ENCODING_NRZI_MARK
: /* not supported */
4619 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: /* not supported */
4622 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4625 } else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4631 write_reg(info
, MD2
, RegValue
);
4634 /* RXS, Receive clock source
4636 * 07 Reserved, must be 0
4637 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4638 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4641 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4643 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4644 RegValue
|= BIT6
+ BIT5
;
4645 write_reg(info
, RXS
, RegValue
);
4647 /* TXS, Transmit clock source
4649 * 07 Reserved, must be 0
4650 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4651 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4654 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4656 if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4657 RegValue
|= BIT6
+ BIT5
;
4658 write_reg(info
, TXS
, RegValue
);
4660 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4661 set_rate(info
, info
->params
.clock_speed
* DpllDivisor
);
4663 set_rate(info
, info
->params
.clock_speed
);
4665 /* GPDATA (General Purpose I/O Data Register)
4667 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4669 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4670 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4672 info
->port_array
[0]->ctrlreg_value
&= ~(BIT0
<< (info
->port_num
* 2));
4673 write_control_reg(info
);
4675 /* RRC Receive Ready Control 0
4677 * 07..05 Reserved, must be 0
4678 * 04..00 RRC<4..0> Rx FIFO trigger active
4680 write_reg(info
, RRC
, rx_active_fifo_level
);
4682 /* TRC0 Transmit Ready Control 0
4684 * 07..05 Reserved, must be 0
4685 * 04..00 TRC<4..0> Tx FIFO trigger active
4687 write_reg(info
, TRC0
, tx_active_fifo_level
);
4689 /* TRC1 Transmit Ready Control 1
4691 * 07..05 Reserved, must be 0
4692 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4694 write_reg(info
, TRC1
, (unsigned char)(tx_negate_fifo_level
- 1));
4696 /* DMR, DMA Mode Register
4698 * 07..05 Reserved, must be 0
4699 * 04 TMOD, Transfer Mode: 1=chained-block
4700 * 03 Reserved, must be 0
4701 * 02 NF, Number of Frames: 1=multi-frame
4702 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4703 * 00 Reserved, must be 0
4707 write_reg(info
, TXDMA
+ DMR
, 0x14);
4708 write_reg(info
, RXDMA
+ DMR
, 0x14);
4710 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4711 write_reg(info
, RXDMA
+ CPB
,
4712 (unsigned char)(info
->buffer_list_phys
>> 16));
4714 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4715 write_reg(info
, TXDMA
+ CPB
,
4716 (unsigned char)(info
->buffer_list_phys
>> 16));
4718 /* enable status interrupts. other code enables/disables
4719 * the individual sources for these two interrupt classes.
4721 info
->ie0_value
|= TXINTE
+ RXINTE
;
4722 write_reg(info
, IE0
, info
->ie0_value
);
4724 /* CTL, MSCI control register
4726 * 07..06 Reserved, set to 0
4727 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4728 * 04 IDLC, idle control, 0=mark 1=idle register
4729 * 03 BRK, break, 0=off 1 =on (async)
4730 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4731 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4732 * 00 RTS, RTS output control, 0=active 1=inactive
4737 if (!(info
->serial_signals
& SerialSignal_RTS
))
4739 write_reg(info
, CTL
, RegValue
);
4741 /* preamble not supported ! */
4747 set_rate(info
, info
->params
.clock_speed
);
4749 if (info
->params
.loopback
)
4750 enable_loopback(info
,1);
4753 /* Set the transmit HDLC idle mode
4755 static void tx_set_idle(SLMP_INFO
*info
)
4757 unsigned char RegValue
= 0xff;
4759 /* Map API idle mode to SCA register bits */
4760 switch(info
->idle_mode
) {
4761 case HDLC_TXIDLE_FLAGS
: RegValue
= 0x7e; break;
4762 case HDLC_TXIDLE_ALT_ZEROS_ONES
: RegValue
= 0xaa; break;
4763 case HDLC_TXIDLE_ZEROS
: RegValue
= 0x00; break;
4764 case HDLC_TXIDLE_ONES
: RegValue
= 0xff; break;
4765 case HDLC_TXIDLE_ALT_MARK_SPACE
: RegValue
= 0xaa; break;
4766 case HDLC_TXIDLE_SPACE
: RegValue
= 0x00; break;
4767 case HDLC_TXIDLE_MARK
: RegValue
= 0xff; break;
4770 write_reg(info
, IDL
, RegValue
);
4773 /* Query the adapter for the state of the V24 status (input) signals.
4775 static void get_signals(SLMP_INFO
*info
)
4777 u16 status
= read_reg(info
, SR3
);
4778 u16 gpstatus
= read_status_reg(info
);
4781 /* clear all serial signals except DTR and RTS */
4782 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4784 /* set serial signal bits to reflect MISR */
4786 if (!(status
& BIT3
))
4787 info
->serial_signals
|= SerialSignal_CTS
;
4789 if ( !(status
& BIT2
))
4790 info
->serial_signals
|= SerialSignal_DCD
;
4792 testbit
= BIT1
<< (info
->port_num
* 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4793 if (!(gpstatus
& testbit
))
4794 info
->serial_signals
|= SerialSignal_RI
;
4796 testbit
= BIT0
<< (info
->port_num
* 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4797 if (!(gpstatus
& testbit
))
4798 info
->serial_signals
|= SerialSignal_DSR
;
4801 /* Set the state of DTR and RTS based on contents of
4802 * serial_signals member of device context.
4804 static void set_signals(SLMP_INFO
*info
)
4806 unsigned char RegValue
;
4809 RegValue
= read_reg(info
, CTL
);
4810 if (info
->serial_signals
& SerialSignal_RTS
)
4814 write_reg(info
, CTL
, RegValue
);
4816 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4817 EnableBit
= BIT1
<< (info
->port_num
*2);
4818 if (info
->serial_signals
& SerialSignal_DTR
)
4819 info
->port_array
[0]->ctrlreg_value
&= ~EnableBit
;
4821 info
->port_array
[0]->ctrlreg_value
|= EnableBit
;
4822 write_control_reg(info
);
4825 /*******************/
4826 /* DMA Buffer Code */
4827 /*******************/
4829 /* Set the count for all receive buffers to SCABUFSIZE
4830 * and set the current buffer to the first buffer. This effectively
4831 * makes all buffers free and discards any data in buffers.
4833 static void rx_reset_buffers(SLMP_INFO
*info
)
4835 rx_free_frame_buffers(info
, 0, info
->rx_buf_count
- 1);
4838 /* Free the buffers used by a received frame
4840 * info pointer to device instance data
4841 * first index of 1st receive buffer of frame
4842 * last index of last receive buffer of frame
4844 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
)
4849 /* reset current buffer for reuse */
4850 info
->rx_buf_list
[first
].status
= 0xff;
4852 if (first
== last
) {
4854 /* set new last rx descriptor address */
4855 write_reg16(info
, RXDMA
+ EDA
, info
->rx_buf_list_ex
[first
].phys_entry
);
4859 if (first
== info
->rx_buf_count
)
4863 /* set current buffer to next buffer after last buffer of frame */
4864 info
->current_rx_buf
= first
;
4867 /* Return a received frame from the receive DMA buffers.
4868 * Only frames received without errors are returned.
4870 * Return Value: true if frame returned, otherwise false
4872 static bool rx_get_frame(SLMP_INFO
*info
)
4874 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
4875 unsigned short status
;
4876 unsigned int framesize
= 0;
4877 bool ReturnCode
= false;
4878 unsigned long flags
;
4879 struct tty_struct
*tty
= info
->tty
;
4880 unsigned char addr_field
= 0xff;
4882 SCADESC_EX
*desc_ex
;
4885 /* assume no frame returned, set zero length */
4890 * current_rx_buf points to the 1st buffer of the next available
4891 * receive frame. To find the last buffer of the frame look for
4892 * a non-zero status field in the buffer entries. (The status
4893 * field is set by the 16C32 after completing a receive frame.
4895 StartIndex
= EndIndex
= info
->current_rx_buf
;
4898 desc
= &info
->rx_buf_list
[EndIndex
];
4899 desc_ex
= &info
->rx_buf_list_ex
[EndIndex
];
4901 if (desc
->status
== 0xff)
4902 goto Cleanup
; /* current desc still in use, no frames available */
4904 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4905 addr_field
= desc_ex
->virt_addr
[0];
4907 framesize
+= desc
->length
;
4909 /* Status != 0 means last buffer of frame */
4914 if (EndIndex
== info
->rx_buf_count
)
4917 if (EndIndex
== info
->current_rx_buf
) {
4918 /* all buffers have been 'used' but none mark */
4919 /* the end of a frame. Reset buffers and receiver. */
4920 if ( info
->rx_enabled
){
4921 spin_lock_irqsave(&info
->lock
,flags
);
4923 spin_unlock_irqrestore(&info
->lock
,flags
);
4930 /* check status of receive frame */
4932 /* frame status is byte stored after frame data
4934 * 7 EOM (end of msg), 1 = last buffer of frame
4935 * 6 Short Frame, 1 = short frame
4936 * 5 Abort, 1 = frame aborted
4937 * 4 Residue, 1 = last byte is partial
4938 * 3 Overrun, 1 = overrun occurred during frame reception
4939 * 2 CRC, 1 = CRC error detected
4942 status
= desc
->status
;
4944 /* ignore CRC bit if not using CRC (bit is undefined) */
4945 /* Note:CRC is not save to data buffer */
4946 if (info
->params
.crc_type
== HDLC_CRC_NONE
)
4949 if (framesize
== 0 ||
4950 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4951 /* discard 0 byte frames, this seems to occur sometime
4952 * when remote is idling flags.
4954 rx_free_frame_buffers(info
, StartIndex
, EndIndex
);
4961 if (status
& (BIT6
+BIT5
+BIT3
+BIT2
)) {
4962 /* received frame has errors,
4963 * update counts and mark frame size as 0
4966 info
->icount
.rxshort
++;
4967 else if (status
& BIT5
)
4968 info
->icount
.rxabort
++;
4969 else if (status
& BIT3
)
4970 info
->icount
.rxover
++;
4972 info
->icount
.rxcrc
++;
4975 #if SYNCLINK_GENERIC_HDLC
4977 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
4979 stats
->rx_frame_errors
++;
4984 if ( debug_level
>= DEBUG_LEVEL_BH
)
4985 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4986 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
4988 if ( debug_level
>= DEBUG_LEVEL_DATA
)
4989 trace_block(info
,info
->rx_buf_list_ex
[StartIndex
].virt_addr
,
4990 min_t(int, framesize
,SCABUFSIZE
),0);
4993 if (framesize
> info
->max_frame_size
)
4994 info
->icount
.rxlong
++;
4996 /* copy dma buffer(s) to contiguous intermediate buffer */
4997 int copy_count
= framesize
;
4998 int index
= StartIndex
;
4999 unsigned char *ptmp
= info
->tmp_rx_buf
;
5000 info
->tmp_rx_buf_count
= framesize
;
5002 info
->icount
.rxok
++;
5005 int partial_count
= min(copy_count
,SCABUFSIZE
);
5007 info
->rx_buf_list_ex
[index
].virt_addr
,
5009 ptmp
+= partial_count
;
5010 copy_count
-= partial_count
;
5012 if ( ++index
== info
->rx_buf_count
)
5016 #if SYNCLINK_GENERIC_HDLC
5018 hdlcdev_rx(info
,info
->tmp_rx_buf
,framesize
);
5021 ldisc_receive_buf(tty
,info
->tmp_rx_buf
,
5022 info
->flag_buf
, framesize
);
5025 /* Free the buffers used by this frame. */
5026 rx_free_frame_buffers( info
, StartIndex
, EndIndex
);
5031 if ( info
->rx_enabled
&& info
->rx_overflow
) {
5032 /* Receiver is enabled, but needs to restarted due to
5033 * rx buffer overflow. If buffers are empty, restart receiver.
5035 if (info
->rx_buf_list
[EndIndex
].status
== 0xff) {
5036 spin_lock_irqsave(&info
->lock
,flags
);
5038 spin_unlock_irqrestore(&info
->lock
,flags
);
5045 /* load the transmit DMA buffer with data
5047 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
)
5049 unsigned short copy_count
;
5052 SCADESC_EX
*desc_ex
;
5054 if ( debug_level
>= DEBUG_LEVEL_DATA
)
5055 trace_block(info
,buf
, min_t(int, count
,SCABUFSIZE
), 1);
5057 /* Copy source buffer to one or more DMA buffers, starting with
5058 * the first transmit dma buffer.
5062 copy_count
= min_t(unsigned short,count
,SCABUFSIZE
);
5064 desc
= &info
->tx_buf_list
[i
];
5065 desc_ex
= &info
->tx_buf_list_ex
[i
];
5067 load_pci_memory(info
, desc_ex
->virt_addr
,buf
,copy_count
);
5069 desc
->length
= copy_count
;
5073 count
-= copy_count
;
5079 if (i
>= info
->tx_buf_count
)
5083 info
->tx_buf_list
[i
].status
= 0x81; /* set EOM and EOT status */
5084 info
->last_tx_buf
= ++i
;
5087 static bool register_test(SLMP_INFO
*info
)
5089 static unsigned char testval
[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5090 static unsigned int count
= ARRAY_SIZE(testval
);
5093 unsigned long flags
;
5095 spin_lock_irqsave(&info
->lock
,flags
);
5098 /* assume failure */
5099 info
->init_error
= DiagStatus_AddressFailure
;
5101 /* Write bit patterns to various registers but do it out of */
5102 /* sync, then read back and verify values. */
5104 for (i
= 0 ; i
< count
; i
++) {
5105 write_reg(info
, TMC
, testval
[i
]);
5106 write_reg(info
, IDL
, testval
[(i
+1)%count
]);
5107 write_reg(info
, SA0
, testval
[(i
+2)%count
]);
5108 write_reg(info
, SA1
, testval
[(i
+3)%count
]);
5110 if ( (read_reg(info
, TMC
) != testval
[i
]) ||
5111 (read_reg(info
, IDL
) != testval
[(i
+1)%count
]) ||
5112 (read_reg(info
, SA0
) != testval
[(i
+2)%count
]) ||
5113 (read_reg(info
, SA1
) != testval
[(i
+3)%count
]) )
5121 spin_unlock_irqrestore(&info
->lock
,flags
);
5126 static bool irq_test(SLMP_INFO
*info
)
5128 unsigned long timeout
;
5129 unsigned long flags
;
5131 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
5133 spin_lock_irqsave(&info
->lock
,flags
);
5136 /* assume failure */
5137 info
->init_error
= DiagStatus_IrqFailure
;
5138 info
->irq_occurred
= false;
5140 /* setup timer0 on SCA0 to interrupt */
5142 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5143 write_reg(info
, IER2
, (unsigned char)((info
->port_num
& 1) ? BIT6
: BIT4
));
5145 write_reg(info
, (unsigned char)(timer
+ TEPR
), 0); /* timer expand prescale */
5146 write_reg16(info
, (unsigned char)(timer
+ TCONR
), 1); /* timer constant */
5149 /* TMCS, Timer Control/Status Register
5151 * 07 CMF, Compare match flag (read only) 1=match
5152 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5153 * 05 Reserved, must be 0
5154 * 04 TME, Timer Enable
5155 * 03..00 Reserved, must be 0
5159 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0x50);
5161 spin_unlock_irqrestore(&info
->lock
,flags
);
5164 while( timeout
-- && !info
->irq_occurred
) {
5165 msleep_interruptible(10);
5168 spin_lock_irqsave(&info
->lock
,flags
);
5170 spin_unlock_irqrestore(&info
->lock
,flags
);
5172 return info
->irq_occurred
;
5175 /* initialize individual SCA device (2 ports)
5177 static bool sca_init(SLMP_INFO
*info
)
5179 /* set wait controller to single mem partition (low), no wait states */
5180 write_reg(info
, PABR0
, 0); /* wait controller addr boundary 0 */
5181 write_reg(info
, PABR1
, 0); /* wait controller addr boundary 1 */
5182 write_reg(info
, WCRL
, 0); /* wait controller low range */
5183 write_reg(info
, WCRM
, 0); /* wait controller mid range */
5184 write_reg(info
, WCRH
, 0); /* wait controller high range */
5186 /* DPCR, DMA Priority Control
5188 * 07..05 Not used, must be 0
5189 * 04 BRC, bus release condition: 0=all transfers complete
5190 * 03 CCC, channel change condition: 0=every cycle
5191 * 02..00 PR<2..0>, priority 100=round robin
5195 write_reg(info
, DPCR
, dma_priority
);
5197 /* DMA Master Enable, BIT7: 1=enable all channels */
5198 write_reg(info
, DMER
, 0x80);
5200 /* enable all interrupt classes */
5201 write_reg(info
, IER0
, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5202 write_reg(info
, IER1
, 0xff); /* DMIB,DMIA (channels 0-3) */
5203 write_reg(info
, IER2
, 0xf0); /* TIRQ (timers 0-3) */
5205 /* ITCR, interrupt control register
5206 * 07 IPC, interrupt priority, 0=MSCI->DMA
5207 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5208 * 04 VOS, Vector Output, 0=unmodified vector
5209 * 03..00 Reserved, must be 0
5211 write_reg(info
, ITCR
, 0);
5216 /* initialize adapter hardware
5218 static bool init_adapter(SLMP_INFO
*info
)
5222 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5223 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5226 info
->misc_ctrl_value
|= BIT30
;
5227 *MiscCtrl
= info
->misc_ctrl_value
;
5230 * Force at least 170ns delay before clearing
5231 * reset bit. Each read from LCR takes at least
5232 * 30ns so 10 times for 300ns to be safe.
5235 readval
= *MiscCtrl
;
5237 info
->misc_ctrl_value
&= ~BIT30
;
5238 *MiscCtrl
= info
->misc_ctrl_value
;
5240 /* init control reg (all DTRs off, all clksel=input) */
5241 info
->ctrlreg_value
= 0xaa;
5242 write_control_reg(info
);
5245 volatile u32
*LCR1BRDR
= (u32
*)(info
->lcr_base
+ 0x2c);
5246 lcr1_brdr_value
&= ~(BIT5
+ BIT4
+ BIT3
);
5248 switch(read_ahead_count
)
5251 lcr1_brdr_value
|= BIT5
+ BIT4
+ BIT3
;
5254 lcr1_brdr_value
|= BIT5
+ BIT4
;
5257 lcr1_brdr_value
|= BIT5
+ BIT3
;
5260 lcr1_brdr_value
|= BIT5
;
5264 *LCR1BRDR
= lcr1_brdr_value
;
5265 *MiscCtrl
= misc_ctrl_value
;
5268 sca_init(info
->port_array
[0]);
5269 sca_init(info
->port_array
[2]);
5274 /* Loopback an HDLC frame to test the hardware
5275 * interrupt and DMA functions.
5277 static bool loopback_test(SLMP_INFO
*info
)
5279 #define TESTFRAMESIZE 20
5281 unsigned long timeout
;
5282 u16 count
= TESTFRAMESIZE
;
5283 unsigned char buf
[TESTFRAMESIZE
];
5285 unsigned long flags
;
5287 struct tty_struct
*oldtty
= info
->tty
;
5288 u32 speed
= info
->params
.clock_speed
;
5290 info
->params
.clock_speed
= 3686400;
5293 /* assume failure */
5294 info
->init_error
= DiagStatus_DmaFailure
;
5296 /* build and send transmit frame */
5297 for (count
= 0; count
< TESTFRAMESIZE
;++count
)
5298 buf
[count
] = (unsigned char)count
;
5300 memset(info
->tmp_rx_buf
,0,TESTFRAMESIZE
);
5302 /* program hardware for HDLC and enabled receiver */
5303 spin_lock_irqsave(&info
->lock
,flags
);
5305 enable_loopback(info
,1);
5307 info
->tx_count
= count
;
5308 tx_load_dma_buffer(info
,buf
,count
);
5310 spin_unlock_irqrestore(&info
->lock
,flags
);
5312 /* wait for receive complete */
5313 /* Set a timeout for waiting for interrupt. */
5314 for ( timeout
= 100; timeout
; --timeout
) {
5315 msleep_interruptible(10);
5317 if (rx_get_frame(info
)) {
5323 /* verify received frame length and contents */
5325 ( info
->tmp_rx_buf_count
!= count
||
5326 memcmp(buf
, info
->tmp_rx_buf
,count
))) {
5330 spin_lock_irqsave(&info
->lock
,flags
);
5331 reset_adapter(info
);
5332 spin_unlock_irqrestore(&info
->lock
,flags
);
5334 info
->params
.clock_speed
= speed
;
5340 /* Perform diagnostics on hardware
5342 static int adapter_test( SLMP_INFO
*info
)
5344 unsigned long flags
;
5345 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5346 printk( "%s(%d):Testing device %s\n",
5347 __FILE__
,__LINE__
,info
->device_name
);
5349 spin_lock_irqsave(&info
->lock
,flags
);
5351 spin_unlock_irqrestore(&info
->lock
,flags
);
5353 info
->port_array
[0]->port_count
= 0;
5355 if ( register_test(info
->port_array
[0]) &&
5356 register_test(info
->port_array
[1])) {
5358 info
->port_array
[0]->port_count
= 2;
5360 if ( register_test(info
->port_array
[2]) &&
5361 register_test(info
->port_array
[3]) )
5362 info
->port_array
[0]->port_count
+= 2;
5365 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5366 __FILE__
,__LINE__
,info
->device_name
, (unsigned long)(info
->phys_sca_base
));
5370 if ( !irq_test(info
->port_array
[0]) ||
5371 !irq_test(info
->port_array
[1]) ||
5372 (info
->port_count
== 4 && !irq_test(info
->port_array
[2])) ||
5373 (info
->port_count
== 4 && !irq_test(info
->port_array
[3]))) {
5374 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5375 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
5379 if (!loopback_test(info
->port_array
[0]) ||
5380 !loopback_test(info
->port_array
[1]) ||
5381 (info
->port_count
== 4 && !loopback_test(info
->port_array
[2])) ||
5382 (info
->port_count
== 4 && !loopback_test(info
->port_array
[3]))) {
5383 printk( "%s(%d):DMA test failure for device %s\n",
5384 __FILE__
,__LINE__
,info
->device_name
);
5388 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5389 printk( "%s(%d):device %s passed diagnostics\n",
5390 __FILE__
,__LINE__
,info
->device_name
);
5392 info
->port_array
[0]->init_error
= 0;
5393 info
->port_array
[1]->init_error
= 0;
5394 if ( info
->port_count
> 2 ) {
5395 info
->port_array
[2]->init_error
= 0;
5396 info
->port_array
[3]->init_error
= 0;
5402 /* Test the shared memory on a PCI adapter.
5404 static bool memory_test(SLMP_INFO
*info
)
5406 static unsigned long testval
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5407 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5408 unsigned long count
= ARRAY_SIZE(testval
);
5410 unsigned long limit
= SCA_MEM_SIZE
/sizeof(unsigned long);
5411 unsigned long * addr
= (unsigned long *)info
->memory_base
;
5413 /* Test data lines with test pattern at one location. */
5415 for ( i
= 0 ; i
< count
; i
++ ) {
5417 if ( *addr
!= testval
[i
] )
5421 /* Test address lines with incrementing pattern over */
5422 /* entire address range. */
5424 for ( i
= 0 ; i
< limit
; i
++ ) {
5429 addr
= (unsigned long *)info
->memory_base
;
5431 for ( i
= 0 ; i
< limit
; i
++ ) {
5432 if ( *addr
!= i
* 4 )
5437 memset( info
->memory_base
, 0, SCA_MEM_SIZE
);
5441 /* Load data into PCI adapter shared memory.
5443 * The PCI9050 releases control of the local bus
5444 * after completing the current read or write operation.
5446 * While the PCI9050 write FIFO not empty, the
5447 * PCI9050 treats all of the writes as a single transaction
5448 * and does not release the bus. This causes DMA latency problems
5449 * at high speeds when copying large data blocks to the shared memory.
5451 * This function breaks a write into multiple transations by
5452 * interleaving a read which flushes the write FIFO and 'completes'
5453 * the write transation. This allows any pending DMA request to gain control
5454 * of the local bus in a timely fasion.
5456 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
)
5458 /* A load interval of 16 allows for 4 32-bit writes at */
5459 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5461 unsigned short interval
= count
/ sca_pci_load_interval
;
5464 for ( i
= 0 ; i
< interval
; i
++ )
5466 memcpy(dest
, src
, sca_pci_load_interval
);
5467 read_status_reg(info
);
5468 dest
+= sca_pci_load_interval
;
5469 src
+= sca_pci_load_interval
;
5472 memcpy(dest
, src
, count
% sca_pci_load_interval
);
5475 static void trace_block(SLMP_INFO
*info
,const char* data
, int count
, int xmit
)
5480 printk("%s tx data:\n",info
->device_name
);
5482 printk("%s rx data:\n",info
->device_name
);
5490 for(i
=0;i
<linecount
;i
++)
5491 printk("%02X ",(unsigned char)data
[i
]);
5494 for(i
=0;i
<linecount
;i
++) {
5495 if (data
[i
]>=040 && data
[i
]<=0176)
5496 printk("%c",data
[i
]);
5505 } /* end of trace_block() */
5507 /* called when HDLC frame times out
5508 * update stats and do tx completion processing
5510 static void tx_timeout(unsigned long context
)
5512 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5513 unsigned long flags
;
5515 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5516 printk( "%s(%d):%s tx_timeout()\n",
5517 __FILE__
,__LINE__
,info
->device_name
);
5518 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
5519 info
->icount
.txtimeout
++;
5521 spin_lock_irqsave(&info
->lock
,flags
);
5522 info
->tx_active
= false;
5523 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
5525 spin_unlock_irqrestore(&info
->lock
,flags
);
5527 #if SYNCLINK_GENERIC_HDLC
5529 hdlcdev_tx_done(info
);
5535 /* called to periodically check the DSR/RI modem signal input status
5537 static void status_timeout(unsigned long context
)
5540 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5541 unsigned long flags
;
5542 unsigned char delta
;
5545 spin_lock_irqsave(&info
->lock
,flags
);
5547 spin_unlock_irqrestore(&info
->lock
,flags
);
5549 /* check for DSR/RI state change */
5551 delta
= info
->old_signals
^ info
->serial_signals
;
5552 info
->old_signals
= info
->serial_signals
;
5554 if (delta
& SerialSignal_DSR
)
5555 status
|= MISCSTATUS_DSR_LATCHED
|(info
->serial_signals
&SerialSignal_DSR
);
5557 if (delta
& SerialSignal_RI
)
5558 status
|= MISCSTATUS_RI_LATCHED
|(info
->serial_signals
&SerialSignal_RI
);
5560 if (delta
& SerialSignal_DCD
)
5561 status
|= MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
);
5563 if (delta
& SerialSignal_CTS
)
5564 status
|= MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
);
5567 isr_io_pin(info
,status
);
5569 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
5573 /* Register Access Routines -
5574 * All registers are memory mapped
5576 #define CALC_REGADDR() \
5577 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5578 if (info->port_num > 1) \
5579 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5580 if ( info->port_num & 1) { \
5582 RegAddr += 0x40; /* DMA access */ \
5583 else if (Addr > 0x1f && Addr < 0x60) \
5584 RegAddr += 0x20; /* MSCI access */ \
5588 static unsigned char read_reg(SLMP_INFO
* info
, unsigned char Addr
)
5593 static void write_reg(SLMP_INFO
* info
, unsigned char Addr
, unsigned char Value
)
5599 static u16
read_reg16(SLMP_INFO
* info
, unsigned char Addr
)
5602 return *((u16
*)RegAddr
);
5605 static void write_reg16(SLMP_INFO
* info
, unsigned char Addr
, u16 Value
)
5608 *((u16
*)RegAddr
) = Value
;
5611 static unsigned char read_status_reg(SLMP_INFO
* info
)
5613 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5617 static void write_control_reg(SLMP_INFO
* info
)
5619 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5620 *RegAddr
= info
->port_array
[0]->ctrlreg_value
;
5624 static int __devinit
synclinkmp_init_one (struct pci_dev
*dev
,
5625 const struct pci_device_id
*ent
)
5627 if (pci_enable_device(dev
)) {
5628 printk("error enabling pci device %p\n", dev
);
5631 device_init( ++synclinkmp_adapter_count
, dev
);
5635 static void __devexit
synclinkmp_remove_one (struct pci_dev
*dev
)