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tty: add more tty_port fields
[deliverable/linux.git] / drivers / char / synclinkmp.c
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266 char char_buf[MAX_ASYNC_BUFFER_SIZE];
267 bool drop_rts_on_tx_done;
268
269 struct _input_signal_events input_signal_events;
270
271 /* SPPP/Cisco HDLC device parts */
272 int netcount;
273 int dosyncppp;
274 spinlock_t netlock;
275
276 #if SYNCLINK_GENERIC_HDLC
277 struct net_device *netdev;
278 #endif
279
280 } SLMP_INFO;
281
282 #define MGSL_MAGIC 0x5401
283
284 /*
285 * define serial signal status change macros
286 */
287 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
288 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
289 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
290 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
291
292 /* Common Register macros */
293 #define LPR 0x00
294 #define PABR0 0x02
295 #define PABR1 0x03
296 #define WCRL 0x04
297 #define WCRM 0x05
298 #define WCRH 0x06
299 #define DPCR 0x08
300 #define DMER 0x09
301 #define ISR0 0x10
302 #define ISR1 0x11
303 #define ISR2 0x12
304 #define IER0 0x14
305 #define IER1 0x15
306 #define IER2 0x16
307 #define ITCR 0x18
308 #define INTVR 0x1a
309 #define IMVR 0x1c
310
311 /* MSCI Register macros */
312 #define TRB 0x20
313 #define TRBL 0x20
314 #define TRBH 0x21
315 #define SR0 0x22
316 #define SR1 0x23
317 #define SR2 0x24
318 #define SR3 0x25
319 #define FST 0x26
320 #define IE0 0x28
321 #define IE1 0x29
322 #define IE2 0x2a
323 #define FIE 0x2b
324 #define CMD 0x2c
325 #define MD0 0x2e
326 #define MD1 0x2f
327 #define MD2 0x30
328 #define CTL 0x31
329 #define SA0 0x32
330 #define SA1 0x33
331 #define IDL 0x34
332 #define TMC 0x35
333 #define RXS 0x36
334 #define TXS 0x37
335 #define TRC0 0x38
336 #define TRC1 0x39
337 #define RRC 0x3a
338 #define CST0 0x3c
339 #define CST1 0x3d
340
341 /* Timer Register Macros */
342 #define TCNT 0x60
343 #define TCNTL 0x60
344 #define TCNTH 0x61
345 #define TCONR 0x62
346 #define TCONRL 0x62
347 #define TCONRH 0x63
348 #define TMCS 0x64
349 #define TEPR 0x65
350
351 /* DMA Controller Register macros */
352 #define DARL 0x80
353 #define DARH 0x81
354 #define DARB 0x82
355 #define BAR 0x80
356 #define BARL 0x80
357 #define BARH 0x81
358 #define BARB 0x82
359 #define SAR 0x84
360 #define SARL 0x84
361 #define SARH 0x85
362 #define SARB 0x86
363 #define CPB 0x86
364 #define CDA 0x88
365 #define CDAL 0x88
366 #define CDAH 0x89
367 #define EDA 0x8a
368 #define EDAL 0x8a
369 #define EDAH 0x8b
370 #define BFL 0x8c
371 #define BFLL 0x8c
372 #define BFLH 0x8d
373 #define BCR 0x8e
374 #define BCRL 0x8e
375 #define BCRH 0x8f
376 #define DSR 0x90
377 #define DMR 0x91
378 #define FCT 0x93
379 #define DIR 0x94
380 #define DCMD 0x95
381
382 /* combine with timer or DMA register address */
383 #define TIMER0 0x00
384 #define TIMER1 0x08
385 #define TIMER2 0x10
386 #define TIMER3 0x18
387 #define RXDMA 0x00
388 #define TXDMA 0x20
389
390 /* SCA Command Codes */
391 #define NOOP 0x00
392 #define TXRESET 0x01
393 #define TXENABLE 0x02
394 #define TXDISABLE 0x03
395 #define TXCRCINIT 0x04
396 #define TXCRCEXCL 0x05
397 #define TXEOM 0x06
398 #define TXABORT 0x07
399 #define MPON 0x08
400 #define TXBUFCLR 0x09
401 #define RXRESET 0x11
402 #define RXENABLE 0x12
403 #define RXDISABLE 0x13
404 #define RXCRCINIT 0x14
405 #define RXREJECT 0x15
406 #define SEARCHMP 0x16
407 #define RXCRCEXCL 0x17
408 #define RXCRCCALC 0x18
409 #define CHRESET 0x21
410 #define HUNT 0x31
411
412 /* DMA command codes */
413 #define SWABORT 0x01
414 #define FEICLEAR 0x02
415
416 /* IE0 */
417 #define TXINTE BIT7
418 #define RXINTE BIT6
419 #define TXRDYE BIT1
420 #define RXRDYE BIT0
421
422 /* IE1 & SR1 */
423 #define UDRN BIT7
424 #define IDLE BIT6
425 #define SYNCD BIT4
426 #define FLGD BIT4
427 #define CCTS BIT3
428 #define CDCD BIT2
429 #define BRKD BIT1
430 #define ABTD BIT1
431 #define GAPD BIT1
432 #define BRKE BIT0
433 #define IDLD BIT0
434
435 /* IE2 & SR2 */
436 #define EOM BIT7
437 #define PMP BIT6
438 #define SHRT BIT6
439 #define PE BIT5
440 #define ABT BIT5
441 #define FRME BIT4
442 #define RBIT BIT4
443 #define OVRN BIT3
444 #define CRCE BIT2
445
446
447 /*
448 * Global linked list of SyncLink devices
449 */
450 static SLMP_INFO *synclinkmp_device_list = NULL;
451 static int synclinkmp_adapter_count = -1;
452 static int synclinkmp_device_count = 0;
453
454 /*
455 * Set this param to non-zero to load eax with the
456 * .text section address and breakpoint on module load.
457 * This is useful for use with gdb and add-symbol-file command.
458 */
459 static int break_on_load = 0;
460
461 /*
462 * Driver major number, defaults to zero to get auto
463 * assigned major number. May be forced as module parameter.
464 */
465 static int ttymajor = 0;
466
467 /*
468 * Array of user specified options for ISA adapters.
469 */
470 static int debug_level = 0;
471 static int maxframe[MAX_DEVICES] = {0,};
472 static int dosyncppp[MAX_DEVICES] = {0,};
473
474 module_param(break_on_load, bool, 0);
475 module_param(ttymajor, int, 0);
476 module_param(debug_level, int, 0);
477 module_param_array(maxframe, int, NULL, 0);
478 module_param_array(dosyncppp, int, NULL, 0);
479
480 static char *driver_name = "SyncLink MultiPort driver";
481 static char *driver_version = "$Revision: 4.38 $";
482
483 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
484 static void synclinkmp_remove_one(struct pci_dev *dev);
485
486 static struct pci_device_id synclinkmp_pci_tbl[] = {
487 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
488 { 0, }, /* terminate list */
489 };
490 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
491
492 MODULE_LICENSE("GPL");
493
494 static struct pci_driver synclinkmp_pci_driver = {
495 .name = "synclinkmp",
496 .id_table = synclinkmp_pci_tbl,
497 .probe = synclinkmp_init_one,
498 .remove = __devexit_p(synclinkmp_remove_one),
499 };
500
501
502 static struct tty_driver *serial_driver;
503
504 /* number of characters left in xmit buffer before we ask for more */
505 #define WAKEUP_CHARS 256
506
507
508 /* tty callbacks */
509
510 static int open(struct tty_struct *tty, struct file * filp);
511 static void close(struct tty_struct *tty, struct file * filp);
512 static void hangup(struct tty_struct *tty);
513 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
514
515 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
516 static int put_char(struct tty_struct *tty, unsigned char ch);
517 static void send_xchar(struct tty_struct *tty, char ch);
518 static void wait_until_sent(struct tty_struct *tty, int timeout);
519 static int write_room(struct tty_struct *tty);
520 static void flush_chars(struct tty_struct *tty);
521 static void flush_buffer(struct tty_struct *tty);
522 static void tx_hold(struct tty_struct *tty);
523 static void tx_release(struct tty_struct *tty);
524
525 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
526 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
527 static int chars_in_buffer(struct tty_struct *tty);
528 static void throttle(struct tty_struct * tty);
529 static void unthrottle(struct tty_struct * tty);
530 static void set_break(struct tty_struct *tty, int break_state);
531
532 #if SYNCLINK_GENERIC_HDLC
533 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
534 static void hdlcdev_tx_done(SLMP_INFO *info);
535 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
536 static int hdlcdev_init(SLMP_INFO *info);
537 static void hdlcdev_exit(SLMP_INFO *info);
538 #endif
539
540 /* ioctl handlers */
541
542 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
543 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
544 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
545 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
546 static int set_txidle(SLMP_INFO *info, int idle_mode);
547 static int tx_enable(SLMP_INFO *info, int enable);
548 static int tx_abort(SLMP_INFO *info);
549 static int rx_enable(SLMP_INFO *info, int enable);
550 static int modem_input_wait(SLMP_INFO *info,int arg);
551 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
552 static int tiocmget(struct tty_struct *tty, struct file *file);
553 static int tiocmset(struct tty_struct *tty, struct file *file,
554 unsigned int set, unsigned int clear);
555 static void set_break(struct tty_struct *tty, int break_state);
556
557 static void add_device(SLMP_INFO *info);
558 static void device_init(int adapter_num, struct pci_dev *pdev);
559 static int claim_resources(SLMP_INFO *info);
560 static void release_resources(SLMP_INFO *info);
561
562 static int startup(SLMP_INFO *info);
563 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
564 static void shutdown(SLMP_INFO *info);
565 static void program_hw(SLMP_INFO *info);
566 static void change_params(SLMP_INFO *info);
567
568 static bool init_adapter(SLMP_INFO *info);
569 static bool register_test(SLMP_INFO *info);
570 static bool irq_test(SLMP_INFO *info);
571 static bool loopback_test(SLMP_INFO *info);
572 static int adapter_test(SLMP_INFO *info);
573 static bool memory_test(SLMP_INFO *info);
574
575 static void reset_adapter(SLMP_INFO *info);
576 static void reset_port(SLMP_INFO *info);
577 static void async_mode(SLMP_INFO *info);
578 static void hdlc_mode(SLMP_INFO *info);
579
580 static void rx_stop(SLMP_INFO *info);
581 static void rx_start(SLMP_INFO *info);
582 static void rx_reset_buffers(SLMP_INFO *info);
583 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
584 static bool rx_get_frame(SLMP_INFO *info);
585
586 static void tx_start(SLMP_INFO *info);
587 static void tx_stop(SLMP_INFO *info);
588 static void tx_load_fifo(SLMP_INFO *info);
589 static void tx_set_idle(SLMP_INFO *info);
590 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
591
592 static void get_signals(SLMP_INFO *info);
593 static void set_signals(SLMP_INFO *info);
594 static void enable_loopback(SLMP_INFO *info, int enable);
595 static void set_rate(SLMP_INFO *info, u32 data_rate);
596
597 static int bh_action(SLMP_INFO *info);
598 static void bh_handler(struct work_struct *work);
599 static void bh_receive(SLMP_INFO *info);
600 static void bh_transmit(SLMP_INFO *info);
601 static void bh_status(SLMP_INFO *info);
602 static void isr_timer(SLMP_INFO *info);
603 static void isr_rxint(SLMP_INFO *info);
604 static void isr_rxrdy(SLMP_INFO *info);
605 static void isr_txint(SLMP_INFO *info);
606 static void isr_txrdy(SLMP_INFO *info);
607 static void isr_rxdmaok(SLMP_INFO *info);
608 static void isr_rxdmaerror(SLMP_INFO *info);
609 static void isr_txdmaok(SLMP_INFO *info);
610 static void isr_txdmaerror(SLMP_INFO *info);
611 static void isr_io_pin(SLMP_INFO *info, u16 status);
612
613 static int alloc_dma_bufs(SLMP_INFO *info);
614 static void free_dma_bufs(SLMP_INFO *info);
615 static int alloc_buf_list(SLMP_INFO *info);
616 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
617 static int alloc_tmp_rx_buf(SLMP_INFO *info);
618 static void free_tmp_rx_buf(SLMP_INFO *info);
619
620 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
621 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
622 static void tx_timeout(unsigned long context);
623 static void status_timeout(unsigned long context);
624
625 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
626 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
627 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
628 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
629 static unsigned char read_status_reg(SLMP_INFO * info);
630 static void write_control_reg(SLMP_INFO * info);
631
632
633 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
634 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
635 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
636
637 static u32 misc_ctrl_value = 0x007e4040;
638 static u32 lcr1_brdr_value = 0x00800028;
639
640 static u32 read_ahead_count = 8;
641
642 /* DPCR, DMA Priority Control
643 *
644 * 07..05 Not used, must be 0
645 * 04 BRC, bus release condition: 0=all transfers complete
646 * 1=release after 1 xfer on all channels
647 * 03 CCC, channel change condition: 0=every cycle
648 * 1=after each channel completes all xfers
649 * 02..00 PR<2..0>, priority 100=round robin
650 *
651 * 00000100 = 0x00
652 */
653 static unsigned char dma_priority = 0x04;
654
655 // Number of bytes that can be written to shared RAM
656 // in a single write operation
657 static u32 sca_pci_load_interval = 64;
658
659 /*
660 * 1st function defined in .text section. Calling this function in
661 * init_module() followed by a breakpoint allows a remote debugger
662 * (gdb) to get the .text address for the add-symbol-file command.
663 * This allows remote debugging of dynamically loadable modules.
664 */
665 static void* synclinkmp_get_text_ptr(void);
666 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
667
668 static inline int sanity_check(SLMP_INFO *info,
669 char *name, const char *routine)
670 {
671 #ifdef SANITY_CHECK
672 static const char *badmagic =
673 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
674 static const char *badinfo =
675 "Warning: null synclinkmp_struct for (%s) in %s\n";
676
677 if (!info) {
678 printk(badinfo, name, routine);
679 return 1;
680 }
681 if (info->magic != MGSL_MAGIC) {
682 printk(badmagic, name, routine);
683 return 1;
684 }
685 #else
686 if (!info)
687 return 1;
688 #endif
689 return 0;
690 }
691
692 /**
693 * line discipline callback wrappers
694 *
695 * The wrappers maintain line discipline references
696 * while calling into the line discipline.
697 *
698 * ldisc_receive_buf - pass receive data to line discipline
699 */
700
701 static void ldisc_receive_buf(struct tty_struct *tty,
702 const __u8 *data, char *flags, int count)
703 {
704 struct tty_ldisc *ld;
705 if (!tty)
706 return;
707 ld = tty_ldisc_ref(tty);
708 if (ld) {
709 if (ld->ops->receive_buf)
710 ld->ops->receive_buf(tty, data, flags, count);
711 tty_ldisc_deref(ld);
712 }
713 }
714
715 /* tty callbacks */
716
717 /* Called when a port is opened. Init and enable port.
718 */
719 static int open(struct tty_struct *tty, struct file *filp)
720 {
721 SLMP_INFO *info;
722 int retval, line;
723 unsigned long flags;
724
725 line = tty->index;
726 if ((line < 0) || (line >= synclinkmp_device_count)) {
727 printk("%s(%d): open with invalid line #%d.\n",
728 __FILE__,__LINE__,line);
729 return -ENODEV;
730 }
731
732 info = synclinkmp_device_list;
733 while(info && info->line != line)
734 info = info->next_device;
735 if (sanity_check(info, tty->name, "open"))
736 return -ENODEV;
737 if ( info->init_error ) {
738 printk("%s(%d):%s device is not allocated, init error=%d\n",
739 __FILE__,__LINE__,info->device_name,info->init_error);
740 return -ENODEV;
741 }
742
743 tty->driver_data = info;
744 info->port.tty = tty;
745
746 if (debug_level >= DEBUG_LEVEL_INFO)
747 printk("%s(%d):%s open(), old ref count = %d\n",
748 __FILE__,__LINE__,tty->driver->name, info->port.count);
749
750 /* If port is closing, signal caller to try again */
751 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
752 if (info->port.flags & ASYNC_CLOSING)
753 interruptible_sleep_on(&info->port.close_wait);
754 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
755 -EAGAIN : -ERESTARTSYS);
756 goto cleanup;
757 }
758
759 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
760
761 spin_lock_irqsave(&info->netlock, flags);
762 if (info->netcount) {
763 retval = -EBUSY;
764 spin_unlock_irqrestore(&info->netlock, flags);
765 goto cleanup;
766 }
767 info->port.count++;
768 spin_unlock_irqrestore(&info->netlock, flags);
769
770 if (info->port.count == 1) {
771 /* 1st open on this device, init hardware */
772 retval = startup(info);
773 if (retval < 0)
774 goto cleanup;
775 }
776
777 retval = block_til_ready(tty, filp, info);
778 if (retval) {
779 if (debug_level >= DEBUG_LEVEL_INFO)
780 printk("%s(%d):%s block_til_ready() returned %d\n",
781 __FILE__,__LINE__, info->device_name, retval);
782 goto cleanup;
783 }
784
785 if (debug_level >= DEBUG_LEVEL_INFO)
786 printk("%s(%d):%s open() success\n",
787 __FILE__,__LINE__, info->device_name);
788 retval = 0;
789
790 cleanup:
791 if (retval) {
792 if (tty->count == 1)
793 info->port.tty = NULL; /* tty layer will release tty struct */
794 if(info->port.count)
795 info->port.count--;
796 }
797
798 return retval;
799 }
800
801 /* Called when port is closed. Wait for remaining data to be
802 * sent. Disable port and free resources.
803 */
804 static void close(struct tty_struct *tty, struct file *filp)
805 {
806 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
807
808 if (sanity_check(info, tty->name, "close"))
809 return;
810
811 if (debug_level >= DEBUG_LEVEL_INFO)
812 printk("%s(%d):%s close() entry, count=%d\n",
813 __FILE__,__LINE__, info->device_name, info->port.count);
814
815 if (!info->port.count)
816 return;
817
818 if (tty_hung_up_p(filp))
819 goto cleanup;
820
821 if ((tty->count == 1) && (info->port.count != 1)) {
822 /*
823 * tty->count is 1 and the tty structure will be freed.
824 * info->port.count should be one in this case.
825 * if it's not, correct it so that the port is shutdown.
826 */
827 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
828 "info->port.count is %d\n",
829 __FILE__,__LINE__, info->device_name, info->port.count);
830 info->port.count = 1;
831 }
832
833 info->port.count--;
834
835 /* if at least one open remaining, leave hardware active */
836 if (info->port.count)
837 goto cleanup;
838
839 info->port.flags |= ASYNC_CLOSING;
840
841 /* set tty->closing to notify line discipline to
842 * only process XON/XOFF characters. Only the N_TTY
843 * discipline appears to use this (ppp does not).
844 */
845 tty->closing = 1;
846
847 /* wait for transmit data to clear all layers */
848
849 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
850 if (debug_level >= DEBUG_LEVEL_INFO)
851 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
852 __FILE__,__LINE__, info->device_name );
853 tty_wait_until_sent(tty, info->port.closing_wait);
854 }
855
856 if (info->port.flags & ASYNC_INITIALIZED)
857 wait_until_sent(tty, info->timeout);
858
859 flush_buffer(tty);
860
861 tty_ldisc_flush(tty);
862
863 shutdown(info);
864
865 tty->closing = 0;
866 info->port.tty = NULL;
867
868 if (info->port.blocked_open) {
869 if (info->port.close_delay) {
870 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
871 }
872 wake_up_interruptible(&info->port.open_wait);
873 }
874
875 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
876
877 wake_up_interruptible(&info->port.close_wait);
878
879 cleanup:
880 if (debug_level >= DEBUG_LEVEL_INFO)
881 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
882 tty->driver->name, info->port.count);
883 }
884
885 /* Called by tty_hangup() when a hangup is signaled.
886 * This is the same as closing all open descriptors for the port.
887 */
888 static void hangup(struct tty_struct *tty)
889 {
890 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
891
892 if (debug_level >= DEBUG_LEVEL_INFO)
893 printk("%s(%d):%s hangup()\n",
894 __FILE__,__LINE__, info->device_name );
895
896 if (sanity_check(info, tty->name, "hangup"))
897 return;
898
899 flush_buffer(tty);
900 shutdown(info);
901
902 info->port.count = 0;
903 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
904 info->port.tty = NULL;
905
906 wake_up_interruptible(&info->port.open_wait);
907 }
908
909 /* Set new termios settings
910 */
911 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
912 {
913 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
914 unsigned long flags;
915
916 if (debug_level >= DEBUG_LEVEL_INFO)
917 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
918 tty->driver->name );
919
920 change_params(info);
921
922 /* Handle transition to B0 status */
923 if (old_termios->c_cflag & CBAUD &&
924 !(tty->termios->c_cflag & CBAUD)) {
925 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
926 spin_lock_irqsave(&info->lock,flags);
927 set_signals(info);
928 spin_unlock_irqrestore(&info->lock,flags);
929 }
930
931 /* Handle transition away from B0 status */
932 if (!(old_termios->c_cflag & CBAUD) &&
933 tty->termios->c_cflag & CBAUD) {
934 info->serial_signals |= SerialSignal_DTR;
935 if (!(tty->termios->c_cflag & CRTSCTS) ||
936 !test_bit(TTY_THROTTLED, &tty->flags)) {
937 info->serial_signals |= SerialSignal_RTS;
938 }
939 spin_lock_irqsave(&info->lock,flags);
940 set_signals(info);
941 spin_unlock_irqrestore(&info->lock,flags);
942 }
943
944 /* Handle turning off CRTSCTS */
945 if (old_termios->c_cflag & CRTSCTS &&
946 !(tty->termios->c_cflag & CRTSCTS)) {
947 tty->hw_stopped = 0;
948 tx_release(tty);
949 }
950 }
951
952 /* Send a block of data
953 *
954 * Arguments:
955 *
956 * tty pointer to tty information structure
957 * buf pointer to buffer containing send data
958 * count size of send data in bytes
959 *
960 * Return Value: number of characters written
961 */
962 static int write(struct tty_struct *tty,
963 const unsigned char *buf, int count)
964 {
965 int c, ret = 0;
966 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
967 unsigned long flags;
968
969 if (debug_level >= DEBUG_LEVEL_INFO)
970 printk("%s(%d):%s write() count=%d\n",
971 __FILE__,__LINE__,info->device_name,count);
972
973 if (sanity_check(info, tty->name, "write"))
974 goto cleanup;
975
976 if (!info->tx_buf)
977 goto cleanup;
978
979 if (info->params.mode == MGSL_MODE_HDLC) {
980 if (count > info->max_frame_size) {
981 ret = -EIO;
982 goto cleanup;
983 }
984 if (info->tx_active)
985 goto cleanup;
986 if (info->tx_count) {
987 /* send accumulated data from send_char() calls */
988 /* as frame and wait before accepting more data. */
989 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
990 goto start;
991 }
992 ret = info->tx_count = count;
993 tx_load_dma_buffer(info, buf, count);
994 goto start;
995 }
996
997 for (;;) {
998 c = min_t(int, count,
999 min(info->max_frame_size - info->tx_count - 1,
1000 info->max_frame_size - info->tx_put));
1001 if (c <= 0)
1002 break;
1003
1004 memcpy(info->tx_buf + info->tx_put, buf, c);
1005
1006 spin_lock_irqsave(&info->lock,flags);
1007 info->tx_put += c;
1008 if (info->tx_put >= info->max_frame_size)
1009 info->tx_put -= info->max_frame_size;
1010 info->tx_count += c;
1011 spin_unlock_irqrestore(&info->lock,flags);
1012
1013 buf += c;
1014 count -= c;
1015 ret += c;
1016 }
1017
1018 if (info->params.mode == MGSL_MODE_HDLC) {
1019 if (count) {
1020 ret = info->tx_count = 0;
1021 goto cleanup;
1022 }
1023 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1024 }
1025 start:
1026 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1027 spin_lock_irqsave(&info->lock,flags);
1028 if (!info->tx_active)
1029 tx_start(info);
1030 spin_unlock_irqrestore(&info->lock,flags);
1031 }
1032
1033 cleanup:
1034 if (debug_level >= DEBUG_LEVEL_INFO)
1035 printk( "%s(%d):%s write() returning=%d\n",
1036 __FILE__,__LINE__,info->device_name,ret);
1037 return ret;
1038 }
1039
1040 /* Add a character to the transmit buffer.
1041 */
1042 static int put_char(struct tty_struct *tty, unsigned char ch)
1043 {
1044 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1045 unsigned long flags;
1046 int ret = 0;
1047
1048 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1049 printk( "%s(%d):%s put_char(%d)\n",
1050 __FILE__,__LINE__,info->device_name,ch);
1051 }
1052
1053 if (sanity_check(info, tty->name, "put_char"))
1054 return 0;
1055
1056 if (!info->tx_buf)
1057 return 0;
1058
1059 spin_lock_irqsave(&info->lock,flags);
1060
1061 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1062 !info->tx_active ) {
1063
1064 if (info->tx_count < info->max_frame_size - 1) {
1065 info->tx_buf[info->tx_put++] = ch;
1066 if (info->tx_put >= info->max_frame_size)
1067 info->tx_put -= info->max_frame_size;
1068 info->tx_count++;
1069 ret = 1;
1070 }
1071 }
1072
1073 spin_unlock_irqrestore(&info->lock,flags);
1074 return ret;
1075 }
1076
1077 /* Send a high-priority XON/XOFF character
1078 */
1079 static void send_xchar(struct tty_struct *tty, char ch)
1080 {
1081 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1082 unsigned long flags;
1083
1084 if (debug_level >= DEBUG_LEVEL_INFO)
1085 printk("%s(%d):%s send_xchar(%d)\n",
1086 __FILE__,__LINE__, info->device_name, ch );
1087
1088 if (sanity_check(info, tty->name, "send_xchar"))
1089 return;
1090
1091 info->x_char = ch;
1092 if (ch) {
1093 /* Make sure transmit interrupts are on */
1094 spin_lock_irqsave(&info->lock,flags);
1095 if (!info->tx_enabled)
1096 tx_start(info);
1097 spin_unlock_irqrestore(&info->lock,flags);
1098 }
1099 }
1100
1101 /* Wait until the transmitter is empty.
1102 */
1103 static void wait_until_sent(struct tty_struct *tty, int timeout)
1104 {
1105 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1106 unsigned long orig_jiffies, char_time;
1107
1108 if (!info )
1109 return;
1110
1111 if (debug_level >= DEBUG_LEVEL_INFO)
1112 printk("%s(%d):%s wait_until_sent() entry\n",
1113 __FILE__,__LINE__, info->device_name );
1114
1115 if (sanity_check(info, tty->name, "wait_until_sent"))
1116 return;
1117
1118 lock_kernel();
1119
1120 if (!(info->port.flags & ASYNC_INITIALIZED))
1121 goto exit;
1122
1123 orig_jiffies = jiffies;
1124
1125 /* Set check interval to 1/5 of estimated time to
1126 * send a character, and make it at least 1. The check
1127 * interval should also be less than the timeout.
1128 * Note: use tight timings here to satisfy the NIST-PCTS.
1129 */
1130
1131 if ( info->params.data_rate ) {
1132 char_time = info->timeout/(32 * 5);
1133 if (!char_time)
1134 char_time++;
1135 } else
1136 char_time = 1;
1137
1138 if (timeout)
1139 char_time = min_t(unsigned long, char_time, timeout);
1140
1141 if ( info->params.mode == MGSL_MODE_HDLC ) {
1142 while (info->tx_active) {
1143 msleep_interruptible(jiffies_to_msecs(char_time));
1144 if (signal_pending(current))
1145 break;
1146 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1147 break;
1148 }
1149 } else {
1150 //TODO: determine if there is something similar to USC16C32
1151 // TXSTATUS_ALL_SENT status
1152 while ( info->tx_active && info->tx_enabled) {
1153 msleep_interruptible(jiffies_to_msecs(char_time));
1154 if (signal_pending(current))
1155 break;
1156 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1157 break;
1158 }
1159 }
1160
1161 exit:
1162 unlock_kernel();
1163 if (debug_level >= DEBUG_LEVEL_INFO)
1164 printk("%s(%d):%s wait_until_sent() exit\n",
1165 __FILE__,__LINE__, info->device_name );
1166 }
1167
1168 /* Return the count of free bytes in transmit buffer
1169 */
1170 static int write_room(struct tty_struct *tty)
1171 {
1172 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1173 int ret;
1174
1175 if (sanity_check(info, tty->name, "write_room"))
1176 return 0;
1177
1178 lock_kernel();
1179 if (info->params.mode == MGSL_MODE_HDLC) {
1180 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1181 } else {
1182 ret = info->max_frame_size - info->tx_count - 1;
1183 if (ret < 0)
1184 ret = 0;
1185 }
1186 unlock_kernel();
1187
1188 if (debug_level >= DEBUG_LEVEL_INFO)
1189 printk("%s(%d):%s write_room()=%d\n",
1190 __FILE__, __LINE__, info->device_name, ret);
1191
1192 return ret;
1193 }
1194
1195 /* enable transmitter and send remaining buffered characters
1196 */
1197 static void flush_chars(struct tty_struct *tty)
1198 {
1199 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1200 unsigned long flags;
1201
1202 if ( debug_level >= DEBUG_LEVEL_INFO )
1203 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1204 __FILE__,__LINE__,info->device_name,info->tx_count);
1205
1206 if (sanity_check(info, tty->name, "flush_chars"))
1207 return;
1208
1209 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1210 !info->tx_buf)
1211 return;
1212
1213 if ( debug_level >= DEBUG_LEVEL_INFO )
1214 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1215 __FILE__,__LINE__,info->device_name );
1216
1217 spin_lock_irqsave(&info->lock,flags);
1218
1219 if (!info->tx_active) {
1220 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1221 info->tx_count ) {
1222 /* operating in synchronous (frame oriented) mode */
1223 /* copy data from circular tx_buf to */
1224 /* transmit DMA buffer. */
1225 tx_load_dma_buffer(info,
1226 info->tx_buf,info->tx_count);
1227 }
1228 tx_start(info);
1229 }
1230
1231 spin_unlock_irqrestore(&info->lock,flags);
1232 }
1233
1234 /* Discard all data in the send buffer
1235 */
1236 static void flush_buffer(struct tty_struct *tty)
1237 {
1238 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1239 unsigned long flags;
1240
1241 if (debug_level >= DEBUG_LEVEL_INFO)
1242 printk("%s(%d):%s flush_buffer() entry\n",
1243 __FILE__,__LINE__, info->device_name );
1244
1245 if (sanity_check(info, tty->name, "flush_buffer"))
1246 return;
1247
1248 spin_lock_irqsave(&info->lock,flags);
1249 info->tx_count = info->tx_put = info->tx_get = 0;
1250 del_timer(&info->tx_timer);
1251 spin_unlock_irqrestore(&info->lock,flags);
1252
1253 tty_wakeup(tty);
1254 }
1255
1256 /* throttle (stop) transmitter
1257 */
1258 static void tx_hold(struct tty_struct *tty)
1259 {
1260 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1261 unsigned long flags;
1262
1263 if (sanity_check(info, tty->name, "tx_hold"))
1264 return;
1265
1266 if ( debug_level >= DEBUG_LEVEL_INFO )
1267 printk("%s(%d):%s tx_hold()\n",
1268 __FILE__,__LINE__,info->device_name);
1269
1270 spin_lock_irqsave(&info->lock,flags);
1271 if (info->tx_enabled)
1272 tx_stop(info);
1273 spin_unlock_irqrestore(&info->lock,flags);
1274 }
1275
1276 /* release (start) transmitter
1277 */
1278 static void tx_release(struct tty_struct *tty)
1279 {
1280 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1281 unsigned long flags;
1282
1283 if (sanity_check(info, tty->name, "tx_release"))
1284 return;
1285
1286 if ( debug_level >= DEBUG_LEVEL_INFO )
1287 printk("%s(%d):%s tx_release()\n",
1288 __FILE__,__LINE__,info->device_name);
1289
1290 spin_lock_irqsave(&info->lock,flags);
1291 if (!info->tx_enabled)
1292 tx_start(info);
1293 spin_unlock_irqrestore(&info->lock,flags);
1294 }
1295
1296 /* Service an IOCTL request
1297 *
1298 * Arguments:
1299 *
1300 * tty pointer to tty instance data
1301 * file pointer to associated file object for device
1302 * cmd IOCTL command code
1303 * arg command argument/context
1304 *
1305 * Return Value: 0 if success, otherwise error code
1306 */
1307 static int do_ioctl(struct tty_struct *tty, struct file *file,
1308 unsigned int cmd, unsigned long arg)
1309 {
1310 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1311 int error;
1312 struct mgsl_icount cnow; /* kernel counter temps */
1313 struct serial_icounter_struct __user *p_cuser; /* user space */
1314 unsigned long flags;
1315 void __user *argp = (void __user *)arg;
1316
1317 if (debug_level >= DEBUG_LEVEL_INFO)
1318 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1319 info->device_name, cmd );
1320
1321 if (sanity_check(info, tty->name, "ioctl"))
1322 return -ENODEV;
1323
1324 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1325 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1326 if (tty->flags & (1 << TTY_IO_ERROR))
1327 return -EIO;
1328 }
1329
1330 switch (cmd) {
1331 case MGSL_IOCGPARAMS:
1332 return get_params(info, argp);
1333 case MGSL_IOCSPARAMS:
1334 return set_params(info, argp);
1335 case MGSL_IOCGTXIDLE:
1336 return get_txidle(info, argp);
1337 case MGSL_IOCSTXIDLE:
1338 return set_txidle(info, (int)arg);
1339 case MGSL_IOCTXENABLE:
1340 return tx_enable(info, (int)arg);
1341 case MGSL_IOCRXENABLE:
1342 return rx_enable(info, (int)arg);
1343 case MGSL_IOCTXABORT:
1344 return tx_abort(info);
1345 case MGSL_IOCGSTATS:
1346 return get_stats(info, argp);
1347 case MGSL_IOCWAITEVENT:
1348 return wait_mgsl_event(info, argp);
1349 case MGSL_IOCLOOPTXDONE:
1350 return 0; // TODO: Not supported, need to document
1351 /* Wait for modem input (DCD,RI,DSR,CTS) change
1352 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1353 */
1354 case TIOCMIWAIT:
1355 return modem_input_wait(info,(int)arg);
1356
1357 /*
1358 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1359 * Return: write counters to the user passed counter struct
1360 * NB: both 1->0 and 0->1 transitions are counted except for
1361 * RI where only 0->1 is counted.
1362 */
1363 case TIOCGICOUNT:
1364 spin_lock_irqsave(&info->lock,flags);
1365 cnow = info->icount;
1366 spin_unlock_irqrestore(&info->lock,flags);
1367 p_cuser = argp;
1368 PUT_USER(error,cnow.cts, &p_cuser->cts);
1369 if (error) return error;
1370 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1371 if (error) return error;
1372 PUT_USER(error,cnow.rng, &p_cuser->rng);
1373 if (error) return error;
1374 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1375 if (error) return error;
1376 PUT_USER(error,cnow.rx, &p_cuser->rx);
1377 if (error) return error;
1378 PUT_USER(error,cnow.tx, &p_cuser->tx);
1379 if (error) return error;
1380 PUT_USER(error,cnow.frame, &p_cuser->frame);
1381 if (error) return error;
1382 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1383 if (error) return error;
1384 PUT_USER(error,cnow.parity, &p_cuser->parity);
1385 if (error) return error;
1386 PUT_USER(error,cnow.brk, &p_cuser->brk);
1387 if (error) return error;
1388 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1389 if (error) return error;
1390 return 0;
1391 default:
1392 return -ENOIOCTLCMD;
1393 }
1394 return 0;
1395 }
1396
1397 static int ioctl(struct tty_struct *tty, struct file *file,
1398 unsigned int cmd, unsigned long arg)
1399 {
1400 int ret;
1401 lock_kernel();
1402 ret = do_ioctl(tty, file, cmd, arg);
1403 unlock_kernel();
1404 return ret;
1405 }
1406
1407 /*
1408 * /proc fs routines....
1409 */
1410
1411 static inline int line_info(char *buf, SLMP_INFO *info)
1412 {
1413 char stat_buf[30];
1414 int ret;
1415 unsigned long flags;
1416
1417 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1418 "\tIRQ=%d MaxFrameSize=%u\n",
1419 info->device_name,
1420 info->phys_sca_base,
1421 info->phys_memory_base,
1422 info->phys_statctrl_base,
1423 info->phys_lcr_base,
1424 info->irq_level,
1425 info->max_frame_size );
1426
1427 /* output current serial signal states */
1428 spin_lock_irqsave(&info->lock,flags);
1429 get_signals(info);
1430 spin_unlock_irqrestore(&info->lock,flags);
1431
1432 stat_buf[0] = 0;
1433 stat_buf[1] = 0;
1434 if (info->serial_signals & SerialSignal_RTS)
1435 strcat(stat_buf, "|RTS");
1436 if (info->serial_signals & SerialSignal_CTS)
1437 strcat(stat_buf, "|CTS");
1438 if (info->serial_signals & SerialSignal_DTR)
1439 strcat(stat_buf, "|DTR");
1440 if (info->serial_signals & SerialSignal_DSR)
1441 strcat(stat_buf, "|DSR");
1442 if (info->serial_signals & SerialSignal_DCD)
1443 strcat(stat_buf, "|CD");
1444 if (info->serial_signals & SerialSignal_RI)
1445 strcat(stat_buf, "|RI");
1446
1447 if (info->params.mode == MGSL_MODE_HDLC) {
1448 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1449 info->icount.txok, info->icount.rxok);
1450 if (info->icount.txunder)
1451 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1452 if (info->icount.txabort)
1453 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1454 if (info->icount.rxshort)
1455 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1456 if (info->icount.rxlong)
1457 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1458 if (info->icount.rxover)
1459 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1460 if (info->icount.rxcrc)
1461 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1462 } else {
1463 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1464 info->icount.tx, info->icount.rx);
1465 if (info->icount.frame)
1466 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1467 if (info->icount.parity)
1468 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1469 if (info->icount.brk)
1470 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1471 if (info->icount.overrun)
1472 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1473 }
1474
1475 /* Append serial signal status to end */
1476 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1477
1478 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1479 info->tx_active,info->bh_requested,info->bh_running,
1480 info->pending_bh);
1481
1482 return ret;
1483 }
1484
1485 /* Called to print information about devices
1486 */
1487 static int read_proc(char *page, char **start, off_t off, int count,
1488 int *eof, void *data)
1489 {
1490 int len = 0, l;
1491 off_t begin = 0;
1492 SLMP_INFO *info;
1493
1494 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1495
1496 info = synclinkmp_device_list;
1497 while( info ) {
1498 l = line_info(page + len, info);
1499 len += l;
1500 if (len+begin > off+count)
1501 goto done;
1502 if (len+begin < off) {
1503 begin += len;
1504 len = 0;
1505 }
1506 info = info->next_device;
1507 }
1508
1509 *eof = 1;
1510 done:
1511 if (off >= len+begin)
1512 return 0;
1513 *start = page + (off-begin);
1514 return ((count < begin+len-off) ? count : begin+len-off);
1515 }
1516
1517 /* Return the count of bytes in transmit buffer
1518 */
1519 static int chars_in_buffer(struct tty_struct *tty)
1520 {
1521 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1522
1523 if (sanity_check(info, tty->name, "chars_in_buffer"))
1524 return 0;
1525
1526 if (debug_level >= DEBUG_LEVEL_INFO)
1527 printk("%s(%d):%s chars_in_buffer()=%d\n",
1528 __FILE__, __LINE__, info->device_name, info->tx_count);
1529
1530 return info->tx_count;
1531 }
1532
1533 /* Signal remote device to throttle send data (our receive data)
1534 */
1535 static void throttle(struct tty_struct * tty)
1536 {
1537 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1538 unsigned long flags;
1539
1540 if (debug_level >= DEBUG_LEVEL_INFO)
1541 printk("%s(%d):%s throttle() entry\n",
1542 __FILE__,__LINE__, info->device_name );
1543
1544 if (sanity_check(info, tty->name, "throttle"))
1545 return;
1546
1547 if (I_IXOFF(tty))
1548 send_xchar(tty, STOP_CHAR(tty));
1549
1550 if (tty->termios->c_cflag & CRTSCTS) {
1551 spin_lock_irqsave(&info->lock,flags);
1552 info->serial_signals &= ~SerialSignal_RTS;
1553 set_signals(info);
1554 spin_unlock_irqrestore(&info->lock,flags);
1555 }
1556 }
1557
1558 /* Signal remote device to stop throttling send data (our receive data)
1559 */
1560 static void unthrottle(struct tty_struct * tty)
1561 {
1562 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1563 unsigned long flags;
1564
1565 if (debug_level >= DEBUG_LEVEL_INFO)
1566 printk("%s(%d):%s unthrottle() entry\n",
1567 __FILE__,__LINE__, info->device_name );
1568
1569 if (sanity_check(info, tty->name, "unthrottle"))
1570 return;
1571
1572 if (I_IXOFF(tty)) {
1573 if (info->x_char)
1574 info->x_char = 0;
1575 else
1576 send_xchar(tty, START_CHAR(tty));
1577 }
1578
1579 if (tty->termios->c_cflag & CRTSCTS) {
1580 spin_lock_irqsave(&info->lock,flags);
1581 info->serial_signals |= SerialSignal_RTS;
1582 set_signals(info);
1583 spin_unlock_irqrestore(&info->lock,flags);
1584 }
1585 }
1586
1587 /* set or clear transmit break condition
1588 * break_state -1=set break condition, 0=clear
1589 */
1590 static void set_break(struct tty_struct *tty, int break_state)
1591 {
1592 unsigned char RegValue;
1593 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1594 unsigned long flags;
1595
1596 if (debug_level >= DEBUG_LEVEL_INFO)
1597 printk("%s(%d):%s set_break(%d)\n",
1598 __FILE__,__LINE__, info->device_name, break_state);
1599
1600 if (sanity_check(info, tty->name, "set_break"))
1601 return;
1602
1603 spin_lock_irqsave(&info->lock,flags);
1604 RegValue = read_reg(info, CTL);
1605 if (break_state == -1)
1606 RegValue |= BIT3;
1607 else
1608 RegValue &= ~BIT3;
1609 write_reg(info, CTL, RegValue);
1610 spin_unlock_irqrestore(&info->lock,flags);
1611 }
1612
1613 #if SYNCLINK_GENERIC_HDLC
1614
1615 /**
1616 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1617 * set encoding and frame check sequence (FCS) options
1618 *
1619 * dev pointer to network device structure
1620 * encoding serial encoding setting
1621 * parity FCS setting
1622 *
1623 * returns 0 if success, otherwise error code
1624 */
1625 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1626 unsigned short parity)
1627 {
1628 SLMP_INFO *info = dev_to_port(dev);
1629 unsigned char new_encoding;
1630 unsigned short new_crctype;
1631
1632 /* return error if TTY interface open */
1633 if (info->port.count)
1634 return -EBUSY;
1635
1636 switch (encoding)
1637 {
1638 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1639 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1640 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1641 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1642 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1643 default: return -EINVAL;
1644 }
1645
1646 switch (parity)
1647 {
1648 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1649 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1650 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1651 default: return -EINVAL;
1652 }
1653
1654 info->params.encoding = new_encoding;
1655 info->params.crc_type = new_crctype;
1656
1657 /* if network interface up, reprogram hardware */
1658 if (info->netcount)
1659 program_hw(info);
1660
1661 return 0;
1662 }
1663
1664 /**
1665 * called by generic HDLC layer to send frame
1666 *
1667 * skb socket buffer containing HDLC frame
1668 * dev pointer to network device structure
1669 *
1670 * returns 0 if success, otherwise error code
1671 */
1672 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1673 {
1674 SLMP_INFO *info = dev_to_port(dev);
1675 struct net_device_stats *stats = hdlc_stats(dev);
1676 unsigned long flags;
1677
1678 if (debug_level >= DEBUG_LEVEL_INFO)
1679 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1680
1681 /* stop sending until this frame completes */
1682 netif_stop_queue(dev);
1683
1684 /* copy data to device buffers */
1685 info->tx_count = skb->len;
1686 tx_load_dma_buffer(info, skb->data, skb->len);
1687
1688 /* update network statistics */
1689 stats->tx_packets++;
1690 stats->tx_bytes += skb->len;
1691
1692 /* done with socket buffer, so free it */
1693 dev_kfree_skb(skb);
1694
1695 /* save start time for transmit timeout detection */
1696 dev->trans_start = jiffies;
1697
1698 /* start hardware transmitter if necessary */
1699 spin_lock_irqsave(&info->lock,flags);
1700 if (!info->tx_active)
1701 tx_start(info);
1702 spin_unlock_irqrestore(&info->lock,flags);
1703
1704 return 0;
1705 }
1706
1707 /**
1708 * called by network layer when interface enabled
1709 * claim resources and initialize hardware
1710 *
1711 * dev pointer to network device structure
1712 *
1713 * returns 0 if success, otherwise error code
1714 */
1715 static int hdlcdev_open(struct net_device *dev)
1716 {
1717 SLMP_INFO *info = dev_to_port(dev);
1718 int rc;
1719 unsigned long flags;
1720
1721 if (debug_level >= DEBUG_LEVEL_INFO)
1722 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1723
1724 /* generic HDLC layer open processing */
1725 if ((rc = hdlc_open(dev)))
1726 return rc;
1727
1728 /* arbitrate between network and tty opens */
1729 spin_lock_irqsave(&info->netlock, flags);
1730 if (info->port.count != 0 || info->netcount != 0) {
1731 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1732 spin_unlock_irqrestore(&info->netlock, flags);
1733 return -EBUSY;
1734 }
1735 info->netcount=1;
1736 spin_unlock_irqrestore(&info->netlock, flags);
1737
1738 /* claim resources and init adapter */
1739 if ((rc = startup(info)) != 0) {
1740 spin_lock_irqsave(&info->netlock, flags);
1741 info->netcount=0;
1742 spin_unlock_irqrestore(&info->netlock, flags);
1743 return rc;
1744 }
1745
1746 /* assert DTR and RTS, apply hardware settings */
1747 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1748 program_hw(info);
1749
1750 /* enable network layer transmit */
1751 dev->trans_start = jiffies;
1752 netif_start_queue(dev);
1753
1754 /* inform generic HDLC layer of current DCD status */
1755 spin_lock_irqsave(&info->lock, flags);
1756 get_signals(info);
1757 spin_unlock_irqrestore(&info->lock, flags);
1758 if (info->serial_signals & SerialSignal_DCD)
1759 netif_carrier_on(dev);
1760 else
1761 netif_carrier_off(dev);
1762 return 0;
1763 }
1764
1765 /**
1766 * called by network layer when interface is disabled
1767 * shutdown hardware and release resources
1768 *
1769 * dev pointer to network device structure
1770 *
1771 * returns 0 if success, otherwise error code
1772 */
1773 static int hdlcdev_close(struct net_device *dev)
1774 {
1775 SLMP_INFO *info = dev_to_port(dev);
1776 unsigned long flags;
1777
1778 if (debug_level >= DEBUG_LEVEL_INFO)
1779 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1780
1781 netif_stop_queue(dev);
1782
1783 /* shutdown adapter and release resources */
1784 shutdown(info);
1785
1786 hdlc_close(dev);
1787
1788 spin_lock_irqsave(&info->netlock, flags);
1789 info->netcount=0;
1790 spin_unlock_irqrestore(&info->netlock, flags);
1791
1792 return 0;
1793 }
1794
1795 /**
1796 * called by network layer to process IOCTL call to network device
1797 *
1798 * dev pointer to network device structure
1799 * ifr pointer to network interface request structure
1800 * cmd IOCTL command code
1801 *
1802 * returns 0 if success, otherwise error code
1803 */
1804 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1805 {
1806 const size_t size = sizeof(sync_serial_settings);
1807 sync_serial_settings new_line;
1808 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1809 SLMP_INFO *info = dev_to_port(dev);
1810 unsigned int flags;
1811
1812 if (debug_level >= DEBUG_LEVEL_INFO)
1813 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1814
1815 /* return error if TTY interface open */
1816 if (info->port.count)
1817 return -EBUSY;
1818
1819 if (cmd != SIOCWANDEV)
1820 return hdlc_ioctl(dev, ifr, cmd);
1821
1822 switch(ifr->ifr_settings.type) {
1823 case IF_GET_IFACE: /* return current sync_serial_settings */
1824
1825 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1826 if (ifr->ifr_settings.size < size) {
1827 ifr->ifr_settings.size = size; /* data size wanted */
1828 return -ENOBUFS;
1829 }
1830
1831 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1832 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1833 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1834 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1835
1836 switch (flags){
1837 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1838 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1839 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1840 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1841 default: new_line.clock_type = CLOCK_DEFAULT;
1842 }
1843
1844 new_line.clock_rate = info->params.clock_speed;
1845 new_line.loopback = info->params.loopback ? 1:0;
1846
1847 if (copy_to_user(line, &new_line, size))
1848 return -EFAULT;
1849 return 0;
1850
1851 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1852
1853 if(!capable(CAP_NET_ADMIN))
1854 return -EPERM;
1855 if (copy_from_user(&new_line, line, size))
1856 return -EFAULT;
1857
1858 switch (new_line.clock_type)
1859 {
1860 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1861 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1862 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1863 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1864 case CLOCK_DEFAULT: flags = info->params.flags &
1865 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1866 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1867 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1868 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1869 default: return -EINVAL;
1870 }
1871
1872 if (new_line.loopback != 0 && new_line.loopback != 1)
1873 return -EINVAL;
1874
1875 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1876 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1877 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1878 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1879 info->params.flags |= flags;
1880
1881 info->params.loopback = new_line.loopback;
1882
1883 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1884 info->params.clock_speed = new_line.clock_rate;
1885 else
1886 info->params.clock_speed = 0;
1887
1888 /* if network interface up, reprogram hardware */
1889 if (info->netcount)
1890 program_hw(info);
1891 return 0;
1892
1893 default:
1894 return hdlc_ioctl(dev, ifr, cmd);
1895 }
1896 }
1897
1898 /**
1899 * called by network layer when transmit timeout is detected
1900 *
1901 * dev pointer to network device structure
1902 */
1903 static void hdlcdev_tx_timeout(struct net_device *dev)
1904 {
1905 SLMP_INFO *info = dev_to_port(dev);
1906 struct net_device_stats *stats = hdlc_stats(dev);
1907 unsigned long flags;
1908
1909 if (debug_level >= DEBUG_LEVEL_INFO)
1910 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1911
1912 stats->tx_errors++;
1913 stats->tx_aborted_errors++;
1914
1915 spin_lock_irqsave(&info->lock,flags);
1916 tx_stop(info);
1917 spin_unlock_irqrestore(&info->lock,flags);
1918
1919 netif_wake_queue(dev);
1920 }
1921
1922 /**
1923 * called by device driver when transmit completes
1924 * reenable network layer transmit if stopped
1925 *
1926 * info pointer to device instance information
1927 */
1928 static void hdlcdev_tx_done(SLMP_INFO *info)
1929 {
1930 if (netif_queue_stopped(info->netdev))
1931 netif_wake_queue(info->netdev);
1932 }
1933
1934 /**
1935 * called by device driver when frame received
1936 * pass frame to network layer
1937 *
1938 * info pointer to device instance information
1939 * buf pointer to buffer contianing frame data
1940 * size count of data bytes in buf
1941 */
1942 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1943 {
1944 struct sk_buff *skb = dev_alloc_skb(size);
1945 struct net_device *dev = info->netdev;
1946 struct net_device_stats *stats = hdlc_stats(dev);
1947
1948 if (debug_level >= DEBUG_LEVEL_INFO)
1949 printk("hdlcdev_rx(%s)\n",dev->name);
1950
1951 if (skb == NULL) {
1952 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1953 stats->rx_dropped++;
1954 return;
1955 }
1956
1957 memcpy(skb_put(skb, size),buf,size);
1958
1959 skb->protocol = hdlc_type_trans(skb, info->netdev);
1960
1961 stats->rx_packets++;
1962 stats->rx_bytes += size;
1963
1964 netif_rx(skb);
1965
1966 info->netdev->last_rx = jiffies;
1967 }
1968
1969 /**
1970 * called by device driver when adding device instance
1971 * do generic HDLC initialization
1972 *
1973 * info pointer to device instance information
1974 *
1975 * returns 0 if success, otherwise error code
1976 */
1977 static int hdlcdev_init(SLMP_INFO *info)
1978 {
1979 int rc;
1980 struct net_device *dev;
1981 hdlc_device *hdlc;
1982
1983 /* allocate and initialize network and HDLC layer objects */
1984
1985 if (!(dev = alloc_hdlcdev(info))) {
1986 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1987 return -ENOMEM;
1988 }
1989
1990 /* for network layer reporting purposes only */
1991 dev->mem_start = info->phys_sca_base;
1992 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1993 dev->irq = info->irq_level;
1994
1995 /* network layer callbacks and settings */
1996 dev->do_ioctl = hdlcdev_ioctl;
1997 dev->open = hdlcdev_open;
1998 dev->stop = hdlcdev_close;
1999 dev->tx_timeout = hdlcdev_tx_timeout;
2000 dev->watchdog_timeo = 10*HZ;
2001 dev->tx_queue_len = 50;
2002
2003 /* generic HDLC layer callbacks and settings */
2004 hdlc = dev_to_hdlc(dev);
2005 hdlc->attach = hdlcdev_attach;
2006 hdlc->xmit = hdlcdev_xmit;
2007
2008 /* register objects with HDLC layer */
2009 if ((rc = register_hdlc_device(dev))) {
2010 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2011 free_netdev(dev);
2012 return rc;
2013 }
2014
2015 info->netdev = dev;
2016 return 0;
2017 }
2018
2019 /**
2020 * called by device driver when removing device instance
2021 * do generic HDLC cleanup
2022 *
2023 * info pointer to device instance information
2024 */
2025 static void hdlcdev_exit(SLMP_INFO *info)
2026 {
2027 unregister_hdlc_device(info->netdev);
2028 free_netdev(info->netdev);
2029 info->netdev = NULL;
2030 }
2031
2032 #endif /* CONFIG_HDLC */
2033
2034
2035 /* Return next bottom half action to perform.
2036 * Return Value: BH action code or 0 if nothing to do.
2037 */
2038 static int bh_action(SLMP_INFO *info)
2039 {
2040 unsigned long flags;
2041 int rc = 0;
2042
2043 spin_lock_irqsave(&info->lock,flags);
2044
2045 if (info->pending_bh & BH_RECEIVE) {
2046 info->pending_bh &= ~BH_RECEIVE;
2047 rc = BH_RECEIVE;
2048 } else if (info->pending_bh & BH_TRANSMIT) {
2049 info->pending_bh &= ~BH_TRANSMIT;
2050 rc = BH_TRANSMIT;
2051 } else if (info->pending_bh & BH_STATUS) {
2052 info->pending_bh &= ~BH_STATUS;
2053 rc = BH_STATUS;
2054 }
2055
2056 if (!rc) {
2057 /* Mark BH routine as complete */
2058 info->bh_running = false;
2059 info->bh_requested = false;
2060 }
2061
2062 spin_unlock_irqrestore(&info->lock,flags);
2063
2064 return rc;
2065 }
2066
2067 /* Perform bottom half processing of work items queued by ISR.
2068 */
2069 static void bh_handler(struct work_struct *work)
2070 {
2071 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2072 int action;
2073
2074 if (!info)
2075 return;
2076
2077 if ( debug_level >= DEBUG_LEVEL_BH )
2078 printk( "%s(%d):%s bh_handler() entry\n",
2079 __FILE__,__LINE__,info->device_name);
2080
2081 info->bh_running = true;
2082
2083 while((action = bh_action(info)) != 0) {
2084
2085 /* Process work item */
2086 if ( debug_level >= DEBUG_LEVEL_BH )
2087 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2088 __FILE__,__LINE__,info->device_name, action);
2089
2090 switch (action) {
2091
2092 case BH_RECEIVE:
2093 bh_receive(info);
2094 break;
2095 case BH_TRANSMIT:
2096 bh_transmit(info);
2097 break;
2098 case BH_STATUS:
2099 bh_status(info);
2100 break;
2101 default:
2102 /* unknown work item ID */
2103 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2104 __FILE__,__LINE__,info->device_name,action);
2105 break;
2106 }
2107 }
2108
2109 if ( debug_level >= DEBUG_LEVEL_BH )
2110 printk( "%s(%d):%s bh_handler() exit\n",
2111 __FILE__,__LINE__,info->device_name);
2112 }
2113
2114 static void bh_receive(SLMP_INFO *info)
2115 {
2116 if ( debug_level >= DEBUG_LEVEL_BH )
2117 printk( "%s(%d):%s bh_receive()\n",
2118 __FILE__,__LINE__,info->device_name);
2119
2120 while( rx_get_frame(info) );
2121 }
2122
2123 static void bh_transmit(SLMP_INFO *info)
2124 {
2125 struct tty_struct *tty = info->port.tty;
2126
2127 if ( debug_level >= DEBUG_LEVEL_BH )
2128 printk( "%s(%d):%s bh_transmit() entry\n",
2129 __FILE__,__LINE__,info->device_name);
2130
2131 if (tty)
2132 tty_wakeup(tty);
2133 }
2134
2135 static void bh_status(SLMP_INFO *info)
2136 {
2137 if ( debug_level >= DEBUG_LEVEL_BH )
2138 printk( "%s(%d):%s bh_status() entry\n",
2139 __FILE__,__LINE__,info->device_name);
2140
2141 info->ri_chkcount = 0;
2142 info->dsr_chkcount = 0;
2143 info->dcd_chkcount = 0;
2144 info->cts_chkcount = 0;
2145 }
2146
2147 static void isr_timer(SLMP_INFO * info)
2148 {
2149 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2150
2151 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2152 write_reg(info, IER2, 0);
2153
2154 /* TMCS, Timer Control/Status Register
2155 *
2156 * 07 CMF, Compare match flag (read only) 1=match
2157 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2158 * 05 Reserved, must be 0
2159 * 04 TME, Timer Enable
2160 * 03..00 Reserved, must be 0
2161 *
2162 * 0000 0000
2163 */
2164 write_reg(info, (unsigned char)(timer + TMCS), 0);
2165
2166 info->irq_occurred = true;
2167
2168 if ( debug_level >= DEBUG_LEVEL_ISR )
2169 printk("%s(%d):%s isr_timer()\n",
2170 __FILE__,__LINE__,info->device_name);
2171 }
2172
2173 static void isr_rxint(SLMP_INFO * info)
2174 {
2175 struct tty_struct *tty = info->port.tty;
2176 struct mgsl_icount *icount = &info->icount;
2177 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2178 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2179
2180 /* clear status bits */
2181 if (status)
2182 write_reg(info, SR1, status);
2183
2184 if (status2)
2185 write_reg(info, SR2, status2);
2186
2187 if ( debug_level >= DEBUG_LEVEL_ISR )
2188 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2189 __FILE__,__LINE__,info->device_name,status,status2);
2190
2191 if (info->params.mode == MGSL_MODE_ASYNC) {
2192 if (status & BRKD) {
2193 icount->brk++;
2194
2195 /* process break detection if tty control
2196 * is not set to ignore it
2197 */
2198 if ( tty ) {
2199 if (!(status & info->ignore_status_mask1)) {
2200 if (info->read_status_mask1 & BRKD) {
2201 tty_insert_flip_char(tty, 0, TTY_BREAK);
2202 if (info->port.flags & ASYNC_SAK)
2203 do_SAK(tty);
2204 }
2205 }
2206 }
2207 }
2208 }
2209 else {
2210 if (status & (FLGD|IDLD)) {
2211 if (status & FLGD)
2212 info->icount.exithunt++;
2213 else if (status & IDLD)
2214 info->icount.rxidle++;
2215 wake_up_interruptible(&info->event_wait_q);
2216 }
2217 }
2218
2219 if (status & CDCD) {
2220 /* simulate a common modem status change interrupt
2221 * for our handler
2222 */
2223 get_signals( info );
2224 isr_io_pin(info,
2225 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2226 }
2227 }
2228
2229 /*
2230 * handle async rx data interrupts
2231 */
2232 static void isr_rxrdy(SLMP_INFO * info)
2233 {
2234 u16 status;
2235 unsigned char DataByte;
2236 struct tty_struct *tty = info->port.tty;
2237 struct mgsl_icount *icount = &info->icount;
2238
2239 if ( debug_level >= DEBUG_LEVEL_ISR )
2240 printk("%s(%d):%s isr_rxrdy\n",
2241 __FILE__,__LINE__,info->device_name);
2242
2243 while((status = read_reg(info,CST0)) & BIT0)
2244 {
2245 int flag = 0;
2246 bool over = false;
2247 DataByte = read_reg(info,TRB);
2248
2249 icount->rx++;
2250
2251 if ( status & (PE + FRME + OVRN) ) {
2252 printk("%s(%d):%s rxerr=%04X\n",
2253 __FILE__,__LINE__,info->device_name,status);
2254
2255 /* update error statistics */
2256 if (status & PE)
2257 icount->parity++;
2258 else if (status & FRME)
2259 icount->frame++;
2260 else if (status & OVRN)
2261 icount->overrun++;
2262
2263 /* discard char if tty control flags say so */
2264 if (status & info->ignore_status_mask2)
2265 continue;
2266
2267 status &= info->read_status_mask2;
2268
2269 if ( tty ) {
2270 if (status & PE)
2271 flag = TTY_PARITY;
2272 else if (status & FRME)
2273 flag = TTY_FRAME;
2274 if (status & OVRN) {
2275 /* Overrun is special, since it's
2276 * reported immediately, and doesn't
2277 * affect the current character
2278 */
2279 over = true;
2280 }
2281 }
2282 } /* end of if (error) */
2283
2284 if ( tty ) {
2285 tty_insert_flip_char(tty, DataByte, flag);
2286 if (over)
2287 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2288 }
2289 }
2290
2291 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2292 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2293 __FILE__,__LINE__,info->device_name,
2294 icount->rx,icount->brk,icount->parity,
2295 icount->frame,icount->overrun);
2296 }
2297
2298 if ( tty )
2299 tty_flip_buffer_push(tty);
2300 }
2301
2302 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2303 {
2304 if ( debug_level >= DEBUG_LEVEL_ISR )
2305 printk("%s(%d):%s isr_txeom status=%02x\n",
2306 __FILE__,__LINE__,info->device_name,status);
2307
2308 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2309 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2310 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2311
2312 if (status & UDRN) {
2313 write_reg(info, CMD, TXRESET);
2314 write_reg(info, CMD, TXENABLE);
2315 } else
2316 write_reg(info, CMD, TXBUFCLR);
2317
2318 /* disable and clear tx interrupts */
2319 info->ie0_value &= ~TXRDYE;
2320 info->ie1_value &= ~(IDLE + UDRN);
2321 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2322 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2323
2324 if ( info->tx_active ) {
2325 if (info->params.mode != MGSL_MODE_ASYNC) {
2326 if (status & UDRN)
2327 info->icount.txunder++;
2328 else if (status & IDLE)
2329 info->icount.txok++;
2330 }
2331
2332 info->tx_active = false;
2333 info->tx_count = info->tx_put = info->tx_get = 0;
2334
2335 del_timer(&info->tx_timer);
2336
2337 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2338 info->serial_signals &= ~SerialSignal_RTS;
2339 info->drop_rts_on_tx_done = false;
2340 set_signals(info);
2341 }
2342
2343 #if SYNCLINK_GENERIC_HDLC
2344 if (info->netcount)
2345 hdlcdev_tx_done(info);
2346 else
2347 #endif
2348 {
2349 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2350 tx_stop(info);
2351 return;
2352 }
2353 info->pending_bh |= BH_TRANSMIT;
2354 }
2355 }
2356 }
2357
2358
2359 /*
2360 * handle tx status interrupts
2361 */
2362 static void isr_txint(SLMP_INFO * info)
2363 {
2364 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2365
2366 /* clear status bits */
2367 write_reg(info, SR1, status);
2368
2369 if ( debug_level >= DEBUG_LEVEL_ISR )
2370 printk("%s(%d):%s isr_txint status=%02x\n",
2371 __FILE__,__LINE__,info->device_name,status);
2372
2373 if (status & (UDRN + IDLE))
2374 isr_txeom(info, status);
2375
2376 if (status & CCTS) {
2377 /* simulate a common modem status change interrupt
2378 * for our handler
2379 */
2380 get_signals( info );
2381 isr_io_pin(info,
2382 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2383
2384 }
2385 }
2386
2387 /*
2388 * handle async tx data interrupts
2389 */
2390 static void isr_txrdy(SLMP_INFO * info)
2391 {
2392 if ( debug_level >= DEBUG_LEVEL_ISR )
2393 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2394 __FILE__,__LINE__,info->device_name,info->tx_count);
2395
2396 if (info->params.mode != MGSL_MODE_ASYNC) {
2397 /* disable TXRDY IRQ, enable IDLE IRQ */
2398 info->ie0_value &= ~TXRDYE;
2399 info->ie1_value |= IDLE;
2400 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2401 return;
2402 }
2403
2404 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2405 tx_stop(info);
2406 return;
2407 }
2408
2409 if ( info->tx_count )
2410 tx_load_fifo( info );
2411 else {
2412 info->tx_active = false;
2413 info->ie0_value &= ~TXRDYE;
2414 write_reg(info, IE0, info->ie0_value);
2415 }
2416
2417 if (info->tx_count < WAKEUP_CHARS)
2418 info->pending_bh |= BH_TRANSMIT;
2419 }
2420
2421 static void isr_rxdmaok(SLMP_INFO * info)
2422 {
2423 /* BIT7 = EOT (end of transfer)
2424 * BIT6 = EOM (end of message/frame)
2425 */
2426 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2427
2428 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2429 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2430
2431 if ( debug_level >= DEBUG_LEVEL_ISR )
2432 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2433 __FILE__,__LINE__,info->device_name,status);
2434
2435 info->pending_bh |= BH_RECEIVE;
2436 }
2437
2438 static void isr_rxdmaerror(SLMP_INFO * info)
2439 {
2440 /* BIT5 = BOF (buffer overflow)
2441 * BIT4 = COF (counter overflow)
2442 */
2443 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2444
2445 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2446 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2447
2448 if ( debug_level >= DEBUG_LEVEL_ISR )
2449 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2450 __FILE__,__LINE__,info->device_name,status);
2451
2452 info->rx_overflow = true;
2453 info->pending_bh |= BH_RECEIVE;
2454 }
2455
2456 static void isr_txdmaok(SLMP_INFO * info)
2457 {
2458 unsigned char status_reg1 = read_reg(info, SR1);
2459
2460 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2461 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2462 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2463
2464 if ( debug_level >= DEBUG_LEVEL_ISR )
2465 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2466 __FILE__,__LINE__,info->device_name,status_reg1);
2467
2468 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2469 write_reg16(info, TRC0, 0);
2470 info->ie0_value |= TXRDYE;
2471 write_reg(info, IE0, info->ie0_value);
2472 }
2473
2474 static void isr_txdmaerror(SLMP_INFO * info)
2475 {
2476 /* BIT5 = BOF (buffer overflow)
2477 * BIT4 = COF (counter overflow)
2478 */
2479 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2480
2481 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2482 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2483
2484 if ( debug_level >= DEBUG_LEVEL_ISR )
2485 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2486 __FILE__,__LINE__,info->device_name,status);
2487 }
2488
2489 /* handle input serial signal changes
2490 */
2491 static void isr_io_pin( SLMP_INFO *info, u16 status )
2492 {
2493 struct mgsl_icount *icount;
2494
2495 if ( debug_level >= DEBUG_LEVEL_ISR )
2496 printk("%s(%d):isr_io_pin status=%04X\n",
2497 __FILE__,__LINE__,status);
2498
2499 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2500 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2501 icount = &info->icount;
2502 /* update input line counters */
2503 if (status & MISCSTATUS_RI_LATCHED) {
2504 icount->rng++;
2505 if ( status & SerialSignal_RI )
2506 info->input_signal_events.ri_up++;
2507 else
2508 info->input_signal_events.ri_down++;
2509 }
2510 if (status & MISCSTATUS_DSR_LATCHED) {
2511 icount->dsr++;
2512 if ( status & SerialSignal_DSR )
2513 info->input_signal_events.dsr_up++;
2514 else
2515 info->input_signal_events.dsr_down++;
2516 }
2517 if (status & MISCSTATUS_DCD_LATCHED) {
2518 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2519 info->ie1_value &= ~CDCD;
2520 write_reg(info, IE1, info->ie1_value);
2521 }
2522 icount->dcd++;
2523 if (status & SerialSignal_DCD) {
2524 info->input_signal_events.dcd_up++;
2525 } else
2526 info->input_signal_events.dcd_down++;
2527 #if SYNCLINK_GENERIC_HDLC
2528 if (info->netcount) {
2529 if (status & SerialSignal_DCD)
2530 netif_carrier_on(info->netdev);
2531 else
2532 netif_carrier_off(info->netdev);
2533 }
2534 #endif
2535 }
2536 if (status & MISCSTATUS_CTS_LATCHED)
2537 {
2538 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2539 info->ie1_value &= ~CCTS;
2540 write_reg(info, IE1, info->ie1_value);
2541 }
2542 icount->cts++;
2543 if ( status & SerialSignal_CTS )
2544 info->input_signal_events.cts_up++;
2545 else
2546 info->input_signal_events.cts_down++;
2547 }
2548 wake_up_interruptible(&info->status_event_wait_q);
2549 wake_up_interruptible(&info->event_wait_q);
2550
2551 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2552 (status & MISCSTATUS_DCD_LATCHED) ) {
2553 if ( debug_level >= DEBUG_LEVEL_ISR )
2554 printk("%s CD now %s...", info->device_name,
2555 (status & SerialSignal_DCD) ? "on" : "off");
2556 if (status & SerialSignal_DCD)
2557 wake_up_interruptible(&info->port.open_wait);
2558 else {
2559 if ( debug_level >= DEBUG_LEVEL_ISR )
2560 printk("doing serial hangup...");
2561 if (info->port.tty)
2562 tty_hangup(info->port.tty);
2563 }
2564 }
2565
2566 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2567 (status & MISCSTATUS_CTS_LATCHED) ) {
2568 if ( info->port.tty ) {
2569 if (info->port.tty->hw_stopped) {
2570 if (status & SerialSignal_CTS) {
2571 if ( debug_level >= DEBUG_LEVEL_ISR )
2572 printk("CTS tx start...");
2573 info->port.tty->hw_stopped = 0;
2574 tx_start(info);
2575 info->pending_bh |= BH_TRANSMIT;
2576 return;
2577 }
2578 } else {
2579 if (!(status & SerialSignal_CTS)) {
2580 if ( debug_level >= DEBUG_LEVEL_ISR )
2581 printk("CTS tx stop...");
2582 info->port.tty->hw_stopped = 1;
2583 tx_stop(info);
2584 }
2585 }
2586 }
2587 }
2588 }
2589
2590 info->pending_bh |= BH_STATUS;
2591 }
2592
2593 /* Interrupt service routine entry point.
2594 *
2595 * Arguments:
2596 * irq interrupt number that caused interrupt
2597 * dev_id device ID supplied during interrupt registration
2598 * regs interrupted processor context
2599 */
2600 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2601 {
2602 SLMP_INFO *info = dev_id;
2603 unsigned char status, status0, status1=0;
2604 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2605 unsigned char timerstatus0, timerstatus1=0;
2606 unsigned char shift;
2607 unsigned int i;
2608 unsigned short tmp;
2609
2610 if ( debug_level >= DEBUG_LEVEL_ISR )
2611 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2612 __FILE__, __LINE__, info->irq_level);
2613
2614 spin_lock(&info->lock);
2615
2616 for(;;) {
2617
2618 /* get status for SCA0 (ports 0-1) */
2619 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2620 status0 = (unsigned char)tmp;
2621 dmastatus0 = (unsigned char)(tmp>>8);
2622 timerstatus0 = read_reg(info, ISR2);
2623
2624 if ( debug_level >= DEBUG_LEVEL_ISR )
2625 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2626 __FILE__, __LINE__, info->device_name,
2627 status0, dmastatus0, timerstatus0);
2628
2629 if (info->port_count == 4) {
2630 /* get status for SCA1 (ports 2-3) */
2631 tmp = read_reg16(info->port_array[2], ISR0);
2632 status1 = (unsigned char)tmp;
2633 dmastatus1 = (unsigned char)(tmp>>8);
2634 timerstatus1 = read_reg(info->port_array[2], ISR2);
2635
2636 if ( debug_level >= DEBUG_LEVEL_ISR )
2637 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2638 __FILE__,__LINE__,info->device_name,
2639 status1,dmastatus1,timerstatus1);
2640 }
2641
2642 if (!status0 && !dmastatus0 && !timerstatus0 &&
2643 !status1 && !dmastatus1 && !timerstatus1)
2644 break;
2645
2646 for(i=0; i < info->port_count ; i++) {
2647 if (info->port_array[i] == NULL)
2648 continue;
2649 if (i < 2) {
2650 status = status0;
2651 dmastatus = dmastatus0;
2652 } else {
2653 status = status1;
2654 dmastatus = dmastatus1;
2655 }
2656
2657 shift = i & 1 ? 4 :0;
2658
2659 if (status & BIT0 << shift)
2660 isr_rxrdy(info->port_array[i]);
2661 if (status & BIT1 << shift)
2662 isr_txrdy(info->port_array[i]);
2663 if (status & BIT2 << shift)
2664 isr_rxint(info->port_array[i]);
2665 if (status & BIT3 << shift)
2666 isr_txint(info->port_array[i]);
2667
2668 if (dmastatus & BIT0 << shift)
2669 isr_rxdmaerror(info->port_array[i]);
2670 if (dmastatus & BIT1 << shift)
2671 isr_rxdmaok(info->port_array[i]);
2672 if (dmastatus & BIT2 << shift)
2673 isr_txdmaerror(info->port_array[i]);
2674 if (dmastatus & BIT3 << shift)
2675 isr_txdmaok(info->port_array[i]);
2676 }
2677
2678 if (timerstatus0 & (BIT5 | BIT4))
2679 isr_timer(info->port_array[0]);
2680 if (timerstatus0 & (BIT7 | BIT6))
2681 isr_timer(info->port_array[1]);
2682 if (timerstatus1 & (BIT5 | BIT4))
2683 isr_timer(info->port_array[2]);
2684 if (timerstatus1 & (BIT7 | BIT6))
2685 isr_timer(info->port_array[3]);
2686 }
2687
2688 for(i=0; i < info->port_count ; i++) {
2689 SLMP_INFO * port = info->port_array[i];
2690
2691 /* Request bottom half processing if there's something
2692 * for it to do and the bh is not already running.
2693 *
2694 * Note: startup adapter diags require interrupts.
2695 * do not request bottom half processing if the
2696 * device is not open in a normal mode.
2697 */
2698 if ( port && (port->port.count || port->netcount) &&
2699 port->pending_bh && !port->bh_running &&
2700 !port->bh_requested ) {
2701 if ( debug_level >= DEBUG_LEVEL_ISR )
2702 printk("%s(%d):%s queueing bh task.\n",
2703 __FILE__,__LINE__,port->device_name);
2704 schedule_work(&port->task);
2705 port->bh_requested = true;
2706 }
2707 }
2708
2709 spin_unlock(&info->lock);
2710
2711 if ( debug_level >= DEBUG_LEVEL_ISR )
2712 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2713 __FILE__, __LINE__, info->irq_level);
2714 return IRQ_HANDLED;
2715 }
2716
2717 /* Initialize and start device.
2718 */
2719 static int startup(SLMP_INFO * info)
2720 {
2721 if ( debug_level >= DEBUG_LEVEL_INFO )
2722 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2723
2724 if (info->port.flags & ASYNC_INITIALIZED)
2725 return 0;
2726
2727 if (!info->tx_buf) {
2728 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2729 if (!info->tx_buf) {
2730 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2731 __FILE__,__LINE__,info->device_name);
2732 return -ENOMEM;
2733 }
2734 }
2735
2736 info->pending_bh = 0;
2737
2738 memset(&info->icount, 0, sizeof(info->icount));
2739
2740 /* program hardware for current parameters */
2741 reset_port(info);
2742
2743 change_params(info);
2744
2745 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2746
2747 if (info->port.tty)
2748 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2749
2750 info->port.flags |= ASYNC_INITIALIZED;
2751
2752 return 0;
2753 }
2754
2755 /* Called by close() and hangup() to shutdown hardware
2756 */
2757 static void shutdown(SLMP_INFO * info)
2758 {
2759 unsigned long flags;
2760
2761 if (!(info->port.flags & ASYNC_INITIALIZED))
2762 return;
2763
2764 if (debug_level >= DEBUG_LEVEL_INFO)
2765 printk("%s(%d):%s synclinkmp_shutdown()\n",
2766 __FILE__,__LINE__, info->device_name );
2767
2768 /* clear status wait queue because status changes */
2769 /* can't happen after shutting down the hardware */
2770 wake_up_interruptible(&info->status_event_wait_q);
2771 wake_up_interruptible(&info->event_wait_q);
2772
2773 del_timer(&info->tx_timer);
2774 del_timer(&info->status_timer);
2775
2776 kfree(info->tx_buf);
2777 info->tx_buf = NULL;
2778
2779 spin_lock_irqsave(&info->lock,flags);
2780
2781 reset_port(info);
2782
2783 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2784 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2785 set_signals(info);
2786 }
2787
2788 spin_unlock_irqrestore(&info->lock,flags);
2789
2790 if (info->port.tty)
2791 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2792
2793 info->port.flags &= ~ASYNC_INITIALIZED;
2794 }
2795
2796 static void program_hw(SLMP_INFO *info)
2797 {
2798 unsigned long flags;
2799
2800 spin_lock_irqsave(&info->lock,flags);
2801
2802 rx_stop(info);
2803 tx_stop(info);
2804
2805 info->tx_count = info->tx_put = info->tx_get = 0;
2806
2807 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2808 hdlc_mode(info);
2809 else
2810 async_mode(info);
2811
2812 set_signals(info);
2813
2814 info->dcd_chkcount = 0;
2815 info->cts_chkcount = 0;
2816 info->ri_chkcount = 0;
2817 info->dsr_chkcount = 0;
2818
2819 info->ie1_value |= (CDCD|CCTS);
2820 write_reg(info, IE1, info->ie1_value);
2821
2822 get_signals(info);
2823
2824 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2825 rx_start(info);
2826
2827 spin_unlock_irqrestore(&info->lock,flags);
2828 }
2829
2830 /* Reconfigure adapter based on new parameters
2831 */
2832 static void change_params(SLMP_INFO *info)
2833 {
2834 unsigned cflag;
2835 int bits_per_char;
2836
2837 if (!info->port.tty || !info->port.tty->termios)
2838 return;
2839
2840 if (debug_level >= DEBUG_LEVEL_INFO)
2841 printk("%s(%d):%s change_params()\n",
2842 __FILE__,__LINE__, info->device_name );
2843
2844 cflag = info->port.tty->termios->c_cflag;
2845
2846 /* if B0 rate (hangup) specified then negate DTR and RTS */
2847 /* otherwise assert DTR and RTS */
2848 if (cflag & CBAUD)
2849 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2850 else
2851 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2852
2853 /* byte size and parity */
2854
2855 switch (cflag & CSIZE) {
2856 case CS5: info->params.data_bits = 5; break;
2857 case CS6: info->params.data_bits = 6; break;
2858 case CS7: info->params.data_bits = 7; break;
2859 case CS8: info->params.data_bits = 8; break;
2860 /* Never happens, but GCC is too dumb to figure it out */
2861 default: info->params.data_bits = 7; break;
2862 }
2863
2864 if (cflag & CSTOPB)
2865 info->params.stop_bits = 2;
2866 else
2867 info->params.stop_bits = 1;
2868
2869 info->params.parity = ASYNC_PARITY_NONE;
2870 if (cflag & PARENB) {
2871 if (cflag & PARODD)
2872 info->params.parity = ASYNC_PARITY_ODD;
2873 else
2874 info->params.parity = ASYNC_PARITY_EVEN;
2875 #ifdef CMSPAR
2876 if (cflag & CMSPAR)
2877 info->params.parity = ASYNC_PARITY_SPACE;
2878 #endif
2879 }
2880
2881 /* calculate number of jiffies to transmit a full
2882 * FIFO (32 bytes) at specified data rate
2883 */
2884 bits_per_char = info->params.data_bits +
2885 info->params.stop_bits + 1;
2886
2887 /* if port data rate is set to 460800 or less then
2888 * allow tty settings to override, otherwise keep the
2889 * current data rate.
2890 */
2891 if (info->params.data_rate <= 460800) {
2892 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2893 }
2894
2895 if ( info->params.data_rate ) {
2896 info->timeout = (32*HZ*bits_per_char) /
2897 info->params.data_rate;
2898 }
2899 info->timeout += HZ/50; /* Add .02 seconds of slop */
2900
2901 if (cflag & CRTSCTS)
2902 info->port.flags |= ASYNC_CTS_FLOW;
2903 else
2904 info->port.flags &= ~ASYNC_CTS_FLOW;
2905
2906 if (cflag & CLOCAL)
2907 info->port.flags &= ~ASYNC_CHECK_CD;
2908 else
2909 info->port.flags |= ASYNC_CHECK_CD;
2910
2911 /* process tty input control flags */
2912
2913 info->read_status_mask2 = OVRN;
2914 if (I_INPCK(info->port.tty))
2915 info->read_status_mask2 |= PE | FRME;
2916 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2917 info->read_status_mask1 |= BRKD;
2918 if (I_IGNPAR(info->port.tty))
2919 info->ignore_status_mask2 |= PE | FRME;
2920 if (I_IGNBRK(info->port.tty)) {
2921 info->ignore_status_mask1 |= BRKD;
2922 /* If ignoring parity and break indicators, ignore
2923 * overruns too. (For real raw support).
2924 */
2925 if (I_IGNPAR(info->port.tty))
2926 info->ignore_status_mask2 |= OVRN;
2927 }
2928
2929 program_hw(info);
2930 }
2931
2932 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2933 {
2934 int err;
2935
2936 if (debug_level >= DEBUG_LEVEL_INFO)
2937 printk("%s(%d):%s get_params()\n",
2938 __FILE__,__LINE__, info->device_name);
2939
2940 if (!user_icount) {
2941 memset(&info->icount, 0, sizeof(info->icount));
2942 } else {
2943 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2944 if (err)
2945 return -EFAULT;
2946 }
2947
2948 return 0;
2949 }
2950
2951 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2952 {
2953 int err;
2954 if (debug_level >= DEBUG_LEVEL_INFO)
2955 printk("%s(%d):%s get_params()\n",
2956 __FILE__,__LINE__, info->device_name);
2957
2958 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2959 if (err) {
2960 if ( debug_level >= DEBUG_LEVEL_INFO )
2961 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2962 __FILE__,__LINE__,info->device_name);
2963 return -EFAULT;
2964 }
2965
2966 return 0;
2967 }
2968
2969 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2970 {
2971 unsigned long flags;
2972 MGSL_PARAMS tmp_params;
2973 int err;
2974
2975 if (debug_level >= DEBUG_LEVEL_INFO)
2976 printk("%s(%d):%s set_params\n",
2977 __FILE__,__LINE__,info->device_name );
2978 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2979 if (err) {
2980 if ( debug_level >= DEBUG_LEVEL_INFO )
2981 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2982 __FILE__,__LINE__,info->device_name);
2983 return -EFAULT;
2984 }
2985
2986 spin_lock_irqsave(&info->lock,flags);
2987 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2988 spin_unlock_irqrestore(&info->lock,flags);
2989
2990 change_params(info);
2991
2992 return 0;
2993 }
2994
2995 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2996 {
2997 int err;
2998
2999 if (debug_level >= DEBUG_LEVEL_INFO)
3000 printk("%s(%d):%s get_txidle()=%d\n",
3001 __FILE__,__LINE__, info->device_name, info->idle_mode);
3002
3003 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3004 if (err) {
3005 if ( debug_level >= DEBUG_LEVEL_INFO )
3006 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3007 __FILE__,__LINE__,info->device_name);
3008 return -EFAULT;
3009 }
3010
3011 return 0;
3012 }
3013
3014 static int set_txidle(SLMP_INFO * info, int idle_mode)
3015 {
3016 unsigned long flags;
3017
3018 if (debug_level >= DEBUG_LEVEL_INFO)
3019 printk("%s(%d):%s set_txidle(%d)\n",
3020 __FILE__,__LINE__,info->device_name, idle_mode );
3021
3022 spin_lock_irqsave(&info->lock,flags);
3023 info->idle_mode = idle_mode;
3024 tx_set_idle( info );
3025 spin_unlock_irqrestore(&info->lock,flags);
3026 return 0;
3027 }
3028
3029 static int tx_enable(SLMP_INFO * info, int enable)
3030 {
3031 unsigned long flags;
3032
3033 if (debug_level >= DEBUG_LEVEL_INFO)
3034 printk("%s(%d):%s tx_enable(%d)\n",
3035 __FILE__,__LINE__,info->device_name, enable);
3036
3037 spin_lock_irqsave(&info->lock,flags);
3038 if ( enable ) {
3039 if ( !info->tx_enabled ) {
3040 tx_start(info);
3041 }
3042 } else {
3043 if ( info->tx_enabled )
3044 tx_stop(info);
3045 }
3046 spin_unlock_irqrestore(&info->lock,flags);
3047 return 0;
3048 }
3049
3050 /* abort send HDLC frame
3051 */
3052 static int tx_abort(SLMP_INFO * info)
3053 {
3054 unsigned long flags;
3055
3056 if (debug_level >= DEBUG_LEVEL_INFO)
3057 printk("%s(%d):%s tx_abort()\n",
3058 __FILE__,__LINE__,info->device_name);
3059
3060 spin_lock_irqsave(&info->lock,flags);
3061 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3062 info->ie1_value &= ~UDRN;
3063 info->ie1_value |= IDLE;
3064 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3065 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3066
3067 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3068 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3069
3070 write_reg(info, CMD, TXABORT);
3071 }
3072 spin_unlock_irqrestore(&info->lock,flags);
3073 return 0;
3074 }
3075
3076 static int rx_enable(SLMP_INFO * info, int enable)
3077 {
3078 unsigned long flags;
3079
3080 if (debug_level >= DEBUG_LEVEL_INFO)
3081 printk("%s(%d):%s rx_enable(%d)\n",
3082 __FILE__,__LINE__,info->device_name,enable);
3083
3084 spin_lock_irqsave(&info->lock,flags);
3085 if ( enable ) {
3086 if ( !info->rx_enabled )
3087 rx_start(info);
3088 } else {
3089 if ( info->rx_enabled )
3090 rx_stop(info);
3091 }
3092 spin_unlock_irqrestore(&info->lock,flags);
3093 return 0;
3094 }
3095
3096 /* wait for specified event to occur
3097 */
3098 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3099 {
3100 unsigned long flags;
3101 int s;
3102 int rc=0;
3103 struct mgsl_icount cprev, cnow;
3104 int events;
3105 int mask;
3106 struct _input_signal_events oldsigs, newsigs;
3107 DECLARE_WAITQUEUE(wait, current);
3108
3109 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3110 if (rc) {
3111 return -EFAULT;
3112 }
3113
3114 if (debug_level >= DEBUG_LEVEL_INFO)
3115 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3116 __FILE__,__LINE__,info->device_name,mask);
3117
3118 spin_lock_irqsave(&info->lock,flags);
3119
3120 /* return immediately if state matches requested events */
3121 get_signals(info);
3122 s = info->serial_signals;
3123
3124 events = mask &
3125 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3126 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3127 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3128 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3129 if (events) {
3130 spin_unlock_irqrestore(&info->lock,flags);
3131 goto exit;
3132 }
3133
3134 /* save current irq counts */
3135 cprev = info->icount;
3136 oldsigs = info->input_signal_events;
3137
3138 /* enable hunt and idle irqs if needed */
3139 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3140 unsigned char oldval = info->ie1_value;
3141 unsigned char newval = oldval +
3142 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3143 (mask & MgslEvent_IdleReceived ? IDLD:0);
3144 if ( oldval != newval ) {
3145 info->ie1_value = newval;
3146 write_reg(info, IE1, info->ie1_value);
3147 }
3148 }
3149
3150 set_current_state(TASK_INTERRUPTIBLE);
3151 add_wait_queue(&info->event_wait_q, &wait);
3152
3153 spin_unlock_irqrestore(&info->lock,flags);
3154
3155 for(;;) {
3156 schedule();
3157 if (signal_pending(current)) {
3158 rc = -ERESTARTSYS;
3159 break;
3160 }
3161
3162 /* get current irq counts */
3163 spin_lock_irqsave(&info->lock,flags);
3164 cnow = info->icount;
3165 newsigs = info->input_signal_events;
3166 set_current_state(TASK_INTERRUPTIBLE);
3167 spin_unlock_irqrestore(&info->lock,flags);
3168
3169 /* if no change, wait aborted for some reason */
3170 if (newsigs.dsr_up == oldsigs.dsr_up &&
3171 newsigs.dsr_down == oldsigs.dsr_down &&
3172 newsigs.dcd_up == oldsigs.dcd_up &&
3173 newsigs.dcd_down == oldsigs.dcd_down &&
3174 newsigs.cts_up == oldsigs.cts_up &&
3175 newsigs.cts_down == oldsigs.cts_down &&
3176 newsigs.ri_up == oldsigs.ri_up &&
3177 newsigs.ri_down == oldsigs.ri_down &&
3178 cnow.exithunt == cprev.exithunt &&
3179 cnow.rxidle == cprev.rxidle) {
3180 rc = -EIO;
3181 break;
3182 }
3183
3184 events = mask &
3185 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3186 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3187 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3188 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3189 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3190 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3191 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3192 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3193 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3194 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3195 if (events)
3196 break;
3197
3198 cprev = cnow;
3199 oldsigs = newsigs;
3200 }
3201
3202 remove_wait_queue(&info->event_wait_q, &wait);
3203 set_current_state(TASK_RUNNING);
3204
3205
3206 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3207 spin_lock_irqsave(&info->lock,flags);
3208 if (!waitqueue_active(&info->event_wait_q)) {
3209 /* disable enable exit hunt mode/idle rcvd IRQs */
3210 info->ie1_value &= ~(FLGD|IDLD);
3211 write_reg(info, IE1, info->ie1_value);
3212 }
3213 spin_unlock_irqrestore(&info->lock,flags);
3214 }
3215 exit:
3216 if ( rc == 0 )
3217 PUT_USER(rc, events, mask_ptr);
3218
3219 return rc;
3220 }
3221
3222 static int modem_input_wait(SLMP_INFO *info,int arg)
3223 {
3224 unsigned long flags;
3225 int rc;
3226 struct mgsl_icount cprev, cnow;
3227 DECLARE_WAITQUEUE(wait, current);
3228
3229 /* save current irq counts */
3230 spin_lock_irqsave(&info->lock,flags);
3231 cprev = info->icount;
3232 add_wait_queue(&info->status_event_wait_q, &wait);
3233 set_current_state(TASK_INTERRUPTIBLE);
3234 spin_unlock_irqrestore(&info->lock,flags);
3235
3236 for(;;) {
3237 schedule();
3238 if (signal_pending(current)) {
3239 rc = -ERESTARTSYS;
3240 break;
3241 }
3242
3243 /* get new irq counts */
3244 spin_lock_irqsave(&info->lock,flags);
3245 cnow = info->icount;
3246 set_current_state(TASK_INTERRUPTIBLE);
3247 spin_unlock_irqrestore(&info->lock,flags);
3248
3249 /* if no change, wait aborted for some reason */
3250 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3251 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3252 rc = -EIO;
3253 break;
3254 }
3255
3256 /* check for change in caller specified modem input */
3257 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3258 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3259 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3260 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3261 rc = 0;
3262 break;
3263 }
3264
3265 cprev = cnow;
3266 }
3267 remove_wait_queue(&info->status_event_wait_q, &wait);
3268 set_current_state(TASK_RUNNING);
3269 return rc;
3270 }
3271
3272 /* return the state of the serial control and status signals
3273 */
3274 static int tiocmget(struct tty_struct *tty, struct file *file)
3275 {
3276 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3277 unsigned int result;
3278 unsigned long flags;
3279
3280 spin_lock_irqsave(&info->lock,flags);
3281 get_signals(info);
3282 spin_unlock_irqrestore(&info->lock,flags);
3283
3284 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3285 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3286 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3287 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3288 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3289 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3290
3291 if (debug_level >= DEBUG_LEVEL_INFO)
3292 printk("%s(%d):%s tiocmget() value=%08X\n",
3293 __FILE__,__LINE__, info->device_name, result );
3294 return result;
3295 }
3296
3297 /* set modem control signals (DTR/RTS)
3298 */
3299 static int tiocmset(struct tty_struct *tty, struct file *file,
3300 unsigned int set, unsigned int clear)
3301 {
3302 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3303 unsigned long flags;
3304
3305 if (debug_level >= DEBUG_LEVEL_INFO)
3306 printk("%s(%d):%s tiocmset(%x,%x)\n",
3307 __FILE__,__LINE__,info->device_name, set, clear);
3308
3309 if (set & TIOCM_RTS)
3310 info->serial_signals |= SerialSignal_RTS;
3311 if (set & TIOCM_DTR)
3312 info->serial_signals |= SerialSignal_DTR;
3313 if (clear & TIOCM_RTS)
3314 info->serial_signals &= ~SerialSignal_RTS;
3315 if (clear & TIOCM_DTR)
3316 info->serial_signals &= ~SerialSignal_DTR;
3317
3318 spin_lock_irqsave(&info->lock,flags);
3319 set_signals(info);
3320 spin_unlock_irqrestore(&info->lock,flags);
3321
3322 return 0;
3323 }
3324
3325
3326
3327 /* Block the current process until the specified port is ready to open.
3328 */
3329 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3330 SLMP_INFO *info)
3331 {
3332 DECLARE_WAITQUEUE(wait, current);
3333 int retval;
3334 bool do_clocal = false;
3335 bool extra_count = false;
3336 unsigned long flags;
3337
3338 if (debug_level >= DEBUG_LEVEL_INFO)
3339 printk("%s(%d):%s block_til_ready()\n",
3340 __FILE__,__LINE__, tty->driver->name );
3341
3342 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3343 /* nonblock mode is set or port is not enabled */
3344 /* just verify that callout device is not active */
3345 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3346 return 0;
3347 }
3348
3349 if (tty->termios->c_cflag & CLOCAL)
3350 do_clocal = true;
3351
3352 /* Wait for carrier detect and the line to become
3353 * free (i.e., not in use by the callout). While we are in
3354 * this loop, info->port.count is dropped by one, so that
3355 * close() knows when to free things. We restore it upon
3356 * exit, either normal or abnormal.
3357 */
3358
3359 retval = 0;
3360 add_wait_queue(&info->port.open_wait, &wait);
3361
3362 if (debug_level >= DEBUG_LEVEL_INFO)
3363 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3364 __FILE__,__LINE__, tty->driver->name, info->port.count );
3365
3366 spin_lock_irqsave(&info->lock, flags);
3367 if (!tty_hung_up_p(filp)) {
3368 extra_count = true;
3369 info->port.count--;
3370 }
3371 spin_unlock_irqrestore(&info->lock, flags);
3372 info->port.blocked_open++;
3373
3374 while (1) {
3375 if ((tty->termios->c_cflag & CBAUD)) {
3376 spin_lock_irqsave(&info->lock,flags);
3377 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3378 set_signals(info);
3379 spin_unlock_irqrestore(&info->lock,flags);
3380 }
3381
3382 set_current_state(TASK_INTERRUPTIBLE);
3383
3384 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3385 retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3386 -EAGAIN : -ERESTARTSYS;
3387 break;
3388 }
3389
3390 spin_lock_irqsave(&info->lock,flags);
3391 get_signals(info);
3392 spin_unlock_irqrestore(&info->lock,flags);
3393
3394 if (!(info->port.flags & ASYNC_CLOSING) &&
3395 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3396 break;
3397 }
3398
3399 if (signal_pending(current)) {
3400 retval = -ERESTARTSYS;
3401 break;
3402 }
3403
3404 if (debug_level >= DEBUG_LEVEL_INFO)
3405 printk("%s(%d):%s block_til_ready() count=%d\n",
3406 __FILE__,__LINE__, tty->driver->name, info->port.count );
3407
3408 schedule();
3409 }
3410
3411 set_current_state(TASK_RUNNING);
3412 remove_wait_queue(&info->port.open_wait, &wait);
3413
3414 if (extra_count)
3415 info->port.count++;
3416 info->port.blocked_open--;
3417
3418 if (debug_level >= DEBUG_LEVEL_INFO)
3419 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3420 __FILE__,__LINE__, tty->driver->name, info->port.count );
3421
3422 if (!retval)
3423 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3424
3425 return retval;
3426 }
3427
3428 static int alloc_dma_bufs(SLMP_INFO *info)
3429 {
3430 unsigned short BuffersPerFrame;
3431 unsigned short BufferCount;
3432
3433 // Force allocation to start at 64K boundary for each port.
3434 // This is necessary because *all* buffer descriptors for a port
3435 // *must* be in the same 64K block. All descriptors on a port
3436 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3437 // into the CBP register.
3438 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3439
3440 /* Calculate the number of DMA buffers necessary to hold the */
3441 /* largest allowable frame size. Note: If the max frame size is */
3442 /* not an even multiple of the DMA buffer size then we need to */
3443 /* round the buffer count per frame up one. */
3444
3445 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3446 if ( info->max_frame_size % SCABUFSIZE )
3447 BuffersPerFrame++;
3448
3449 /* calculate total number of data buffers (SCABUFSIZE) possible
3450 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3451 * for the descriptor list (BUFFERLISTSIZE).
3452 */
3453 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3454
3455 /* limit number of buffers to maximum amount of descriptors */
3456 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3457 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3458
3459 /* use enough buffers to transmit one max size frame */
3460 info->tx_buf_count = BuffersPerFrame + 1;
3461
3462 /* never use more than half the available buffers for transmit */
3463 if (info->tx_buf_count > (BufferCount/2))
3464 info->tx_buf_count = BufferCount/2;
3465
3466 if (info->tx_buf_count > SCAMAXDESC)
3467 info->tx_buf_count = SCAMAXDESC;
3468
3469 /* use remaining buffers for receive */
3470 info->rx_buf_count = BufferCount - info->tx_buf_count;
3471
3472 if (info->rx_buf_count > SCAMAXDESC)
3473 info->rx_buf_count = SCAMAXDESC;
3474
3475 if ( debug_level >= DEBUG_LEVEL_INFO )
3476 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3477 __FILE__,__LINE__, info->device_name,
3478 info->tx_buf_count,info->rx_buf_count);
3479
3480 if ( alloc_buf_list( info ) < 0 ||
3481 alloc_frame_bufs(info,
3482 info->rx_buf_list,
3483 info->rx_buf_list_ex,
3484 info->rx_buf_count) < 0 ||
3485 alloc_frame_bufs(info,
3486 info->tx_buf_list,
3487 info->tx_buf_list_ex,
3488 info->tx_buf_count) < 0 ||
3489 alloc_tmp_rx_buf(info) < 0 ) {
3490 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3491 __FILE__,__LINE__, info->device_name);
3492 return -ENOMEM;
3493 }
3494
3495 rx_reset_buffers( info );
3496
3497 return 0;
3498 }
3499
3500 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3501 */
3502 static int alloc_buf_list(SLMP_INFO *info)
3503 {
3504 unsigned int i;
3505
3506 /* build list in adapter shared memory */
3507 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3508 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3509 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3510
3511 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3512
3513 /* Save virtual address pointers to the receive and */
3514 /* transmit buffer lists. (Receive 1st). These pointers will */
3515 /* be used by the processor to access the lists. */
3516 info->rx_buf_list = (SCADESC *)info->buffer_list;
3517
3518 info->tx_buf_list = (SCADESC *)info->buffer_list;
3519 info->tx_buf_list += info->rx_buf_count;
3520
3521 /* Build links for circular buffer entry lists (tx and rx)
3522 *
3523 * Note: links are physical addresses read by the SCA device
3524 * to determine the next buffer entry to use.
3525 */
3526
3527 for ( i = 0; i < info->rx_buf_count; i++ ) {
3528 /* calculate and store physical address of this buffer entry */
3529 info->rx_buf_list_ex[i].phys_entry =
3530 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3531
3532 /* calculate and store physical address of */
3533 /* next entry in cirular list of entries */
3534 info->rx_buf_list[i].next = info->buffer_list_phys;
3535 if ( i < info->rx_buf_count - 1 )
3536 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3537
3538 info->rx_buf_list[i].length = SCABUFSIZE;
3539 }
3540
3541 for ( i = 0; i < info->tx_buf_count; i++ ) {
3542 /* calculate and store physical address of this buffer entry */
3543 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3544 ((info->rx_buf_count + i) * sizeof(SCADESC));
3545
3546 /* calculate and store physical address of */
3547 /* next entry in cirular list of entries */
3548
3549 info->tx_buf_list[i].next = info->buffer_list_phys +
3550 info->rx_buf_count * sizeof(SCADESC);
3551
3552 if ( i < info->tx_buf_count - 1 )
3553 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3554 }
3555
3556 return 0;
3557 }
3558
3559 /* Allocate the frame DMA buffers used by the specified buffer list.
3560 */
3561 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3562 {
3563 int i;
3564 unsigned long phys_addr;
3565
3566 for ( i = 0; i < count; i++ ) {
3567 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3568 phys_addr = info->port_array[0]->last_mem_alloc;
3569 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3570
3571 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3572 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3573 }
3574
3575 return 0;
3576 }
3577
3578 static void free_dma_bufs(SLMP_INFO *info)
3579 {
3580 info->buffer_list = NULL;
3581 info->rx_buf_list = NULL;
3582 info->tx_buf_list = NULL;
3583 }
3584
3585 /* allocate buffer large enough to hold max_frame_size.
3586 * This buffer is used to pass an assembled frame to the line discipline.
3587 */
3588 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3589 {
3590 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3591 if (info->tmp_rx_buf == NULL)
3592 return -ENOMEM;
3593 return 0;
3594 }
3595
3596 static void free_tmp_rx_buf(SLMP_INFO *info)
3597 {
3598 kfree(info->tmp_rx_buf);
3599 info->tmp_rx_buf = NULL;
3600 }
3601
3602 static int claim_resources(SLMP_INFO *info)
3603 {
3604 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3605 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3606 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3607 info->init_error = DiagStatus_AddressConflict;
3608 goto errout;
3609 }
3610 else
3611 info->shared_mem_requested = true;
3612
3613 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3614 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3615 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3616 info->init_error = DiagStatus_AddressConflict;
3617 goto errout;
3618 }
3619 else
3620 info->lcr_mem_requested = true;
3621
3622 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3623 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3624 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3625 info->init_error = DiagStatus_AddressConflict;
3626 goto errout;
3627 }
3628 else
3629 info->sca_base_requested = true;
3630
3631 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3632 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3633 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3634 info->init_error = DiagStatus_AddressConflict;
3635 goto errout;
3636 }
3637 else
3638 info->sca_statctrl_requested = true;
3639
3640 info->memory_base = ioremap_nocache(info->phys_memory_base,
3641 SCA_MEM_SIZE);
3642 if (!info->memory_base) {
3643 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3644 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3645 info->init_error = DiagStatus_CantAssignPciResources;
3646 goto errout;
3647 }
3648
3649 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3650 if (!info->lcr_base) {
3651 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3652 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3653 info->init_error = DiagStatus_CantAssignPciResources;
3654 goto errout;
3655 }
3656 info->lcr_base += info->lcr_offset;
3657
3658 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3659 if (!info->sca_base) {
3660 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3661 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3662 info->init_error = DiagStatus_CantAssignPciResources;
3663 goto errout;
3664 }
3665 info->sca_base += info->sca_offset;
3666
3667 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3668 PAGE_SIZE);
3669 if (!info->statctrl_base) {
3670 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3671 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3672 info->init_error = DiagStatus_CantAssignPciResources;
3673 goto errout;
3674 }
3675 info->statctrl_base += info->statctrl_offset;
3676
3677 if ( !memory_test(info) ) {
3678 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3679 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3680 info->init_error = DiagStatus_MemoryError;
3681 goto errout;
3682 }
3683
3684 return 0;
3685
3686 errout:
3687 release_resources( info );
3688 return -ENODEV;
3689 }
3690
3691 static void release_resources(SLMP_INFO *info)
3692 {
3693 if ( debug_level >= DEBUG_LEVEL_INFO )
3694 printk( "%s(%d):%s release_resources() entry\n",
3695 __FILE__,__LINE__,info->device_name );
3696
3697 if ( info->irq_requested ) {
3698 free_irq(info->irq_level, info);
3699 info->irq_requested = false;
3700 }
3701
3702 if ( info->shared_mem_requested ) {
3703 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3704 info->shared_mem_requested = false;
3705 }
3706 if ( info->lcr_mem_requested ) {
3707 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3708 info->lcr_mem_requested = false;
3709 }
3710 if ( info->sca_base_requested ) {
3711 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3712 info->sca_base_requested = false;
3713 }
3714 if ( info->sca_statctrl_requested ) {
3715 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3716 info->sca_statctrl_requested = false;
3717 }
3718
3719 if (info->memory_base){
3720 iounmap(info->memory_base);
3721 info->memory_base = NULL;
3722 }
3723
3724 if (info->sca_base) {
3725 iounmap(info->sca_base - info->sca_offset);
3726 info->sca_base=NULL;
3727 }
3728
3729 if (info->statctrl_base) {
3730 iounmap(info->statctrl_base - info->statctrl_offset);
3731 info->statctrl_base=NULL;
3732 }
3733
3734 if (info->lcr_base){
3735 iounmap(info->lcr_base - info->lcr_offset);
3736 info->lcr_base = NULL;
3737 }
3738
3739 if ( debug_level >= DEBUG_LEVEL_INFO )
3740 printk( "%s(%d):%s release_resources() exit\n",
3741 __FILE__,__LINE__,info->device_name );
3742 }
3743
3744 /* Add the specified device instance data structure to the
3745 * global linked list of devices and increment the device count.
3746 */
3747 static void add_device(SLMP_INFO *info)
3748 {
3749 info->next_device = NULL;
3750 info->line = synclinkmp_device_count;
3751 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3752
3753 if (info->line < MAX_DEVICES) {
3754 if (maxframe[info->line])
3755 info->max_frame_size = maxframe[info->line];
3756 info->dosyncppp = dosyncppp[info->line];
3757 }
3758
3759 synclinkmp_device_count++;
3760
3761 if ( !synclinkmp_device_list )
3762 synclinkmp_device_list = info;
3763 else {
3764 SLMP_INFO *current_dev = synclinkmp_device_list;
3765 while( current_dev->next_device )
3766 current_dev = current_dev->next_device;
3767 current_dev->next_device = info;
3768 }
3769
3770 if ( info->max_frame_size < 4096 )
3771 info->max_frame_size = 4096;
3772 else if ( info->max_frame_size > 65535 )
3773 info->max_frame_size = 65535;
3774
3775 printk( "SyncLink MultiPort %s: "
3776 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3777 info->device_name,
3778 info->phys_sca_base,
3779 info->phys_memory_base,
3780 info->phys_statctrl_base,
3781 info->phys_lcr_base,
3782 info->irq_level,
3783 info->max_frame_size );
3784
3785 #if SYNCLINK_GENERIC_HDLC
3786 hdlcdev_init(info);
3787 #endif
3788 }
3789
3790 /* Allocate and initialize a device instance structure
3791 *
3792 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3793 */
3794 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3795 {
3796 SLMP_INFO *info;
3797
3798 info = kzalloc(sizeof(SLMP_INFO),
3799 GFP_KERNEL);
3800
3801 if (!info) {
3802 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3803 __FILE__,__LINE__, adapter_num, port_num);
3804 } else {
3805 tty_port_init(&info->port);
3806 info->magic = MGSL_MAGIC;
3807 INIT_WORK(&info->task, bh_handler);
3808 info->max_frame_size = 4096;
3809 info->port.close_delay = 5*HZ/10;
3810 info->port.closing_wait = 30*HZ;
3811 init_waitqueue_head(&info->status_event_wait_q);
3812 init_waitqueue_head(&info->event_wait_q);
3813 spin_lock_init(&info->netlock);
3814 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3815 info->idle_mode = HDLC_TXIDLE_FLAGS;
3816 info->adapter_num = adapter_num;
3817 info->port_num = port_num;
3818
3819 /* Copy configuration info to device instance data */
3820 info->irq_level = pdev->irq;
3821 info->phys_lcr_base = pci_resource_start(pdev,0);
3822 info->phys_sca_base = pci_resource_start(pdev,2);
3823 info->phys_memory_base = pci_resource_start(pdev,3);
3824 info->phys_statctrl_base = pci_resource_start(pdev,4);
3825
3826 /* Because veremap only works on page boundaries we must map
3827 * a larger area than is actually implemented for the LCR
3828 * memory range. We map a full page starting at the page boundary.
3829 */
3830 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3831 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3832
3833 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3834 info->phys_sca_base &= ~(PAGE_SIZE-1);
3835
3836 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3837 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3838
3839 info->bus_type = MGSL_BUS_TYPE_PCI;
3840 info->irq_flags = IRQF_SHARED;
3841
3842 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3843 setup_timer(&info->status_timer, status_timeout,
3844 (unsigned long)info);
3845
3846 /* Store the PCI9050 misc control register value because a flaw
3847 * in the PCI9050 prevents LCR registers from being read if
3848 * BIOS assigns an LCR base address with bit 7 set.
3849 *
3850 * Only the misc control register is accessed for which only
3851 * write access is needed, so set an initial value and change
3852 * bits to the device instance data as we write the value
3853 * to the actual misc control register.
3854 */
3855 info->misc_ctrl_value = 0x087e4546;
3856
3857 /* initial port state is unknown - if startup errors
3858 * occur, init_error will be set to indicate the
3859 * problem. Once the port is fully initialized,
3860 * this value will be set to 0 to indicate the
3861 * port is available.
3862 */
3863 info->init_error = -1;
3864 }
3865
3866 return info;
3867 }
3868
3869 static void device_init(int adapter_num, struct pci_dev *pdev)
3870 {
3871 SLMP_INFO *port_array[SCA_MAX_PORTS];
3872 int port;
3873
3874 /* allocate device instances for up to SCA_MAX_PORTS devices */
3875 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3876 port_array[port] = alloc_dev(adapter_num,port,pdev);
3877 if( port_array[port] == NULL ) {
3878 for ( --port; port >= 0; --port )
3879 kfree(port_array[port]);
3880 return;
3881 }
3882 }
3883
3884 /* give copy of port_array to all ports and add to device list */
3885 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3886 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3887 add_device( port_array[port] );
3888 spin_lock_init(&port_array[port]->lock);
3889 }
3890
3891 /* Allocate and claim adapter resources */
3892 if ( !claim_resources(port_array[0]) ) {
3893
3894 alloc_dma_bufs(port_array[0]);
3895
3896 /* copy resource information from first port to others */
3897 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3898 port_array[port]->lock = port_array[0]->lock;
3899 port_array[port]->irq_level = port_array[0]->irq_level;
3900 port_array[port]->memory_base = port_array[0]->memory_base;
3901 port_array[port]->sca_base = port_array[0]->sca_base;
3902 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3903 port_array[port]->lcr_base = port_array[0]->lcr_base;
3904 alloc_dma_bufs(port_array[port]);
3905 }
3906
3907 if ( request_irq(port_array[0]->irq_level,
3908 synclinkmp_interrupt,
3909 port_array[0]->irq_flags,
3910 port_array[0]->device_name,
3911 port_array[0]) < 0 ) {
3912 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3913 __FILE__,__LINE__,
3914 port_array[0]->device_name,
3915 port_array[0]->irq_level );
3916 }
3917 else {
3918 port_array[0]->irq_requested = true;
3919 adapter_test(port_array[0]);
3920 }
3921 }
3922 }
3923
3924 static const struct tty_operations ops = {
3925 .open = open,
3926 .close = close,
3927 .write = write,
3928 .put_char = put_char,
3929 .flush_chars = flush_chars,
3930 .write_room = write_room,
3931 .chars_in_buffer = chars_in_buffer,
3932 .flush_buffer = flush_buffer,
3933 .ioctl = ioctl,
3934 .throttle = throttle,
3935 .unthrottle = unthrottle,
3936 .send_xchar = send_xchar,
3937 .break_ctl = set_break,
3938 .wait_until_sent = wait_until_sent,
3939 .read_proc = read_proc,
3940 .set_termios = set_termios,
3941 .stop = tx_hold,
3942 .start = tx_release,
3943 .hangup = hangup,
3944 .tiocmget = tiocmget,
3945 .tiocmset = tiocmset,
3946 };
3947
3948 static void synclinkmp_cleanup(void)
3949 {
3950 int rc;
3951 SLMP_INFO *info;
3952 SLMP_INFO *tmp;
3953
3954 printk("Unloading %s %s\n", driver_name, driver_version);
3955
3956 if (serial_driver) {
3957 if ((rc = tty_unregister_driver(serial_driver)))
3958 printk("%s(%d) failed to unregister tty driver err=%d\n",
3959 __FILE__,__LINE__,rc);
3960 put_tty_driver(serial_driver);
3961 }
3962
3963 /* reset devices */
3964 info = synclinkmp_device_list;
3965 while(info) {
3966 reset_port(info);
3967 info = info->next_device;
3968 }
3969
3970 /* release devices */
3971 info = synclinkmp_device_list;
3972 while(info) {
3973 #if SYNCLINK_GENERIC_HDLC
3974 hdlcdev_exit(info);
3975 #endif
3976 free_dma_bufs(info);
3977 free_tmp_rx_buf(info);
3978 if ( info->port_num == 0 ) {
3979 if (info->sca_base)
3980 write_reg(info, LPR, 1); /* set low power mode */
3981 release_resources(info);
3982 }
3983 tmp = info;
3984 info = info->next_device;
3985 kfree(tmp);
3986 }
3987
3988 pci_unregister_driver(&synclinkmp_pci_driver);
3989 }
3990
3991 /* Driver initialization entry point.
3992 */
3993
3994 static int __init synclinkmp_init(void)
3995 {
3996 int rc;
3997
3998 if (break_on_load) {
3999 synclinkmp_get_text_ptr();
4000 BREAKPOINT();
4001 }
4002
4003 printk("%s %s\n", driver_name, driver_version);
4004
4005 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4006 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4007 return rc;
4008 }
4009
4010 serial_driver = alloc_tty_driver(128);
4011 if (!serial_driver) {
4012 rc = -ENOMEM;
4013 goto error;
4014 }
4015
4016 /* Initialize the tty_driver structure */
4017
4018 serial_driver->owner = THIS_MODULE;
4019 serial_driver->driver_name = "synclinkmp";
4020 serial_driver->name = "ttySLM";
4021 serial_driver->major = ttymajor;
4022 serial_driver->minor_start = 64;
4023 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4024 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4025 serial_driver->init_termios = tty_std_termios;
4026 serial_driver->init_termios.c_cflag =
4027 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4028 serial_driver->init_termios.c_ispeed = 9600;
4029 serial_driver->init_termios.c_ospeed = 9600;
4030 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4031 tty_set_operations(serial_driver, &ops);
4032 if ((rc = tty_register_driver(serial_driver)) < 0) {
4033 printk("%s(%d):Couldn't register serial driver\n",
4034 __FILE__,__LINE__);
4035 put_tty_driver(serial_driver);
4036 serial_driver = NULL;
4037 goto error;
4038 }
4039
4040 printk("%s %s, tty major#%d\n",
4041 driver_name, driver_version,
4042 serial_driver->major);
4043
4044 return 0;
4045
4046 error:
4047 synclinkmp_cleanup();
4048 return rc;
4049 }
4050
4051 static void __exit synclinkmp_exit(void)
4052 {
4053 synclinkmp_cleanup();
4054 }
4055
4056 module_init(synclinkmp_init);
4057 module_exit(synclinkmp_exit);
4058
4059 /* Set the port for internal loopback mode.
4060 * The TxCLK and RxCLK signals are generated from the BRG and
4061 * the TxD is looped back to the RxD internally.
4062 */
4063 static void enable_loopback(SLMP_INFO *info, int enable)
4064 {
4065 if (enable) {
4066 /* MD2 (Mode Register 2)
4067 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4068 */
4069 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4070
4071 /* degate external TxC clock source */
4072 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4073 write_control_reg(info);
4074
4075 /* RXS/TXS (Rx/Tx clock source)
4076 * 07 Reserved, must be 0
4077 * 06..04 Clock Source, 100=BRG
4078 * 03..00 Clock Divisor, 0000=1
4079 */
4080 write_reg(info, RXS, 0x40);
4081 write_reg(info, TXS, 0x40);
4082
4083 } else {
4084 /* MD2 (Mode Register 2)
4085 * 01..00 CNCT<1..0> Channel connection, 0=normal
4086 */
4087 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4088
4089 /* RXS/TXS (Rx/Tx clock source)
4090 * 07 Reserved, must be 0
4091 * 06..04 Clock Source, 000=RxC/TxC Pin
4092 * 03..00 Clock Divisor, 0000=1
4093 */
4094 write_reg(info, RXS, 0x00);
4095 write_reg(info, TXS, 0x00);
4096 }
4097
4098 /* set LinkSpeed if available, otherwise default to 2Mbps */
4099 if (info->params.clock_speed)
4100 set_rate(info, info->params.clock_speed);
4101 else
4102 set_rate(info, 3686400);
4103 }
4104
4105 /* Set the baud rate register to the desired speed
4106 *
4107 * data_rate data rate of clock in bits per second
4108 * A data rate of 0 disables the AUX clock.
4109 */
4110 static void set_rate( SLMP_INFO *info, u32 data_rate )
4111 {
4112 u32 TMCValue;
4113 unsigned char BRValue;
4114 u32 Divisor=0;
4115
4116 /* fBRG = fCLK/(TMC * 2^BR)
4117 */
4118 if (data_rate != 0) {
4119 Divisor = 14745600/data_rate;
4120 if (!Divisor)
4121 Divisor = 1;
4122
4123 TMCValue = Divisor;
4124
4125 BRValue = 0;
4126 if (TMCValue != 1 && TMCValue != 2) {
4127 /* BRValue of 0 provides 50/50 duty cycle *only* when
4128 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4129 * 50/50 duty cycle.
4130 */
4131 BRValue = 1;
4132 TMCValue >>= 1;
4133 }
4134
4135 /* while TMCValue is too big for TMC register, divide
4136 * by 2 and increment BR exponent.
4137 */
4138 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4139 TMCValue >>= 1;
4140
4141 write_reg(info, TXS,
4142 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4143 write_reg(info, RXS,
4144 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4145 write_reg(info, TMC, (unsigned char)TMCValue);
4146 }
4147 else {
4148 write_reg(info, TXS,0);
4149 write_reg(info, RXS,0);
4150 write_reg(info, TMC, 0);
4151 }
4152 }
4153
4154 /* Disable receiver
4155 */
4156 static void rx_stop(SLMP_INFO *info)
4157 {
4158 if (debug_level >= DEBUG_LEVEL_ISR)
4159 printk("%s(%d):%s rx_stop()\n",
4160 __FILE__,__LINE__, info->device_name );
4161
4162 write_reg(info, CMD, RXRESET);
4163
4164 info->ie0_value &= ~RXRDYE;
4165 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4166
4167 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4168 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4169 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4170
4171 info->rx_enabled = false;
4172 info->rx_overflow = false;
4173 }
4174
4175 /* enable the receiver
4176 */
4177 static void rx_start(SLMP_INFO *info)
4178 {
4179 int i;
4180
4181 if (debug_level >= DEBUG_LEVEL_ISR)
4182 printk("%s(%d):%s rx_start()\n",
4183 __FILE__,__LINE__, info->device_name );
4184
4185 write_reg(info, CMD, RXRESET);
4186
4187 if ( info->params.mode == MGSL_MODE_HDLC ) {
4188 /* HDLC, disabe IRQ on rxdata */
4189 info->ie0_value &= ~RXRDYE;
4190 write_reg(info, IE0, info->ie0_value);
4191
4192 /* Reset all Rx DMA buffers and program rx dma */
4193 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4194 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4195
4196 for (i = 0; i < info->rx_buf_count; i++) {
4197 info->rx_buf_list[i].status = 0xff;
4198
4199 // throttle to 4 shared memory writes at a time to prevent
4200 // hogging local bus (keep latency time for DMA requests low).
4201 if (!(i % 4))
4202 read_status_reg(info);
4203 }
4204 info->current_rx_buf = 0;
4205
4206 /* set current/1st descriptor address */
4207 write_reg16(info, RXDMA + CDA,
4208 info->rx_buf_list_ex[0].phys_entry);
4209
4210 /* set new last rx descriptor address */
4211 write_reg16(info, RXDMA + EDA,
4212 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4213
4214 /* set buffer length (shared by all rx dma data buffers) */
4215 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4216
4217 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4218 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4219 } else {
4220 /* async, enable IRQ on rxdata */
4221 info->ie0_value |= RXRDYE;
4222 write_reg(info, IE0, info->ie0_value);
4223 }
4224
4225 write_reg(info, CMD, RXENABLE);
4226
4227 info->rx_overflow = false;
4228 info->rx_enabled = true;
4229 }
4230
4231 /* Enable the transmitter and send a transmit frame if
4232 * one is loaded in the DMA buffers.
4233 */
4234 static void tx_start(SLMP_INFO *info)
4235 {
4236 if (debug_level >= DEBUG_LEVEL_ISR)
4237 printk("%s(%d):%s tx_start() tx_count=%d\n",
4238 __FILE__,__LINE__, info->device_name,info->tx_count );
4239
4240 if (!info->tx_enabled ) {
4241 write_reg(info, CMD, TXRESET);
4242 write_reg(info, CMD, TXENABLE);
4243 info->tx_enabled = true;
4244 }
4245
4246 if ( info->tx_count ) {
4247
4248 /* If auto RTS enabled and RTS is inactive, then assert */
4249 /* RTS and set a flag indicating that the driver should */
4250 /* negate RTS when the transmission completes. */
4251
4252 info->drop_rts_on_tx_done = false;
4253
4254 if (info->params.mode != MGSL_MODE_ASYNC) {
4255
4256 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4257 get_signals( info );
4258 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4259 info->serial_signals |= SerialSignal_RTS;
4260 set_signals( info );
4261 info->drop_rts_on_tx_done = true;
4262 }
4263 }
4264
4265 write_reg16(info, TRC0,
4266 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4267
4268 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4269 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4270
4271 /* set TX CDA (current descriptor address) */
4272 write_reg16(info, TXDMA + CDA,
4273 info->tx_buf_list_ex[0].phys_entry);
4274
4275 /* set TX EDA (last descriptor address) */
4276 write_reg16(info, TXDMA + EDA,
4277 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4278
4279 /* enable underrun IRQ */
4280 info->ie1_value &= ~IDLE;
4281 info->ie1_value |= UDRN;
4282 write_reg(info, IE1, info->ie1_value);
4283 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4284
4285 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4286 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4287
4288 mod_timer(&info->tx_timer, jiffies +
4289 msecs_to_jiffies(5000));
4290 }
4291 else {
4292 tx_load_fifo(info);
4293 /* async, enable IRQ on txdata */
4294 info->ie0_value |= TXRDYE;
4295 write_reg(info, IE0, info->ie0_value);
4296 }
4297
4298 info->tx_active = true;
4299 }
4300 }
4301
4302 /* stop the transmitter and DMA
4303 */
4304 static void tx_stop( SLMP_INFO *info )
4305 {
4306 if (debug_level >= DEBUG_LEVEL_ISR)
4307 printk("%s(%d):%s tx_stop()\n",
4308 __FILE__,__LINE__, info->device_name );
4309
4310 del_timer(&info->tx_timer);
4311
4312 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4313 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4314
4315 write_reg(info, CMD, TXRESET);
4316
4317 info->ie1_value &= ~(UDRN + IDLE);
4318 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4319 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4320
4321 info->ie0_value &= ~TXRDYE;
4322 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4323
4324 info->tx_enabled = false;
4325 info->tx_active = false;
4326 }
4327
4328 /* Fill the transmit FIFO until the FIFO is full or
4329 * there is no more data to load.
4330 */
4331 static void tx_load_fifo(SLMP_INFO *info)
4332 {
4333 u8 TwoBytes[2];
4334
4335 /* do nothing is now tx data available and no XON/XOFF pending */
4336
4337 if ( !info->tx_count && !info->x_char )
4338 return;
4339
4340 /* load the Transmit FIFO until FIFOs full or all data sent */
4341
4342 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4343
4344 /* there is more space in the transmit FIFO and */
4345 /* there is more data in transmit buffer */
4346
4347 if ( (info->tx_count > 1) && !info->x_char ) {
4348 /* write 16-bits */
4349 TwoBytes[0] = info->tx_buf[info->tx_get++];
4350 if (info->tx_get >= info->max_frame_size)
4351 info->tx_get -= info->max_frame_size;
4352 TwoBytes[1] = info->tx_buf[info->tx_get++];
4353 if (info->tx_get >= info->max_frame_size)
4354 info->tx_get -= info->max_frame_size;
4355
4356 write_reg16(info, TRB, *((u16 *)TwoBytes));
4357
4358 info->tx_count -= 2;
4359 info->icount.tx += 2;
4360 } else {
4361 /* only 1 byte left to transmit or 1 FIFO slot left */
4362
4363 if (info->x_char) {
4364 /* transmit pending high priority char */
4365 write_reg(info, TRB, info->x_char);
4366 info->x_char = 0;
4367 } else {
4368 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4369 if (info->tx_get >= info->max_frame_size)
4370 info->tx_get -= info->max_frame_size;
4371 info->tx_count--;
4372 }
4373 info->icount.tx++;
4374 }
4375 }
4376 }
4377
4378 /* Reset a port to a known state
4379 */
4380 static void reset_port(SLMP_INFO *info)
4381 {
4382 if (info->sca_base) {
4383
4384 tx_stop(info);
4385 rx_stop(info);
4386
4387 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4388 set_signals(info);
4389
4390 /* disable all port interrupts */
4391 info->ie0_value = 0;
4392 info->ie1_value = 0;
4393 info->ie2_value = 0;
4394 write_reg(info, IE0, info->ie0_value);
4395 write_reg(info, IE1, info->ie1_value);
4396 write_reg(info, IE2, info->ie2_value);
4397
4398 write_reg(info, CMD, CHRESET);
4399 }
4400 }
4401
4402 /* Reset all the ports to a known state.
4403 */
4404 static void reset_adapter(SLMP_INFO *info)
4405 {
4406 int i;
4407
4408 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4409 if (info->port_array[i])
4410 reset_port(info->port_array[i]);
4411 }
4412 }
4413
4414 /* Program port for asynchronous communications.
4415 */
4416 static void async_mode(SLMP_INFO *info)
4417 {
4418
4419 unsigned char RegValue;
4420
4421 tx_stop(info);
4422 rx_stop(info);
4423
4424 /* MD0, Mode Register 0
4425 *
4426 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4427 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4428 * 03 Reserved, must be 0
4429 * 02 CRCCC, CRC Calculation, 0=disabled
4430 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4431 *
4432 * 0000 0000
4433 */
4434 RegValue = 0x00;
4435 if (info->params.stop_bits != 1)
4436 RegValue |= BIT1;
4437 write_reg(info, MD0, RegValue);
4438
4439 /* MD1, Mode Register 1
4440 *
4441 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4442 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4443 * 03..02 RXCHR<1..0>, rx char size
4444 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4445 *
4446 * 0100 0000
4447 */
4448 RegValue = 0x40;
4449 switch (info->params.data_bits) {
4450 case 7: RegValue |= BIT4 + BIT2; break;
4451 case 6: RegValue |= BIT5 + BIT3; break;
4452 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4453 }
4454 if (info->params.parity != ASYNC_PARITY_NONE) {
4455 RegValue |= BIT1;
4456 if (info->params.parity == ASYNC_PARITY_ODD)
4457 RegValue |= BIT0;
4458 }
4459 write_reg(info, MD1, RegValue);
4460
4461 /* MD2, Mode Register 2
4462 *
4463 * 07..02 Reserved, must be 0
4464 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4465 *
4466 * 0000 0000
4467 */
4468 RegValue = 0x00;
4469 if (info->params.loopback)
4470 RegValue |= (BIT1 + BIT0);
4471 write_reg(info, MD2, RegValue);
4472
4473 /* RXS, Receive clock source
4474 *
4475 * 07 Reserved, must be 0
4476 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4477 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4478 */
4479 RegValue=BIT6;
4480 write_reg(info, RXS, RegValue);
4481
4482 /* TXS, Transmit clock source
4483 *
4484 * 07 Reserved, must be 0
4485 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4486 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4487 */
4488 RegValue=BIT6;
4489 write_reg(info, TXS, RegValue);
4490
4491 /* Control Register
4492 *
4493 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4494 */
4495 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4496 write_control_reg(info);
4497
4498 tx_set_idle(info);
4499
4500 /* RRC Receive Ready Control 0
4501 *
4502 * 07..05 Reserved, must be 0
4503 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4504 */
4505 write_reg(info, RRC, 0x00);
4506
4507 /* TRC0 Transmit Ready Control 0
4508 *
4509 * 07..05 Reserved, must be 0
4510 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4511 */
4512 write_reg(info, TRC0, 0x10);
4513
4514 /* TRC1 Transmit Ready Control 1
4515 *
4516 * 07..05 Reserved, must be 0
4517 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4518 */
4519 write_reg(info, TRC1, 0x1e);
4520
4521 /* CTL, MSCI control register
4522 *
4523 * 07..06 Reserved, set to 0
4524 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4525 * 04 IDLC, idle control, 0=mark 1=idle register
4526 * 03 BRK, break, 0=off 1 =on (async)
4527 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4528 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4529 * 00 RTS, RTS output control, 0=active 1=inactive
4530 *
4531 * 0001 0001
4532 */
4533 RegValue = 0x10;
4534 if (!(info->serial_signals & SerialSignal_RTS))
4535 RegValue |= 0x01;
4536 write_reg(info, CTL, RegValue);
4537
4538 /* enable status interrupts */
4539 info->ie0_value |= TXINTE + RXINTE;
4540 write_reg(info, IE0, info->ie0_value);
4541
4542 /* enable break detect interrupt */
4543 info->ie1_value = BRKD;
4544 write_reg(info, IE1, info->ie1_value);
4545
4546 /* enable rx overrun interrupt */
4547 info->ie2_value = OVRN;
4548 write_reg(info, IE2, info->ie2_value);
4549
4550 set_rate( info, info->params.data_rate * 16 );
4551 }
4552
4553 /* Program the SCA for HDLC communications.
4554 */
4555 static void hdlc_mode(SLMP_INFO *info)
4556 {
4557 unsigned char RegValue;
4558 u32 DpllDivisor;
4559
4560 // Can't use DPLL because SCA outputs recovered clock on RxC when
4561 // DPLL mode selected. This causes output contention with RxC receiver.
4562 // Use of DPLL would require external hardware to disable RxC receiver
4563 // when DPLL mode selected.
4564 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4565
4566 /* disable DMA interrupts */
4567 write_reg(info, TXDMA + DIR, 0);
4568 write_reg(info, RXDMA + DIR, 0);
4569
4570 /* MD0, Mode Register 0
4571 *
4572 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4573 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4574 * 03 Reserved, must be 0
4575 * 02 CRCCC, CRC Calculation, 1=enabled
4576 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4577 * 00 CRC0, CRC initial value, 1 = all 1s
4578 *
4579 * 1000 0001
4580 */
4581 RegValue = 0x81;
4582 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4583 RegValue |= BIT4;
4584 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4585 RegValue |= BIT4;
4586 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4587 RegValue |= BIT2 + BIT1;
4588 write_reg(info, MD0, RegValue);
4589
4590 /* MD1, Mode Register 1
4591 *
4592 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4593 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4594 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4595 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4596 *
4597 * 0000 0000
4598 */
4599 RegValue = 0x00;
4600 write_reg(info, MD1, RegValue);
4601
4602 /* MD2, Mode Register 2
4603 *
4604 * 07 NRZFM, 0=NRZ, 1=FM
4605 * 06..05 CODE<1..0> Encoding, 00=NRZ
4606 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4607 * 02 Reserved, must be 0
4608 * 01..00 CNCT<1..0> Channel connection, 0=normal
4609 *
4610 * 0000 0000
4611 */
4612 RegValue = 0x00;
4613 switch(info->params.encoding) {
4614 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4615 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4616 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4617 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4618 #if 0
4619 case HDLC_ENCODING_NRZB: /* not supported */
4620 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4621 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4622 #endif
4623 }
4624 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4625 DpllDivisor = 16;
4626 RegValue |= BIT3;
4627 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4628 DpllDivisor = 8;
4629 } else {
4630 DpllDivisor = 32;
4631 RegValue |= BIT4;
4632 }
4633 write_reg(info, MD2, RegValue);
4634
4635
4636 /* RXS, Receive clock source
4637 *
4638 * 07 Reserved, must be 0
4639 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4640 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4641 */
4642 RegValue=0;
4643 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4644 RegValue |= BIT6;
4645 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4646 RegValue |= BIT6 + BIT5;
4647 write_reg(info, RXS, RegValue);
4648
4649 /* TXS, Transmit clock source
4650 *
4651 * 07 Reserved, must be 0
4652 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4653 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4654 */
4655 RegValue=0;
4656 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4657 RegValue |= BIT6;
4658 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4659 RegValue |= BIT6 + BIT5;
4660 write_reg(info, TXS, RegValue);
4661
4662 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4663 set_rate(info, info->params.clock_speed * DpllDivisor);
4664 else
4665 set_rate(info, info->params.clock_speed);
4666
4667 /* GPDATA (General Purpose I/O Data Register)
4668 *
4669 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4670 */
4671 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4672 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4673 else
4674 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4675 write_control_reg(info);
4676
4677 /* RRC Receive Ready Control 0
4678 *
4679 * 07..05 Reserved, must be 0
4680 * 04..00 RRC<4..0> Rx FIFO trigger active
4681 */
4682 write_reg(info, RRC, rx_active_fifo_level);
4683
4684 /* TRC0 Transmit Ready Control 0
4685 *
4686 * 07..05 Reserved, must be 0
4687 * 04..00 TRC<4..0> Tx FIFO trigger active
4688 */
4689 write_reg(info, TRC0, tx_active_fifo_level);
4690
4691 /* TRC1 Transmit Ready Control 1
4692 *
4693 * 07..05 Reserved, must be 0
4694 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4695 */
4696 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4697
4698 /* DMR, DMA Mode Register
4699 *
4700 * 07..05 Reserved, must be 0
4701 * 04 TMOD, Transfer Mode: 1=chained-block
4702 * 03 Reserved, must be 0
4703 * 02 NF, Number of Frames: 1=multi-frame
4704 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4705 * 00 Reserved, must be 0
4706 *
4707 * 0001 0100
4708 */
4709 write_reg(info, TXDMA + DMR, 0x14);
4710 write_reg(info, RXDMA + DMR, 0x14);
4711
4712 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4713 write_reg(info, RXDMA + CPB,
4714 (unsigned char)(info->buffer_list_phys >> 16));
4715
4716 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4717 write_reg(info, TXDMA + CPB,
4718 (unsigned char)(info->buffer_list_phys >> 16));
4719
4720 /* enable status interrupts. other code enables/disables
4721 * the individual sources for these two interrupt classes.
4722 */
4723 info->ie0_value |= TXINTE + RXINTE;
4724 write_reg(info, IE0, info->ie0_value);
4725
4726 /* CTL, MSCI control register
4727 *
4728 * 07..06 Reserved, set to 0
4729 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4730 * 04 IDLC, idle control, 0=mark 1=idle register
4731 * 03 BRK, break, 0=off 1 =on (async)
4732 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4733 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4734 * 00 RTS, RTS output control, 0=active 1=inactive
4735 *
4736 * 0001 0001
4737 */
4738 RegValue = 0x10;
4739 if (!(info->serial_signals & SerialSignal_RTS))
4740 RegValue |= 0x01;
4741 write_reg(info, CTL, RegValue);
4742
4743 /* preamble not supported ! */
4744
4745 tx_set_idle(info);
4746 tx_stop(info);
4747 rx_stop(info);
4748
4749 set_rate(info, info->params.clock_speed);
4750
4751 if (info->params.loopback)
4752 enable_loopback(info,1);
4753 }
4754
4755 /* Set the transmit HDLC idle mode
4756 */
4757 static void tx_set_idle(SLMP_INFO *info)
4758 {
4759 unsigned char RegValue = 0xff;
4760
4761 /* Map API idle mode to SCA register bits */
4762 switch(info->idle_mode) {
4763 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4764 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4765 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4766 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4767 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4768 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4769 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4770 }
4771
4772 write_reg(info, IDL, RegValue);
4773 }
4774
4775 /* Query the adapter for the state of the V24 status (input) signals.
4776 */
4777 static void get_signals(SLMP_INFO *info)
4778 {
4779 u16 status = read_reg(info, SR3);
4780 u16 gpstatus = read_status_reg(info);
4781 u16 testbit;
4782
4783 /* clear all serial signals except DTR and RTS */
4784 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4785
4786 /* set serial signal bits to reflect MISR */
4787
4788 if (!(status & BIT3))
4789 info->serial_signals |= SerialSignal_CTS;
4790
4791 if ( !(status & BIT2))
4792 info->serial_signals |= SerialSignal_DCD;
4793
4794 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4795 if (!(gpstatus & testbit))
4796 info->serial_signals |= SerialSignal_RI;
4797
4798 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4799 if (!(gpstatus & testbit))
4800 info->serial_signals |= SerialSignal_DSR;
4801 }
4802
4803 /* Set the state of DTR and RTS based on contents of
4804 * serial_signals member of device context.
4805 */
4806 static void set_signals(SLMP_INFO *info)
4807 {
4808 unsigned char RegValue;
4809 u16 EnableBit;
4810
4811 RegValue = read_reg(info, CTL);
4812 if (info->serial_signals & SerialSignal_RTS)
4813 RegValue &= ~BIT0;
4814 else
4815 RegValue |= BIT0;
4816 write_reg(info, CTL, RegValue);
4817
4818 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4819 EnableBit = BIT1 << (info->port_num*2);
4820 if (info->serial_signals & SerialSignal_DTR)
4821 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4822 else
4823 info->port_array[0]->ctrlreg_value |= EnableBit;
4824 write_control_reg(info);
4825 }
4826
4827 /*******************/
4828 /* DMA Buffer Code */
4829 /*******************/
4830
4831 /* Set the count for all receive buffers to SCABUFSIZE
4832 * and set the current buffer to the first buffer. This effectively
4833 * makes all buffers free and discards any data in buffers.
4834 */
4835 static void rx_reset_buffers(SLMP_INFO *info)
4836 {
4837 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4838 }
4839
4840 /* Free the buffers used by a received frame
4841 *
4842 * info pointer to device instance data
4843 * first index of 1st receive buffer of frame
4844 * last index of last receive buffer of frame
4845 */
4846 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4847 {
4848 bool done = false;
4849
4850 while(!done) {
4851 /* reset current buffer for reuse */
4852 info->rx_buf_list[first].status = 0xff;
4853
4854 if (first == last) {
4855 done = true;
4856 /* set new last rx descriptor address */
4857 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4858 }
4859
4860 first++;
4861 if (first == info->rx_buf_count)
4862 first = 0;
4863 }
4864
4865 /* set current buffer to next buffer after last buffer of frame */
4866 info->current_rx_buf = first;
4867 }
4868
4869 /* Return a received frame from the receive DMA buffers.
4870 * Only frames received without errors are returned.
4871 *
4872 * Return Value: true if frame returned, otherwise false
4873 */
4874 static bool rx_get_frame(SLMP_INFO *info)
4875 {
4876 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4877 unsigned short status;
4878 unsigned int framesize = 0;
4879 bool ReturnCode = false;
4880 unsigned long flags;
4881 struct tty_struct *tty = info->port.tty;
4882 unsigned char addr_field = 0xff;
4883 SCADESC *desc;
4884 SCADESC_EX *desc_ex;
4885
4886 CheckAgain:
4887 /* assume no frame returned, set zero length */
4888 framesize = 0;
4889 addr_field = 0xff;
4890
4891 /*
4892 * current_rx_buf points to the 1st buffer of the next available
4893 * receive frame. To find the last buffer of the frame look for
4894 * a non-zero status field in the buffer entries. (The status
4895 * field is set by the 16C32 after completing a receive frame.
4896 */
4897 StartIndex = EndIndex = info->current_rx_buf;
4898
4899 for ( ;; ) {
4900 desc = &info->rx_buf_list[EndIndex];
4901 desc_ex = &info->rx_buf_list_ex[EndIndex];
4902
4903 if (desc->status == 0xff)
4904 goto Cleanup; /* current desc still in use, no frames available */
4905
4906 if (framesize == 0 && info->params.addr_filter != 0xff)
4907 addr_field = desc_ex->virt_addr[0];
4908
4909 framesize += desc->length;
4910
4911 /* Status != 0 means last buffer of frame */
4912 if (desc->status)
4913 break;
4914
4915 EndIndex++;
4916 if (EndIndex == info->rx_buf_count)
4917 EndIndex = 0;
4918
4919 if (EndIndex == info->current_rx_buf) {
4920 /* all buffers have been 'used' but none mark */
4921 /* the end of a frame. Reset buffers and receiver. */
4922 if ( info->rx_enabled ){
4923 spin_lock_irqsave(&info->lock,flags);
4924 rx_start(info);
4925 spin_unlock_irqrestore(&info->lock,flags);
4926 }
4927 goto Cleanup;
4928 }
4929
4930 }
4931
4932 /* check status of receive frame */
4933
4934 /* frame status is byte stored after frame data
4935 *
4936 * 7 EOM (end of msg), 1 = last buffer of frame
4937 * 6 Short Frame, 1 = short frame
4938 * 5 Abort, 1 = frame aborted
4939 * 4 Residue, 1 = last byte is partial
4940 * 3 Overrun, 1 = overrun occurred during frame reception
4941 * 2 CRC, 1 = CRC error detected
4942 *
4943 */
4944 status = desc->status;
4945
4946 /* ignore CRC bit if not using CRC (bit is undefined) */
4947 /* Note:CRC is not save to data buffer */
4948 if (info->params.crc_type == HDLC_CRC_NONE)
4949 status &= ~BIT2;
4950
4951 if (framesize == 0 ||
4952 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4953 /* discard 0 byte frames, this seems to occur sometime
4954 * when remote is idling flags.
4955 */
4956 rx_free_frame_buffers(info, StartIndex, EndIndex);
4957 goto CheckAgain;
4958 }
4959
4960 if (framesize < 2)
4961 status |= BIT6;
4962
4963 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4964 /* received frame has errors,
4965 * update counts and mark frame size as 0
4966 */
4967 if (status & BIT6)
4968 info->icount.rxshort++;
4969 else if (status & BIT5)
4970 info->icount.rxabort++;
4971 else if (status & BIT3)
4972 info->icount.rxover++;
4973 else
4974 info->icount.rxcrc++;
4975
4976 framesize = 0;
4977 #if SYNCLINK_GENERIC_HDLC
4978 {
4979 struct net_device_stats *stats = hdlc_stats(info->netdev);
4980 stats->rx_errors++;
4981 stats->rx_frame_errors++;
4982 }
4983 #endif
4984 }
4985
4986 if ( debug_level >= DEBUG_LEVEL_BH )
4987 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4988 __FILE__,__LINE__,info->device_name,status,framesize);
4989
4990 if ( debug_level >= DEBUG_LEVEL_DATA )
4991 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4992 min_t(int, framesize,SCABUFSIZE),0);
4993
4994 if (framesize) {
4995 if (framesize > info->max_frame_size)
4996 info->icount.rxlong++;
4997 else {
4998 /* copy dma buffer(s) to contiguous intermediate buffer */
4999 int copy_count = framesize;
5000 int index = StartIndex;
5001 unsigned char *ptmp = info->tmp_rx_buf;
5002 info->tmp_rx_buf_count = framesize;
5003
5004 info->icount.rxok++;
5005
5006 while(copy_count) {
5007 int partial_count = min(copy_count,SCABUFSIZE);
5008 memcpy( ptmp,
5009 info->rx_buf_list_ex[index].virt_addr,
5010 partial_count );
5011 ptmp += partial_count;
5012 copy_count -= partial_count;
5013
5014 if ( ++index == info->rx_buf_count )
5015 index = 0;
5016 }
5017
5018 #if SYNCLINK_GENERIC_HDLC
5019 if (info->netcount)
5020 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5021 else
5022 #endif
5023 ldisc_receive_buf(tty,info->tmp_rx_buf,
5024 info->flag_buf, framesize);
5025 }
5026 }
5027 /* Free the buffers used by this frame. */
5028 rx_free_frame_buffers( info, StartIndex, EndIndex );
5029
5030 ReturnCode = true;
5031
5032 Cleanup:
5033 if ( info->rx_enabled && info->rx_overflow ) {
5034 /* Receiver is enabled, but needs to restarted due to
5035 * rx buffer overflow. If buffers are empty, restart receiver.
5036 */
5037 if (info->rx_buf_list[EndIndex].status == 0xff) {
5038 spin_lock_irqsave(&info->lock,flags);
5039 rx_start(info);
5040 spin_unlock_irqrestore(&info->lock,flags);
5041 }
5042 }
5043
5044 return ReturnCode;
5045 }
5046
5047 /* load the transmit DMA buffer with data
5048 */
5049 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5050 {
5051 unsigned short copy_count;
5052 unsigned int i = 0;
5053 SCADESC *desc;
5054 SCADESC_EX *desc_ex;
5055
5056 if ( debug_level >= DEBUG_LEVEL_DATA )
5057 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5058
5059 /* Copy source buffer to one or more DMA buffers, starting with
5060 * the first transmit dma buffer.
5061 */
5062 for(i=0;;)
5063 {
5064 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5065
5066 desc = &info->tx_buf_list[i];
5067 desc_ex = &info->tx_buf_list_ex[i];
5068
5069 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5070
5071 desc->length = copy_count;
5072 desc->status = 0;
5073
5074 buf += copy_count;
5075 count -= copy_count;
5076
5077 if (!count)
5078 break;
5079
5080 i++;
5081 if (i >= info->tx_buf_count)
5082 i = 0;
5083 }
5084
5085 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5086 info->last_tx_buf = ++i;
5087 }
5088
5089 static bool register_test(SLMP_INFO *info)
5090 {
5091 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5092 static unsigned int count = ARRAY_SIZE(testval);
5093 unsigned int i;
5094 bool rc = true;
5095 unsigned long flags;
5096
5097 spin_lock_irqsave(&info->lock,flags);
5098 reset_port(info);
5099
5100 /* assume failure */
5101 info->init_error = DiagStatus_AddressFailure;
5102
5103 /* Write bit patterns to various registers but do it out of */
5104 /* sync, then read back and verify values. */
5105
5106 for (i = 0 ; i < count ; i++) {
5107 write_reg(info, TMC, testval[i]);
5108 write_reg(info, IDL, testval[(i+1)%count]);
5109 write_reg(info, SA0, testval[(i+2)%count]);
5110 write_reg(info, SA1, testval[(i+3)%count]);
5111
5112 if ( (read_reg(info, TMC) != testval[i]) ||
5113 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5114 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5115 (read_reg(info, SA1) != testval[(i+3)%count]) )
5116 {
5117 rc = false;
5118 break;
5119 }
5120 }
5121
5122 reset_port(info);
5123 spin_unlock_irqrestore(&info->lock,flags);
5124
5125 return rc;
5126 }
5127
5128 static bool irq_test(SLMP_INFO *info)
5129 {
5130 unsigned long timeout;
5131 unsigned long flags;
5132
5133 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5134
5135 spin_lock_irqsave(&info->lock,flags);
5136 reset_port(info);
5137
5138 /* assume failure */
5139 info->init_error = DiagStatus_IrqFailure;
5140 info->irq_occurred = false;
5141
5142 /* setup timer0 on SCA0 to interrupt */
5143
5144 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5145 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5146
5147 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5148 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5149
5150
5151 /* TMCS, Timer Control/Status Register
5152 *
5153 * 07 CMF, Compare match flag (read only) 1=match
5154 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5155 * 05 Reserved, must be 0
5156 * 04 TME, Timer Enable
5157 * 03..00 Reserved, must be 0
5158 *
5159 * 0101 0000
5160 */
5161 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5162
5163 spin_unlock_irqrestore(&info->lock,flags);
5164
5165 timeout=100;
5166 while( timeout-- && !info->irq_occurred ) {
5167 msleep_interruptible(10);
5168 }
5169
5170 spin_lock_irqsave(&info->lock,flags);
5171 reset_port(info);
5172 spin_unlock_irqrestore(&info->lock,flags);
5173
5174 return info->irq_occurred;
5175 }
5176
5177 /* initialize individual SCA device (2 ports)
5178 */
5179 static bool sca_init(SLMP_INFO *info)
5180 {
5181 /* set wait controller to single mem partition (low), no wait states */
5182 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5183 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5184 write_reg(info, WCRL, 0); /* wait controller low range */
5185 write_reg(info, WCRM, 0); /* wait controller mid range */
5186 write_reg(info, WCRH, 0); /* wait controller high range */
5187
5188 /* DPCR, DMA Priority Control
5189 *
5190 * 07..05 Not used, must be 0
5191 * 04 BRC, bus release condition: 0=all transfers complete
5192 * 03 CCC, channel change condition: 0=every cycle
5193 * 02..00 PR<2..0>, priority 100=round robin
5194 *
5195 * 00000100 = 0x04
5196 */
5197 write_reg(info, DPCR, dma_priority);
5198
5199 /* DMA Master Enable, BIT7: 1=enable all channels */
5200 write_reg(info, DMER, 0x80);
5201
5202 /* enable all interrupt classes */
5203 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5204 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5205 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5206
5207 /* ITCR, interrupt control register
5208 * 07 IPC, interrupt priority, 0=MSCI->DMA
5209 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5210 * 04 VOS, Vector Output, 0=unmodified vector
5211 * 03..00 Reserved, must be 0
5212 */
5213 write_reg(info, ITCR, 0);
5214
5215 return true;
5216 }
5217
5218 /* initialize adapter hardware
5219 */
5220 static bool init_adapter(SLMP_INFO *info)
5221 {
5222 int i;
5223
5224 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5225 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5226 u32 readval;
5227
5228 info->misc_ctrl_value |= BIT30;
5229 *MiscCtrl = info->misc_ctrl_value;
5230
5231 /*
5232 * Force at least 170ns delay before clearing
5233 * reset bit. Each read from LCR takes at least
5234 * 30ns so 10 times for 300ns to be safe.
5235 */
5236 for(i=0;i<10;i++)
5237 readval = *MiscCtrl;
5238
5239 info->misc_ctrl_value &= ~BIT30;
5240 *MiscCtrl = info->misc_ctrl_value;
5241
5242 /* init control reg (all DTRs off, all clksel=input) */
5243 info->ctrlreg_value = 0xaa;
5244 write_control_reg(info);
5245
5246 {
5247 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5248 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5249
5250 switch(read_ahead_count)
5251 {
5252 case 16:
5253 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5254 break;
5255 case 8:
5256 lcr1_brdr_value |= BIT5 + BIT4;
5257 break;
5258 case 4:
5259 lcr1_brdr_value |= BIT5 + BIT3;
5260 break;
5261 case 0:
5262 lcr1_brdr_value |= BIT5;
5263 break;
5264 }
5265
5266 *LCR1BRDR = lcr1_brdr_value;
5267 *MiscCtrl = misc_ctrl_value;
5268 }
5269
5270 sca_init(info->port_array[0]);
5271 sca_init(info->port_array[2]);
5272
5273 return true;
5274 }
5275
5276 /* Loopback an HDLC frame to test the hardware
5277 * interrupt and DMA functions.
5278 */
5279 static bool loopback_test(SLMP_INFO *info)
5280 {
5281 #define TESTFRAMESIZE 20
5282
5283 unsigned long timeout;
5284 u16 count = TESTFRAMESIZE;
5285 unsigned char buf[TESTFRAMESIZE];
5286 bool rc = false;
5287 unsigned long flags;
5288
5289 struct tty_struct *oldtty = info->port.tty;
5290 u32 speed = info->params.clock_speed;
5291
5292 info->params.clock_speed = 3686400;
5293 info->port.tty = NULL;
5294
5295 /* assume failure */
5296 info->init_error = DiagStatus_DmaFailure;
5297
5298 /* build and send transmit frame */
5299 for (count = 0; count < TESTFRAMESIZE;++count)
5300 buf[count] = (unsigned char)count;
5301
5302 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5303
5304 /* program hardware for HDLC and enabled receiver */
5305 spin_lock_irqsave(&info->lock,flags);
5306 hdlc_mode(info);
5307 enable_loopback(info,1);
5308 rx_start(info);
5309 info->tx_count = count;
5310 tx_load_dma_buffer(info,buf,count);
5311 tx_start(info);
5312 spin_unlock_irqrestore(&info->lock,flags);
5313
5314 /* wait for receive complete */
5315 /* Set a timeout for waiting for interrupt. */
5316 for ( timeout = 100; timeout; --timeout ) {
5317 msleep_interruptible(10);
5318
5319 if (rx_get_frame(info)) {
5320 rc = true;
5321 break;
5322 }
5323 }
5324
5325 /* verify received frame length and contents */
5326 if (rc &&
5327 ( info->tmp_rx_buf_count != count ||
5328 memcmp(buf, info->tmp_rx_buf,count))) {
5329 rc = false;
5330 }
5331
5332 spin_lock_irqsave(&info->lock,flags);
5333 reset_adapter(info);
5334 spin_unlock_irqrestore(&info->lock,flags);
5335
5336 info->params.clock_speed = speed;
5337 info->port.tty = oldtty;
5338
5339 return rc;
5340 }
5341
5342 /* Perform diagnostics on hardware
5343 */
5344 static int adapter_test( SLMP_INFO *info )
5345 {
5346 unsigned long flags;
5347 if ( debug_level >= DEBUG_LEVEL_INFO )
5348 printk( "%s(%d):Testing device %s\n",
5349 __FILE__,__LINE__,info->device_name );
5350
5351 spin_lock_irqsave(&info->lock,flags);
5352 init_adapter(info);
5353 spin_unlock_irqrestore(&info->lock,flags);
5354
5355 info->port_array[0]->port_count = 0;
5356
5357 if ( register_test(info->port_array[0]) &&
5358 register_test(info->port_array[1])) {
5359
5360 info->port_array[0]->port_count = 2;
5361
5362 if ( register_test(info->port_array[2]) &&
5363 register_test(info->port_array[3]) )
5364 info->port_array[0]->port_count += 2;
5365 }
5366 else {
5367 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5368 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5369 return -ENODEV;
5370 }
5371
5372 if ( !irq_test(info->port_array[0]) ||
5373 !irq_test(info->port_array[1]) ||
5374 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5375 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5376 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5377 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5378 return -ENODEV;
5379 }
5380
5381 if (!loopback_test(info->port_array[0]) ||
5382 !loopback_test(info->port_array[1]) ||
5383 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5384 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5385 printk( "%s(%d):DMA test failure for device %s\n",
5386 __FILE__,__LINE__,info->device_name);
5387 return -ENODEV;
5388 }
5389
5390 if ( debug_level >= DEBUG_LEVEL_INFO )
5391 printk( "%s(%d):device %s passed diagnostics\n",
5392 __FILE__,__LINE__,info->device_name );
5393
5394 info->port_array[0]->init_error = 0;
5395 info->port_array[1]->init_error = 0;
5396 if ( info->port_count > 2 ) {
5397 info->port_array[2]->init_error = 0;
5398 info->port_array[3]->init_error = 0;
5399 }
5400
5401 return 0;
5402 }
5403
5404 /* Test the shared memory on a PCI adapter.
5405 */
5406 static bool memory_test(SLMP_INFO *info)
5407 {
5408 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5409 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5410 unsigned long count = ARRAY_SIZE(testval);
5411 unsigned long i;
5412 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5413 unsigned long * addr = (unsigned long *)info->memory_base;
5414
5415 /* Test data lines with test pattern at one location. */
5416
5417 for ( i = 0 ; i < count ; i++ ) {
5418 *addr = testval[i];
5419 if ( *addr != testval[i] )
5420 return false;
5421 }
5422
5423 /* Test address lines with incrementing pattern over */
5424 /* entire address range. */
5425
5426 for ( i = 0 ; i < limit ; i++ ) {
5427 *addr = i * 4;
5428 addr++;
5429 }
5430
5431 addr = (unsigned long *)info->memory_base;
5432
5433 for ( i = 0 ; i < limit ; i++ ) {
5434 if ( *addr != i * 4 )
5435 return false;
5436 addr++;
5437 }
5438
5439 memset( info->memory_base, 0, SCA_MEM_SIZE );
5440 return true;
5441 }
5442
5443 /* Load data into PCI adapter shared memory.
5444 *
5445 * The PCI9050 releases control of the local bus
5446 * after completing the current read or write operation.
5447 *
5448 * While the PCI9050 write FIFO not empty, the
5449 * PCI9050 treats all of the writes as a single transaction
5450 * and does not release the bus. This causes DMA latency problems
5451 * at high speeds when copying large data blocks to the shared memory.
5452 *
5453 * This function breaks a write into multiple transations by
5454 * interleaving a read which flushes the write FIFO and 'completes'
5455 * the write transation. This allows any pending DMA request to gain control
5456 * of the local bus in a timely fasion.
5457 */
5458 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5459 {
5460 /* A load interval of 16 allows for 4 32-bit writes at */
5461 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5462
5463 unsigned short interval = count / sca_pci_load_interval;
5464 unsigned short i;
5465
5466 for ( i = 0 ; i < interval ; i++ )
5467 {
5468 memcpy(dest, src, sca_pci_load_interval);
5469 read_status_reg(info);
5470 dest += sca_pci_load_interval;
5471 src += sca_pci_load_interval;
5472 }
5473
5474 memcpy(dest, src, count % sca_pci_load_interval);
5475 }
5476
5477 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5478 {
5479 int i;
5480 int linecount;
5481 if (xmit)
5482 printk("%s tx data:\n",info->device_name);
5483 else
5484 printk("%s rx data:\n",info->device_name);
5485
5486 while(count) {
5487 if (count > 16)
5488 linecount = 16;
5489 else
5490 linecount = count;
5491
5492 for(i=0;i<linecount;i++)
5493 printk("%02X ",(unsigned char)data[i]);
5494 for(;i<17;i++)
5495 printk(" ");
5496 for(i=0;i<linecount;i++) {
5497 if (data[i]>=040 && data[i]<=0176)
5498 printk("%c",data[i]);
5499 else
5500 printk(".");
5501 }
5502 printk("\n");
5503
5504 data += linecount;
5505 count -= linecount;
5506 }
5507 } /* end of trace_block() */
5508
5509 /* called when HDLC frame times out
5510 * update stats and do tx completion processing
5511 */
5512 static void tx_timeout(unsigned long context)
5513 {
5514 SLMP_INFO *info = (SLMP_INFO*)context;
5515 unsigned long flags;
5516
5517 if ( debug_level >= DEBUG_LEVEL_INFO )
5518 printk( "%s(%d):%s tx_timeout()\n",
5519 __FILE__,__LINE__,info->device_name);
5520 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5521 info->icount.txtimeout++;
5522 }
5523 spin_lock_irqsave(&info->lock,flags);
5524 info->tx_active = false;
5525 info->tx_count = info->tx_put = info->tx_get = 0;
5526
5527 spin_unlock_irqrestore(&info->lock,flags);
5528
5529 #if SYNCLINK_GENERIC_HDLC
5530 if (info->netcount)
5531 hdlcdev_tx_done(info);
5532 else
5533 #endif
5534 bh_transmit(info);
5535 }
5536
5537 /* called to periodically check the DSR/RI modem signal input status
5538 */
5539 static void status_timeout(unsigned long context)
5540 {
5541 u16 status = 0;
5542 SLMP_INFO *info = (SLMP_INFO*)context;
5543 unsigned long flags;
5544 unsigned char delta;
5545
5546
5547 spin_lock_irqsave(&info->lock,flags);
5548 get_signals(info);
5549 spin_unlock_irqrestore(&info->lock,flags);
5550
5551 /* check for DSR/RI state change */
5552
5553 delta = info->old_signals ^ info->serial_signals;
5554 info->old_signals = info->serial_signals;
5555
5556 if (delta & SerialSignal_DSR)
5557 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5558
5559 if (delta & SerialSignal_RI)
5560 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5561
5562 if (delta & SerialSignal_DCD)
5563 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5564
5565 if (delta & SerialSignal_CTS)
5566 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5567
5568 if (status)
5569 isr_io_pin(info,status);
5570
5571 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5572 }
5573
5574
5575 /* Register Access Routines -
5576 * All registers are memory mapped
5577 */
5578 #define CALC_REGADDR() \
5579 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5580 if (info->port_num > 1) \
5581 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5582 if ( info->port_num & 1) { \
5583 if (Addr > 0x7f) \
5584 RegAddr += 0x40; /* DMA access */ \
5585 else if (Addr > 0x1f && Addr < 0x60) \
5586 RegAddr += 0x20; /* MSCI access */ \
5587 }
5588
5589
5590 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5591 {
5592 CALC_REGADDR();
5593 return *RegAddr;
5594 }
5595 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5596 {
5597 CALC_REGADDR();
5598 *RegAddr = Value;
5599 }
5600
5601 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5602 {
5603 CALC_REGADDR();
5604 return *((u16 *)RegAddr);
5605 }
5606
5607 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5608 {
5609 CALC_REGADDR();
5610 *((u16 *)RegAddr) = Value;
5611 }
5612
5613 static unsigned char read_status_reg(SLMP_INFO * info)
5614 {
5615 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5616 return *RegAddr;
5617 }
5618
5619 static void write_control_reg(SLMP_INFO * info)
5620 {
5621 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5622 *RegAddr = info->port_array[0]->ctrlreg_value;
5623 }
5624
5625
5626 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5627 const struct pci_device_id *ent)
5628 {
5629 if (pci_enable_device(dev)) {
5630 printk("error enabling pci device %p\n", dev);
5631 return -EIO;
5632 }
5633 device_init( ++synclinkmp_adapter_count, dev );
5634 return 0;
5635 }
5636
5637 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5638 {
5639 }
Linux kernel - Deliverables
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