2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/config.h>
38 #include <linux/module.h>
39 #include <linux/errno.h>
40 #include <linux/signal.h>
41 #include <linux/sched.h>
42 #include <linux/timer.h>
43 #include <linux/interrupt.h>
44 #include <linux/pci.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial.h>
48 #include <linux/major.h>
49 #include <linux/string.h>
50 #include <linux/fcntl.h>
51 #include <linux/ptrace.h>
52 #include <linux/ioport.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
61 #include <asm/system.h>
65 #include <linux/bitops.h>
66 #include <asm/types.h>
67 #include <linux/termios.h>
68 #include <linux/workqueue.h>
69 #include <linux/hdlc.h>
71 #ifdef CONFIG_HDLC_MODULE
75 #define GET_USER(error,value,addr) error = get_user(value,addr)
76 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
77 #define PUT_USER(error,value,addr) error = put_user(value,addr)
78 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
80 #include <asm/uaccess.h>
82 #include "linux/synclink.h"
84 static MGSL_PARAMS default_params
= {
85 MGSL_MODE_HDLC
, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE
/* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next
; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr
; /* lower 16 bits of buffer addr */
115 u8 buf_base
; /* upper 8 bits of buffer addr */
117 u16 length
; /* length of buffer */
118 u8 status
; /* status of buffer */
120 } SCADESC
, *PSCADESC
;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr
; /* virtual address of data buffer */
126 u16 phys_entry
; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX
, *PSCADESC_EX
;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
139 struct _input_signal_events
{
151 * Device instance data structure
153 typedef struct _synclinkmp_info
{
154 void *if_ptr
; /* General purpose pointer (used by SPPP) */
157 int count
; /* count of opens */
159 unsigned short close_delay
;
160 unsigned short closing_wait
; /* time to wait before closing */
162 struct mgsl_icount icount
;
164 struct tty_struct
*tty
;
166 int x_char
; /* xon/xoff character */
167 int blocked_open
; /* # of blocked opens */
168 u16 read_status_mask1
; /* break detection (SR1 indications) */
169 u16 read_status_mask2
; /* parity/framing/overun (SR2 indications) */
170 unsigned char ignore_status_mask1
; /* break detection (SR1 indications) */
171 unsigned char ignore_status_mask2
; /* parity/framing/overun (SR2 indications) */
172 unsigned char *tx_buf
;
177 wait_queue_head_t open_wait
;
178 wait_queue_head_t close_wait
;
180 wait_queue_head_t status_event_wait_q
;
181 wait_queue_head_t event_wait_q
;
182 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
183 struct _synclinkmp_info
*next_device
; /* device list link */
184 struct timer_list status_timer
; /* input signal status check timer */
186 spinlock_t lock
; /* spinlock for synchronizing with ISR */
187 struct work_struct task
; /* task structure for scheduling bh */
189 u32 max_frame_size
; /* as set by device config */
193 int bh_running
; /* Protection from multiple */
197 int dcd_chkcount
; /* check counts to prevent */
198 int cts_chkcount
; /* too many IRQs if a signal */
199 int dsr_chkcount
; /* is floating */
202 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
203 unsigned long buffer_list_phys
;
205 unsigned int rx_buf_count
; /* count of total allocated Rx buffers */
206 SCADESC
*rx_buf_list
; /* list of receive buffer entries */
207 SCADESC_EX rx_buf_list_ex
[SCAMAXDESC
]; /* list of receive buffer entries */
208 unsigned int current_rx_buf
;
210 unsigned int tx_buf_count
; /* count of total allocated Tx buffers */
211 SCADESC
*tx_buf_list
; /* list of transmit buffer entries */
212 SCADESC_EX tx_buf_list_ex
[SCAMAXDESC
]; /* list of transmit buffer entries */
213 unsigned int last_tx_buf
;
215 unsigned char *tmp_rx_buf
;
216 unsigned int tmp_rx_buf_count
;
225 unsigned char ie0_value
;
226 unsigned char ie1_value
;
227 unsigned char ie2_value
;
228 unsigned char ctrlreg_value
;
229 unsigned char old_signals
;
231 char device_name
[25]; /* device instance name */
237 struct _synclinkmp_info
*port_array
[SCA_MAX_PORTS
];
239 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
241 unsigned int irq_level
; /* interrupt level */
242 unsigned long irq_flags
;
243 int irq_requested
; /* nonzero if IRQ requested */
245 MGSL_PARAMS params
; /* communications parameters */
247 unsigned char serial_signals
; /* current serial signal states */
249 int irq_occurred
; /* for diagnostics use */
250 unsigned int init_error
; /* Initialization startup error */
253 unsigned char* memory_base
; /* shared memory address (PCI only) */
254 u32 phys_memory_base
;
255 int shared_mem_requested
;
257 unsigned char* sca_base
; /* HD64570 SCA Memory address */
260 int sca_base_requested
;
262 unsigned char* lcr_base
; /* local config registers (PCI only) */
265 int lcr_mem_requested
;
267 unsigned char* statctrl_base
; /* status/control register memory */
268 u32 phys_statctrl_base
;
270 int sca_statctrl_requested
;
273 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
274 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
275 BOOLEAN drop_rts_on_tx_done
;
277 struct _input_signal_events input_signal_events
;
279 /* SPPP/Cisco HDLC device parts */
285 struct net_device
*netdev
;
290 #define MGSL_MAGIC 0x5401
293 * define serial signal status change macros
295 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
296 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
297 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
298 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
300 /* Common Register macros */
319 /* MSCI Register macros */
349 /* Timer Register Macros */
359 /* DMA Controller Register macros */
390 /* combine with timer or DMA register address */
398 /* SCA Command Codes */
401 #define TXENABLE 0x02
402 #define TXDISABLE 0x03
403 #define TXCRCINIT 0x04
404 #define TXCRCEXCL 0x05
408 #define TXBUFCLR 0x09
410 #define RXENABLE 0x12
411 #define RXDISABLE 0x13
412 #define RXCRCINIT 0x14
413 #define RXREJECT 0x15
414 #define SEARCHMP 0x16
415 #define RXCRCEXCL 0x17
416 #define RXCRCCALC 0x18
420 /* DMA command codes */
422 #define FEICLEAR 0x02
456 * Global linked list of SyncLink devices
458 static SLMP_INFO
*synclinkmp_device_list
= NULL
;
459 static int synclinkmp_adapter_count
= -1;
460 static int synclinkmp_device_count
= 0;
463 * Set this param to non-zero to load eax with the
464 * .text section address and breakpoint on module load.
465 * This is useful for use with gdb and add-symbol-file command.
467 static int break_on_load
=0;
470 * Driver major number, defaults to zero to get auto
471 * assigned major number. May be forced as module parameter.
473 static int ttymajor
=0;
476 * Array of user specified options for ISA adapters.
478 static int debug_level
= 0;
479 static int maxframe
[MAX_DEVICES
] = {0,};
480 static int dosyncppp
[MAX_DEVICES
] = {0,};
482 module_param(break_on_load
, bool, 0);
483 module_param(ttymajor
, int, 0);
484 module_param(debug_level
, int, 0);
485 module_param_array(maxframe
, int, NULL
, 0);
486 module_param_array(dosyncppp
, int, NULL
, 0);
488 static char *driver_name
= "SyncLink MultiPort driver";
489 static char *driver_version
= "$Revision: 4.38 $";
491 static int synclinkmp_init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
492 static void synclinkmp_remove_one(struct pci_dev
*dev
);
494 static struct pci_device_id synclinkmp_pci_tbl
[] = {
495 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_SCA
, PCI_ANY_ID
, PCI_ANY_ID
, },
496 { 0, }, /* terminate list */
498 MODULE_DEVICE_TABLE(pci
, synclinkmp_pci_tbl
);
500 MODULE_LICENSE("GPL");
502 static struct pci_driver synclinkmp_pci_driver
= {
503 .owner
= THIS_MODULE
,
504 .name
= "synclinkmp",
505 .id_table
= synclinkmp_pci_tbl
,
506 .probe
= synclinkmp_init_one
,
507 .remove
= __devexit_p(synclinkmp_remove_one
),
511 static struct tty_driver
*serial_driver
;
513 /* number of characters left in xmit buffer before we ask for more */
514 #define WAKEUP_CHARS 256
519 static int open(struct tty_struct
*tty
, struct file
* filp
);
520 static void close(struct tty_struct
*tty
, struct file
* filp
);
521 static void hangup(struct tty_struct
*tty
);
522 static void set_termios(struct tty_struct
*tty
, struct termios
*old_termios
);
524 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
525 static void put_char(struct tty_struct
*tty
, unsigned char ch
);
526 static void send_xchar(struct tty_struct
*tty
, char ch
);
527 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
528 static int write_room(struct tty_struct
*tty
);
529 static void flush_chars(struct tty_struct
*tty
);
530 static void flush_buffer(struct tty_struct
*tty
);
531 static void tx_hold(struct tty_struct
*tty
);
532 static void tx_release(struct tty_struct
*tty
);
534 static int ioctl(struct tty_struct
*tty
, struct file
*file
, unsigned int cmd
, unsigned long arg
);
535 static int read_proc(char *page
, char **start
, off_t off
, int count
,int *eof
, void *data
);
536 static int chars_in_buffer(struct tty_struct
*tty
);
537 static void throttle(struct tty_struct
* tty
);
538 static void unthrottle(struct tty_struct
* tty
);
539 static void set_break(struct tty_struct
*tty
, int break_state
);
542 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
543 static void hdlcdev_tx_done(SLMP_INFO
*info
);
544 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
);
545 static int hdlcdev_init(SLMP_INFO
*info
);
546 static void hdlcdev_exit(SLMP_INFO
*info
);
551 static int get_stats(SLMP_INFO
*info
, struct mgsl_icount __user
*user_icount
);
552 static int get_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
553 static int set_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
554 static int get_txidle(SLMP_INFO
*info
, int __user
*idle_mode
);
555 static int set_txidle(SLMP_INFO
*info
, int idle_mode
);
556 static int tx_enable(SLMP_INFO
*info
, int enable
);
557 static int tx_abort(SLMP_INFO
*info
);
558 static int rx_enable(SLMP_INFO
*info
, int enable
);
559 static int modem_input_wait(SLMP_INFO
*info
,int arg
);
560 static int wait_mgsl_event(SLMP_INFO
*info
, int __user
*mask_ptr
);
561 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
562 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
563 unsigned int set
, unsigned int clear
);
564 static void set_break(struct tty_struct
*tty
, int break_state
);
566 static void add_device(SLMP_INFO
*info
);
567 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
568 static int claim_resources(SLMP_INFO
*info
);
569 static void release_resources(SLMP_INFO
*info
);
571 static int startup(SLMP_INFO
*info
);
572 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,SLMP_INFO
*info
);
573 static void shutdown(SLMP_INFO
*info
);
574 static void program_hw(SLMP_INFO
*info
);
575 static void change_params(SLMP_INFO
*info
);
577 static int init_adapter(SLMP_INFO
*info
);
578 static int register_test(SLMP_INFO
*info
);
579 static int irq_test(SLMP_INFO
*info
);
580 static int loopback_test(SLMP_INFO
*info
);
581 static int adapter_test(SLMP_INFO
*info
);
582 static int memory_test(SLMP_INFO
*info
);
584 static void reset_adapter(SLMP_INFO
*info
);
585 static void reset_port(SLMP_INFO
*info
);
586 static void async_mode(SLMP_INFO
*info
);
587 static void hdlc_mode(SLMP_INFO
*info
);
589 static void rx_stop(SLMP_INFO
*info
);
590 static void rx_start(SLMP_INFO
*info
);
591 static void rx_reset_buffers(SLMP_INFO
*info
);
592 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
);
593 static int rx_get_frame(SLMP_INFO
*info
);
595 static void tx_start(SLMP_INFO
*info
);
596 static void tx_stop(SLMP_INFO
*info
);
597 static void tx_load_fifo(SLMP_INFO
*info
);
598 static void tx_set_idle(SLMP_INFO
*info
);
599 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
);
601 static void get_signals(SLMP_INFO
*info
);
602 static void set_signals(SLMP_INFO
*info
);
603 static void enable_loopback(SLMP_INFO
*info
, int enable
);
604 static void set_rate(SLMP_INFO
*info
, u32 data_rate
);
606 static int bh_action(SLMP_INFO
*info
);
607 static void bh_handler(void* Context
);
608 static void bh_receive(SLMP_INFO
*info
);
609 static void bh_transmit(SLMP_INFO
*info
);
610 static void bh_status(SLMP_INFO
*info
);
611 static void isr_timer(SLMP_INFO
*info
);
612 static void isr_rxint(SLMP_INFO
*info
);
613 static void isr_rxrdy(SLMP_INFO
*info
);
614 static void isr_txint(SLMP_INFO
*info
);
615 static void isr_txrdy(SLMP_INFO
*info
);
616 static void isr_rxdmaok(SLMP_INFO
*info
);
617 static void isr_rxdmaerror(SLMP_INFO
*info
);
618 static void isr_txdmaok(SLMP_INFO
*info
);
619 static void isr_txdmaerror(SLMP_INFO
*info
);
620 static void isr_io_pin(SLMP_INFO
*info
, u16 status
);
622 static int alloc_dma_bufs(SLMP_INFO
*info
);
623 static void free_dma_bufs(SLMP_INFO
*info
);
624 static int alloc_buf_list(SLMP_INFO
*info
);
625 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*list
, SCADESC_EX
*list_ex
,int count
);
626 static int alloc_tmp_rx_buf(SLMP_INFO
*info
);
627 static void free_tmp_rx_buf(SLMP_INFO
*info
);
629 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
);
630 static void trace_block(SLMP_INFO
*info
, const char* data
, int count
, int xmit
);
631 static void tx_timeout(unsigned long context
);
632 static void status_timeout(unsigned long context
);
634 static unsigned char read_reg(SLMP_INFO
*info
, unsigned char addr
);
635 static void write_reg(SLMP_INFO
*info
, unsigned char addr
, unsigned char val
);
636 static u16
read_reg16(SLMP_INFO
*info
, unsigned char addr
);
637 static void write_reg16(SLMP_INFO
*info
, unsigned char addr
, u16 val
);
638 static unsigned char read_status_reg(SLMP_INFO
* info
);
639 static void write_control_reg(SLMP_INFO
* info
);
642 static unsigned char rx_active_fifo_level
= 16; // rx request FIFO activation level in bytes
643 static unsigned char tx_active_fifo_level
= 16; // tx request FIFO activation level in bytes
644 static unsigned char tx_negate_fifo_level
= 32; // tx request FIFO negation level in bytes
646 static u32 misc_ctrl_value
= 0x007e4040;
647 static u32 lcr1_brdr_value
= 0x00800028;
649 static u32 read_ahead_count
= 8;
651 /* DPCR, DMA Priority Control
653 * 07..05 Not used, must be 0
654 * 04 BRC, bus release condition: 0=all transfers complete
655 * 1=release after 1 xfer on all channels
656 * 03 CCC, channel change condition: 0=every cycle
657 * 1=after each channel completes all xfers
658 * 02..00 PR<2..0>, priority 100=round robin
662 static unsigned char dma_priority
= 0x04;
664 // Number of bytes that can be written to shared RAM
665 // in a single write operation
666 static u32 sca_pci_load_interval
= 64;
669 * 1st function defined in .text section. Calling this function in
670 * init_module() followed by a breakpoint allows a remote debugger
671 * (gdb) to get the .text address for the add-symbol-file command.
672 * This allows remote debugging of dynamically loadable modules.
674 static void* synclinkmp_get_text_ptr(void);
675 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr
;}
677 static inline int sanity_check(SLMP_INFO
*info
,
678 char *name
, const char *routine
)
681 static const char *badmagic
=
682 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
683 static const char *badinfo
=
684 "Warning: null synclinkmp_struct for (%s) in %s\n";
687 printk(badinfo
, name
, routine
);
690 if (info
->magic
!= MGSL_MAGIC
) {
691 printk(badmagic
, name
, routine
);
702 * line discipline callback wrappers
704 * The wrappers maintain line discipline references
705 * while calling into the line discipline.
707 * ldisc_receive_buf - pass receive data to line discipline
710 static void ldisc_receive_buf(struct tty_struct
*tty
,
711 const __u8
*data
, char *flags
, int count
)
713 struct tty_ldisc
*ld
;
716 ld
= tty_ldisc_ref(tty
);
719 ld
->receive_buf(tty
, data
, flags
, count
);
726 /* Called when a port is opened. Init and enable port.
728 static int open(struct tty_struct
*tty
, struct file
*filp
)
735 if ((line
< 0) || (line
>= synclinkmp_device_count
)) {
736 printk("%s(%d): open with invalid line #%d.\n",
737 __FILE__
,__LINE__
,line
);
741 info
= synclinkmp_device_list
;
742 while(info
&& info
->line
!= line
)
743 info
= info
->next_device
;
744 if (sanity_check(info
, tty
->name
, "open"))
746 if ( info
->init_error
) {
747 printk("%s(%d):%s device is not allocated, init error=%d\n",
748 __FILE__
,__LINE__
,info
->device_name
,info
->init_error
);
752 tty
->driver_data
= info
;
755 if (debug_level
>= DEBUG_LEVEL_INFO
)
756 printk("%s(%d):%s open(), old ref count = %d\n",
757 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
759 /* If port is closing, signal caller to try again */
760 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
761 if (info
->flags
& ASYNC_CLOSING
)
762 interruptible_sleep_on(&info
->close_wait
);
763 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
764 -EAGAIN
: -ERESTARTSYS
);
768 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
770 spin_lock_irqsave(&info
->netlock
, flags
);
771 if (info
->netcount
) {
773 spin_unlock_irqrestore(&info
->netlock
, flags
);
777 spin_unlock_irqrestore(&info
->netlock
, flags
);
779 if (info
->count
== 1) {
780 /* 1st open on this device, init hardware */
781 retval
= startup(info
);
786 retval
= block_til_ready(tty
, filp
, info
);
788 if (debug_level
>= DEBUG_LEVEL_INFO
)
789 printk("%s(%d):%s block_til_ready() returned %d\n",
790 __FILE__
,__LINE__
, info
->device_name
, retval
);
794 if (debug_level
>= DEBUG_LEVEL_INFO
)
795 printk("%s(%d):%s open() success\n",
796 __FILE__
,__LINE__
, info
->device_name
);
802 info
->tty
= NULL
; /* tty layer will release tty struct */
810 /* Called when port is closed. Wait for remaining data to be
811 * sent. Disable port and free resources.
813 static void close(struct tty_struct
*tty
, struct file
*filp
)
815 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
817 if (sanity_check(info
, tty
->name
, "close"))
820 if (debug_level
>= DEBUG_LEVEL_INFO
)
821 printk("%s(%d):%s close() entry, count=%d\n",
822 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
827 if (tty_hung_up_p(filp
))
830 if ((tty
->count
== 1) && (info
->count
!= 1)) {
832 * tty->count is 1 and the tty structure will be freed.
833 * info->count should be one in this case.
834 * if it's not, correct it so that the port is shutdown.
836 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
837 "info->count is %d\n",
838 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
844 /* if at least one open remaining, leave hardware active */
848 info
->flags
|= ASYNC_CLOSING
;
850 /* set tty->closing to notify line discipline to
851 * only process XON/XOFF characters. Only the N_TTY
852 * discipline appears to use this (ppp does not).
856 /* wait for transmit data to clear all layers */
858 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
859 if (debug_level
>= DEBUG_LEVEL_INFO
)
860 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
861 __FILE__
,__LINE__
, info
->device_name
);
862 tty_wait_until_sent(tty
, info
->closing_wait
);
865 if (info
->flags
& ASYNC_INITIALIZED
)
866 wait_until_sent(tty
, info
->timeout
);
868 if (tty
->driver
->flush_buffer
)
869 tty
->driver
->flush_buffer(tty
);
871 tty_ldisc_flush(tty
);
878 if (info
->blocked_open
) {
879 if (info
->close_delay
) {
880 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
882 wake_up_interruptible(&info
->open_wait
);
885 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
887 wake_up_interruptible(&info
->close_wait
);
890 if (debug_level
>= DEBUG_LEVEL_INFO
)
891 printk("%s(%d):%s close() exit, count=%d\n", __FILE__
,__LINE__
,
892 tty
->driver
->name
, info
->count
);
895 /* Called by tty_hangup() when a hangup is signaled.
896 * This is the same as closing all open descriptors for the port.
898 static void hangup(struct tty_struct
*tty
)
900 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
902 if (debug_level
>= DEBUG_LEVEL_INFO
)
903 printk("%s(%d):%s hangup()\n",
904 __FILE__
,__LINE__
, info
->device_name
);
906 if (sanity_check(info
, tty
->name
, "hangup"))
913 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
916 wake_up_interruptible(&info
->open_wait
);
919 /* Set new termios settings
921 static void set_termios(struct tty_struct
*tty
, struct termios
*old_termios
)
923 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
926 if (debug_level
>= DEBUG_LEVEL_INFO
)
927 printk("%s(%d):%s set_termios()\n", __FILE__
,__LINE__
,
930 /* just return if nothing has changed */
931 if ((tty
->termios
->c_cflag
== old_termios
->c_cflag
)
932 && (RELEVANT_IFLAG(tty
->termios
->c_iflag
)
933 == RELEVANT_IFLAG(old_termios
->c_iflag
)))
938 /* Handle transition to B0 status */
939 if (old_termios
->c_cflag
& CBAUD
&&
940 !(tty
->termios
->c_cflag
& CBAUD
)) {
941 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
942 spin_lock_irqsave(&info
->lock
,flags
);
944 spin_unlock_irqrestore(&info
->lock
,flags
);
947 /* Handle transition away from B0 status */
948 if (!(old_termios
->c_cflag
& CBAUD
) &&
949 tty
->termios
->c_cflag
& CBAUD
) {
950 info
->serial_signals
|= SerialSignal_DTR
;
951 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
952 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
953 info
->serial_signals
|= SerialSignal_RTS
;
955 spin_lock_irqsave(&info
->lock
,flags
);
957 spin_unlock_irqrestore(&info
->lock
,flags
);
960 /* Handle turning off CRTSCTS */
961 if (old_termios
->c_cflag
& CRTSCTS
&&
962 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
968 /* Send a block of data
972 * tty pointer to tty information structure
973 * buf pointer to buffer containing send data
974 * count size of send data in bytes
976 * Return Value: number of characters written
978 static int write(struct tty_struct
*tty
,
979 const unsigned char *buf
, int count
)
982 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
985 if (debug_level
>= DEBUG_LEVEL_INFO
)
986 printk("%s(%d):%s write() count=%d\n",
987 __FILE__
,__LINE__
,info
->device_name
,count
);
989 if (sanity_check(info
, tty
->name
, "write"))
992 if (!tty
|| !info
->tx_buf
)
995 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
996 if (count
> info
->max_frame_size
) {
1000 if (info
->tx_active
)
1002 if (info
->tx_count
) {
1003 /* send accumulated data from send_char() calls */
1004 /* as frame and wait before accepting more data. */
1005 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
1008 ret
= info
->tx_count
= count
;
1009 tx_load_dma_buffer(info
, buf
, count
);
1014 c
= min_t(int, count
,
1015 min(info
->max_frame_size
- info
->tx_count
- 1,
1016 info
->max_frame_size
- info
->tx_put
));
1020 memcpy(info
->tx_buf
+ info
->tx_put
, buf
, c
);
1022 spin_lock_irqsave(&info
->lock
,flags
);
1024 if (info
->tx_put
>= info
->max_frame_size
)
1025 info
->tx_put
-= info
->max_frame_size
;
1026 info
->tx_count
+= c
;
1027 spin_unlock_irqrestore(&info
->lock
,flags
);
1034 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1036 ret
= info
->tx_count
= 0;
1039 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
1042 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
1043 spin_lock_irqsave(&info
->lock
,flags
);
1044 if (!info
->tx_active
)
1046 spin_unlock_irqrestore(&info
->lock
,flags
);
1050 if (debug_level
>= DEBUG_LEVEL_INFO
)
1051 printk( "%s(%d):%s write() returning=%d\n",
1052 __FILE__
,__LINE__
,info
->device_name
,ret
);
1056 /* Add a character to the transmit buffer.
1058 static void put_char(struct tty_struct
*tty
, unsigned char ch
)
1060 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1061 unsigned long flags
;
1063 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
1064 printk( "%s(%d):%s put_char(%d)\n",
1065 __FILE__
,__LINE__
,info
->device_name
,ch
);
1068 if (sanity_check(info
, tty
->name
, "put_char"))
1071 if (!tty
|| !info
->tx_buf
)
1074 spin_lock_irqsave(&info
->lock
,flags
);
1076 if ( (info
->params
.mode
!= MGSL_MODE_HDLC
) ||
1077 !info
->tx_active
) {
1079 if (info
->tx_count
< info
->max_frame_size
- 1) {
1080 info
->tx_buf
[info
->tx_put
++] = ch
;
1081 if (info
->tx_put
>= info
->max_frame_size
)
1082 info
->tx_put
-= info
->max_frame_size
;
1087 spin_unlock_irqrestore(&info
->lock
,flags
);
1090 /* Send a high-priority XON/XOFF character
1092 static void send_xchar(struct tty_struct
*tty
, char ch
)
1094 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1095 unsigned long flags
;
1097 if (debug_level
>= DEBUG_LEVEL_INFO
)
1098 printk("%s(%d):%s send_xchar(%d)\n",
1099 __FILE__
,__LINE__
, info
->device_name
, ch
);
1101 if (sanity_check(info
, tty
->name
, "send_xchar"))
1106 /* Make sure transmit interrupts are on */
1107 spin_lock_irqsave(&info
->lock
,flags
);
1108 if (!info
->tx_enabled
)
1110 spin_unlock_irqrestore(&info
->lock
,flags
);
1114 /* Wait until the transmitter is empty.
1116 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
1118 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1119 unsigned long orig_jiffies
, char_time
;
1124 if (debug_level
>= DEBUG_LEVEL_INFO
)
1125 printk("%s(%d):%s wait_until_sent() entry\n",
1126 __FILE__
,__LINE__
, info
->device_name
);
1128 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
1131 if (!(info
->flags
& ASYNC_INITIALIZED
))
1134 orig_jiffies
= jiffies
;
1136 /* Set check interval to 1/5 of estimated time to
1137 * send a character, and make it at least 1. The check
1138 * interval should also be less than the timeout.
1139 * Note: use tight timings here to satisfy the NIST-PCTS.
1142 if ( info
->params
.data_rate
) {
1143 char_time
= info
->timeout
/(32 * 5);
1150 char_time
= min_t(unsigned long, char_time
, timeout
);
1152 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
1153 while (info
->tx_active
) {
1154 msleep_interruptible(jiffies_to_msecs(char_time
));
1155 if (signal_pending(current
))
1157 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1161 //TODO: determine if there is something similar to USC16C32
1162 // TXSTATUS_ALL_SENT status
1163 while ( info
->tx_active
&& info
->tx_enabled
) {
1164 msleep_interruptible(jiffies_to_msecs(char_time
));
1165 if (signal_pending(current
))
1167 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1173 if (debug_level
>= DEBUG_LEVEL_INFO
)
1174 printk("%s(%d):%s wait_until_sent() exit\n",
1175 __FILE__
,__LINE__
, info
->device_name
);
1178 /* Return the count of free bytes in transmit buffer
1180 static int write_room(struct tty_struct
*tty
)
1182 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1185 if (sanity_check(info
, tty
->name
, "write_room"))
1188 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1189 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1191 ret
= info
->max_frame_size
- info
->tx_count
- 1;
1196 if (debug_level
>= DEBUG_LEVEL_INFO
)
1197 printk("%s(%d):%s write_room()=%d\n",
1198 __FILE__
, __LINE__
, info
->device_name
, ret
);
1203 /* enable transmitter and send remaining buffered characters
1205 static void flush_chars(struct tty_struct
*tty
)
1207 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1208 unsigned long flags
;
1210 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1211 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1212 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
1214 if (sanity_check(info
, tty
->name
, "flush_chars"))
1217 if (info
->tx_count
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
1221 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1222 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1223 __FILE__
,__LINE__
,info
->device_name
);
1225 spin_lock_irqsave(&info
->lock
,flags
);
1227 if (!info
->tx_active
) {
1228 if ( (info
->params
.mode
== MGSL_MODE_HDLC
) &&
1230 /* operating in synchronous (frame oriented) mode */
1231 /* copy data from circular tx_buf to */
1232 /* transmit DMA buffer. */
1233 tx_load_dma_buffer(info
,
1234 info
->tx_buf
,info
->tx_count
);
1239 spin_unlock_irqrestore(&info
->lock
,flags
);
1242 /* Discard all data in the send buffer
1244 static void flush_buffer(struct tty_struct
*tty
)
1246 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1247 unsigned long flags
;
1249 if (debug_level
>= DEBUG_LEVEL_INFO
)
1250 printk("%s(%d):%s flush_buffer() entry\n",
1251 __FILE__
,__LINE__
, info
->device_name
);
1253 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1256 spin_lock_irqsave(&info
->lock
,flags
);
1257 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
1258 del_timer(&info
->tx_timer
);
1259 spin_unlock_irqrestore(&info
->lock
,flags
);
1261 wake_up_interruptible(&tty
->write_wait
);
1265 /* throttle (stop) transmitter
1267 static void tx_hold(struct tty_struct
*tty
)
1269 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1270 unsigned long flags
;
1272 if (sanity_check(info
, tty
->name
, "tx_hold"))
1275 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1276 printk("%s(%d):%s tx_hold()\n",
1277 __FILE__
,__LINE__
,info
->device_name
);
1279 spin_lock_irqsave(&info
->lock
,flags
);
1280 if (info
->tx_enabled
)
1282 spin_unlock_irqrestore(&info
->lock
,flags
);
1285 /* release (start) transmitter
1287 static void tx_release(struct tty_struct
*tty
)
1289 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1290 unsigned long flags
;
1292 if (sanity_check(info
, tty
->name
, "tx_release"))
1295 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1296 printk("%s(%d):%s tx_release()\n",
1297 __FILE__
,__LINE__
,info
->device_name
);
1299 spin_lock_irqsave(&info
->lock
,flags
);
1300 if (!info
->tx_enabled
)
1302 spin_unlock_irqrestore(&info
->lock
,flags
);
1305 /* Service an IOCTL request
1309 * tty pointer to tty instance data
1310 * file pointer to associated file object for device
1311 * cmd IOCTL command code
1312 * arg command argument/context
1314 * Return Value: 0 if success, otherwise error code
1316 static int ioctl(struct tty_struct
*tty
, struct file
*file
,
1317 unsigned int cmd
, unsigned long arg
)
1319 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1321 struct mgsl_icount cnow
; /* kernel counter temps */
1322 struct serial_icounter_struct __user
*p_cuser
; /* user space */
1323 unsigned long flags
;
1324 void __user
*argp
= (void __user
*)arg
;
1326 if (debug_level
>= DEBUG_LEVEL_INFO
)
1327 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__
,__LINE__
,
1328 info
->device_name
, cmd
);
1330 if (sanity_check(info
, tty
->name
, "ioctl"))
1333 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1334 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
1335 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1340 case MGSL_IOCGPARAMS
:
1341 return get_params(info
, argp
);
1342 case MGSL_IOCSPARAMS
:
1343 return set_params(info
, argp
);
1344 case MGSL_IOCGTXIDLE
:
1345 return get_txidle(info
, argp
);
1346 case MGSL_IOCSTXIDLE
:
1347 return set_txidle(info
, (int)arg
);
1348 case MGSL_IOCTXENABLE
:
1349 return tx_enable(info
, (int)arg
);
1350 case MGSL_IOCRXENABLE
:
1351 return rx_enable(info
, (int)arg
);
1352 case MGSL_IOCTXABORT
:
1353 return tx_abort(info
);
1354 case MGSL_IOCGSTATS
:
1355 return get_stats(info
, argp
);
1356 case MGSL_IOCWAITEVENT
:
1357 return wait_mgsl_event(info
, argp
);
1358 case MGSL_IOCLOOPTXDONE
:
1359 return 0; // TODO: Not supported, need to document
1360 /* Wait for modem input (DCD,RI,DSR,CTS) change
1361 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1364 return modem_input_wait(info
,(int)arg
);
1367 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1368 * Return: write counters to the user passed counter struct
1369 * NB: both 1->0 and 0->1 transitions are counted except for
1370 * RI where only 0->1 is counted.
1373 spin_lock_irqsave(&info
->lock
,flags
);
1374 cnow
= info
->icount
;
1375 spin_unlock_irqrestore(&info
->lock
,flags
);
1377 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
1378 if (error
) return error
;
1379 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
1380 if (error
) return error
;
1381 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
1382 if (error
) return error
;
1383 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
1384 if (error
) return error
;
1385 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
1386 if (error
) return error
;
1387 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
1388 if (error
) return error
;
1389 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
1390 if (error
) return error
;
1391 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
1392 if (error
) return error
;
1393 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
1394 if (error
) return error
;
1395 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
1396 if (error
) return error
;
1397 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
1398 if (error
) return error
;
1401 return -ENOIOCTLCMD
;
1407 * /proc fs routines....
1410 static inline int line_info(char *buf
, SLMP_INFO
*info
)
1414 unsigned long flags
;
1416 ret
= sprintf(buf
, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1417 "\tIRQ=%d MaxFrameSize=%u\n",
1419 info
->phys_sca_base
,
1420 info
->phys_memory_base
,
1421 info
->phys_statctrl_base
,
1422 info
->phys_lcr_base
,
1424 info
->max_frame_size
);
1426 /* output current serial signal states */
1427 spin_lock_irqsave(&info
->lock
,flags
);
1429 spin_unlock_irqrestore(&info
->lock
,flags
);
1433 if (info
->serial_signals
& SerialSignal_RTS
)
1434 strcat(stat_buf
, "|RTS");
1435 if (info
->serial_signals
& SerialSignal_CTS
)
1436 strcat(stat_buf
, "|CTS");
1437 if (info
->serial_signals
& SerialSignal_DTR
)
1438 strcat(stat_buf
, "|DTR");
1439 if (info
->serial_signals
& SerialSignal_DSR
)
1440 strcat(stat_buf
, "|DSR");
1441 if (info
->serial_signals
& SerialSignal_DCD
)
1442 strcat(stat_buf
, "|CD");
1443 if (info
->serial_signals
& SerialSignal_RI
)
1444 strcat(stat_buf
, "|RI");
1446 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1447 ret
+= sprintf(buf
+ret
, "\tHDLC txok:%d rxok:%d",
1448 info
->icount
.txok
, info
->icount
.rxok
);
1449 if (info
->icount
.txunder
)
1450 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
1451 if (info
->icount
.txabort
)
1452 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
1453 if (info
->icount
.rxshort
)
1454 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
1455 if (info
->icount
.rxlong
)
1456 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
1457 if (info
->icount
.rxover
)
1458 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
1459 if (info
->icount
.rxcrc
)
1460 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxcrc
);
1462 ret
+= sprintf(buf
+ret
, "\tASYNC tx:%d rx:%d",
1463 info
->icount
.tx
, info
->icount
.rx
);
1464 if (info
->icount
.frame
)
1465 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
1466 if (info
->icount
.parity
)
1467 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
1468 if (info
->icount
.brk
)
1469 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
1470 if (info
->icount
.overrun
)
1471 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
1474 /* Append serial signal status to end */
1475 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
1477 ret
+= sprintf(buf
+ret
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1478 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1484 /* Called to print information about devices
1486 int read_proc(char *page
, char **start
, off_t off
, int count
,
1487 int *eof
, void *data
)
1493 len
+= sprintf(page
, "synclinkmp driver:%s\n", driver_version
);
1495 info
= synclinkmp_device_list
;
1497 l
= line_info(page
+ len
, info
);
1499 if (len
+begin
> off
+count
)
1501 if (len
+begin
< off
) {
1505 info
= info
->next_device
;
1510 if (off
>= len
+begin
)
1512 *start
= page
+ (off
-begin
);
1513 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
1516 /* Return the count of bytes in transmit buffer
1518 static int chars_in_buffer(struct tty_struct
*tty
)
1520 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1522 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1525 if (debug_level
>= DEBUG_LEVEL_INFO
)
1526 printk("%s(%d):%s chars_in_buffer()=%d\n",
1527 __FILE__
, __LINE__
, info
->device_name
, info
->tx_count
);
1529 return info
->tx_count
;
1532 /* Signal remote device to throttle send data (our receive data)
1534 static void throttle(struct tty_struct
* tty
)
1536 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1537 unsigned long flags
;
1539 if (debug_level
>= DEBUG_LEVEL_INFO
)
1540 printk("%s(%d):%s throttle() entry\n",
1541 __FILE__
,__LINE__
, info
->device_name
);
1543 if (sanity_check(info
, tty
->name
, "throttle"))
1547 send_xchar(tty
, STOP_CHAR(tty
));
1549 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1550 spin_lock_irqsave(&info
->lock
,flags
);
1551 info
->serial_signals
&= ~SerialSignal_RTS
;
1553 spin_unlock_irqrestore(&info
->lock
,flags
);
1557 /* Signal remote device to stop throttling send data (our receive data)
1559 static void unthrottle(struct tty_struct
* tty
)
1561 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1562 unsigned long flags
;
1564 if (debug_level
>= DEBUG_LEVEL_INFO
)
1565 printk("%s(%d):%s unthrottle() entry\n",
1566 __FILE__
,__LINE__
, info
->device_name
);
1568 if (sanity_check(info
, tty
->name
, "unthrottle"))
1575 send_xchar(tty
, START_CHAR(tty
));
1578 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1579 spin_lock_irqsave(&info
->lock
,flags
);
1580 info
->serial_signals
|= SerialSignal_RTS
;
1582 spin_unlock_irqrestore(&info
->lock
,flags
);
1586 /* set or clear transmit break condition
1587 * break_state -1=set break condition, 0=clear
1589 static void set_break(struct tty_struct
*tty
, int break_state
)
1591 unsigned char RegValue
;
1592 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1593 unsigned long flags
;
1595 if (debug_level
>= DEBUG_LEVEL_INFO
)
1596 printk("%s(%d):%s set_break(%d)\n",
1597 __FILE__
,__LINE__
, info
->device_name
, break_state
);
1599 if (sanity_check(info
, tty
->name
, "set_break"))
1602 spin_lock_irqsave(&info
->lock
,flags
);
1603 RegValue
= read_reg(info
, CTL
);
1604 if (break_state
== -1)
1608 write_reg(info
, CTL
, RegValue
);
1609 spin_unlock_irqrestore(&info
->lock
,flags
);
1615 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1616 * set encoding and frame check sequence (FCS) options
1618 * dev pointer to network device structure
1619 * encoding serial encoding setting
1620 * parity FCS setting
1622 * returns 0 if success, otherwise error code
1624 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1625 unsigned short parity
)
1627 SLMP_INFO
*info
= dev_to_port(dev
);
1628 unsigned char new_encoding
;
1629 unsigned short new_crctype
;
1631 /* return error if TTY interface open */
1637 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1638 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1639 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1640 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1641 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1642 default: return -EINVAL
;
1647 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1648 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1649 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1650 default: return -EINVAL
;
1653 info
->params
.encoding
= new_encoding
;
1654 info
->params
.crc_type
= new_crctype
;;
1656 /* if network interface up, reprogram hardware */
1664 * called by generic HDLC layer to send frame
1666 * skb socket buffer containing HDLC frame
1667 * dev pointer to network device structure
1669 * returns 0 if success, otherwise error code
1671 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1673 SLMP_INFO
*info
= dev_to_port(dev
);
1674 struct net_device_stats
*stats
= hdlc_stats(dev
);
1675 unsigned long flags
;
1677 if (debug_level
>= DEBUG_LEVEL_INFO
)
1678 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
1680 /* stop sending until this frame completes */
1681 netif_stop_queue(dev
);
1683 /* copy data to device buffers */
1684 info
->tx_count
= skb
->len
;
1685 tx_load_dma_buffer(info
, skb
->data
, skb
->len
);
1687 /* update network statistics */
1688 stats
->tx_packets
++;
1689 stats
->tx_bytes
+= skb
->len
;
1691 /* done with socket buffer, so free it */
1694 /* save start time for transmit timeout detection */
1695 dev
->trans_start
= jiffies
;
1697 /* start hardware transmitter if necessary */
1698 spin_lock_irqsave(&info
->lock
,flags
);
1699 if (!info
->tx_active
)
1701 spin_unlock_irqrestore(&info
->lock
,flags
);
1707 * called by network layer when interface enabled
1708 * claim resources and initialize hardware
1710 * dev pointer to network device structure
1712 * returns 0 if success, otherwise error code
1714 static int hdlcdev_open(struct net_device
*dev
)
1716 SLMP_INFO
*info
= dev_to_port(dev
);
1718 unsigned long flags
;
1720 if (debug_level
>= DEBUG_LEVEL_INFO
)
1721 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
1723 /* generic HDLC layer open processing */
1724 if ((rc
= hdlc_open(dev
)))
1727 /* arbitrate between network and tty opens */
1728 spin_lock_irqsave(&info
->netlock
, flags
);
1729 if (info
->count
!= 0 || info
->netcount
!= 0) {
1730 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
1731 spin_unlock_irqrestore(&info
->netlock
, flags
);
1735 spin_unlock_irqrestore(&info
->netlock
, flags
);
1737 /* claim resources and init adapter */
1738 if ((rc
= startup(info
)) != 0) {
1739 spin_lock_irqsave(&info
->netlock
, flags
);
1741 spin_unlock_irqrestore(&info
->netlock
, flags
);
1745 /* assert DTR and RTS, apply hardware settings */
1746 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1749 /* enable network layer transmit */
1750 dev
->trans_start
= jiffies
;
1751 netif_start_queue(dev
);
1753 /* inform generic HDLC layer of current DCD status */
1754 spin_lock_irqsave(&info
->lock
, flags
);
1756 spin_unlock_irqrestore(&info
->lock
, flags
);
1757 hdlc_set_carrier(info
->serial_signals
& SerialSignal_DCD
, dev
);
1763 * called by network layer when interface is disabled
1764 * shutdown hardware and release resources
1766 * dev pointer to network device structure
1768 * returns 0 if success, otherwise error code
1770 static int hdlcdev_close(struct net_device
*dev
)
1772 SLMP_INFO
*info
= dev_to_port(dev
);
1773 unsigned long flags
;
1775 if (debug_level
>= DEBUG_LEVEL_INFO
)
1776 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
1778 netif_stop_queue(dev
);
1780 /* shutdown adapter and release resources */
1785 spin_lock_irqsave(&info
->netlock
, flags
);
1787 spin_unlock_irqrestore(&info
->netlock
, flags
);
1793 * called by network layer to process IOCTL call to network device
1795 * dev pointer to network device structure
1796 * ifr pointer to network interface request structure
1797 * cmd IOCTL command code
1799 * returns 0 if success, otherwise error code
1801 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1803 const size_t size
= sizeof(sync_serial_settings
);
1804 sync_serial_settings new_line
;
1805 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1806 SLMP_INFO
*info
= dev_to_port(dev
);
1809 if (debug_level
>= DEBUG_LEVEL_INFO
)
1810 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
1812 /* return error if TTY interface open */
1816 if (cmd
!= SIOCWANDEV
)
1817 return hdlc_ioctl(dev
, ifr
, cmd
);
1819 switch(ifr
->ifr_settings
.type
) {
1820 case IF_GET_IFACE
: /* return current sync_serial_settings */
1822 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1823 if (ifr
->ifr_settings
.size
< size
) {
1824 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1828 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1829 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1830 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1831 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1834 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1835 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1836 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1837 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1838 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1841 new_line
.clock_rate
= info
->params
.clock_speed
;
1842 new_line
.loopback
= info
->params
.loopback
? 1:0;
1844 if (copy_to_user(line
, &new_line
, size
))
1848 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1850 if(!capable(CAP_NET_ADMIN
))
1852 if (copy_from_user(&new_line
, line
, size
))
1855 switch (new_line
.clock_type
)
1857 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1858 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1859 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1860 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1861 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1862 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1863 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1864 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1865 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1866 default: return -EINVAL
;
1869 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1872 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1873 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1874 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1875 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1876 info
->params
.flags
|= flags
;
1878 info
->params
.loopback
= new_line
.loopback
;
1880 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1881 info
->params
.clock_speed
= new_line
.clock_rate
;
1883 info
->params
.clock_speed
= 0;
1885 /* if network interface up, reprogram hardware */
1891 return hdlc_ioctl(dev
, ifr
, cmd
);
1896 * called by network layer when transmit timeout is detected
1898 * dev pointer to network device structure
1900 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1902 SLMP_INFO
*info
= dev_to_port(dev
);
1903 struct net_device_stats
*stats
= hdlc_stats(dev
);
1904 unsigned long flags
;
1906 if (debug_level
>= DEBUG_LEVEL_INFO
)
1907 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
1910 stats
->tx_aborted_errors
++;
1912 spin_lock_irqsave(&info
->lock
,flags
);
1914 spin_unlock_irqrestore(&info
->lock
,flags
);
1916 netif_wake_queue(dev
);
1920 * called by device driver when transmit completes
1921 * reenable network layer transmit if stopped
1923 * info pointer to device instance information
1925 static void hdlcdev_tx_done(SLMP_INFO
*info
)
1927 if (netif_queue_stopped(info
->netdev
))
1928 netif_wake_queue(info
->netdev
);
1932 * called by device driver when frame received
1933 * pass frame to network layer
1935 * info pointer to device instance information
1936 * buf pointer to buffer contianing frame data
1937 * size count of data bytes in buf
1939 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
)
1941 struct sk_buff
*skb
= dev_alloc_skb(size
);
1942 struct net_device
*dev
= info
->netdev
;
1943 struct net_device_stats
*stats
= hdlc_stats(dev
);
1945 if (debug_level
>= DEBUG_LEVEL_INFO
)
1946 printk("hdlcdev_rx(%s)\n",dev
->name
);
1949 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
1950 stats
->rx_dropped
++;
1954 memcpy(skb_put(skb
, size
),buf
,size
);
1956 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
1958 stats
->rx_packets
++;
1959 stats
->rx_bytes
+= size
;
1963 info
->netdev
->last_rx
= jiffies
;
1967 * called by device driver when adding device instance
1968 * do generic HDLC initialization
1970 * info pointer to device instance information
1972 * returns 0 if success, otherwise error code
1974 static int hdlcdev_init(SLMP_INFO
*info
)
1977 struct net_device
*dev
;
1980 /* allocate and initialize network and HDLC layer objects */
1982 if (!(dev
= alloc_hdlcdev(info
))) {
1983 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
1987 /* for network layer reporting purposes only */
1988 dev
->mem_start
= info
->phys_sca_base
;
1989 dev
->mem_end
= info
->phys_sca_base
+ SCA_BASE_SIZE
- 1;
1990 dev
->irq
= info
->irq_level
;
1992 /* network layer callbacks and settings */
1993 dev
->do_ioctl
= hdlcdev_ioctl
;
1994 dev
->open
= hdlcdev_open
;
1995 dev
->stop
= hdlcdev_close
;
1996 dev
->tx_timeout
= hdlcdev_tx_timeout
;
1997 dev
->watchdog_timeo
= 10*HZ
;
1998 dev
->tx_queue_len
= 50;
2000 /* generic HDLC layer callbacks and settings */
2001 hdlc
= dev_to_hdlc(dev
);
2002 hdlc
->attach
= hdlcdev_attach
;
2003 hdlc
->xmit
= hdlcdev_xmit
;
2005 /* register objects with HDLC layer */
2006 if ((rc
= register_hdlc_device(dev
))) {
2007 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
2017 * called by device driver when removing device instance
2018 * do generic HDLC cleanup
2020 * info pointer to device instance information
2022 static void hdlcdev_exit(SLMP_INFO
*info
)
2024 unregister_hdlc_device(info
->netdev
);
2025 free_netdev(info
->netdev
);
2026 info
->netdev
= NULL
;
2029 #endif /* CONFIG_HDLC */
2032 /* Return next bottom half action to perform.
2033 * Return Value: BH action code or 0 if nothing to do.
2035 int bh_action(SLMP_INFO
*info
)
2037 unsigned long flags
;
2040 spin_lock_irqsave(&info
->lock
,flags
);
2042 if (info
->pending_bh
& BH_RECEIVE
) {
2043 info
->pending_bh
&= ~BH_RECEIVE
;
2045 } else if (info
->pending_bh
& BH_TRANSMIT
) {
2046 info
->pending_bh
&= ~BH_TRANSMIT
;
2048 } else if (info
->pending_bh
& BH_STATUS
) {
2049 info
->pending_bh
&= ~BH_STATUS
;
2054 /* Mark BH routine as complete */
2055 info
->bh_running
= 0;
2056 info
->bh_requested
= 0;
2059 spin_unlock_irqrestore(&info
->lock
,flags
);
2064 /* Perform bottom half processing of work items queued by ISR.
2066 void bh_handler(void* Context
)
2068 SLMP_INFO
*info
= (SLMP_INFO
*)Context
;
2074 if ( debug_level
>= DEBUG_LEVEL_BH
)
2075 printk( "%s(%d):%s bh_handler() entry\n",
2076 __FILE__
,__LINE__
,info
->device_name
);
2078 info
->bh_running
= 1;
2080 while((action
= bh_action(info
)) != 0) {
2082 /* Process work item */
2083 if ( debug_level
>= DEBUG_LEVEL_BH
)
2084 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2085 __FILE__
,__LINE__
,info
->device_name
, action
);
2099 /* unknown work item ID */
2100 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2101 __FILE__
,__LINE__
,info
->device_name
,action
);
2106 if ( debug_level
>= DEBUG_LEVEL_BH
)
2107 printk( "%s(%d):%s bh_handler() exit\n",
2108 __FILE__
,__LINE__
,info
->device_name
);
2111 void bh_receive(SLMP_INFO
*info
)
2113 if ( debug_level
>= DEBUG_LEVEL_BH
)
2114 printk( "%s(%d):%s bh_receive()\n",
2115 __FILE__
,__LINE__
,info
->device_name
);
2117 while( rx_get_frame(info
) );
2120 void bh_transmit(SLMP_INFO
*info
)
2122 struct tty_struct
*tty
= info
->tty
;
2124 if ( debug_level
>= DEBUG_LEVEL_BH
)
2125 printk( "%s(%d):%s bh_transmit() entry\n",
2126 __FILE__
,__LINE__
,info
->device_name
);
2130 wake_up_interruptible(&tty
->write_wait
);
2134 void bh_status(SLMP_INFO
*info
)
2136 if ( debug_level
>= DEBUG_LEVEL_BH
)
2137 printk( "%s(%d):%s bh_status() entry\n",
2138 __FILE__
,__LINE__
,info
->device_name
);
2140 info
->ri_chkcount
= 0;
2141 info
->dsr_chkcount
= 0;
2142 info
->dcd_chkcount
= 0;
2143 info
->cts_chkcount
= 0;
2146 void isr_timer(SLMP_INFO
* info
)
2148 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
2150 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2151 write_reg(info
, IER2
, 0);
2153 /* TMCS, Timer Control/Status Register
2155 * 07 CMF, Compare match flag (read only) 1=match
2156 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2157 * 05 Reserved, must be 0
2158 * 04 TME, Timer Enable
2159 * 03..00 Reserved, must be 0
2163 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0);
2165 info
->irq_occurred
= TRUE
;
2167 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2168 printk("%s(%d):%s isr_timer()\n",
2169 __FILE__
,__LINE__
,info
->device_name
);
2172 void isr_rxint(SLMP_INFO
* info
)
2174 struct tty_struct
*tty
= info
->tty
;
2175 struct mgsl_icount
*icount
= &info
->icount
;
2176 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (FLGD
+ IDLD
+ CDCD
+ BRKD
);
2177 unsigned char status2
= read_reg(info
, SR2
) & info
->ie2_value
& OVRN
;
2179 /* clear status bits */
2181 write_reg(info
, SR1
, status
);
2184 write_reg(info
, SR2
, status2
);
2186 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2187 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2188 __FILE__
,__LINE__
,info
->device_name
,status
,status2
);
2190 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2191 if (status
& BRKD
) {
2194 /* process break detection if tty control
2195 * is not set to ignore it
2198 if (!(status
& info
->ignore_status_mask1
)) {
2199 if (info
->read_status_mask1
& BRKD
) {
2200 *tty
->flip
.flag_buf_ptr
= TTY_BREAK
;
2201 if (info
->flags
& ASYNC_SAK
)
2209 if (status
& (FLGD
|IDLD
)) {
2211 info
->icount
.exithunt
++;
2212 else if (status
& IDLD
)
2213 info
->icount
.rxidle
++;
2214 wake_up_interruptible(&info
->event_wait_q
);
2218 if (status
& CDCD
) {
2219 /* simulate a common modem status change interrupt
2222 get_signals( info
);
2224 MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
));
2229 * handle async rx data interrupts
2231 void isr_rxrdy(SLMP_INFO
* info
)
2234 unsigned char DataByte
;
2235 struct tty_struct
*tty
= info
->tty
;
2236 struct mgsl_icount
*icount
= &info
->icount
;
2238 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2239 printk("%s(%d):%s isr_rxrdy\n",
2240 __FILE__
,__LINE__
,info
->device_name
);
2242 while((status
= read_reg(info
,CST0
)) & BIT0
)
2244 DataByte
= read_reg(info
,TRB
);
2247 if (tty
->flip
.count
>= TTY_FLIPBUF_SIZE
)
2250 *tty
->flip
.char_buf_ptr
= DataByte
;
2251 *tty
->flip
.flag_buf_ptr
= 0;
2256 if ( status
& (PE
+ FRME
+ OVRN
) ) {
2257 printk("%s(%d):%s rxerr=%04X\n",
2258 __FILE__
,__LINE__
,info
->device_name
,status
);
2260 /* update error statistics */
2263 else if (status
& FRME
)
2265 else if (status
& OVRN
)
2268 /* discard char if tty control flags say so */
2269 if (status
& info
->ignore_status_mask2
)
2272 status
&= info
->read_status_mask2
;
2276 *tty
->flip
.flag_buf_ptr
= TTY_PARITY
;
2277 else if (status
& FRME
)
2278 *tty
->flip
.flag_buf_ptr
= TTY_FRAME
;
2279 if (status
& OVRN
) {
2280 /* Overrun is special, since it's
2281 * reported immediately, and doesn't
2282 * affect the current character
2284 if (tty
->flip
.count
< TTY_FLIPBUF_SIZE
) {
2286 tty
->flip
.flag_buf_ptr
++;
2287 tty
->flip
.char_buf_ptr
++;
2288 *tty
->flip
.flag_buf_ptr
= TTY_OVERRUN
;
2292 } /* end of if (error) */
2295 tty
->flip
.flag_buf_ptr
++;
2296 tty
->flip
.char_buf_ptr
++;
2301 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
2302 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2303 __FILE__
,__LINE__
,info
->device_name
,
2304 tty
? tty
->flip
.count
: 0);
2305 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2306 __FILE__
,__LINE__
,info
->device_name
,
2307 icount
->rx
,icount
->brk
,icount
->parity
,
2308 icount
->frame
,icount
->overrun
);
2311 if ( tty
&& tty
->flip
.count
)
2312 tty_flip_buffer_push(tty
);
2315 static void isr_txeom(SLMP_INFO
* info
, unsigned char status
)
2317 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2318 printk("%s(%d):%s isr_txeom status=%02x\n",
2319 __FILE__
,__LINE__
,info
->device_name
,status
);
2321 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2322 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2323 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2325 if (status
& UDRN
) {
2326 write_reg(info
, CMD
, TXRESET
);
2327 write_reg(info
, CMD
, TXENABLE
);
2329 write_reg(info
, CMD
, TXBUFCLR
);
2331 /* disable and clear tx interrupts */
2332 info
->ie0_value
&= ~TXRDYE
;
2333 info
->ie1_value
&= ~(IDLE
+ UDRN
);
2334 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2335 write_reg(info
, SR1
, (unsigned char)(UDRN
+ IDLE
));
2337 if ( info
->tx_active
) {
2338 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2340 info
->icount
.txunder
++;
2341 else if (status
& IDLE
)
2342 info
->icount
.txok
++;
2345 info
->tx_active
= 0;
2346 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2348 del_timer(&info
->tx_timer
);
2350 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2351 info
->serial_signals
&= ~SerialSignal_RTS
;
2352 info
->drop_rts_on_tx_done
= 0;
2358 hdlcdev_tx_done(info
);
2362 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2366 info
->pending_bh
|= BH_TRANSMIT
;
2373 * handle tx status interrupts
2375 void isr_txint(SLMP_INFO
* info
)
2377 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (UDRN
+ IDLE
+ CCTS
);
2379 /* clear status bits */
2380 write_reg(info
, SR1
, status
);
2382 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2383 printk("%s(%d):%s isr_txint status=%02x\n",
2384 __FILE__
,__LINE__
,info
->device_name
,status
);
2386 if (status
& (UDRN
+ IDLE
))
2387 isr_txeom(info
, status
);
2389 if (status
& CCTS
) {
2390 /* simulate a common modem status change interrupt
2393 get_signals( info
);
2395 MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
));
2401 * handle async tx data interrupts
2403 void isr_txrdy(SLMP_INFO
* info
)
2405 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2406 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2407 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
2409 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2410 /* disable TXRDY IRQ, enable IDLE IRQ */
2411 info
->ie0_value
&= ~TXRDYE
;
2412 info
->ie1_value
|= IDLE
;
2413 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2417 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2422 if ( info
->tx_count
)
2423 tx_load_fifo( info
);
2425 info
->tx_active
= 0;
2426 info
->ie0_value
&= ~TXRDYE
;
2427 write_reg(info
, IE0
, info
->ie0_value
);
2430 if (info
->tx_count
< WAKEUP_CHARS
)
2431 info
->pending_bh
|= BH_TRANSMIT
;
2434 void isr_rxdmaok(SLMP_INFO
* info
)
2436 /* BIT7 = EOT (end of transfer)
2437 * BIT6 = EOM (end of message/frame)
2439 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0xc0;
2441 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2442 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2444 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2445 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2446 __FILE__
,__LINE__
,info
->device_name
,status
);
2448 info
->pending_bh
|= BH_RECEIVE
;
2451 void isr_rxdmaerror(SLMP_INFO
* info
)
2453 /* BIT5 = BOF (buffer overflow)
2454 * BIT4 = COF (counter overflow)
2456 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0x30;
2458 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2459 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2461 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2462 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2463 __FILE__
,__LINE__
,info
->device_name
,status
);
2465 info
->rx_overflow
= TRUE
;
2466 info
->pending_bh
|= BH_RECEIVE
;
2469 void isr_txdmaok(SLMP_INFO
* info
)
2471 unsigned char status_reg1
= read_reg(info
, SR1
);
2473 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2474 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2475 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2477 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2478 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2479 __FILE__
,__LINE__
,info
->device_name
,status_reg1
);
2481 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2482 write_reg16(info
, TRC0
, 0);
2483 info
->ie0_value
|= TXRDYE
;
2484 write_reg(info
, IE0
, info
->ie0_value
);
2487 void isr_txdmaerror(SLMP_INFO
* info
)
2489 /* BIT5 = BOF (buffer overflow)
2490 * BIT4 = COF (counter overflow)
2492 unsigned char status
= read_reg(info
,TXDMA
+ DSR
) & 0x30;
2494 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2495 write_reg(info
, TXDMA
+ DSR
, (unsigned char)(status
| 1));
2497 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2498 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2499 __FILE__
,__LINE__
,info
->device_name
,status
);
2502 /* handle input serial signal changes
2504 void isr_io_pin( SLMP_INFO
*info
, u16 status
)
2506 struct mgsl_icount
*icount
;
2508 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2509 printk("%s(%d):isr_io_pin status=%04X\n",
2510 __FILE__
,__LINE__
,status
);
2512 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
2513 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
2514 icount
= &info
->icount
;
2515 /* update input line counters */
2516 if (status
& MISCSTATUS_RI_LATCHED
) {
2518 if ( status
& SerialSignal_RI
)
2519 info
->input_signal_events
.ri_up
++;
2521 info
->input_signal_events
.ri_down
++;
2523 if (status
& MISCSTATUS_DSR_LATCHED
) {
2525 if ( status
& SerialSignal_DSR
)
2526 info
->input_signal_events
.dsr_up
++;
2528 info
->input_signal_events
.dsr_down
++;
2530 if (status
& MISCSTATUS_DCD_LATCHED
) {
2531 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2532 info
->ie1_value
&= ~CDCD
;
2533 write_reg(info
, IE1
, info
->ie1_value
);
2536 if (status
& SerialSignal_DCD
) {
2537 info
->input_signal_events
.dcd_up
++;
2539 info
->input_signal_events
.dcd_down
++;
2542 hdlc_set_carrier(status
& SerialSignal_DCD
, info
->netdev
);
2545 if (status
& MISCSTATUS_CTS_LATCHED
)
2547 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2548 info
->ie1_value
&= ~CCTS
;
2549 write_reg(info
, IE1
, info
->ie1_value
);
2552 if ( status
& SerialSignal_CTS
)
2553 info
->input_signal_events
.cts_up
++;
2555 info
->input_signal_events
.cts_down
++;
2557 wake_up_interruptible(&info
->status_event_wait_q
);
2558 wake_up_interruptible(&info
->event_wait_q
);
2560 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
2561 (status
& MISCSTATUS_DCD_LATCHED
) ) {
2562 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2563 printk("%s CD now %s...", info
->device_name
,
2564 (status
& SerialSignal_DCD
) ? "on" : "off");
2565 if (status
& SerialSignal_DCD
)
2566 wake_up_interruptible(&info
->open_wait
);
2568 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2569 printk("doing serial hangup...");
2571 tty_hangup(info
->tty
);
2575 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
2576 (status
& MISCSTATUS_CTS_LATCHED
) ) {
2578 if (info
->tty
->hw_stopped
) {
2579 if (status
& SerialSignal_CTS
) {
2580 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2581 printk("CTS tx start...");
2582 info
->tty
->hw_stopped
= 0;
2584 info
->pending_bh
|= BH_TRANSMIT
;
2588 if (!(status
& SerialSignal_CTS
)) {
2589 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2590 printk("CTS tx stop...");
2591 info
->tty
->hw_stopped
= 1;
2599 info
->pending_bh
|= BH_STATUS
;
2602 /* Interrupt service routine entry point.
2605 * irq interrupt number that caused interrupt
2606 * dev_id device ID supplied during interrupt registration
2607 * regs interrupted processor context
2609 static irqreturn_t
synclinkmp_interrupt(int irq
, void *dev_id
,
2610 struct pt_regs
*regs
)
2613 unsigned char status
, status0
, status1
=0;
2614 unsigned char dmastatus
, dmastatus0
, dmastatus1
=0;
2615 unsigned char timerstatus0
, timerstatus1
=0;
2616 unsigned char shift
;
2620 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2621 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2622 __FILE__
,__LINE__
,irq
);
2624 info
= (SLMP_INFO
*)dev_id
;
2628 spin_lock(&info
->lock
);
2632 /* get status for SCA0 (ports 0-1) */
2633 tmp
= read_reg16(info
, ISR0
); /* get ISR0 and ISR1 in one read */
2634 status0
= (unsigned char)tmp
;
2635 dmastatus0
= (unsigned char)(tmp
>>8);
2636 timerstatus0
= read_reg(info
, ISR2
);
2638 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2639 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2640 __FILE__
,__LINE__
,info
->device_name
,
2641 status0
,dmastatus0
,timerstatus0
);
2643 if (info
->port_count
== 4) {
2644 /* get status for SCA1 (ports 2-3) */
2645 tmp
= read_reg16(info
->port_array
[2], ISR0
);
2646 status1
= (unsigned char)tmp
;
2647 dmastatus1
= (unsigned char)(tmp
>>8);
2648 timerstatus1
= read_reg(info
->port_array
[2], ISR2
);
2650 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2651 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2652 __FILE__
,__LINE__
,info
->device_name
,
2653 status1
,dmastatus1
,timerstatus1
);
2656 if (!status0
&& !dmastatus0
&& !timerstatus0
&&
2657 !status1
&& !dmastatus1
&& !timerstatus1
)
2660 for(i
=0; i
< info
->port_count
; i
++) {
2661 if (info
->port_array
[i
] == NULL
)
2665 dmastatus
= dmastatus0
;
2668 dmastatus
= dmastatus1
;
2671 shift
= i
& 1 ? 4 :0;
2673 if (status
& BIT0
<< shift
)
2674 isr_rxrdy(info
->port_array
[i
]);
2675 if (status
& BIT1
<< shift
)
2676 isr_txrdy(info
->port_array
[i
]);
2677 if (status
& BIT2
<< shift
)
2678 isr_rxint(info
->port_array
[i
]);
2679 if (status
& BIT3
<< shift
)
2680 isr_txint(info
->port_array
[i
]);
2682 if (dmastatus
& BIT0
<< shift
)
2683 isr_rxdmaerror(info
->port_array
[i
]);
2684 if (dmastatus
& BIT1
<< shift
)
2685 isr_rxdmaok(info
->port_array
[i
]);
2686 if (dmastatus
& BIT2
<< shift
)
2687 isr_txdmaerror(info
->port_array
[i
]);
2688 if (dmastatus
& BIT3
<< shift
)
2689 isr_txdmaok(info
->port_array
[i
]);
2692 if (timerstatus0
& (BIT5
| BIT4
))
2693 isr_timer(info
->port_array
[0]);
2694 if (timerstatus0
& (BIT7
| BIT6
))
2695 isr_timer(info
->port_array
[1]);
2696 if (timerstatus1
& (BIT5
| BIT4
))
2697 isr_timer(info
->port_array
[2]);
2698 if (timerstatus1
& (BIT7
| BIT6
))
2699 isr_timer(info
->port_array
[3]);
2702 for(i
=0; i
< info
->port_count
; i
++) {
2703 SLMP_INFO
* port
= info
->port_array
[i
];
2705 /* Request bottom half processing if there's something
2706 * for it to do and the bh is not already running.
2708 * Note: startup adapter diags require interrupts.
2709 * do not request bottom half processing if the
2710 * device is not open in a normal mode.
2712 if ( port
&& (port
->count
|| port
->netcount
) &&
2713 port
->pending_bh
&& !port
->bh_running
&&
2714 !port
->bh_requested
) {
2715 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2716 printk("%s(%d):%s queueing bh task.\n",
2717 __FILE__
,__LINE__
,port
->device_name
);
2718 schedule_work(&port
->task
);
2719 port
->bh_requested
= 1;
2723 spin_unlock(&info
->lock
);
2725 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2726 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2727 __FILE__
,__LINE__
,irq
);
2731 /* Initialize and start device.
2733 static int startup(SLMP_INFO
* info
)
2735 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2736 printk("%s(%d):%s tx_releaseup()\n",__FILE__
,__LINE__
,info
->device_name
);
2738 if (info
->flags
& ASYNC_INITIALIZED
)
2741 if (!info
->tx_buf
) {
2742 info
->tx_buf
= (unsigned char *)kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2743 if (!info
->tx_buf
) {
2744 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
2745 __FILE__
,__LINE__
,info
->device_name
);
2750 info
->pending_bh
= 0;
2752 memset(&info
->icount
, 0, sizeof(info
->icount
));
2754 /* program hardware for current parameters */
2757 change_params(info
);
2759 info
->status_timer
.expires
= jiffies
+ msecs_to_jiffies(10);
2760 add_timer(&info
->status_timer
);
2763 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2765 info
->flags
|= ASYNC_INITIALIZED
;
2770 /* Called by close() and hangup() to shutdown hardware
2772 static void shutdown(SLMP_INFO
* info
)
2774 unsigned long flags
;
2776 if (!(info
->flags
& ASYNC_INITIALIZED
))
2779 if (debug_level
>= DEBUG_LEVEL_INFO
)
2780 printk("%s(%d):%s synclinkmp_shutdown()\n",
2781 __FILE__
,__LINE__
, info
->device_name
);
2783 /* clear status wait queue because status changes */
2784 /* can't happen after shutting down the hardware */
2785 wake_up_interruptible(&info
->status_event_wait_q
);
2786 wake_up_interruptible(&info
->event_wait_q
);
2788 del_timer(&info
->tx_timer
);
2789 del_timer(&info
->status_timer
);
2791 kfree(info
->tx_buf
);
2792 info
->tx_buf
= NULL
;
2794 spin_lock_irqsave(&info
->lock
,flags
);
2798 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
2799 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2803 spin_unlock_irqrestore(&info
->lock
,flags
);
2806 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2808 info
->flags
&= ~ASYNC_INITIALIZED
;
2811 static void program_hw(SLMP_INFO
*info
)
2813 unsigned long flags
;
2815 spin_lock_irqsave(&info
->lock
,flags
);
2820 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2822 if (info
->params
.mode
== MGSL_MODE_HDLC
|| info
->netcount
)
2829 info
->dcd_chkcount
= 0;
2830 info
->cts_chkcount
= 0;
2831 info
->ri_chkcount
= 0;
2832 info
->dsr_chkcount
= 0;
2834 info
->ie1_value
|= (CDCD
|CCTS
);
2835 write_reg(info
, IE1
, info
->ie1_value
);
2839 if (info
->netcount
|| (info
->tty
&& info
->tty
->termios
->c_cflag
& CREAD
) )
2842 spin_unlock_irqrestore(&info
->lock
,flags
);
2845 /* Reconfigure adapter based on new parameters
2847 static void change_params(SLMP_INFO
*info
)
2852 if (!info
->tty
|| !info
->tty
->termios
)
2855 if (debug_level
>= DEBUG_LEVEL_INFO
)
2856 printk("%s(%d):%s change_params()\n",
2857 __FILE__
,__LINE__
, info
->device_name
);
2859 cflag
= info
->tty
->termios
->c_cflag
;
2861 /* if B0 rate (hangup) specified then negate DTR and RTS */
2862 /* otherwise assert DTR and RTS */
2864 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2866 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2868 /* byte size and parity */
2870 switch (cflag
& CSIZE
) {
2871 case CS5
: info
->params
.data_bits
= 5; break;
2872 case CS6
: info
->params
.data_bits
= 6; break;
2873 case CS7
: info
->params
.data_bits
= 7; break;
2874 case CS8
: info
->params
.data_bits
= 8; break;
2875 /* Never happens, but GCC is too dumb to figure it out */
2876 default: info
->params
.data_bits
= 7; break;
2880 info
->params
.stop_bits
= 2;
2882 info
->params
.stop_bits
= 1;
2884 info
->params
.parity
= ASYNC_PARITY_NONE
;
2885 if (cflag
& PARENB
) {
2887 info
->params
.parity
= ASYNC_PARITY_ODD
;
2889 info
->params
.parity
= ASYNC_PARITY_EVEN
;
2892 info
->params
.parity
= ASYNC_PARITY_SPACE
;
2896 /* calculate number of jiffies to transmit a full
2897 * FIFO (32 bytes) at specified data rate
2899 bits_per_char
= info
->params
.data_bits
+
2900 info
->params
.stop_bits
+ 1;
2902 /* if port data rate is set to 460800 or less then
2903 * allow tty settings to override, otherwise keep the
2904 * current data rate.
2906 if (info
->params
.data_rate
<= 460800) {
2907 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2910 if ( info
->params
.data_rate
) {
2911 info
->timeout
= (32*HZ
*bits_per_char
) /
2912 info
->params
.data_rate
;
2914 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2916 if (cflag
& CRTSCTS
)
2917 info
->flags
|= ASYNC_CTS_FLOW
;
2919 info
->flags
&= ~ASYNC_CTS_FLOW
;
2922 info
->flags
&= ~ASYNC_CHECK_CD
;
2924 info
->flags
|= ASYNC_CHECK_CD
;
2926 /* process tty input control flags */
2928 info
->read_status_mask2
= OVRN
;
2929 if (I_INPCK(info
->tty
))
2930 info
->read_status_mask2
|= PE
| FRME
;
2931 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2932 info
->read_status_mask1
|= BRKD
;
2933 if (I_IGNPAR(info
->tty
))
2934 info
->ignore_status_mask2
|= PE
| FRME
;
2935 if (I_IGNBRK(info
->tty
)) {
2936 info
->ignore_status_mask1
|= BRKD
;
2937 /* If ignoring parity and break indicators, ignore
2938 * overruns too. (For real raw support).
2940 if (I_IGNPAR(info
->tty
))
2941 info
->ignore_status_mask2
|= OVRN
;
2947 static int get_stats(SLMP_INFO
* info
, struct mgsl_icount __user
*user_icount
)
2951 if (debug_level
>= DEBUG_LEVEL_INFO
)
2952 printk("%s(%d):%s get_params()\n",
2953 __FILE__
,__LINE__
, info
->device_name
);
2956 memset(&info
->icount
, 0, sizeof(info
->icount
));
2958 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2966 static int get_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*user_params
)
2969 if (debug_level
>= DEBUG_LEVEL_INFO
)
2970 printk("%s(%d):%s get_params()\n",
2971 __FILE__
,__LINE__
, info
->device_name
);
2973 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2975 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2976 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2977 __FILE__
,__LINE__
,info
->device_name
);
2984 static int set_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*new_params
)
2986 unsigned long flags
;
2987 MGSL_PARAMS tmp_params
;
2990 if (debug_level
>= DEBUG_LEVEL_INFO
)
2991 printk("%s(%d):%s set_params\n",
2992 __FILE__
,__LINE__
,info
->device_name
);
2993 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2995 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2996 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2997 __FILE__
,__LINE__
,info
->device_name
);
3001 spin_lock_irqsave(&info
->lock
,flags
);
3002 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
3003 spin_unlock_irqrestore(&info
->lock
,flags
);
3005 change_params(info
);
3010 static int get_txidle(SLMP_INFO
* info
, int __user
*idle_mode
)
3014 if (debug_level
>= DEBUG_LEVEL_INFO
)
3015 printk("%s(%d):%s get_txidle()=%d\n",
3016 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
3018 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
3020 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3021 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3022 __FILE__
,__LINE__
,info
->device_name
);
3029 static int set_txidle(SLMP_INFO
* info
, int idle_mode
)
3031 unsigned long flags
;
3033 if (debug_level
>= DEBUG_LEVEL_INFO
)
3034 printk("%s(%d):%s set_txidle(%d)\n",
3035 __FILE__
,__LINE__
,info
->device_name
, idle_mode
);
3037 spin_lock_irqsave(&info
->lock
,flags
);
3038 info
->idle_mode
= idle_mode
;
3039 tx_set_idle( info
);
3040 spin_unlock_irqrestore(&info
->lock
,flags
);
3044 static int tx_enable(SLMP_INFO
* info
, int enable
)
3046 unsigned long flags
;
3048 if (debug_level
>= DEBUG_LEVEL_INFO
)
3049 printk("%s(%d):%s tx_enable(%d)\n",
3050 __FILE__
,__LINE__
,info
->device_name
, enable
);
3052 spin_lock_irqsave(&info
->lock
,flags
);
3054 if ( !info
->tx_enabled
) {
3058 if ( info
->tx_enabled
)
3061 spin_unlock_irqrestore(&info
->lock
,flags
);
3065 /* abort send HDLC frame
3067 static int tx_abort(SLMP_INFO
* info
)
3069 unsigned long flags
;
3071 if (debug_level
>= DEBUG_LEVEL_INFO
)
3072 printk("%s(%d):%s tx_abort()\n",
3073 __FILE__
,__LINE__
,info
->device_name
);
3075 spin_lock_irqsave(&info
->lock
,flags
);
3076 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
3077 info
->ie1_value
&= ~UDRN
;
3078 info
->ie1_value
|= IDLE
;
3079 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
3080 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
3082 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
3083 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
3085 write_reg(info
, CMD
, TXABORT
);
3087 spin_unlock_irqrestore(&info
->lock
,flags
);
3091 static int rx_enable(SLMP_INFO
* info
, int enable
)
3093 unsigned long flags
;
3095 if (debug_level
>= DEBUG_LEVEL_INFO
)
3096 printk("%s(%d):%s rx_enable(%d)\n",
3097 __FILE__
,__LINE__
,info
->device_name
,enable
);
3099 spin_lock_irqsave(&info
->lock
,flags
);
3101 if ( !info
->rx_enabled
)
3104 if ( info
->rx_enabled
)
3107 spin_unlock_irqrestore(&info
->lock
,flags
);
3111 /* wait for specified event to occur
3113 static int wait_mgsl_event(SLMP_INFO
* info
, int __user
*mask_ptr
)
3115 unsigned long flags
;
3118 struct mgsl_icount cprev
, cnow
;
3121 struct _input_signal_events oldsigs
, newsigs
;
3122 DECLARE_WAITQUEUE(wait
, current
);
3124 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
3129 if (debug_level
>= DEBUG_LEVEL_INFO
)
3130 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3131 __FILE__
,__LINE__
,info
->device_name
,mask
);
3133 spin_lock_irqsave(&info
->lock
,flags
);
3135 /* return immediately if state matches requested events */
3137 s
= info
->serial_signals
;
3140 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
3141 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
3142 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
3143 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
3145 spin_unlock_irqrestore(&info
->lock
,flags
);
3149 /* save current irq counts */
3150 cprev
= info
->icount
;
3151 oldsigs
= info
->input_signal_events
;
3153 /* enable hunt and idle irqs if needed */
3154 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
3155 unsigned char oldval
= info
->ie1_value
;
3156 unsigned char newval
= oldval
+
3157 (mask
& MgslEvent_ExitHuntMode
? FLGD
:0) +
3158 (mask
& MgslEvent_IdleReceived
? IDLD
:0);
3159 if ( oldval
!= newval
) {
3160 info
->ie1_value
= newval
;
3161 write_reg(info
, IE1
, info
->ie1_value
);
3165 set_current_state(TASK_INTERRUPTIBLE
);
3166 add_wait_queue(&info
->event_wait_q
, &wait
);
3168 spin_unlock_irqrestore(&info
->lock
,flags
);
3172 if (signal_pending(current
)) {
3177 /* get current irq counts */
3178 spin_lock_irqsave(&info
->lock
,flags
);
3179 cnow
= info
->icount
;
3180 newsigs
= info
->input_signal_events
;
3181 set_current_state(TASK_INTERRUPTIBLE
);
3182 spin_unlock_irqrestore(&info
->lock
,flags
);
3184 /* if no change, wait aborted for some reason */
3185 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
3186 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
3187 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
3188 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
3189 newsigs
.cts_up
== oldsigs
.cts_up
&&
3190 newsigs
.cts_down
== oldsigs
.cts_down
&&
3191 newsigs
.ri_up
== oldsigs
.ri_up
&&
3192 newsigs
.ri_down
== oldsigs
.ri_down
&&
3193 cnow
.exithunt
== cprev
.exithunt
&&
3194 cnow
.rxidle
== cprev
.rxidle
) {
3200 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
3201 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
3202 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
3203 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
3204 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
3205 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
3206 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
3207 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
3208 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
3209 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
3217 remove_wait_queue(&info
->event_wait_q
, &wait
);
3218 set_current_state(TASK_RUNNING
);
3221 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
3222 spin_lock_irqsave(&info
->lock
,flags
);
3223 if (!waitqueue_active(&info
->event_wait_q
)) {
3224 /* disable enable exit hunt mode/idle rcvd IRQs */
3225 info
->ie1_value
&= ~(FLGD
|IDLD
);
3226 write_reg(info
, IE1
, info
->ie1_value
);
3228 spin_unlock_irqrestore(&info
->lock
,flags
);
3232 PUT_USER(rc
, events
, mask_ptr
);
3237 static int modem_input_wait(SLMP_INFO
*info
,int arg
)
3239 unsigned long flags
;
3241 struct mgsl_icount cprev
, cnow
;
3242 DECLARE_WAITQUEUE(wait
, current
);
3244 /* save current irq counts */
3245 spin_lock_irqsave(&info
->lock
,flags
);
3246 cprev
= info
->icount
;
3247 add_wait_queue(&info
->status_event_wait_q
, &wait
);
3248 set_current_state(TASK_INTERRUPTIBLE
);
3249 spin_unlock_irqrestore(&info
->lock
,flags
);
3253 if (signal_pending(current
)) {
3258 /* get new irq counts */
3259 spin_lock_irqsave(&info
->lock
,flags
);
3260 cnow
= info
->icount
;
3261 set_current_state(TASK_INTERRUPTIBLE
);
3262 spin_unlock_irqrestore(&info
->lock
,flags
);
3264 /* if no change, wait aborted for some reason */
3265 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
3266 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
3271 /* check for change in caller specified modem input */
3272 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
3273 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
3274 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
3275 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
3282 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
3283 set_current_state(TASK_RUNNING
);
3287 /* return the state of the serial control and status signals
3289 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
3291 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3292 unsigned int result
;
3293 unsigned long flags
;
3295 spin_lock_irqsave(&info
->lock
,flags
);
3297 spin_unlock_irqrestore(&info
->lock
,flags
);
3299 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
3300 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
3301 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
3302 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
3303 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
3304 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
3306 if (debug_level
>= DEBUG_LEVEL_INFO
)
3307 printk("%s(%d):%s tiocmget() value=%08X\n",
3308 __FILE__
,__LINE__
, info
->device_name
, result
);
3312 /* set modem control signals (DTR/RTS)
3314 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
3315 unsigned int set
, unsigned int clear
)
3317 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3318 unsigned long flags
;
3320 if (debug_level
>= DEBUG_LEVEL_INFO
)
3321 printk("%s(%d):%s tiocmset(%x,%x)\n",
3322 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
3324 if (set
& TIOCM_RTS
)
3325 info
->serial_signals
|= SerialSignal_RTS
;
3326 if (set
& TIOCM_DTR
)
3327 info
->serial_signals
|= SerialSignal_DTR
;
3328 if (clear
& TIOCM_RTS
)
3329 info
->serial_signals
&= ~SerialSignal_RTS
;
3330 if (clear
& TIOCM_DTR
)
3331 info
->serial_signals
&= ~SerialSignal_DTR
;
3333 spin_lock_irqsave(&info
->lock
,flags
);
3335 spin_unlock_irqrestore(&info
->lock
,flags
);
3342 /* Block the current process until the specified port is ready to open.
3344 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
3347 DECLARE_WAITQUEUE(wait
, current
);
3349 int do_clocal
= 0, extra_count
= 0;
3350 unsigned long flags
;
3352 if (debug_level
>= DEBUG_LEVEL_INFO
)
3353 printk("%s(%d):%s block_til_ready()\n",
3354 __FILE__
,__LINE__
, tty
->driver
->name
);
3356 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3357 /* nonblock mode is set or port is not enabled */
3358 /* just verify that callout device is not active */
3359 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3363 if (tty
->termios
->c_cflag
& CLOCAL
)
3366 /* Wait for carrier detect and the line to become
3367 * free (i.e., not in use by the callout). While we are in
3368 * this loop, info->count is dropped by one, so that
3369 * close() knows when to free things. We restore it upon
3370 * exit, either normal or abnormal.
3374 add_wait_queue(&info
->open_wait
, &wait
);
3376 if (debug_level
>= DEBUG_LEVEL_INFO
)
3377 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3378 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3380 spin_lock_irqsave(&info
->lock
, flags
);
3381 if (!tty_hung_up_p(filp
)) {
3385 spin_unlock_irqrestore(&info
->lock
, flags
);
3386 info
->blocked_open
++;
3389 if ((tty
->termios
->c_cflag
& CBAUD
)) {
3390 spin_lock_irqsave(&info
->lock
,flags
);
3391 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3393 spin_unlock_irqrestore(&info
->lock
,flags
);
3396 set_current_state(TASK_INTERRUPTIBLE
);
3398 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3399 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3400 -EAGAIN
: -ERESTARTSYS
;
3404 spin_lock_irqsave(&info
->lock
,flags
);
3406 spin_unlock_irqrestore(&info
->lock
,flags
);
3408 if (!(info
->flags
& ASYNC_CLOSING
) &&
3409 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3413 if (signal_pending(current
)) {
3414 retval
= -ERESTARTSYS
;
3418 if (debug_level
>= DEBUG_LEVEL_INFO
)
3419 printk("%s(%d):%s block_til_ready() count=%d\n",
3420 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3425 set_current_state(TASK_RUNNING
);
3426 remove_wait_queue(&info
->open_wait
, &wait
);
3430 info
->blocked_open
--;
3432 if (debug_level
>= DEBUG_LEVEL_INFO
)
3433 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3434 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3437 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3442 int alloc_dma_bufs(SLMP_INFO
*info
)
3444 unsigned short BuffersPerFrame
;
3445 unsigned short BufferCount
;
3447 // Force allocation to start at 64K boundary for each port.
3448 // This is necessary because *all* buffer descriptors for a port
3449 // *must* be in the same 64K block. All descriptors on a port
3450 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3451 // into the CBP register.
3452 info
->port_array
[0]->last_mem_alloc
= (SCA_MEM_SIZE
/4) * info
->port_num
;
3454 /* Calculate the number of DMA buffers necessary to hold the */
3455 /* largest allowable frame size. Note: If the max frame size is */
3456 /* not an even multiple of the DMA buffer size then we need to */
3457 /* round the buffer count per frame up one. */
3459 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/SCABUFSIZE
);
3460 if ( info
->max_frame_size
% SCABUFSIZE
)
3463 /* calculate total number of data buffers (SCABUFSIZE) possible
3464 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3465 * for the descriptor list (BUFFERLISTSIZE).
3467 BufferCount
= (SCA_MEM_SIZE
/4 - BUFFERLISTSIZE
)/SCABUFSIZE
;
3469 /* limit number of buffers to maximum amount of descriptors */
3470 if (BufferCount
> BUFFERLISTSIZE
/sizeof(SCADESC
))
3471 BufferCount
= BUFFERLISTSIZE
/sizeof(SCADESC
);
3473 /* use enough buffers to transmit one max size frame */
3474 info
->tx_buf_count
= BuffersPerFrame
+ 1;
3476 /* never use more than half the available buffers for transmit */
3477 if (info
->tx_buf_count
> (BufferCount
/2))
3478 info
->tx_buf_count
= BufferCount
/2;
3480 if (info
->tx_buf_count
> SCAMAXDESC
)
3481 info
->tx_buf_count
= SCAMAXDESC
;
3483 /* use remaining buffers for receive */
3484 info
->rx_buf_count
= BufferCount
- info
->tx_buf_count
;
3486 if (info
->rx_buf_count
> SCAMAXDESC
)
3487 info
->rx_buf_count
= SCAMAXDESC
;
3489 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3490 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3491 __FILE__
,__LINE__
, info
->device_name
,
3492 info
->tx_buf_count
,info
->rx_buf_count
);
3494 if ( alloc_buf_list( info
) < 0 ||
3495 alloc_frame_bufs(info
,
3497 info
->rx_buf_list_ex
,
3498 info
->rx_buf_count
) < 0 ||
3499 alloc_frame_bufs(info
,
3501 info
->tx_buf_list_ex
,
3502 info
->tx_buf_count
) < 0 ||
3503 alloc_tmp_rx_buf(info
) < 0 ) {
3504 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3505 __FILE__
,__LINE__
, info
->device_name
);
3509 rx_reset_buffers( info
);
3514 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3516 int alloc_buf_list(SLMP_INFO
*info
)
3520 /* build list in adapter shared memory */
3521 info
->buffer_list
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3522 info
->buffer_list_phys
= info
->port_array
[0]->last_mem_alloc
;
3523 info
->port_array
[0]->last_mem_alloc
+= BUFFERLISTSIZE
;
3525 memset(info
->buffer_list
, 0, BUFFERLISTSIZE
);
3527 /* Save virtual address pointers to the receive and */
3528 /* transmit buffer lists. (Receive 1st). These pointers will */
3529 /* be used by the processor to access the lists. */
3530 info
->rx_buf_list
= (SCADESC
*)info
->buffer_list
;
3532 info
->tx_buf_list
= (SCADESC
*)info
->buffer_list
;
3533 info
->tx_buf_list
+= info
->rx_buf_count
;
3535 /* Build links for circular buffer entry lists (tx and rx)
3537 * Note: links are physical addresses read by the SCA device
3538 * to determine the next buffer entry to use.
3541 for ( i
= 0; i
< info
->rx_buf_count
; i
++ ) {
3542 /* calculate and store physical address of this buffer entry */
3543 info
->rx_buf_list_ex
[i
].phys_entry
=
3544 info
->buffer_list_phys
+ (i
* sizeof(SCABUFSIZE
));
3546 /* calculate and store physical address of */
3547 /* next entry in cirular list of entries */
3548 info
->rx_buf_list
[i
].next
= info
->buffer_list_phys
;
3549 if ( i
< info
->rx_buf_count
- 1 )
3550 info
->rx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3552 info
->rx_buf_list
[i
].length
= SCABUFSIZE
;
3555 for ( i
= 0; i
< info
->tx_buf_count
; i
++ ) {
3556 /* calculate and store physical address of this buffer entry */
3557 info
->tx_buf_list_ex
[i
].phys_entry
= info
->buffer_list_phys
+
3558 ((info
->rx_buf_count
+ i
) * sizeof(SCADESC
));
3560 /* calculate and store physical address of */
3561 /* next entry in cirular list of entries */
3563 info
->tx_buf_list
[i
].next
= info
->buffer_list_phys
+
3564 info
->rx_buf_count
* sizeof(SCADESC
);
3566 if ( i
< info
->tx_buf_count
- 1 )
3567 info
->tx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3573 /* Allocate the frame DMA buffers used by the specified buffer list.
3575 int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*buf_list
,SCADESC_EX
*buf_list_ex
,int count
)
3578 unsigned long phys_addr
;
3580 for ( i
= 0; i
< count
; i
++ ) {
3581 buf_list_ex
[i
].virt_addr
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3582 phys_addr
= info
->port_array
[0]->last_mem_alloc
;
3583 info
->port_array
[0]->last_mem_alloc
+= SCABUFSIZE
;
3585 buf_list
[i
].buf_ptr
= (unsigned short)phys_addr
;
3586 buf_list
[i
].buf_base
= (unsigned char)(phys_addr
>> 16);
3592 void free_dma_bufs(SLMP_INFO
*info
)
3594 info
->buffer_list
= NULL
;
3595 info
->rx_buf_list
= NULL
;
3596 info
->tx_buf_list
= NULL
;
3599 /* allocate buffer large enough to hold max_frame_size.
3600 * This buffer is used to pass an assembled frame to the line discipline.
3602 int alloc_tmp_rx_buf(SLMP_INFO
*info
)
3604 info
->tmp_rx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3605 if (info
->tmp_rx_buf
== NULL
)
3610 void free_tmp_rx_buf(SLMP_INFO
*info
)
3612 kfree(info
->tmp_rx_buf
);
3613 info
->tmp_rx_buf
= NULL
;
3616 int claim_resources(SLMP_INFO
*info
)
3618 if (request_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
,"synclinkmp") == NULL
) {
3619 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3620 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3621 info
->init_error
= DiagStatus_AddressConflict
;
3625 info
->shared_mem_requested
= 1;
3627 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclinkmp") == NULL
) {
3628 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3629 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3630 info
->init_error
= DiagStatus_AddressConflict
;
3634 info
->lcr_mem_requested
= 1;
3636 if (request_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
,"synclinkmp") == NULL
) {
3637 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3638 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3639 info
->init_error
= DiagStatus_AddressConflict
;
3643 info
->sca_base_requested
= 1;
3645 if (request_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
,"synclinkmp") == NULL
) {
3646 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3647 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3648 info
->init_error
= DiagStatus_AddressConflict
;
3652 info
->sca_statctrl_requested
= 1;
3654 info
->memory_base
= ioremap(info
->phys_memory_base
,SCA_MEM_SIZE
);
3655 if (!info
->memory_base
) {
3656 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3657 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3658 info
->init_error
= DiagStatus_CantAssignPciResources
;
3662 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
);
3663 if (!info
->lcr_base
) {
3664 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3665 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3666 info
->init_error
= DiagStatus_CantAssignPciResources
;
3669 info
->lcr_base
+= info
->lcr_offset
;
3671 info
->sca_base
= ioremap(info
->phys_sca_base
,PAGE_SIZE
);
3672 if (!info
->sca_base
) {
3673 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3674 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3675 info
->init_error
= DiagStatus_CantAssignPciResources
;
3678 info
->sca_base
+= info
->sca_offset
;
3680 info
->statctrl_base
= ioremap(info
->phys_statctrl_base
,PAGE_SIZE
);
3681 if (!info
->statctrl_base
) {
3682 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3683 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3684 info
->init_error
= DiagStatus_CantAssignPciResources
;
3687 info
->statctrl_base
+= info
->statctrl_offset
;
3689 if ( !memory_test(info
) ) {
3690 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3691 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3692 info
->init_error
= DiagStatus_MemoryError
;
3699 release_resources( info
);
3703 void release_resources(SLMP_INFO
*info
)
3705 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3706 printk( "%s(%d):%s release_resources() entry\n",
3707 __FILE__
,__LINE__
,info
->device_name
);
3709 if ( info
->irq_requested
) {
3710 free_irq(info
->irq_level
, info
);
3711 info
->irq_requested
= 0;
3714 if ( info
->shared_mem_requested
) {
3715 release_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
);
3716 info
->shared_mem_requested
= 0;
3718 if ( info
->lcr_mem_requested
) {
3719 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
3720 info
->lcr_mem_requested
= 0;
3722 if ( info
->sca_base_requested
) {
3723 release_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
);
3724 info
->sca_base_requested
= 0;
3726 if ( info
->sca_statctrl_requested
) {
3727 release_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
);
3728 info
->sca_statctrl_requested
= 0;
3731 if (info
->memory_base
){
3732 iounmap(info
->memory_base
);
3733 info
->memory_base
= NULL
;
3736 if (info
->sca_base
) {
3737 iounmap(info
->sca_base
- info
->sca_offset
);
3738 info
->sca_base
=NULL
;
3741 if (info
->statctrl_base
) {
3742 iounmap(info
->statctrl_base
- info
->statctrl_offset
);
3743 info
->statctrl_base
=NULL
;
3746 if (info
->lcr_base
){
3747 iounmap(info
->lcr_base
- info
->lcr_offset
);
3748 info
->lcr_base
= NULL
;
3751 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3752 printk( "%s(%d):%s release_resources() exit\n",
3753 __FILE__
,__LINE__
,info
->device_name
);
3756 /* Add the specified device instance data structure to the
3757 * global linked list of devices and increment the device count.
3759 void add_device(SLMP_INFO
*info
)
3761 info
->next_device
= NULL
;
3762 info
->line
= synclinkmp_device_count
;
3763 sprintf(info
->device_name
,"ttySLM%dp%d",info
->adapter_num
,info
->port_num
);
3765 if (info
->line
< MAX_DEVICES
) {
3766 if (maxframe
[info
->line
])
3767 info
->max_frame_size
= maxframe
[info
->line
];
3768 info
->dosyncppp
= dosyncppp
[info
->line
];
3771 synclinkmp_device_count
++;
3773 if ( !synclinkmp_device_list
)
3774 synclinkmp_device_list
= info
;
3776 SLMP_INFO
*current_dev
= synclinkmp_device_list
;
3777 while( current_dev
->next_device
)
3778 current_dev
= current_dev
->next_device
;
3779 current_dev
->next_device
= info
;
3782 if ( info
->max_frame_size
< 4096 )
3783 info
->max_frame_size
= 4096;
3784 else if ( info
->max_frame_size
> 65535 )
3785 info
->max_frame_size
= 65535;
3787 printk( "SyncLink MultiPort %s: "
3788 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3790 info
->phys_sca_base
,
3791 info
->phys_memory_base
,
3792 info
->phys_statctrl_base
,
3793 info
->phys_lcr_base
,
3795 info
->max_frame_size
);
3802 /* Allocate and initialize a device instance structure
3804 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3806 static SLMP_INFO
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3810 info
= (SLMP_INFO
*)kmalloc(sizeof(SLMP_INFO
),
3814 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3815 __FILE__
,__LINE__
, adapter_num
, port_num
);
3817 memset(info
, 0, sizeof(SLMP_INFO
));
3818 info
->magic
= MGSL_MAGIC
;
3819 INIT_WORK(&info
->task
, bh_handler
, info
);
3820 info
->max_frame_size
= 4096;
3821 info
->close_delay
= 5*HZ
/10;
3822 info
->closing_wait
= 30*HZ
;
3823 init_waitqueue_head(&info
->open_wait
);
3824 init_waitqueue_head(&info
->close_wait
);
3825 init_waitqueue_head(&info
->status_event_wait_q
);
3826 init_waitqueue_head(&info
->event_wait_q
);
3827 spin_lock_init(&info
->netlock
);
3828 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3829 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3830 info
->adapter_num
= adapter_num
;
3831 info
->port_num
= port_num
;
3833 /* Copy configuration info to device instance data */
3834 info
->irq_level
= pdev
->irq
;
3835 info
->phys_lcr_base
= pci_resource_start(pdev
,0);
3836 info
->phys_sca_base
= pci_resource_start(pdev
,2);
3837 info
->phys_memory_base
= pci_resource_start(pdev
,3);
3838 info
->phys_statctrl_base
= pci_resource_start(pdev
,4);
3840 /* Because veremap only works on page boundaries we must map
3841 * a larger area than is actually implemented for the LCR
3842 * memory range. We map a full page starting at the page boundary.
3844 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
3845 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
3847 info
->sca_offset
= info
->phys_sca_base
& (PAGE_SIZE
-1);
3848 info
->phys_sca_base
&= ~(PAGE_SIZE
-1);
3850 info
->statctrl_offset
= info
->phys_statctrl_base
& (PAGE_SIZE
-1);
3851 info
->phys_statctrl_base
&= ~(PAGE_SIZE
-1);
3853 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3854 info
->irq_flags
= SA_SHIRQ
;
3856 init_timer(&info
->tx_timer
);
3857 info
->tx_timer
.data
= (unsigned long)info
;
3858 info
->tx_timer
.function
= tx_timeout
;
3860 init_timer(&info
->status_timer
);
3861 info
->status_timer
.data
= (unsigned long)info
;
3862 info
->status_timer
.function
= status_timeout
;
3864 /* Store the PCI9050 misc control register value because a flaw
3865 * in the PCI9050 prevents LCR registers from being read if
3866 * BIOS assigns an LCR base address with bit 7 set.
3868 * Only the misc control register is accessed for which only
3869 * write access is needed, so set an initial value and change
3870 * bits to the device instance data as we write the value
3871 * to the actual misc control register.
3873 info
->misc_ctrl_value
= 0x087e4546;
3875 /* initial port state is unknown - if startup errors
3876 * occur, init_error will be set to indicate the
3877 * problem. Once the port is fully initialized,
3878 * this value will be set to 0 to indicate the
3879 * port is available.
3881 info
->init_error
= -1;
3887 void device_init(int adapter_num
, struct pci_dev
*pdev
)
3889 SLMP_INFO
*port_array
[SCA_MAX_PORTS
];
3892 /* allocate device instances for up to SCA_MAX_PORTS devices */
3893 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3894 port_array
[port
] = alloc_dev(adapter_num
,port
,pdev
);
3895 if( port_array
[port
] == NULL
) {
3896 for ( --port
; port
>= 0; --port
)
3897 kfree(port_array
[port
]);
3902 /* give copy of port_array to all ports and add to device list */
3903 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3904 memcpy(port_array
[port
]->port_array
,port_array
,sizeof(port_array
));
3905 add_device( port_array
[port
] );
3906 spin_lock_init(&port_array
[port
]->lock
);
3909 /* Allocate and claim adapter resources */
3910 if ( !claim_resources(port_array
[0]) ) {
3912 alloc_dma_bufs(port_array
[0]);
3914 /* copy resource information from first port to others */
3915 for ( port
= 1; port
< SCA_MAX_PORTS
; ++port
) {
3916 port_array
[port
]->lock
= port_array
[0]->lock
;
3917 port_array
[port
]->irq_level
= port_array
[0]->irq_level
;
3918 port_array
[port
]->memory_base
= port_array
[0]->memory_base
;
3919 port_array
[port
]->sca_base
= port_array
[0]->sca_base
;
3920 port_array
[port
]->statctrl_base
= port_array
[0]->statctrl_base
;
3921 port_array
[port
]->lcr_base
= port_array
[0]->lcr_base
;
3922 alloc_dma_bufs(port_array
[port
]);
3925 if ( request_irq(port_array
[0]->irq_level
,
3926 synclinkmp_interrupt
,
3927 port_array
[0]->irq_flags
,
3928 port_array
[0]->device_name
,
3929 port_array
[0]) < 0 ) {
3930 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3932 port_array
[0]->device_name
,
3933 port_array
[0]->irq_level
);
3936 port_array
[0]->irq_requested
= 1;
3937 adapter_test(port_array
[0]);
3942 static struct tty_operations ops
= {
3946 .put_char
= put_char
,
3947 .flush_chars
= flush_chars
,
3948 .write_room
= write_room
,
3949 .chars_in_buffer
= chars_in_buffer
,
3950 .flush_buffer
= flush_buffer
,
3952 .throttle
= throttle
,
3953 .unthrottle
= unthrottle
,
3954 .send_xchar
= send_xchar
,
3955 .break_ctl
= set_break
,
3956 .wait_until_sent
= wait_until_sent
,
3957 .read_proc
= read_proc
,
3958 .set_termios
= set_termios
,
3960 .start
= tx_release
,
3962 .tiocmget
= tiocmget
,
3963 .tiocmset
= tiocmset
,
3966 static void synclinkmp_cleanup(void)
3972 printk("Unloading %s %s\n", driver_name
, driver_version
);
3974 if (serial_driver
) {
3975 if ((rc
= tty_unregister_driver(serial_driver
)))
3976 printk("%s(%d) failed to unregister tty driver err=%d\n",
3977 __FILE__
,__LINE__
,rc
);
3978 put_tty_driver(serial_driver
);
3982 info
= synclinkmp_device_list
;
3985 info
= info
->next_device
;
3988 /* release devices */
3989 info
= synclinkmp_device_list
;
3994 free_dma_bufs(info
);
3995 free_tmp_rx_buf(info
);
3996 if ( info
->port_num
== 0 ) {
3998 write_reg(info
, LPR
, 1); /* set low power mode */
3999 release_resources(info
);
4002 info
= info
->next_device
;
4006 pci_unregister_driver(&synclinkmp_pci_driver
);
4009 /* Driver initialization entry point.
4012 static int __init
synclinkmp_init(void)
4016 if (break_on_load
) {
4017 synclinkmp_get_text_ptr();
4021 printk("%s %s\n", driver_name
, driver_version
);
4023 if ((rc
= pci_register_driver(&synclinkmp_pci_driver
)) < 0) {
4024 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4028 serial_driver
= alloc_tty_driver(128);
4029 if (!serial_driver
) {
4034 /* Initialize the tty_driver structure */
4036 serial_driver
->owner
= THIS_MODULE
;
4037 serial_driver
->driver_name
= "synclinkmp";
4038 serial_driver
->name
= "ttySLM";
4039 serial_driver
->major
= ttymajor
;
4040 serial_driver
->minor_start
= 64;
4041 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4042 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4043 serial_driver
->init_termios
= tty_std_termios
;
4044 serial_driver
->init_termios
.c_cflag
=
4045 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4046 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4047 tty_set_operations(serial_driver
, &ops
);
4048 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4049 printk("%s(%d):Couldn't register serial driver\n",
4051 put_tty_driver(serial_driver
);
4052 serial_driver
= NULL
;
4056 printk("%s %s, tty major#%d\n",
4057 driver_name
, driver_version
,
4058 serial_driver
->major
);
4063 synclinkmp_cleanup();
4067 static void __exit
synclinkmp_exit(void)
4069 synclinkmp_cleanup();
4072 module_init(synclinkmp_init
);
4073 module_exit(synclinkmp_exit
);
4075 /* Set the port for internal loopback mode.
4076 * The TxCLK and RxCLK signals are generated from the BRG and
4077 * the TxD is looped back to the RxD internally.
4079 void enable_loopback(SLMP_INFO
*info
, int enable
)
4082 /* MD2 (Mode Register 2)
4083 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4085 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) | (BIT1
+ BIT0
)));
4087 /* degate external TxC clock source */
4088 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4089 write_control_reg(info
);
4091 /* RXS/TXS (Rx/Tx clock source)
4092 * 07 Reserved, must be 0
4093 * 06..04 Clock Source, 100=BRG
4094 * 03..00 Clock Divisor, 0000=1
4096 write_reg(info
, RXS
, 0x40);
4097 write_reg(info
, TXS
, 0x40);
4100 /* MD2 (Mode Register 2)
4101 * 01..00 CNCT<1..0> Channel connection, 0=normal
4103 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) & ~(BIT1
+ BIT0
)));
4105 /* RXS/TXS (Rx/Tx clock source)
4106 * 07 Reserved, must be 0
4107 * 06..04 Clock Source, 000=RxC/TxC Pin
4108 * 03..00 Clock Divisor, 0000=1
4110 write_reg(info
, RXS
, 0x00);
4111 write_reg(info
, TXS
, 0x00);
4114 /* set LinkSpeed if available, otherwise default to 2Mbps */
4115 if (info
->params
.clock_speed
)
4116 set_rate(info
, info
->params
.clock_speed
);
4118 set_rate(info
, 3686400);
4121 /* Set the baud rate register to the desired speed
4123 * data_rate data rate of clock in bits per second
4124 * A data rate of 0 disables the AUX clock.
4126 void set_rate( SLMP_INFO
*info
, u32 data_rate
)
4129 unsigned char BRValue
;
4132 /* fBRG = fCLK/(TMC * 2^BR)
4134 if (data_rate
!= 0) {
4135 Divisor
= 14745600/data_rate
;
4142 if (TMCValue
!= 1 && TMCValue
!= 2) {
4143 /* BRValue of 0 provides 50/50 duty cycle *only* when
4144 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4151 /* while TMCValue is too big for TMC register, divide
4152 * by 2 and increment BR exponent.
4154 for(; TMCValue
> 256 && BRValue
< 10; BRValue
++)
4157 write_reg(info
, TXS
,
4158 (unsigned char)((read_reg(info
, TXS
) & 0xf0) | BRValue
));
4159 write_reg(info
, RXS
,
4160 (unsigned char)((read_reg(info
, RXS
) & 0xf0) | BRValue
));
4161 write_reg(info
, TMC
, (unsigned char)TMCValue
);
4164 write_reg(info
, TXS
,0);
4165 write_reg(info
, RXS
,0);
4166 write_reg(info
, TMC
, 0);
4172 void rx_stop(SLMP_INFO
*info
)
4174 if (debug_level
>= DEBUG_LEVEL_ISR
)
4175 printk("%s(%d):%s rx_stop()\n",
4176 __FILE__
,__LINE__
, info
->device_name
);
4178 write_reg(info
, CMD
, RXRESET
);
4180 info
->ie0_value
&= ~RXRDYE
;
4181 write_reg(info
, IE0
, info
->ie0_value
); /* disable Rx data interrupts */
4183 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4184 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4185 write_reg(info
, RXDMA
+ DIR, 0); /* disable Rx DMA interrupts */
4187 info
->rx_enabled
= 0;
4188 info
->rx_overflow
= 0;
4191 /* enable the receiver
4193 void rx_start(SLMP_INFO
*info
)
4197 if (debug_level
>= DEBUG_LEVEL_ISR
)
4198 printk("%s(%d):%s rx_start()\n",
4199 __FILE__
,__LINE__
, info
->device_name
);
4201 write_reg(info
, CMD
, RXRESET
);
4203 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
4204 /* HDLC, disabe IRQ on rxdata */
4205 info
->ie0_value
&= ~RXRDYE
;
4206 write_reg(info
, IE0
, info
->ie0_value
);
4208 /* Reset all Rx DMA buffers and program rx dma */
4209 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4210 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4212 for (i
= 0; i
< info
->rx_buf_count
; i
++) {
4213 info
->rx_buf_list
[i
].status
= 0xff;
4215 // throttle to 4 shared memory writes at a time to prevent
4216 // hogging local bus (keep latency time for DMA requests low).
4218 read_status_reg(info
);
4220 info
->current_rx_buf
= 0;
4222 /* set current/1st descriptor address */
4223 write_reg16(info
, RXDMA
+ CDA
,
4224 info
->rx_buf_list_ex
[0].phys_entry
);
4226 /* set new last rx descriptor address */
4227 write_reg16(info
, RXDMA
+ EDA
,
4228 info
->rx_buf_list_ex
[info
->rx_buf_count
- 1].phys_entry
);
4230 /* set buffer length (shared by all rx dma data buffers) */
4231 write_reg16(info
, RXDMA
+ BFL
, SCABUFSIZE
);
4233 write_reg(info
, RXDMA
+ DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4234 write_reg(info
, RXDMA
+ DSR
, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4236 /* async, enable IRQ on rxdata */
4237 info
->ie0_value
|= RXRDYE
;
4238 write_reg(info
, IE0
, info
->ie0_value
);
4241 write_reg(info
, CMD
, RXENABLE
);
4243 info
->rx_overflow
= FALSE
;
4244 info
->rx_enabled
= 1;
4247 /* Enable the transmitter and send a transmit frame if
4248 * one is loaded in the DMA buffers.
4250 void tx_start(SLMP_INFO
*info
)
4252 if (debug_level
>= DEBUG_LEVEL_ISR
)
4253 printk("%s(%d):%s tx_start() tx_count=%d\n",
4254 __FILE__
,__LINE__
, info
->device_name
,info
->tx_count
);
4256 if (!info
->tx_enabled
) {
4257 write_reg(info
, CMD
, TXRESET
);
4258 write_reg(info
, CMD
, TXENABLE
);
4259 info
->tx_enabled
= TRUE
;
4262 if ( info
->tx_count
) {
4264 /* If auto RTS enabled and RTS is inactive, then assert */
4265 /* RTS and set a flag indicating that the driver should */
4266 /* negate RTS when the transmission completes. */
4268 info
->drop_rts_on_tx_done
= 0;
4270 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
4272 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
4273 get_signals( info
);
4274 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
4275 info
->serial_signals
|= SerialSignal_RTS
;
4276 set_signals( info
);
4277 info
->drop_rts_on_tx_done
= 1;
4281 write_reg16(info
, TRC0
,
4282 (unsigned short)(((tx_negate_fifo_level
-1)<<8) + tx_active_fifo_level
));
4284 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4285 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4287 /* set TX CDA (current descriptor address) */
4288 write_reg16(info
, TXDMA
+ CDA
,
4289 info
->tx_buf_list_ex
[0].phys_entry
);
4291 /* set TX EDA (last descriptor address) */
4292 write_reg16(info
, TXDMA
+ EDA
,
4293 info
->tx_buf_list_ex
[info
->last_tx_buf
].phys_entry
);
4295 /* enable underrun IRQ */
4296 info
->ie1_value
&= ~IDLE
;
4297 info
->ie1_value
|= UDRN
;
4298 write_reg(info
, IE1
, info
->ie1_value
);
4299 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
));
4301 write_reg(info
, TXDMA
+ DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4302 write_reg(info
, TXDMA
+ DSR
, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4304 info
->tx_timer
.expires
= jiffies
+ msecs_to_jiffies(5000);
4305 add_timer(&info
->tx_timer
);
4309 /* async, enable IRQ on txdata */
4310 info
->ie0_value
|= TXRDYE
;
4311 write_reg(info
, IE0
, info
->ie0_value
);
4314 info
->tx_active
= 1;
4318 /* stop the transmitter and DMA
4320 void tx_stop( SLMP_INFO
*info
)
4322 if (debug_level
>= DEBUG_LEVEL_ISR
)
4323 printk("%s(%d):%s tx_stop()\n",
4324 __FILE__
,__LINE__
, info
->device_name
);
4326 del_timer(&info
->tx_timer
);
4328 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4329 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4331 write_reg(info
, CMD
, TXRESET
);
4333 info
->ie1_value
&= ~(UDRN
+ IDLE
);
4334 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
4335 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
4337 info
->ie0_value
&= ~TXRDYE
;
4338 write_reg(info
, IE0
, info
->ie0_value
); /* disable tx data interrupts */
4340 info
->tx_enabled
= 0;
4341 info
->tx_active
= 0;
4344 /* Fill the transmit FIFO until the FIFO is full or
4345 * there is no more data to load.
4347 void tx_load_fifo(SLMP_INFO
*info
)
4351 /* do nothing is now tx data available and no XON/XOFF pending */
4353 if ( !info
->tx_count
&& !info
->x_char
)
4356 /* load the Transmit FIFO until FIFOs full or all data sent */
4358 while( info
->tx_count
&& (read_reg(info
,SR0
) & BIT1
) ) {
4360 /* there is more space in the transmit FIFO and */
4361 /* there is more data in transmit buffer */
4363 if ( (info
->tx_count
> 1) && !info
->x_char
) {
4365 TwoBytes
[0] = info
->tx_buf
[info
->tx_get
++];
4366 if (info
->tx_get
>= info
->max_frame_size
)
4367 info
->tx_get
-= info
->max_frame_size
;
4368 TwoBytes
[1] = info
->tx_buf
[info
->tx_get
++];
4369 if (info
->tx_get
>= info
->max_frame_size
)
4370 info
->tx_get
-= info
->max_frame_size
;
4372 write_reg16(info
, TRB
, *((u16
*)TwoBytes
));
4374 info
->tx_count
-= 2;
4375 info
->icount
.tx
+= 2;
4377 /* only 1 byte left to transmit or 1 FIFO slot left */
4380 /* transmit pending high priority char */
4381 write_reg(info
, TRB
, info
->x_char
);
4384 write_reg(info
, TRB
, info
->tx_buf
[info
->tx_get
++]);
4385 if (info
->tx_get
>= info
->max_frame_size
)
4386 info
->tx_get
-= info
->max_frame_size
;
4394 /* Reset a port to a known state
4396 void reset_port(SLMP_INFO
*info
)
4398 if (info
->sca_base
) {
4403 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
4406 /* disable all port interrupts */
4407 info
->ie0_value
= 0;
4408 info
->ie1_value
= 0;
4409 info
->ie2_value
= 0;
4410 write_reg(info
, IE0
, info
->ie0_value
);
4411 write_reg(info
, IE1
, info
->ie1_value
);
4412 write_reg(info
, IE2
, info
->ie2_value
);
4414 write_reg(info
, CMD
, CHRESET
);
4418 /* Reset all the ports to a known state.
4420 void reset_adapter(SLMP_INFO
*info
)
4424 for ( i
=0; i
< SCA_MAX_PORTS
; ++i
) {
4425 if (info
->port_array
[i
])
4426 reset_port(info
->port_array
[i
]);
4430 /* Program port for asynchronous communications.
4432 void async_mode(SLMP_INFO
*info
)
4435 unsigned char RegValue
;
4440 /* MD0, Mode Register 0
4442 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4443 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4444 * 03 Reserved, must be 0
4445 * 02 CRCCC, CRC Calculation, 0=disabled
4446 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4451 if (info
->params
.stop_bits
!= 1)
4453 write_reg(info
, MD0
, RegValue
);
4455 /* MD1, Mode Register 1
4457 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4458 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4459 * 03..02 RXCHR<1..0>, rx char size
4460 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4465 switch (info
->params
.data_bits
) {
4466 case 7: RegValue
|= BIT4
+ BIT2
; break;
4467 case 6: RegValue
|= BIT5
+ BIT3
; break;
4468 case 5: RegValue
|= BIT5
+ BIT4
+ BIT3
+ BIT2
; break;
4470 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4472 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4475 write_reg(info
, MD1
, RegValue
);
4477 /* MD2, Mode Register 2
4479 * 07..02 Reserved, must be 0
4480 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4485 if (info
->params
.loopback
)
4486 RegValue
|= (BIT1
+ BIT0
);
4487 write_reg(info
, MD2
, RegValue
);
4489 /* RXS, Receive clock source
4491 * 07 Reserved, must be 0
4492 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4493 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4496 write_reg(info
, RXS
, RegValue
);
4498 /* TXS, Transmit clock source
4500 * 07 Reserved, must be 0
4501 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4502 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4505 write_reg(info
, TXS
, RegValue
);
4509 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4511 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4512 write_control_reg(info
);
4516 /* RRC Receive Ready Control 0
4518 * 07..05 Reserved, must be 0
4519 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4521 write_reg(info
, RRC
, 0x00);
4523 /* TRC0 Transmit Ready Control 0
4525 * 07..05 Reserved, must be 0
4526 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4528 write_reg(info
, TRC0
, 0x10);
4530 /* TRC1 Transmit Ready Control 1
4532 * 07..05 Reserved, must be 0
4533 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4535 write_reg(info
, TRC1
, 0x1e);
4537 /* CTL, MSCI control register
4539 * 07..06 Reserved, set to 0
4540 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4541 * 04 IDLC, idle control, 0=mark 1=idle register
4542 * 03 BRK, break, 0=off 1 =on (async)
4543 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4544 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4545 * 00 RTS, RTS output control, 0=active 1=inactive
4550 if (!(info
->serial_signals
& SerialSignal_RTS
))
4552 write_reg(info
, CTL
, RegValue
);
4554 /* enable status interrupts */
4555 info
->ie0_value
|= TXINTE
+ RXINTE
;
4556 write_reg(info
, IE0
, info
->ie0_value
);
4558 /* enable break detect interrupt */
4559 info
->ie1_value
= BRKD
;
4560 write_reg(info
, IE1
, info
->ie1_value
);
4562 /* enable rx overrun interrupt */
4563 info
->ie2_value
= OVRN
;
4564 write_reg(info
, IE2
, info
->ie2_value
);
4566 set_rate( info
, info
->params
.data_rate
* 16 );
4569 /* Program the SCA for HDLC communications.
4571 void hdlc_mode(SLMP_INFO
*info
)
4573 unsigned char RegValue
;
4576 // Can't use DPLL because SCA outputs recovered clock on RxC when
4577 // DPLL mode selected. This causes output contention with RxC receiver.
4578 // Use of DPLL would require external hardware to disable RxC receiver
4579 // when DPLL mode selected.
4580 info
->params
.flags
&= ~(HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
);
4582 /* disable DMA interrupts */
4583 write_reg(info
, TXDMA
+ DIR, 0);
4584 write_reg(info
, RXDMA
+ DIR, 0);
4586 /* MD0, Mode Register 0
4588 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4589 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4590 * 03 Reserved, must be 0
4591 * 02 CRCCC, CRC Calculation, 1=enabled
4592 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4593 * 00 CRC0, CRC initial value, 1 = all 1s
4598 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4600 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4602 if (info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4603 RegValue
|= BIT2
+ BIT1
;
4604 write_reg(info
, MD0
, RegValue
);
4606 /* MD1, Mode Register 1
4608 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4609 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4610 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4611 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4616 write_reg(info
, MD1
, RegValue
);
4618 /* MD2, Mode Register 2
4620 * 07 NRZFM, 0=NRZ, 1=FM
4621 * 06..05 CODE<1..0> Encoding, 00=NRZ
4622 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4623 * 02 Reserved, must be 0
4624 * 01..00 CNCT<1..0> Channel connection, 0=normal
4629 switch(info
->params
.encoding
) {
4630 case HDLC_ENCODING_NRZI
: RegValue
|= BIT5
; break;
4631 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT7
+ BIT5
; break; /* aka FM1 */
4632 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT7
+ BIT6
; break; /* aka FM0 */
4633 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT7
; break; /* aka Manchester */
4635 case HDLC_ENCODING_NRZB
: /* not supported */
4636 case HDLC_ENCODING_NRZI_MARK
: /* not supported */
4637 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: /* not supported */
4640 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4643 } else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4649 write_reg(info
, MD2
, RegValue
);
4652 /* RXS, Receive clock source
4654 * 07 Reserved, must be 0
4655 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4656 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4659 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4661 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4662 RegValue
|= BIT6
+ BIT5
;
4663 write_reg(info
, RXS
, RegValue
);
4665 /* TXS, Transmit clock source
4667 * 07 Reserved, must be 0
4668 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4669 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4672 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4674 if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4675 RegValue
|= BIT6
+ BIT5
;
4676 write_reg(info
, TXS
, RegValue
);
4678 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4679 set_rate(info
, info
->params
.clock_speed
* DpllDivisor
);
4681 set_rate(info
, info
->params
.clock_speed
);
4683 /* GPDATA (General Purpose I/O Data Register)
4685 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4687 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4688 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4690 info
->port_array
[0]->ctrlreg_value
&= ~(BIT0
<< (info
->port_num
* 2));
4691 write_control_reg(info
);
4693 /* RRC Receive Ready Control 0
4695 * 07..05 Reserved, must be 0
4696 * 04..00 RRC<4..0> Rx FIFO trigger active
4698 write_reg(info
, RRC
, rx_active_fifo_level
);
4700 /* TRC0 Transmit Ready Control 0
4702 * 07..05 Reserved, must be 0
4703 * 04..00 TRC<4..0> Tx FIFO trigger active
4705 write_reg(info
, TRC0
, tx_active_fifo_level
);
4707 /* TRC1 Transmit Ready Control 1
4709 * 07..05 Reserved, must be 0
4710 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4712 write_reg(info
, TRC1
, (unsigned char)(tx_negate_fifo_level
- 1));
4714 /* DMR, DMA Mode Register
4716 * 07..05 Reserved, must be 0
4717 * 04 TMOD, Transfer Mode: 1=chained-block
4718 * 03 Reserved, must be 0
4719 * 02 NF, Number of Frames: 1=multi-frame
4720 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4721 * 00 Reserved, must be 0
4725 write_reg(info
, TXDMA
+ DMR
, 0x14);
4726 write_reg(info
, RXDMA
+ DMR
, 0x14);
4728 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4729 write_reg(info
, RXDMA
+ CPB
,
4730 (unsigned char)(info
->buffer_list_phys
>> 16));
4732 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4733 write_reg(info
, TXDMA
+ CPB
,
4734 (unsigned char)(info
->buffer_list_phys
>> 16));
4736 /* enable status interrupts. other code enables/disables
4737 * the individual sources for these two interrupt classes.
4739 info
->ie0_value
|= TXINTE
+ RXINTE
;
4740 write_reg(info
, IE0
, info
->ie0_value
);
4742 /* CTL, MSCI control register
4744 * 07..06 Reserved, set to 0
4745 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4746 * 04 IDLC, idle control, 0=mark 1=idle register
4747 * 03 BRK, break, 0=off 1 =on (async)
4748 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4749 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4750 * 00 RTS, RTS output control, 0=active 1=inactive
4755 if (!(info
->serial_signals
& SerialSignal_RTS
))
4757 write_reg(info
, CTL
, RegValue
);
4759 /* preamble not supported ! */
4765 set_rate(info
, info
->params
.clock_speed
);
4767 if (info
->params
.loopback
)
4768 enable_loopback(info
,1);
4771 /* Set the transmit HDLC idle mode
4773 void tx_set_idle(SLMP_INFO
*info
)
4775 unsigned char RegValue
= 0xff;
4777 /* Map API idle mode to SCA register bits */
4778 switch(info
->idle_mode
) {
4779 case HDLC_TXIDLE_FLAGS
: RegValue
= 0x7e; break;
4780 case HDLC_TXIDLE_ALT_ZEROS_ONES
: RegValue
= 0xaa; break;
4781 case HDLC_TXIDLE_ZEROS
: RegValue
= 0x00; break;
4782 case HDLC_TXIDLE_ONES
: RegValue
= 0xff; break;
4783 case HDLC_TXIDLE_ALT_MARK_SPACE
: RegValue
= 0xaa; break;
4784 case HDLC_TXIDLE_SPACE
: RegValue
= 0x00; break;
4785 case HDLC_TXIDLE_MARK
: RegValue
= 0xff; break;
4788 write_reg(info
, IDL
, RegValue
);
4791 /* Query the adapter for the state of the V24 status (input) signals.
4793 void get_signals(SLMP_INFO
*info
)
4795 u16 status
= read_reg(info
, SR3
);
4796 u16 gpstatus
= read_status_reg(info
);
4799 /* clear all serial signals except DTR and RTS */
4800 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4802 /* set serial signal bits to reflect MISR */
4804 if (!(status
& BIT3
))
4805 info
->serial_signals
|= SerialSignal_CTS
;
4807 if ( !(status
& BIT2
))
4808 info
->serial_signals
|= SerialSignal_DCD
;
4810 testbit
= BIT1
<< (info
->port_num
* 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4811 if (!(gpstatus
& testbit
))
4812 info
->serial_signals
|= SerialSignal_RI
;
4814 testbit
= BIT0
<< (info
->port_num
* 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4815 if (!(gpstatus
& testbit
))
4816 info
->serial_signals
|= SerialSignal_DSR
;
4819 /* Set the state of DTR and RTS based on contents of
4820 * serial_signals member of device context.
4822 void set_signals(SLMP_INFO
*info
)
4824 unsigned char RegValue
;
4827 RegValue
= read_reg(info
, CTL
);
4828 if (info
->serial_signals
& SerialSignal_RTS
)
4832 write_reg(info
, CTL
, RegValue
);
4834 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4835 EnableBit
= BIT1
<< (info
->port_num
*2);
4836 if (info
->serial_signals
& SerialSignal_DTR
)
4837 info
->port_array
[0]->ctrlreg_value
&= ~EnableBit
;
4839 info
->port_array
[0]->ctrlreg_value
|= EnableBit
;
4840 write_control_reg(info
);
4843 /*******************/
4844 /* DMA Buffer Code */
4845 /*******************/
4847 /* Set the count for all receive buffers to SCABUFSIZE
4848 * and set the current buffer to the first buffer. This effectively
4849 * makes all buffers free and discards any data in buffers.
4851 void rx_reset_buffers(SLMP_INFO
*info
)
4853 rx_free_frame_buffers(info
, 0, info
->rx_buf_count
- 1);
4856 /* Free the buffers used by a received frame
4858 * info pointer to device instance data
4859 * first index of 1st receive buffer of frame
4860 * last index of last receive buffer of frame
4862 void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
)
4867 /* reset current buffer for reuse */
4868 info
->rx_buf_list
[first
].status
= 0xff;
4870 if (first
== last
) {
4872 /* set new last rx descriptor address */
4873 write_reg16(info
, RXDMA
+ EDA
, info
->rx_buf_list_ex
[first
].phys_entry
);
4877 if (first
== info
->rx_buf_count
)
4881 /* set current buffer to next buffer after last buffer of frame */
4882 info
->current_rx_buf
= first
;
4885 /* Return a received frame from the receive DMA buffers.
4886 * Only frames received without errors are returned.
4888 * Return Value: 1 if frame returned, otherwise 0
4890 int rx_get_frame(SLMP_INFO
*info
)
4892 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
4893 unsigned short status
;
4894 unsigned int framesize
= 0;
4896 unsigned long flags
;
4897 struct tty_struct
*tty
= info
->tty
;
4898 unsigned char addr_field
= 0xff;
4900 SCADESC_EX
*desc_ex
;
4903 /* assume no frame returned, set zero length */
4908 * current_rx_buf points to the 1st buffer of the next available
4909 * receive frame. To find the last buffer of the frame look for
4910 * a non-zero status field in the buffer entries. (The status
4911 * field is set by the 16C32 after completing a receive frame.
4913 StartIndex
= EndIndex
= info
->current_rx_buf
;
4916 desc
= &info
->rx_buf_list
[EndIndex
];
4917 desc_ex
= &info
->rx_buf_list_ex
[EndIndex
];
4919 if (desc
->status
== 0xff)
4920 goto Cleanup
; /* current desc still in use, no frames available */
4922 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4923 addr_field
= desc_ex
->virt_addr
[0];
4925 framesize
+= desc
->length
;
4927 /* Status != 0 means last buffer of frame */
4932 if (EndIndex
== info
->rx_buf_count
)
4935 if (EndIndex
== info
->current_rx_buf
) {
4936 /* all buffers have been 'used' but none mark */
4937 /* the end of a frame. Reset buffers and receiver. */
4938 if ( info
->rx_enabled
){
4939 spin_lock_irqsave(&info
->lock
,flags
);
4941 spin_unlock_irqrestore(&info
->lock
,flags
);
4948 /* check status of receive frame */
4950 /* frame status is byte stored after frame data
4952 * 7 EOM (end of msg), 1 = last buffer of frame
4953 * 6 Short Frame, 1 = short frame
4954 * 5 Abort, 1 = frame aborted
4955 * 4 Residue, 1 = last byte is partial
4956 * 3 Overrun, 1 = overrun occurred during frame reception
4957 * 2 CRC, 1 = CRC error detected
4960 status
= desc
->status
;
4962 /* ignore CRC bit if not using CRC (bit is undefined) */
4963 /* Note:CRC is not save to data buffer */
4964 if (info
->params
.crc_type
== HDLC_CRC_NONE
)
4967 if (framesize
== 0 ||
4968 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4969 /* discard 0 byte frames, this seems to occur sometime
4970 * when remote is idling flags.
4972 rx_free_frame_buffers(info
, StartIndex
, EndIndex
);
4979 if (status
& (BIT6
+BIT5
+BIT3
+BIT2
)) {
4980 /* received frame has errors,
4981 * update counts and mark frame size as 0
4984 info
->icount
.rxshort
++;
4985 else if (status
& BIT5
)
4986 info
->icount
.rxabort
++;
4987 else if (status
& BIT3
)
4988 info
->icount
.rxover
++;
4990 info
->icount
.rxcrc
++;
4995 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
4997 stats
->rx_frame_errors
++;
5002 if ( debug_level
>= DEBUG_LEVEL_BH
)
5003 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5004 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
5006 if ( debug_level
>= DEBUG_LEVEL_DATA
)
5007 trace_block(info
,info
->rx_buf_list_ex
[StartIndex
].virt_addr
,
5008 min_t(int, framesize
,SCABUFSIZE
),0);
5011 if (framesize
> info
->max_frame_size
)
5012 info
->icount
.rxlong
++;
5014 /* copy dma buffer(s) to contiguous intermediate buffer */
5015 int copy_count
= framesize
;
5016 int index
= StartIndex
;
5017 unsigned char *ptmp
= info
->tmp_rx_buf
;
5018 info
->tmp_rx_buf_count
= framesize
;
5020 info
->icount
.rxok
++;
5023 int partial_count
= min(copy_count
,SCABUFSIZE
);
5025 info
->rx_buf_list_ex
[index
].virt_addr
,
5027 ptmp
+= partial_count
;
5028 copy_count
-= partial_count
;
5030 if ( ++index
== info
->rx_buf_count
)
5036 hdlcdev_rx(info
,info
->tmp_rx_buf
,framesize
);
5039 ldisc_receive_buf(tty
,info
->tmp_rx_buf
,
5040 info
->flag_buf
, framesize
);
5043 /* Free the buffers used by this frame. */
5044 rx_free_frame_buffers( info
, StartIndex
, EndIndex
);
5049 if ( info
->rx_enabled
&& info
->rx_overflow
) {
5050 /* Receiver is enabled, but needs to restarted due to
5051 * rx buffer overflow. If buffers are empty, restart receiver.
5053 if (info
->rx_buf_list
[EndIndex
].status
== 0xff) {
5054 spin_lock_irqsave(&info
->lock
,flags
);
5056 spin_unlock_irqrestore(&info
->lock
,flags
);
5063 /* load the transmit DMA buffer with data
5065 void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
)
5067 unsigned short copy_count
;
5070 SCADESC_EX
*desc_ex
;
5072 if ( debug_level
>= DEBUG_LEVEL_DATA
)
5073 trace_block(info
,buf
, min_t(int, count
,SCABUFSIZE
), 1);
5075 /* Copy source buffer to one or more DMA buffers, starting with
5076 * the first transmit dma buffer.
5080 copy_count
= min_t(unsigned short,count
,SCABUFSIZE
);
5082 desc
= &info
->tx_buf_list
[i
];
5083 desc_ex
= &info
->tx_buf_list_ex
[i
];
5085 load_pci_memory(info
, desc_ex
->virt_addr
,buf
,copy_count
);
5087 desc
->length
= copy_count
;
5091 count
-= copy_count
;
5097 if (i
>= info
->tx_buf_count
)
5101 info
->tx_buf_list
[i
].status
= 0x81; /* set EOM and EOT status */
5102 info
->last_tx_buf
= ++i
;
5105 int register_test(SLMP_INFO
*info
)
5107 static unsigned char testval
[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5108 static unsigned int count
= sizeof(testval
)/sizeof(unsigned char);
5111 unsigned long flags
;
5113 spin_lock_irqsave(&info
->lock
,flags
);
5116 /* assume failure */
5117 info
->init_error
= DiagStatus_AddressFailure
;
5119 /* Write bit patterns to various registers but do it out of */
5120 /* sync, then read back and verify values. */
5122 for (i
= 0 ; i
< count
; i
++) {
5123 write_reg(info
, TMC
, testval
[i
]);
5124 write_reg(info
, IDL
, testval
[(i
+1)%count
]);
5125 write_reg(info
, SA0
, testval
[(i
+2)%count
]);
5126 write_reg(info
, SA1
, testval
[(i
+3)%count
]);
5128 if ( (read_reg(info
, TMC
) != testval
[i
]) ||
5129 (read_reg(info
, IDL
) != testval
[(i
+1)%count
]) ||
5130 (read_reg(info
, SA0
) != testval
[(i
+2)%count
]) ||
5131 (read_reg(info
, SA1
) != testval
[(i
+3)%count
]) )
5139 spin_unlock_irqrestore(&info
->lock
,flags
);
5144 int irq_test(SLMP_INFO
*info
)
5146 unsigned long timeout
;
5147 unsigned long flags
;
5149 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
5151 spin_lock_irqsave(&info
->lock
,flags
);
5154 /* assume failure */
5155 info
->init_error
= DiagStatus_IrqFailure
;
5156 info
->irq_occurred
= FALSE
;
5158 /* setup timer0 on SCA0 to interrupt */
5160 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5161 write_reg(info
, IER2
, (unsigned char)((info
->port_num
& 1) ? BIT6
: BIT4
));
5163 write_reg(info
, (unsigned char)(timer
+ TEPR
), 0); /* timer expand prescale */
5164 write_reg16(info
, (unsigned char)(timer
+ TCONR
), 1); /* timer constant */
5167 /* TMCS, Timer Control/Status Register
5169 * 07 CMF, Compare match flag (read only) 1=match
5170 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5171 * 05 Reserved, must be 0
5172 * 04 TME, Timer Enable
5173 * 03..00 Reserved, must be 0
5177 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0x50);
5179 spin_unlock_irqrestore(&info
->lock
,flags
);
5182 while( timeout
-- && !info
->irq_occurred
) {
5183 msleep_interruptible(10);
5186 spin_lock_irqsave(&info
->lock
,flags
);
5188 spin_unlock_irqrestore(&info
->lock
,flags
);
5190 return info
->irq_occurred
;
5193 /* initialize individual SCA device (2 ports)
5195 static int sca_init(SLMP_INFO
*info
)
5197 /* set wait controller to single mem partition (low), no wait states */
5198 write_reg(info
, PABR0
, 0); /* wait controller addr boundary 0 */
5199 write_reg(info
, PABR1
, 0); /* wait controller addr boundary 1 */
5200 write_reg(info
, WCRL
, 0); /* wait controller low range */
5201 write_reg(info
, WCRM
, 0); /* wait controller mid range */
5202 write_reg(info
, WCRH
, 0); /* wait controller high range */
5204 /* DPCR, DMA Priority Control
5206 * 07..05 Not used, must be 0
5207 * 04 BRC, bus release condition: 0=all transfers complete
5208 * 03 CCC, channel change condition: 0=every cycle
5209 * 02..00 PR<2..0>, priority 100=round robin
5213 write_reg(info
, DPCR
, dma_priority
);
5215 /* DMA Master Enable, BIT7: 1=enable all channels */
5216 write_reg(info
, DMER
, 0x80);
5218 /* enable all interrupt classes */
5219 write_reg(info
, IER0
, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5220 write_reg(info
, IER1
, 0xff); /* DMIB,DMIA (channels 0-3) */
5221 write_reg(info
, IER2
, 0xf0); /* TIRQ (timers 0-3) */
5223 /* ITCR, interrupt control register
5224 * 07 IPC, interrupt priority, 0=MSCI->DMA
5225 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5226 * 04 VOS, Vector Output, 0=unmodified vector
5227 * 03..00 Reserved, must be 0
5229 write_reg(info
, ITCR
, 0);
5234 /* initialize adapter hardware
5236 int init_adapter(SLMP_INFO
*info
)
5240 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5241 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5244 info
->misc_ctrl_value
|= BIT30
;
5245 *MiscCtrl
= info
->misc_ctrl_value
;
5248 * Force at least 170ns delay before clearing
5249 * reset bit. Each read from LCR takes at least
5250 * 30ns so 10 times for 300ns to be safe.
5253 readval
= *MiscCtrl
;
5255 info
->misc_ctrl_value
&= ~BIT30
;
5256 *MiscCtrl
= info
->misc_ctrl_value
;
5258 /* init control reg (all DTRs off, all clksel=input) */
5259 info
->ctrlreg_value
= 0xaa;
5260 write_control_reg(info
);
5263 volatile u32
*LCR1BRDR
= (u32
*)(info
->lcr_base
+ 0x2c);
5264 lcr1_brdr_value
&= ~(BIT5
+ BIT4
+ BIT3
);
5266 switch(read_ahead_count
)
5269 lcr1_brdr_value
|= BIT5
+ BIT4
+ BIT3
;
5272 lcr1_brdr_value
|= BIT5
+ BIT4
;
5275 lcr1_brdr_value
|= BIT5
+ BIT3
;
5278 lcr1_brdr_value
|= BIT5
;
5282 *LCR1BRDR
= lcr1_brdr_value
;
5283 *MiscCtrl
= misc_ctrl_value
;
5286 sca_init(info
->port_array
[0]);
5287 sca_init(info
->port_array
[2]);
5292 /* Loopback an HDLC frame to test the hardware
5293 * interrupt and DMA functions.
5295 int loopback_test(SLMP_INFO
*info
)
5297 #define TESTFRAMESIZE 20
5299 unsigned long timeout
;
5300 u16 count
= TESTFRAMESIZE
;
5301 unsigned char buf
[TESTFRAMESIZE
];
5303 unsigned long flags
;
5305 struct tty_struct
*oldtty
= info
->tty
;
5306 u32 speed
= info
->params
.clock_speed
;
5308 info
->params
.clock_speed
= 3686400;
5311 /* assume failure */
5312 info
->init_error
= DiagStatus_DmaFailure
;
5314 /* build and send transmit frame */
5315 for (count
= 0; count
< TESTFRAMESIZE
;++count
)
5316 buf
[count
] = (unsigned char)count
;
5318 memset(info
->tmp_rx_buf
,0,TESTFRAMESIZE
);
5320 /* program hardware for HDLC and enabled receiver */
5321 spin_lock_irqsave(&info
->lock
,flags
);
5323 enable_loopback(info
,1);
5325 info
->tx_count
= count
;
5326 tx_load_dma_buffer(info
,buf
,count
);
5328 spin_unlock_irqrestore(&info
->lock
,flags
);
5330 /* wait for receive complete */
5331 /* Set a timeout for waiting for interrupt. */
5332 for ( timeout
= 100; timeout
; --timeout
) {
5333 msleep_interruptible(10);
5335 if (rx_get_frame(info
)) {
5341 /* verify received frame length and contents */
5343 ( info
->tmp_rx_buf_count
!= count
||
5344 memcmp(buf
, info
->tmp_rx_buf
,count
))) {
5348 spin_lock_irqsave(&info
->lock
,flags
);
5349 reset_adapter(info
);
5350 spin_unlock_irqrestore(&info
->lock
,flags
);
5352 info
->params
.clock_speed
= speed
;
5358 /* Perform diagnostics on hardware
5360 int adapter_test( SLMP_INFO
*info
)
5362 unsigned long flags
;
5363 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5364 printk( "%s(%d):Testing device %s\n",
5365 __FILE__
,__LINE__
,info
->device_name
);
5367 spin_lock_irqsave(&info
->lock
,flags
);
5369 spin_unlock_irqrestore(&info
->lock
,flags
);
5371 info
->port_array
[0]->port_count
= 0;
5373 if ( register_test(info
->port_array
[0]) &&
5374 register_test(info
->port_array
[1])) {
5376 info
->port_array
[0]->port_count
= 2;
5378 if ( register_test(info
->port_array
[2]) &&
5379 register_test(info
->port_array
[3]) )
5380 info
->port_array
[0]->port_count
+= 2;
5383 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5384 __FILE__
,__LINE__
,info
->device_name
, (unsigned long)(info
->phys_sca_base
));
5388 if ( !irq_test(info
->port_array
[0]) ||
5389 !irq_test(info
->port_array
[1]) ||
5390 (info
->port_count
== 4 && !irq_test(info
->port_array
[2])) ||
5391 (info
->port_count
== 4 && !irq_test(info
->port_array
[3]))) {
5392 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5393 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
5397 if (!loopback_test(info
->port_array
[0]) ||
5398 !loopback_test(info
->port_array
[1]) ||
5399 (info
->port_count
== 4 && !loopback_test(info
->port_array
[2])) ||
5400 (info
->port_count
== 4 && !loopback_test(info
->port_array
[3]))) {
5401 printk( "%s(%d):DMA test failure for device %s\n",
5402 __FILE__
,__LINE__
,info
->device_name
);
5406 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5407 printk( "%s(%d):device %s passed diagnostics\n",
5408 __FILE__
,__LINE__
,info
->device_name
);
5410 info
->port_array
[0]->init_error
= 0;
5411 info
->port_array
[1]->init_error
= 0;
5412 if ( info
->port_count
> 2 ) {
5413 info
->port_array
[2]->init_error
= 0;
5414 info
->port_array
[3]->init_error
= 0;
5420 /* Test the shared memory on a PCI adapter.
5422 int memory_test(SLMP_INFO
*info
)
5424 static unsigned long testval
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5425 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5426 unsigned long count
= sizeof(testval
)/sizeof(unsigned long);
5428 unsigned long limit
= SCA_MEM_SIZE
/sizeof(unsigned long);
5429 unsigned long * addr
= (unsigned long *)info
->memory_base
;
5431 /* Test data lines with test pattern at one location. */
5433 for ( i
= 0 ; i
< count
; i
++ ) {
5435 if ( *addr
!= testval
[i
] )
5439 /* Test address lines with incrementing pattern over */
5440 /* entire address range. */
5442 for ( i
= 0 ; i
< limit
; i
++ ) {
5447 addr
= (unsigned long *)info
->memory_base
;
5449 for ( i
= 0 ; i
< limit
; i
++ ) {
5450 if ( *addr
!= i
* 4 )
5455 memset( info
->memory_base
, 0, SCA_MEM_SIZE
);
5459 /* Load data into PCI adapter shared memory.
5461 * The PCI9050 releases control of the local bus
5462 * after completing the current read or write operation.
5464 * While the PCI9050 write FIFO not empty, the
5465 * PCI9050 treats all of the writes as a single transaction
5466 * and does not release the bus. This causes DMA latency problems
5467 * at high speeds when copying large data blocks to the shared memory.
5469 * This function breaks a write into multiple transations by
5470 * interleaving a read which flushes the write FIFO and 'completes'
5471 * the write transation. This allows any pending DMA request to gain control
5472 * of the local bus in a timely fasion.
5474 void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
)
5476 /* A load interval of 16 allows for 4 32-bit writes at */
5477 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5479 unsigned short interval
= count
/ sca_pci_load_interval
;
5482 for ( i
= 0 ; i
< interval
; i
++ )
5484 memcpy(dest
, src
, sca_pci_load_interval
);
5485 read_status_reg(info
);
5486 dest
+= sca_pci_load_interval
;
5487 src
+= sca_pci_load_interval
;
5490 memcpy(dest
, src
, count
% sca_pci_load_interval
);
5493 void trace_block(SLMP_INFO
*info
,const char* data
, int count
, int xmit
)
5498 printk("%s tx data:\n",info
->device_name
);
5500 printk("%s rx data:\n",info
->device_name
);
5508 for(i
=0;i
<linecount
;i
++)
5509 printk("%02X ",(unsigned char)data
[i
]);
5512 for(i
=0;i
<linecount
;i
++) {
5513 if (data
[i
]>=040 && data
[i
]<=0176)
5514 printk("%c",data
[i
]);
5523 } /* end of trace_block() */
5525 /* called when HDLC frame times out
5526 * update stats and do tx completion processing
5528 void tx_timeout(unsigned long context
)
5530 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5531 unsigned long flags
;
5533 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5534 printk( "%s(%d):%s tx_timeout()\n",
5535 __FILE__
,__LINE__
,info
->device_name
);
5536 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
5537 info
->icount
.txtimeout
++;
5539 spin_lock_irqsave(&info
->lock
,flags
);
5540 info
->tx_active
= 0;
5541 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
5543 spin_unlock_irqrestore(&info
->lock
,flags
);
5547 hdlcdev_tx_done(info
);
5553 /* called to periodically check the DSR/RI modem signal input status
5555 void status_timeout(unsigned long context
)
5558 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5559 unsigned long flags
;
5560 unsigned char delta
;
5563 spin_lock_irqsave(&info
->lock
,flags
);
5565 spin_unlock_irqrestore(&info
->lock
,flags
);
5567 /* check for DSR/RI state change */
5569 delta
= info
->old_signals
^ info
->serial_signals
;
5570 info
->old_signals
= info
->serial_signals
;
5572 if (delta
& SerialSignal_DSR
)
5573 status
|= MISCSTATUS_DSR_LATCHED
|(info
->serial_signals
&SerialSignal_DSR
);
5575 if (delta
& SerialSignal_RI
)
5576 status
|= MISCSTATUS_RI_LATCHED
|(info
->serial_signals
&SerialSignal_RI
);
5578 if (delta
& SerialSignal_DCD
)
5579 status
|= MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
);
5581 if (delta
& SerialSignal_CTS
)
5582 status
|= MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
);
5585 isr_io_pin(info
,status
);
5587 info
->status_timer
.data
= (unsigned long)info
;
5588 info
->status_timer
.function
= status_timeout
;
5589 info
->status_timer
.expires
= jiffies
+ msecs_to_jiffies(10);
5590 add_timer(&info
->status_timer
);
5594 /* Register Access Routines -
5595 * All registers are memory mapped
5597 #define CALC_REGADDR() \
5598 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5599 if (info->port_num > 1) \
5600 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5601 if ( info->port_num & 1) { \
5603 RegAddr += 0x40; /* DMA access */ \
5604 else if (Addr > 0x1f && Addr < 0x60) \
5605 RegAddr += 0x20; /* MSCI access */ \
5609 unsigned char read_reg(SLMP_INFO
* info
, unsigned char Addr
)
5614 void write_reg(SLMP_INFO
* info
, unsigned char Addr
, unsigned char Value
)
5620 u16
read_reg16(SLMP_INFO
* info
, unsigned char Addr
)
5623 return *((u16
*)RegAddr
);
5626 void write_reg16(SLMP_INFO
* info
, unsigned char Addr
, u16 Value
)
5629 *((u16
*)RegAddr
) = Value
;
5632 unsigned char read_status_reg(SLMP_INFO
* info
)
5634 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5638 void write_control_reg(SLMP_INFO
* info
)
5640 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5641 *RegAddr
= info
->port_array
[0]->ctrlreg_value
;
5645 static int __devinit
synclinkmp_init_one (struct pci_dev
*dev
,
5646 const struct pci_device_id
*ent
)
5648 if (pci_enable_device(dev
)) {
5649 printk("error enabling pci device %p\n", dev
);
5652 device_init( ++synclinkmp_adapter_count
, dev
);
5656 static void __devexit
synclinkmp_remove_one (struct pci_dev
*dev
)