drivers/clk/bcm/clk-iproc.h

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef _CLK_IPROC_H
  15 #define _CLK_IPROC_H
  16
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/slab.h>
  21 #include <linux/device.h>
  22 #include <linux/of.h>
  23 #include <linux/clk-provider.h>
  24
  25 #define IPROC_CLK_NAME_LEN 25
  26 #define IPROC_CLK_INVALID_OFFSET 0xffffffff
  27 #define bit_mask(width) ((1 << (width)) - 1)
  28
  29 /* clocks that should not be disabled at runtime */
  30 #define IPROC_CLK_AON BIT(0)
  31
  32 /* PLL that requires gating through ASIU */
  33 #define IPROC_CLK_PLL_ASIU BIT(1)
  34
  35 /* PLL that has fractional part of the NDIV */
  36 #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
  37
  38 /*
  39  * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
  40  * of the same register following the write to flush the write transaction into
  41  * the intended register
  42  */
  43 #define IPROC_CLK_NEEDS_READ_BACK BIT(3)
  44
  45 /*
  46  * Some PLLs require the PLL SW override bit to be set before changes can be
  47  * applied to the PLL
  48  */
  49 #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
  50
  51 /*
  52  * Parameters for VCO frequency configuration
  53  *
  54  * VCO frequency =
  55  * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy  / pdiv)
  56  */
  57 struct iproc_pll_vco_param {
  58         unsigned long rate;
  59         unsigned int ndiv_int;
  60         unsigned int ndiv_frac;
  61         unsigned int pdiv;
  62 };
  63
  64 struct iproc_clk_reg_op {
  65         unsigned int offset;
  66         unsigned int shift;
  67         unsigned int width;
  68 };
  69
  70 /*
  71  * Clock gating control at the top ASIU level
  72  */
  73 struct iproc_asiu_gate {
  74         unsigned int offset;
  75         unsigned int en_shift;
  76 };
  77
  78 /*
  79  * Control of powering on/off of a PLL
  80  *
  81  * Before powering off a PLL, input isolation (ISO) needs to be enabled
  82  */
  83 struct iproc_pll_aon_pwr_ctrl {
  84         unsigned int offset;
  85         unsigned int pwr_width;
  86         unsigned int pwr_shift;
  87         unsigned int iso_shift;
  88 };
  89
  90 /*
  91  * Control of the PLL reset, with Ki, Kp, and Ka parameters
  92  */
  93 struct iproc_pll_reset_ctrl {
  94         unsigned int offset;
  95         unsigned int reset_shift;
  96         unsigned int p_reset_shift;
  97         unsigned int ki_shift;
  98         unsigned int ki_width;
  99         unsigned int kp_shift;
 100         unsigned int kp_width;
 101         unsigned int ka_shift;
 102         unsigned int ka_width;
 103 };
 104
 105 /*
 106  * To enable SW control of the PLL
 107  */
 108 struct iproc_pll_sw_ctrl {
 109         unsigned int offset;
 110         unsigned int shift;
 111 };
 112
 113 struct iproc_pll_vco_ctrl {
 114         unsigned int u_offset;
 115         unsigned int l_offset;
 116 };
 117
 118 /*
 119  * Main PLL control parameters
 120  */
 121 struct iproc_pll_ctrl {
 122         unsigned long flags;
 123         struct iproc_pll_aon_pwr_ctrl aon;
 124         struct iproc_asiu_gate asiu;
 125         struct iproc_pll_reset_ctrl reset;
 126         struct iproc_pll_sw_ctrl sw_ctrl;
 127         struct iproc_clk_reg_op ndiv_int;
 128         struct iproc_clk_reg_op ndiv_frac;
 129         struct iproc_clk_reg_op pdiv;
 130         struct iproc_pll_vco_ctrl vco_ctrl;
 131         struct iproc_clk_reg_op status;
 132 };
 133
 134 /*
 135  * Controls enabling/disabling a PLL derived clock
 136  */
 137 struct iproc_clk_enable_ctrl {
 138         unsigned int offset;
 139         unsigned int enable_shift;
 140         unsigned int hold_shift;
 141         unsigned int bypass_shift;
 142 };
 143
 144 /*
 145  * Main clock control parameters for clocks derived from the PLLs
 146  */
 147 struct iproc_clk_ctrl {
 148         unsigned int channel;
 149         unsigned long flags;
 150         struct iproc_clk_enable_ctrl enable;
 151         struct iproc_clk_reg_op mdiv;
 152 };
 153
 154 /*
 155  * Divisor of the ASIU clocks
 156  */
 157 struct iproc_asiu_div {
 158         unsigned int offset;
 159         unsigned int en_shift;
 160         unsigned int high_shift;
 161         unsigned int high_width;
 162         unsigned int low_shift;
 163         unsigned int low_width;
 164 };
 165
 166 void __init iproc_armpll_setup(struct device_node *node);
 167 void __init iproc_pll_clk_setup(struct device_node *node,
 168                                 const struct iproc_pll_ctrl *pll_ctrl,
 169                                 const struct iproc_pll_vco_param *vco,
 170                                 unsigned int num_vco_entries,
 171                                 const struct iproc_clk_ctrl *clk_ctrl,
 172                                 unsigned int num_clks);
 173 void __init iproc_asiu_setup(struct device_node *node,
 174                              const struct iproc_asiu_div *div,
 175                              const struct iproc_asiu_gate *gate,
 176                              unsigned int num_clks);
 177
 178 #endif /* _CLK_IPROC_H */