drivers/clk/clk-fractional-divider.c

   1 /*
   2  * Copyright (C) 2014 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Adjustable fractional divider clock implementation.
   9  * Output rate = (m / n) * parent_rate.
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/module.h>
  14 #include <linux/device.h>
  15 #include <linux/slab.h>
  16 #include <linux/gcd.h>
  17
  18 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
  19
  20 static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
  21                                         unsigned long parent_rate)
  22 {
  23         struct clk_fractional_divider *fd = to_clk_fd(hw);
  24         unsigned long flags = 0;
  25         u32 val, m, n;
  26         u64 ret;
  27
  28         if (fd->lock)
  29                 spin_lock_irqsave(fd->lock, flags);
  30         else
  31                 __acquire(fd->lock);
  32
  33         val = clk_readl(fd->reg);
  34
  35         if (fd->lock)
  36                 spin_unlock_irqrestore(fd->lock, flags);
  37         else
  38                 __release(fd->lock);
  39
  40         m = (val & fd->mmask) >> fd->mshift;
  41         n = (val & fd->nmask) >> fd->nshift;
  42
  43         if (!n || !m)
  44                 return parent_rate;
  45
  46         ret = (u64)parent_rate * m;
  47         do_div(ret, n);
  48
  49         return ret;
  50 }
  51
  52 static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
  53                               unsigned long *prate)
  54 {
  55         struct clk_fractional_divider *fd = to_clk_fd(hw);
  56         unsigned maxn = (fd->nmask >> fd->nshift) + 1;
  57         unsigned div;
  58
  59         if (!rate || rate >= *prate)
  60                 return *prate;
  61
  62         div = gcd(*prate, rate);
  63
  64         while ((*prate / div) > maxn) {
  65                 div <<= 1;
  66                 rate <<= 1;
  67         }
  68
  69         return rate;
  70 }
  71
  72 static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
  73                            unsigned long parent_rate)
  74 {
  75         struct clk_fractional_divider *fd = to_clk_fd(hw);
  76         unsigned long flags = 0;
  77         unsigned long div;
  78         unsigned n, m;
  79         u32 val;
  80
  81         div = gcd(parent_rate, rate);
  82         m = rate / div;
  83         n = parent_rate / div;
  84
  85         if (fd->lock)
  86                 spin_lock_irqsave(fd->lock, flags);
  87         else
  88                 __acquire(fd->lock);
  89
  90         val = clk_readl(fd->reg);
  91         val &= ~(fd->mmask | fd->nmask);
  92         val |= (m << fd->mshift) | (n << fd->nshift);
  93         clk_writel(val, fd->reg);
  94
  95         if (fd->lock)
  96                 spin_unlock_irqrestore(fd->lock, flags);
  97         else
  98                 __release(fd->lock);
  99
 100         return 0;
 101 }
 102
 103 const struct clk_ops clk_fractional_divider_ops = {
 104         .recalc_rate = clk_fd_recalc_rate,
 105         .round_rate = clk_fd_round_rate,
 106         .set_rate = clk_fd_set_rate,
 107 };
 108 EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
 109
 110 struct clk *clk_register_fractional_divider(struct device *dev,
 111                 const char *name, const char *parent_name, unsigned long flags,
 112                 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
 113                 u8 clk_divider_flags, spinlock_t *lock)
 114 {
 115         struct clk_fractional_divider *fd;
 116         struct clk_init_data init;
 117         struct clk *clk;
 118
 119         fd = kzalloc(sizeof(*fd), GFP_KERNEL);
 120         if (!fd)
 121                 return ERR_PTR(-ENOMEM);
 122
 123         init.name = name;
 124         init.ops = &clk_fractional_divider_ops;
 125         init.flags = flags | CLK_IS_BASIC;
 126         init.parent_names = parent_name ? &parent_name : NULL;
 127         init.num_parents = parent_name ? 1 : 0;
 128
 129         fd->reg = reg;
 130         fd->mshift = mshift;
 131         fd->mmask = (BIT(mwidth) - 1) << mshift;
 132         fd->nshift = nshift;
 133         fd->nmask = (BIT(nwidth) - 1) << nshift;
 134         fd->flags = clk_divider_flags;
 135         fd->lock = lock;
 136         fd->hw.init = &init;
 137
 138         clk = clk_register(dev, &fd->hw);
 139         if (IS_ERR(clk))
 140                 kfree(fd);
 141
 142         return clk;
 143 }
 144 EXPORT_SYMBOL_GPL(clk_register_fractional_divider);