2 * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 * Rabeeh Khoury <rabeeh@solid-run.com>
8 * [1] "Si5351A/B/C Data Sheet"
9 * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
10 * [2] "Manually Generating an Si5351 Register Map"
11 * http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/clkdev.h>
22 #include <linux/clk-provider.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/errno.h>
26 #include <linux/rational.h>
27 #include <linux/i2c.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_data/si5351.h>
30 #include <linux/regmap.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <asm/div64.h>
35 #include "clk-si5351.h"
37 struct si5351_driver_data
;
39 struct si5351_parameters
{
46 struct si5351_hw_data
{
48 struct si5351_driver_data
*drvdata
;
49 struct si5351_parameters params
;
53 struct si5351_driver_data
{
54 enum si5351_variant variant
;
55 struct i2c_client
*client
;
56 struct regmap
*regmap
;
57 struct clk_onecell_data onecell
;
60 const char *pxtal_name
;
63 const char *pclkin_name
;
66 struct si5351_hw_data pll
[2];
67 struct si5351_hw_data
*msynth
;
68 struct si5351_hw_data
*clkout
;
71 static const char * const si5351_input_names
[] = {
74 static const char * const si5351_pll_names
[] = {
75 "plla", "pllb", "vxco"
77 static const char * const si5351_msynth_names
[] = {
78 "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
80 static const char * const si5351_clkout_names
[] = {
81 "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
87 static inline u8
si5351_reg_read(struct si5351_driver_data
*drvdata
, u8 reg
)
92 ret
= regmap_read(drvdata
->regmap
, reg
, &val
);
94 dev_err(&drvdata
->client
->dev
,
95 "unable to read from reg%02x\n", reg
);
102 static inline int si5351_bulk_read(struct si5351_driver_data
*drvdata
,
103 u8 reg
, u8 count
, u8
*buf
)
105 return regmap_bulk_read(drvdata
->regmap
, reg
, buf
, count
);
108 static inline int si5351_reg_write(struct si5351_driver_data
*drvdata
,
111 return regmap_write(drvdata
->regmap
, reg
, val
);
114 static inline int si5351_bulk_write(struct si5351_driver_data
*drvdata
,
115 u8 reg
, u8 count
, const u8
*buf
)
117 return regmap_raw_write(drvdata
->regmap
, reg
, buf
, count
);
120 static inline int si5351_set_bits(struct si5351_driver_data
*drvdata
,
121 u8 reg
, u8 mask
, u8 val
)
123 return regmap_update_bits(drvdata
->regmap
, reg
, mask
, val
);
126 static inline u8
si5351_msynth_params_address(int num
)
129 return SI5351_CLK6_PARAMETERS
+ (num
- 6);
130 return SI5351_CLK0_PARAMETERS
+ (SI5351_PARAMETERS_LENGTH
* num
);
133 static void si5351_read_parameters(struct si5351_driver_data
*drvdata
,
134 u8 reg
, struct si5351_parameters
*params
)
136 u8 buf
[SI5351_PARAMETERS_LENGTH
];
139 case SI5351_CLK6_PARAMETERS
:
140 case SI5351_CLK7_PARAMETERS
:
141 buf
[0] = si5351_reg_read(drvdata
, reg
);
147 si5351_bulk_read(drvdata
, reg
, SI5351_PARAMETERS_LENGTH
, buf
);
148 params
->p1
= ((buf
[2] & 0x03) << 16) | (buf
[3] << 8) | buf
[4];
149 params
->p2
= ((buf
[5] & 0x0f) << 16) | (buf
[6] << 8) | buf
[7];
150 params
->p3
= ((buf
[5] & 0xf0) << 12) | (buf
[0] << 8) | buf
[1];
155 static void si5351_write_parameters(struct si5351_driver_data
*drvdata
,
156 u8 reg
, struct si5351_parameters
*params
)
158 u8 buf
[SI5351_PARAMETERS_LENGTH
];
161 case SI5351_CLK6_PARAMETERS
:
162 case SI5351_CLK7_PARAMETERS
:
163 buf
[0] = params
->p1
& 0xff;
164 si5351_reg_write(drvdata
, reg
, buf
[0]);
167 buf
[0] = ((params
->p3
& 0x0ff00) >> 8) & 0xff;
168 buf
[1] = params
->p3
& 0xff;
169 /* save rdiv and divby4 */
170 buf
[2] = si5351_reg_read(drvdata
, reg
+ 2) & ~0x03;
171 buf
[2] |= ((params
->p1
& 0x30000) >> 16) & 0x03;
172 buf
[3] = ((params
->p1
& 0x0ff00) >> 8) & 0xff;
173 buf
[4] = params
->p1
& 0xff;
174 buf
[5] = ((params
->p3
& 0xf0000) >> 12) |
175 ((params
->p2
& 0xf0000) >> 16);
176 buf
[6] = ((params
->p2
& 0x0ff00) >> 8) & 0xff;
177 buf
[7] = params
->p2
& 0xff;
178 si5351_bulk_write(drvdata
, reg
, SI5351_PARAMETERS_LENGTH
, buf
);
182 static bool si5351_regmap_is_volatile(struct device
*dev
, unsigned int reg
)
185 case SI5351_DEVICE_STATUS
:
186 case SI5351_INTERRUPT_STATUS
:
187 case SI5351_PLL_RESET
:
193 static bool si5351_regmap_is_writeable(struct device
*dev
, unsigned int reg
)
195 /* reserved registers */
196 if (reg
>= 4 && reg
<= 8)
198 if (reg
>= 10 && reg
<= 14)
200 if (reg
>= 173 && reg
<= 176)
202 if (reg
>= 178 && reg
<= 182)
205 if (reg
== SI5351_DEVICE_STATUS
)
210 static const struct regmap_config si5351_regmap_config
= {
213 .cache_type
= REGCACHE_RBTREE
,
215 .writeable_reg
= si5351_regmap_is_writeable
,
216 .volatile_reg
= si5351_regmap_is_volatile
,
220 * Si5351 xtal clock input
222 static int si5351_xtal_prepare(struct clk_hw
*hw
)
224 struct si5351_driver_data
*drvdata
=
225 container_of(hw
, struct si5351_driver_data
, xtal
);
226 si5351_set_bits(drvdata
, SI5351_FANOUT_ENABLE
,
227 SI5351_XTAL_ENABLE
, SI5351_XTAL_ENABLE
);
231 static void si5351_xtal_unprepare(struct clk_hw
*hw
)
233 struct si5351_driver_data
*drvdata
=
234 container_of(hw
, struct si5351_driver_data
, xtal
);
235 si5351_set_bits(drvdata
, SI5351_FANOUT_ENABLE
,
236 SI5351_XTAL_ENABLE
, 0);
239 static const struct clk_ops si5351_xtal_ops
= {
240 .prepare
= si5351_xtal_prepare
,
241 .unprepare
= si5351_xtal_unprepare
,
245 * Si5351 clkin clock input (Si5351C only)
247 static int si5351_clkin_prepare(struct clk_hw
*hw
)
249 struct si5351_driver_data
*drvdata
=
250 container_of(hw
, struct si5351_driver_data
, clkin
);
251 si5351_set_bits(drvdata
, SI5351_FANOUT_ENABLE
,
252 SI5351_CLKIN_ENABLE
, SI5351_CLKIN_ENABLE
);
256 static void si5351_clkin_unprepare(struct clk_hw
*hw
)
258 struct si5351_driver_data
*drvdata
=
259 container_of(hw
, struct si5351_driver_data
, clkin
);
260 si5351_set_bits(drvdata
, SI5351_FANOUT_ENABLE
,
261 SI5351_CLKIN_ENABLE
, 0);
265 * CMOS clock source constraints:
266 * The input frequency range of the PLL is 10Mhz to 40MHz.
267 * If CLKIN is >40MHz, the input divider must be used.
269 static unsigned long si5351_clkin_recalc_rate(struct clk_hw
*hw
,
270 unsigned long parent_rate
)
272 struct si5351_driver_data
*drvdata
=
273 container_of(hw
, struct si5351_driver_data
, clkin
);
278 if (parent_rate
> 160000000) {
279 idiv
= SI5351_CLKIN_DIV_8
;
281 } else if (parent_rate
> 80000000) {
282 idiv
= SI5351_CLKIN_DIV_4
;
284 } else if (parent_rate
> 40000000) {
285 idiv
= SI5351_CLKIN_DIV_2
;
288 idiv
= SI5351_CLKIN_DIV_1
;
291 si5351_set_bits(drvdata
, SI5351_PLL_INPUT_SOURCE
,
292 SI5351_CLKIN_DIV_MASK
, idiv
);
294 dev_dbg(&drvdata
->client
->dev
, "%s - clkin div = %d, rate = %lu\n",
295 __func__
, (1 << (idiv
>> 6)), rate
);
300 static const struct clk_ops si5351_clkin_ops
= {
301 .prepare
= si5351_clkin_prepare
,
302 .unprepare
= si5351_clkin_unprepare
,
303 .recalc_rate
= si5351_clkin_recalc_rate
,
307 * Si5351 vxco clock input (Si5351B only)
310 static int si5351_vxco_prepare(struct clk_hw
*hw
)
312 struct si5351_hw_data
*hwdata
=
313 container_of(hw
, struct si5351_hw_data
, hw
);
315 dev_warn(&hwdata
->drvdata
->client
->dev
, "VXCO currently unsupported\n");
320 static void si5351_vxco_unprepare(struct clk_hw
*hw
)
324 static unsigned long si5351_vxco_recalc_rate(struct clk_hw
*hw
,
325 unsigned long parent_rate
)
330 static int si5351_vxco_set_rate(struct clk_hw
*hw
, unsigned long rate
,
331 unsigned long parent
)
336 static const struct clk_ops si5351_vxco_ops
= {
337 .prepare
= si5351_vxco_prepare
,
338 .unprepare
= si5351_vxco_unprepare
,
339 .recalc_rate
= si5351_vxco_recalc_rate
,
340 .set_rate
= si5351_vxco_set_rate
,
346 * Feedback Multisynth Divider Equations [2]
348 * fVCO = fIN * (a + b/c)
350 * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
351 * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
353 * Feedback Multisynth Register Equations
355 * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
356 * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
357 * (3) MSNx_P3[19:0] = c
359 * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
361 * Using (4) on (1) yields:
362 * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
363 * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
365 * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
366 * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
369 static int _si5351_pll_reparent(struct si5351_driver_data
*drvdata
,
370 int num
, enum si5351_pll_src parent
)
372 u8 mask
= (num
== 0) ? SI5351_PLLA_SOURCE
: SI5351_PLLB_SOURCE
;
374 if (parent
== SI5351_PLL_SRC_DEFAULT
)
380 if (drvdata
->variant
!= SI5351_VARIANT_C
&&
381 parent
!= SI5351_PLL_SRC_XTAL
)
384 si5351_set_bits(drvdata
, SI5351_PLL_INPUT_SOURCE
, mask
,
385 (parent
== SI5351_PLL_SRC_XTAL
) ? 0 : mask
);
389 static unsigned char si5351_pll_get_parent(struct clk_hw
*hw
)
391 struct si5351_hw_data
*hwdata
=
392 container_of(hw
, struct si5351_hw_data
, hw
);
393 u8 mask
= (hwdata
->num
== 0) ? SI5351_PLLA_SOURCE
: SI5351_PLLB_SOURCE
;
396 val
= si5351_reg_read(hwdata
->drvdata
, SI5351_PLL_INPUT_SOURCE
);
398 return (val
& mask
) ? 1 : 0;
401 static int si5351_pll_set_parent(struct clk_hw
*hw
, u8 index
)
403 struct si5351_hw_data
*hwdata
=
404 container_of(hw
, struct si5351_hw_data
, hw
);
406 if (hwdata
->drvdata
->variant
!= SI5351_VARIANT_C
&&
413 return _si5351_pll_reparent(hwdata
->drvdata
, hwdata
->num
,
414 (index
== 0) ? SI5351_PLL_SRC_XTAL
:
415 SI5351_PLL_SRC_CLKIN
);
418 static unsigned long si5351_pll_recalc_rate(struct clk_hw
*hw
,
419 unsigned long parent_rate
)
421 struct si5351_hw_data
*hwdata
=
422 container_of(hw
, struct si5351_hw_data
, hw
);
423 u8 reg
= (hwdata
->num
== 0) ? SI5351_PLLA_PARAMETERS
:
424 SI5351_PLLB_PARAMETERS
;
425 unsigned long long rate
;
427 if (!hwdata
->params
.valid
)
428 si5351_read_parameters(hwdata
->drvdata
, reg
, &hwdata
->params
);
430 if (hwdata
->params
.p3
== 0)
433 /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
434 rate
= hwdata
->params
.p1
* hwdata
->params
.p3
;
435 rate
+= 512 * hwdata
->params
.p3
;
436 rate
+= hwdata
->params
.p2
;
438 do_div(rate
, 128 * hwdata
->params
.p3
);
440 dev_dbg(&hwdata
->drvdata
->client
->dev
,
441 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
442 __func__
, __clk_get_name(hwdata
->hw
.clk
),
443 hwdata
->params
.p1
, hwdata
->params
.p2
, hwdata
->params
.p3
,
444 parent_rate
, (unsigned long)rate
);
446 return (unsigned long)rate
;
449 static long si5351_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
450 unsigned long *parent_rate
)
452 struct si5351_hw_data
*hwdata
=
453 container_of(hw
, struct si5351_hw_data
, hw
);
454 unsigned long rfrac
, denom
, a
, b
, c
;
455 unsigned long long lltmp
;
457 if (rate
< SI5351_PLL_VCO_MIN
)
458 rate
= SI5351_PLL_VCO_MIN
;
459 if (rate
> SI5351_PLL_VCO_MAX
)
460 rate
= SI5351_PLL_VCO_MAX
;
462 /* determine integer part of feedback equation */
463 a
= rate
/ *parent_rate
;
465 if (a
< SI5351_PLL_A_MIN
)
466 rate
= *parent_rate
* SI5351_PLL_A_MIN
;
467 if (a
> SI5351_PLL_A_MAX
)
468 rate
= *parent_rate
* SI5351_PLL_A_MAX
;
470 /* find best approximation for b/c = fVCO mod fIN */
472 lltmp
= rate
% (*parent_rate
);
474 do_div(lltmp
, *parent_rate
);
475 rfrac
= (unsigned long)lltmp
;
480 rational_best_approximation(rfrac
, denom
,
481 SI5351_PLL_B_MAX
, SI5351_PLL_C_MAX
, &b
, &c
);
483 /* calculate parameters */
484 hwdata
->params
.p3
= c
;
485 hwdata
->params
.p2
= (128 * b
) % c
;
486 hwdata
->params
.p1
= 128 * a
;
487 hwdata
->params
.p1
+= (128 * b
/ c
);
488 hwdata
->params
.p1
-= 512;
490 /* recalculate rate by fIN * (a + b/c) */
491 lltmp
= *parent_rate
;
495 rate
= (unsigned long)lltmp
;
496 rate
+= *parent_rate
* a
;
498 dev_dbg(&hwdata
->drvdata
->client
->dev
,
499 "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
500 __func__
, __clk_get_name(hwdata
->hw
.clk
), a
, b
, c
,
506 static int si5351_pll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
507 unsigned long parent_rate
)
509 struct si5351_hw_data
*hwdata
=
510 container_of(hw
, struct si5351_hw_data
, hw
);
511 u8 reg
= (hwdata
->num
== 0) ? SI5351_PLLA_PARAMETERS
:
512 SI5351_PLLB_PARAMETERS
;
514 /* write multisynth parameters */
515 si5351_write_parameters(hwdata
->drvdata
, reg
, &hwdata
->params
);
517 /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
518 si5351_set_bits(hwdata
->drvdata
, SI5351_CLK6_CTRL
+ hwdata
->num
,
519 SI5351_CLK_INTEGER_MODE
,
520 (hwdata
->params
.p2
== 0) ? SI5351_CLK_INTEGER_MODE
: 0);
522 dev_dbg(&hwdata
->drvdata
->client
->dev
,
523 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
524 __func__
, __clk_get_name(hwdata
->hw
.clk
),
525 hwdata
->params
.p1
, hwdata
->params
.p2
, hwdata
->params
.p3
,
531 static const struct clk_ops si5351_pll_ops
= {
532 .set_parent
= si5351_pll_set_parent
,
533 .get_parent
= si5351_pll_get_parent
,
534 .recalc_rate
= si5351_pll_recalc_rate
,
535 .round_rate
= si5351_pll_round_rate
,
536 .set_rate
= si5351_pll_set_rate
,
540 * Si5351 multisync divider
542 * for fOUT <= 150 MHz:
544 * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
546 * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
549 * Output Clock Multisynth Register Equations
551 * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
552 * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
555 * MS[6,7] are integer (P1) divide only, P1 = divide value,
556 * P2 and P3 are not applicable
558 * for 150MHz < fOUT <= 160MHz:
560 * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
562 static int _si5351_msynth_reparent(struct si5351_driver_data
*drvdata
,
563 int num
, enum si5351_multisynth_src parent
)
565 if (parent
== SI5351_MULTISYNTH_SRC_DEFAULT
)
571 si5351_set_bits(drvdata
, SI5351_CLK0_CTRL
+ num
, SI5351_CLK_PLL_SELECT
,
572 (parent
== SI5351_MULTISYNTH_SRC_VCO0
) ? 0 :
573 SI5351_CLK_PLL_SELECT
);
577 static unsigned char si5351_msynth_get_parent(struct clk_hw
*hw
)
579 struct si5351_hw_data
*hwdata
=
580 container_of(hw
, struct si5351_hw_data
, hw
);
583 val
= si5351_reg_read(hwdata
->drvdata
, SI5351_CLK0_CTRL
+ hwdata
->num
);
585 return (val
& SI5351_CLK_PLL_SELECT
) ? 1 : 0;
588 static int si5351_msynth_set_parent(struct clk_hw
*hw
, u8 index
)
590 struct si5351_hw_data
*hwdata
=
591 container_of(hw
, struct si5351_hw_data
, hw
);
593 return _si5351_msynth_reparent(hwdata
->drvdata
, hwdata
->num
,
594 (index
== 0) ? SI5351_MULTISYNTH_SRC_VCO0
:
595 SI5351_MULTISYNTH_SRC_VCO1
);
598 static unsigned long si5351_msynth_recalc_rate(struct clk_hw
*hw
,
599 unsigned long parent_rate
)
601 struct si5351_hw_data
*hwdata
=
602 container_of(hw
, struct si5351_hw_data
, hw
);
603 u8 reg
= si5351_msynth_params_address(hwdata
->num
);
604 unsigned long long rate
;
607 if (!hwdata
->params
.valid
)
608 si5351_read_parameters(hwdata
->drvdata
, reg
, &hwdata
->params
);
610 if (hwdata
->params
.p3
== 0)
614 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
615 * multisync6-7: fOUT = fIN / P1
618 if (hwdata
->num
> 5) {
619 m
= hwdata
->params
.p1
;
620 } else if ((si5351_reg_read(hwdata
->drvdata
, reg
+ 2) &
621 SI5351_OUTPUT_CLK_DIVBY4
) == SI5351_OUTPUT_CLK_DIVBY4
) {
624 rate
*= 128 * hwdata
->params
.p3
;
625 m
= hwdata
->params
.p1
* hwdata
->params
.p3
;
626 m
+= hwdata
->params
.p2
;
627 m
+= 512 * hwdata
->params
.p3
;
634 dev_dbg(&hwdata
->drvdata
->client
->dev
,
635 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
636 __func__
, __clk_get_name(hwdata
->hw
.clk
),
637 hwdata
->params
.p1
, hwdata
->params
.p2
, hwdata
->params
.p3
,
638 m
, parent_rate
, (unsigned long)rate
);
640 return (unsigned long)rate
;
643 static long si5351_msynth_round_rate(struct clk_hw
*hw
, unsigned long rate
,
644 unsigned long *parent_rate
)
646 struct si5351_hw_data
*hwdata
=
647 container_of(hw
, struct si5351_hw_data
, hw
);
648 unsigned long long lltmp
;
649 unsigned long a
, b
, c
;
652 /* multisync6-7 can only handle freqencies < 150MHz */
653 if (hwdata
->num
>= 6 && rate
> SI5351_MULTISYNTH67_MAX_FREQ
)
654 rate
= SI5351_MULTISYNTH67_MAX_FREQ
;
656 /* multisync frequency is 1MHz .. 160MHz */
657 if (rate
> SI5351_MULTISYNTH_MAX_FREQ
)
658 rate
= SI5351_MULTISYNTH_MAX_FREQ
;
659 if (rate
< SI5351_MULTISYNTH_MIN_FREQ
)
660 rate
= SI5351_MULTISYNTH_MIN_FREQ
;
663 if (rate
> SI5351_MULTISYNTH_DIVBY4_FREQ
)
666 /* multisync can set pll */
667 if (__clk_get_flags(hwdata
->hw
.clk
) & CLK_SET_RATE_PARENT
) {
669 * find largest integer divider for max
670 * vco frequency and given target rate
673 lltmp
= SI5351_PLL_VCO_MAX
;
675 a
= (unsigned long)lltmp
;
682 *parent_rate
= a
* rate
;
683 } else if (hwdata
->num
>= 6) {
684 /* determine the closest integer divider */
685 a
= DIV_ROUND_CLOSEST(*parent_rate
, rate
);
686 if (a
< SI5351_MULTISYNTH_A_MIN
)
687 a
= SI5351_MULTISYNTH_A_MIN
;
688 if (a
> SI5351_MULTISYNTH67_A_MAX
)
689 a
= SI5351_MULTISYNTH67_A_MAX
;
694 unsigned long rfrac
, denom
;
698 rate
= SI5351_MULTISYNTH_DIVBY4_FREQ
;
702 /* determine integer part of divider equation */
703 a
= *parent_rate
/ rate
;
704 if (a
< SI5351_MULTISYNTH_A_MIN
)
705 a
= SI5351_MULTISYNTH_A_MIN
;
706 if (a
> SI5351_MULTISYNTH_A_MAX
)
707 a
= SI5351_MULTISYNTH_A_MAX
;
709 /* find best approximation for b/c = fVCO mod fOUT */
711 lltmp
= (*parent_rate
) % rate
;
714 rfrac
= (unsigned long)lltmp
;
719 rational_best_approximation(rfrac
, denom
,
720 SI5351_MULTISYNTH_B_MAX
, SI5351_MULTISYNTH_C_MAX
,
724 /* recalculate rate by fOUT = fIN / (a + b/c) */
725 lltmp
= *parent_rate
;
727 do_div(lltmp
, a
* c
+ b
);
728 rate
= (unsigned long)lltmp
;
730 /* calculate parameters */
732 hwdata
->params
.p3
= 1;
733 hwdata
->params
.p2
= 0;
734 hwdata
->params
.p1
= 0;
735 } else if (hwdata
->num
>= 6) {
736 hwdata
->params
.p3
= 0;
737 hwdata
->params
.p2
= 0;
738 hwdata
->params
.p1
= a
;
740 hwdata
->params
.p3
= c
;
741 hwdata
->params
.p2
= (128 * b
) % c
;
742 hwdata
->params
.p1
= 128 * a
;
743 hwdata
->params
.p1
+= (128 * b
/ c
);
744 hwdata
->params
.p1
-= 512;
747 dev_dbg(&hwdata
->drvdata
->client
->dev
,
748 "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
749 __func__
, __clk_get_name(hwdata
->hw
.clk
), a
, b
, c
, divby4
,
755 static int si5351_msynth_set_rate(struct clk_hw
*hw
, unsigned long rate
,
756 unsigned long parent_rate
)
758 struct si5351_hw_data
*hwdata
=
759 container_of(hw
, struct si5351_hw_data
, hw
);
760 u8 reg
= si5351_msynth_params_address(hwdata
->num
);
763 /* write multisynth parameters */
764 si5351_write_parameters(hwdata
->drvdata
, reg
, &hwdata
->params
);
766 if (rate
> SI5351_MULTISYNTH_DIVBY4_FREQ
)
769 /* enable/disable integer mode and divby4 on multisynth0-5 */
770 if (hwdata
->num
< 6) {
771 si5351_set_bits(hwdata
->drvdata
, reg
+ 2,
772 SI5351_OUTPUT_CLK_DIVBY4
,
773 (divby4
) ? SI5351_OUTPUT_CLK_DIVBY4
: 0);
774 si5351_set_bits(hwdata
->drvdata
, SI5351_CLK0_CTRL
+ hwdata
->num
,
775 SI5351_CLK_INTEGER_MODE
,
776 (hwdata
->params
.p2
== 0) ? SI5351_CLK_INTEGER_MODE
: 0);
779 dev_dbg(&hwdata
->drvdata
->client
->dev
,
780 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
781 __func__
, __clk_get_name(hwdata
->hw
.clk
),
782 hwdata
->params
.p1
, hwdata
->params
.p2
, hwdata
->params
.p3
,
783 divby4
, parent_rate
, rate
);
788 static const struct clk_ops si5351_msynth_ops
= {
789 .set_parent
= si5351_msynth_set_parent
,
790 .get_parent
= si5351_msynth_get_parent
,
791 .recalc_rate
= si5351_msynth_recalc_rate
,
792 .round_rate
= si5351_msynth_round_rate
,
793 .set_rate
= si5351_msynth_set_rate
,
797 * Si5351 clkout divider
799 static int _si5351_clkout_reparent(struct si5351_driver_data
*drvdata
,
800 int num
, enum si5351_clkout_src parent
)
808 case SI5351_CLKOUT_SRC_MSYNTH_N
:
809 val
= SI5351_CLK_INPUT_MULTISYNTH_N
;
811 case SI5351_CLKOUT_SRC_MSYNTH_0_4
:
812 /* clk0/clk4 can only connect to its own multisync */
813 if (num
== 0 || num
== 4)
814 val
= SI5351_CLK_INPUT_MULTISYNTH_N
;
816 val
= SI5351_CLK_INPUT_MULTISYNTH_0_4
;
818 case SI5351_CLKOUT_SRC_XTAL
:
819 val
= SI5351_CLK_INPUT_XTAL
;
821 case SI5351_CLKOUT_SRC_CLKIN
:
822 if (drvdata
->variant
!= SI5351_VARIANT_C
)
825 val
= SI5351_CLK_INPUT_CLKIN
;
831 si5351_set_bits(drvdata
, SI5351_CLK0_CTRL
+ num
,
832 SI5351_CLK_INPUT_MASK
, val
);
836 static int _si5351_clkout_set_drive_strength(
837 struct si5351_driver_data
*drvdata
, int num
,
838 enum si5351_drive_strength drive
)
846 case SI5351_DRIVE_2MA
:
847 mask
= SI5351_CLK_DRIVE_STRENGTH_2MA
;
849 case SI5351_DRIVE_4MA
:
850 mask
= SI5351_CLK_DRIVE_STRENGTH_4MA
;
852 case SI5351_DRIVE_6MA
:
853 mask
= SI5351_CLK_DRIVE_STRENGTH_6MA
;
855 case SI5351_DRIVE_8MA
:
856 mask
= SI5351_CLK_DRIVE_STRENGTH_8MA
;
862 si5351_set_bits(drvdata
, SI5351_CLK0_CTRL
+ num
,
863 SI5351_CLK_DRIVE_STRENGTH_MASK
, mask
);
867 static int _si5351_clkout_set_disable_state(
868 struct si5351_driver_data
*drvdata
, int num
,
869 enum si5351_disable_state state
)
871 u8 reg
= (num
< 4) ? SI5351_CLK3_0_DISABLE_STATE
:
872 SI5351_CLK7_4_DISABLE_STATE
;
873 u8 shift
= (num
< 4) ? (2 * num
) : (2 * (num
-4));
874 u8 mask
= SI5351_CLK_DISABLE_STATE_MASK
<< shift
;
881 case SI5351_DISABLE_LOW
:
882 val
= SI5351_CLK_DISABLE_STATE_LOW
;
884 case SI5351_DISABLE_HIGH
:
885 val
= SI5351_CLK_DISABLE_STATE_HIGH
;
887 case SI5351_DISABLE_FLOATING
:
888 val
= SI5351_CLK_DISABLE_STATE_FLOAT
;
890 case SI5351_DISABLE_NEVER
:
891 val
= SI5351_CLK_DISABLE_STATE_NEVER
;
897 si5351_set_bits(drvdata
, reg
, mask
, val
<< shift
);
902 static int si5351_clkout_prepare(struct clk_hw
*hw
)
904 struct si5351_hw_data
*hwdata
=
905 container_of(hw
, struct si5351_hw_data
, hw
);
907 si5351_set_bits(hwdata
->drvdata
, SI5351_CLK0_CTRL
+ hwdata
->num
,
908 SI5351_CLK_POWERDOWN
, 0);
909 si5351_set_bits(hwdata
->drvdata
, SI5351_OUTPUT_ENABLE_CTRL
,
910 (1 << hwdata
->num
), 0);
914 static void si5351_clkout_unprepare(struct clk_hw
*hw
)
916 struct si5351_hw_data
*hwdata
=
917 container_of(hw
, struct si5351_hw_data
, hw
);
919 si5351_set_bits(hwdata
->drvdata
, SI5351_CLK0_CTRL
+ hwdata
->num
,
920 SI5351_CLK_POWERDOWN
, SI5351_CLK_POWERDOWN
);
921 si5351_set_bits(hwdata
->drvdata
, SI5351_OUTPUT_ENABLE_CTRL
,
922 (1 << hwdata
->num
), (1 << hwdata
->num
));
925 static u8
si5351_clkout_get_parent(struct clk_hw
*hw
)
927 struct si5351_hw_data
*hwdata
=
928 container_of(hw
, struct si5351_hw_data
, hw
);
932 val
= si5351_reg_read(hwdata
->drvdata
, SI5351_CLK0_CTRL
+ hwdata
->num
);
933 switch (val
& SI5351_CLK_INPUT_MASK
) {
934 case SI5351_CLK_INPUT_MULTISYNTH_N
:
937 case SI5351_CLK_INPUT_MULTISYNTH_0_4
:
940 case SI5351_CLK_INPUT_XTAL
:
943 case SI5351_CLK_INPUT_CLKIN
:
951 static int si5351_clkout_set_parent(struct clk_hw
*hw
, u8 index
)
953 struct si5351_hw_data
*hwdata
=
954 container_of(hw
, struct si5351_hw_data
, hw
);
955 enum si5351_clkout_src parent
= SI5351_CLKOUT_SRC_DEFAULT
;
959 parent
= SI5351_CLKOUT_SRC_MSYNTH_N
;
962 parent
= SI5351_CLKOUT_SRC_MSYNTH_0_4
;
965 parent
= SI5351_CLKOUT_SRC_XTAL
;
968 parent
= SI5351_CLKOUT_SRC_CLKIN
;
972 return _si5351_clkout_reparent(hwdata
->drvdata
, hwdata
->num
, parent
);
975 static unsigned long si5351_clkout_recalc_rate(struct clk_hw
*hw
,
976 unsigned long parent_rate
)
978 struct si5351_hw_data
*hwdata
=
979 container_of(hw
, struct si5351_hw_data
, hw
);
983 if (hwdata
->num
<= 5)
984 reg
= si5351_msynth_params_address(hwdata
->num
) + 2;
986 reg
= SI5351_CLK6_7_OUTPUT_DIVIDER
;
988 rdiv
= si5351_reg_read(hwdata
->drvdata
, reg
);
989 if (hwdata
->num
== 6) {
990 rdiv
&= SI5351_OUTPUT_CLK6_DIV_MASK
;
992 rdiv
&= SI5351_OUTPUT_CLK_DIV_MASK
;
993 rdiv
>>= SI5351_OUTPUT_CLK_DIV_SHIFT
;
996 return parent_rate
>> rdiv
;
999 static long si5351_clkout_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1000 unsigned long *parent_rate
)
1002 struct si5351_hw_data
*hwdata
=
1003 container_of(hw
, struct si5351_hw_data
, hw
);
1006 /* clkout6/7 can only handle output freqencies < 150MHz */
1007 if (hwdata
->num
>= 6 && rate
> SI5351_CLKOUT67_MAX_FREQ
)
1008 rate
= SI5351_CLKOUT67_MAX_FREQ
;
1010 /* clkout freqency is 8kHz - 160MHz */
1011 if (rate
> SI5351_CLKOUT_MAX_FREQ
)
1012 rate
= SI5351_CLKOUT_MAX_FREQ
;
1013 if (rate
< SI5351_CLKOUT_MIN_FREQ
)
1014 rate
= SI5351_CLKOUT_MIN_FREQ
;
1016 /* request frequency if multisync master */
1017 if (__clk_get_flags(hwdata
->hw
.clk
) & CLK_SET_RATE_PARENT
) {
1018 /* use r divider for frequencies below 1MHz */
1019 rdiv
= SI5351_OUTPUT_CLK_DIV_1
;
1020 while (rate
< SI5351_MULTISYNTH_MIN_FREQ
&&
1021 rdiv
< SI5351_OUTPUT_CLK_DIV_128
) {
1025 *parent_rate
= rate
;
1027 unsigned long new_rate
, new_err
, err
;
1029 /* round to closed rdiv */
1030 rdiv
= SI5351_OUTPUT_CLK_DIV_1
;
1031 new_rate
= *parent_rate
;
1032 err
= abs(new_rate
- rate
);
1035 new_err
= abs(new_rate
- rate
);
1036 if (new_err
> err
|| rdiv
== SI5351_OUTPUT_CLK_DIV_128
)
1042 rate
= *parent_rate
>> rdiv
;
1044 dev_dbg(&hwdata
->drvdata
->client
->dev
,
1045 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1046 __func__
, __clk_get_name(hwdata
->hw
.clk
), (1 << rdiv
),
1047 *parent_rate
, rate
);
1052 static int si5351_clkout_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1053 unsigned long parent_rate
)
1055 struct si5351_hw_data
*hwdata
=
1056 container_of(hw
, struct si5351_hw_data
, hw
);
1057 unsigned long new_rate
, new_err
, err
;
1060 /* round to closed rdiv */
1061 rdiv
= SI5351_OUTPUT_CLK_DIV_1
;
1062 new_rate
= parent_rate
;
1063 err
= abs(new_rate
- rate
);
1066 new_err
= abs(new_rate
- rate
);
1067 if (new_err
> err
|| rdiv
== SI5351_OUTPUT_CLK_DIV_128
)
1073 /* write output divider */
1074 switch (hwdata
->num
) {
1076 si5351_set_bits(hwdata
->drvdata
, SI5351_CLK6_7_OUTPUT_DIVIDER
,
1077 SI5351_OUTPUT_CLK6_DIV_MASK
, rdiv
);
1080 si5351_set_bits(hwdata
->drvdata
, SI5351_CLK6_7_OUTPUT_DIVIDER
,
1081 SI5351_OUTPUT_CLK_DIV_MASK
,
1082 rdiv
<< SI5351_OUTPUT_CLK_DIV_SHIFT
);
1085 si5351_set_bits(hwdata
->drvdata
,
1086 si5351_msynth_params_address(hwdata
->num
) + 2,
1087 SI5351_OUTPUT_CLK_DIV_MASK
,
1088 rdiv
<< SI5351_OUTPUT_CLK_DIV_SHIFT
);
1091 /* powerup clkout */
1092 si5351_set_bits(hwdata
->drvdata
, SI5351_CLK0_CTRL
+ hwdata
->num
,
1093 SI5351_CLK_POWERDOWN
, 0);
1095 dev_dbg(&hwdata
->drvdata
->client
->dev
,
1096 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1097 __func__
, __clk_get_name(hwdata
->hw
.clk
), (1 << rdiv
),
1103 static const struct clk_ops si5351_clkout_ops
= {
1104 .prepare
= si5351_clkout_prepare
,
1105 .unprepare
= si5351_clkout_unprepare
,
1106 .set_parent
= si5351_clkout_set_parent
,
1107 .get_parent
= si5351_clkout_get_parent
,
1108 .recalc_rate
= si5351_clkout_recalc_rate
,
1109 .round_rate
= si5351_clkout_round_rate
,
1110 .set_rate
= si5351_clkout_set_rate
,
1114 * Si5351 i2c probe and DT
1117 static const struct of_device_id si5351_dt_ids
[] = {
1118 { .compatible
= "silabs,si5351a", .data
= (void *)SI5351_VARIANT_A
, },
1119 { .compatible
= "silabs,si5351a-msop",
1120 .data
= (void *)SI5351_VARIANT_A3
, },
1121 { .compatible
= "silabs,si5351b", .data
= (void *)SI5351_VARIANT_B
, },
1122 { .compatible
= "silabs,si5351c", .data
= (void *)SI5351_VARIANT_C
, },
1125 MODULE_DEVICE_TABLE(of
, si5351_dt_ids
);
1127 static int si5351_dt_parse(struct i2c_client
*client
,
1128 enum si5351_variant variant
)
1130 struct device_node
*child
, *np
= client
->dev
.of_node
;
1131 struct si5351_platform_data
*pdata
;
1132 struct property
*prop
;
1140 pdata
= devm_kzalloc(&client
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1145 * property silabs,pll-source : <num src>, [<..>]
1146 * allow to selectively set pll source
1148 of_property_for_each_u32(np
, "silabs,pll-source", prop
, p
, num
) {
1150 dev_err(&client
->dev
,
1151 "invalid pll %d on pll-source prop\n", num
);
1155 p
= of_prop_next_u32(prop
, p
, &val
);
1157 dev_err(&client
->dev
,
1158 "missing pll-source for pll %d\n", num
);
1164 pdata
->pll_src
[num
] = SI5351_PLL_SRC_XTAL
;
1167 if (variant
!= SI5351_VARIANT_C
) {
1168 dev_err(&client
->dev
,
1169 "invalid parent %d for pll %d\n",
1173 pdata
->pll_src
[num
] = SI5351_PLL_SRC_CLKIN
;
1176 dev_err(&client
->dev
,
1177 "invalid parent %d for pll %d\n", val
, num
);
1182 /* per clkout properties */
1183 for_each_child_of_node(np
, child
) {
1184 if (of_property_read_u32(child
, "reg", &num
)) {
1185 dev_err(&client
->dev
, "missing reg property of %s\n",
1191 (variant
== SI5351_VARIANT_A3
&& num
>= 3)) {
1192 dev_err(&client
->dev
, "invalid clkout %d\n", num
);
1196 if (!of_property_read_u32(child
, "silabs,multisynth-source",
1200 pdata
->clkout
[num
].multisynth_src
=
1201 SI5351_MULTISYNTH_SRC_VCO0
;
1204 pdata
->clkout
[num
].multisynth_src
=
1205 SI5351_MULTISYNTH_SRC_VCO1
;
1208 dev_err(&client
->dev
,
1209 "invalid parent %d for multisynth %d\n",
1215 if (!of_property_read_u32(child
, "silabs,clock-source", &val
)) {
1218 pdata
->clkout
[num
].clkout_src
=
1219 SI5351_CLKOUT_SRC_MSYNTH_N
;
1222 pdata
->clkout
[num
].clkout_src
=
1223 SI5351_CLKOUT_SRC_MSYNTH_0_4
;
1226 pdata
->clkout
[num
].clkout_src
=
1227 SI5351_CLKOUT_SRC_XTAL
;
1230 if (variant
!= SI5351_VARIANT_C
) {
1231 dev_err(&client
->dev
,
1232 "invalid parent %d for clkout %d\n",
1236 pdata
->clkout
[num
].clkout_src
=
1237 SI5351_CLKOUT_SRC_CLKIN
;
1240 dev_err(&client
->dev
,
1241 "invalid parent %d for clkout %d\n",
1247 if (!of_property_read_u32(child
, "silabs,drive-strength",
1250 case SI5351_DRIVE_2MA
:
1251 case SI5351_DRIVE_4MA
:
1252 case SI5351_DRIVE_6MA
:
1253 case SI5351_DRIVE_8MA
:
1254 pdata
->clkout
[num
].drive
= val
;
1257 dev_err(&client
->dev
,
1258 "invalid drive strength %d for clkout %d\n",
1264 if (!of_property_read_u32(child
, "silabs,disable-state",
1268 pdata
->clkout
[num
].disable_state
=
1272 pdata
->clkout
[num
].disable_state
=
1273 SI5351_DISABLE_HIGH
;
1276 pdata
->clkout
[num
].disable_state
=
1277 SI5351_DISABLE_FLOATING
;
1280 pdata
->clkout
[num
].disable_state
=
1281 SI5351_DISABLE_NEVER
;
1284 dev_err(&client
->dev
,
1285 "invalid disable state %d for clkout %d\n",
1291 if (!of_property_read_u32(child
, "clock-frequency", &val
))
1292 pdata
->clkout
[num
].rate
= val
;
1294 pdata
->clkout
[num
].pll_master
=
1295 of_property_read_bool(child
, "silabs,pll-master");
1297 client
->dev
.platform_data
= pdata
;
1302 static int si5351_dt_parse(struct i2c_client
*client
, enum si5351_variant variant
)
1306 #endif /* CONFIG_OF */
1308 static int si5351_i2c_probe(struct i2c_client
*client
,
1309 const struct i2c_device_id
*id
)
1311 enum si5351_variant variant
= (enum si5351_variant
)id
->driver_data
;
1312 struct si5351_platform_data
*pdata
;
1313 struct si5351_driver_data
*drvdata
;
1314 struct clk_init_data init
;
1316 const char *parent_names
[4];
1317 u8 num_parents
, num_clocks
;
1320 ret
= si5351_dt_parse(client
, variant
);
1324 pdata
= client
->dev
.platform_data
;
1328 drvdata
= devm_kzalloc(&client
->dev
, sizeof(*drvdata
), GFP_KERNEL
);
1329 if (drvdata
== NULL
) {
1330 dev_err(&client
->dev
, "unable to allocate driver data\n");
1334 i2c_set_clientdata(client
, drvdata
);
1335 drvdata
->client
= client
;
1336 drvdata
->variant
= variant
;
1337 drvdata
->pxtal
= devm_clk_get(&client
->dev
, "xtal");
1338 drvdata
->pclkin
= devm_clk_get(&client
->dev
, "clkin");
1340 if (PTR_ERR(drvdata
->pxtal
) == -EPROBE_DEFER
||
1341 PTR_ERR(drvdata
->pclkin
) == -EPROBE_DEFER
)
1342 return -EPROBE_DEFER
;
1345 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
1346 * VARIANT_C can have CLKIN instead.
1348 if (IS_ERR(drvdata
->pxtal
) &&
1349 (drvdata
->variant
!= SI5351_VARIANT_C
|| IS_ERR(drvdata
->pclkin
))) {
1350 dev_err(&client
->dev
, "missing parent clock\n");
1354 drvdata
->regmap
= devm_regmap_init_i2c(client
, &si5351_regmap_config
);
1355 if (IS_ERR(drvdata
->regmap
)) {
1356 dev_err(&client
->dev
, "failed to allocate register map\n");
1357 return PTR_ERR(drvdata
->regmap
);
1360 /* Disable interrupts */
1361 si5351_reg_write(drvdata
, SI5351_INTERRUPT_MASK
, 0xf0);
1362 /* Ensure pll select is on XTAL for Si5351A/B */
1363 if (drvdata
->variant
!= SI5351_VARIANT_C
)
1364 si5351_set_bits(drvdata
, SI5351_PLL_INPUT_SOURCE
,
1365 SI5351_PLLA_SOURCE
| SI5351_PLLB_SOURCE
, 0);
1367 /* setup clock configuration */
1368 for (n
= 0; n
< 2; n
++) {
1369 ret
= _si5351_pll_reparent(drvdata
, n
, pdata
->pll_src
[n
]);
1371 dev_err(&client
->dev
,
1372 "failed to reparent pll %d to %d\n",
1373 n
, pdata
->pll_src
[n
]);
1378 for (n
= 0; n
< 8; n
++) {
1379 ret
= _si5351_msynth_reparent(drvdata
, n
,
1380 pdata
->clkout
[n
].multisynth_src
);
1382 dev_err(&client
->dev
,
1383 "failed to reparent multisynth %d to %d\n",
1384 n
, pdata
->clkout
[n
].multisynth_src
);
1388 ret
= _si5351_clkout_reparent(drvdata
, n
,
1389 pdata
->clkout
[n
].clkout_src
);
1391 dev_err(&client
->dev
,
1392 "failed to reparent clkout %d to %d\n",
1393 n
, pdata
->clkout
[n
].clkout_src
);
1397 ret
= _si5351_clkout_set_drive_strength(drvdata
, n
,
1398 pdata
->clkout
[n
].drive
);
1400 dev_err(&client
->dev
,
1401 "failed set drive strength of clkout%d to %d\n",
1402 n
, pdata
->clkout
[n
].drive
);
1406 ret
= _si5351_clkout_set_disable_state(drvdata
, n
,
1407 pdata
->clkout
[n
].disable_state
);
1409 dev_err(&client
->dev
,
1410 "failed set disable state of clkout%d to %d\n",
1411 n
, pdata
->clkout
[n
].disable_state
);
1416 if (!IS_ERR(drvdata
->pxtal
))
1417 clk_prepare_enable(drvdata
->pxtal
);
1418 if (!IS_ERR(drvdata
->pclkin
))
1419 clk_prepare_enable(drvdata
->pclkin
);
1421 /* register xtal input clock gate */
1422 memset(&init
, 0, sizeof(init
));
1423 init
.name
= si5351_input_names
[0];
1424 init
.ops
= &si5351_xtal_ops
;
1426 if (!IS_ERR(drvdata
->pxtal
)) {
1427 drvdata
->pxtal_name
= __clk_get_name(drvdata
->pxtal
);
1428 init
.parent_names
= &drvdata
->pxtal_name
;
1429 init
.num_parents
= 1;
1431 drvdata
->xtal
.init
= &init
;
1432 clk
= devm_clk_register(&client
->dev
, &drvdata
->xtal
);
1434 dev_err(&client
->dev
, "unable to register %s\n", init
.name
);
1439 /* register clkin input clock gate */
1440 if (drvdata
->variant
== SI5351_VARIANT_C
) {
1441 memset(&init
, 0, sizeof(init
));
1442 init
.name
= si5351_input_names
[1];
1443 init
.ops
= &si5351_clkin_ops
;
1444 if (!IS_ERR(drvdata
->pclkin
)) {
1445 drvdata
->pclkin_name
= __clk_get_name(drvdata
->pclkin
);
1446 init
.parent_names
= &drvdata
->pclkin_name
;
1447 init
.num_parents
= 1;
1449 drvdata
->clkin
.init
= &init
;
1450 clk
= devm_clk_register(&client
->dev
, &drvdata
->clkin
);
1452 dev_err(&client
->dev
, "unable to register %s\n",
1459 /* Si5351C allows to mux either xtal or clkin to PLL input */
1460 num_parents
= (drvdata
->variant
== SI5351_VARIANT_C
) ? 2 : 1;
1461 parent_names
[0] = si5351_input_names
[0];
1462 parent_names
[1] = si5351_input_names
[1];
1465 drvdata
->pll
[0].num
= 0;
1466 drvdata
->pll
[0].drvdata
= drvdata
;
1467 drvdata
->pll
[0].hw
.init
= &init
;
1468 memset(&init
, 0, sizeof(init
));
1469 init
.name
= si5351_pll_names
[0];
1470 init
.ops
= &si5351_pll_ops
;
1472 init
.parent_names
= parent_names
;
1473 init
.num_parents
= num_parents
;
1474 clk
= devm_clk_register(&client
->dev
, &drvdata
->pll
[0].hw
);
1476 dev_err(&client
->dev
, "unable to register %s\n", init
.name
);
1481 /* register PLLB or VXCO (Si5351B) */
1482 drvdata
->pll
[1].num
= 1;
1483 drvdata
->pll
[1].drvdata
= drvdata
;
1484 drvdata
->pll
[1].hw
.init
= &init
;
1485 memset(&init
, 0, sizeof(init
));
1486 if (drvdata
->variant
== SI5351_VARIANT_B
) {
1487 init
.name
= si5351_pll_names
[2];
1488 init
.ops
= &si5351_vxco_ops
;
1489 init
.flags
= CLK_IS_ROOT
;
1490 init
.parent_names
= NULL
;
1491 init
.num_parents
= 0;
1493 init
.name
= si5351_pll_names
[1];
1494 init
.ops
= &si5351_pll_ops
;
1496 init
.parent_names
= parent_names
;
1497 init
.num_parents
= num_parents
;
1499 clk
= devm_clk_register(&client
->dev
, &drvdata
->pll
[1].hw
);
1501 dev_err(&client
->dev
, "unable to register %s\n", init
.name
);
1506 /* register clk multisync and clk out divider */
1507 num_clocks
= (drvdata
->variant
== SI5351_VARIANT_A3
) ? 3 : 8;
1508 parent_names
[0] = si5351_pll_names
[0];
1509 if (drvdata
->variant
== SI5351_VARIANT_B
)
1510 parent_names
[1] = si5351_pll_names
[2];
1512 parent_names
[1] = si5351_pll_names
[1];
1514 drvdata
->msynth
= devm_kzalloc(&client
->dev
, num_clocks
*
1515 sizeof(*drvdata
->msynth
), GFP_KERNEL
);
1516 drvdata
->clkout
= devm_kzalloc(&client
->dev
, num_clocks
*
1517 sizeof(*drvdata
->clkout
), GFP_KERNEL
);
1519 drvdata
->onecell
.clk_num
= num_clocks
;
1520 drvdata
->onecell
.clks
= devm_kzalloc(&client
->dev
,
1521 num_clocks
* sizeof(*drvdata
->onecell
.clks
), GFP_KERNEL
);
1523 if (WARN_ON(!drvdata
->msynth
|| !drvdata
->clkout
||
1524 !drvdata
->onecell
.clks
)) {
1529 for (n
= 0; n
< num_clocks
; n
++) {
1530 drvdata
->msynth
[n
].num
= n
;
1531 drvdata
->msynth
[n
].drvdata
= drvdata
;
1532 drvdata
->msynth
[n
].hw
.init
= &init
;
1533 memset(&init
, 0, sizeof(init
));
1534 init
.name
= si5351_msynth_names
[n
];
1535 init
.ops
= &si5351_msynth_ops
;
1537 if (pdata
->clkout
[n
].pll_master
)
1538 init
.flags
|= CLK_SET_RATE_PARENT
;
1539 init
.parent_names
= parent_names
;
1540 init
.num_parents
= 2;
1541 clk
= devm_clk_register(&client
->dev
, &drvdata
->msynth
[n
].hw
);
1543 dev_err(&client
->dev
, "unable to register %s\n",
1550 num_parents
= (drvdata
->variant
== SI5351_VARIANT_C
) ? 4 : 3;
1551 parent_names
[2] = si5351_input_names
[0];
1552 parent_names
[3] = si5351_input_names
[1];
1553 for (n
= 0; n
< num_clocks
; n
++) {
1554 parent_names
[0] = si5351_msynth_names
[n
];
1555 parent_names
[1] = (n
< 4) ? si5351_msynth_names
[0] :
1556 si5351_msynth_names
[4];
1558 drvdata
->clkout
[n
].num
= n
;
1559 drvdata
->clkout
[n
].drvdata
= drvdata
;
1560 drvdata
->clkout
[n
].hw
.init
= &init
;
1561 memset(&init
, 0, sizeof(init
));
1562 init
.name
= si5351_clkout_names
[n
];
1563 init
.ops
= &si5351_clkout_ops
;
1565 if (pdata
->clkout
[n
].clkout_src
== SI5351_CLKOUT_SRC_MSYNTH_N
)
1566 init
.flags
|= CLK_SET_RATE_PARENT
;
1567 init
.parent_names
= parent_names
;
1568 init
.num_parents
= num_parents
;
1569 clk
= devm_clk_register(&client
->dev
, &drvdata
->clkout
[n
].hw
);
1571 dev_err(&client
->dev
, "unable to register %s\n",
1576 drvdata
->onecell
.clks
[n
] = clk
;
1578 /* set initial clkout rate */
1579 if (pdata
->clkout
[n
].rate
!= 0) {
1581 ret
= clk_set_rate(clk
, pdata
->clkout
[n
].rate
);
1583 dev_err(&client
->dev
, "Cannot set rate : %d\n",
1589 ret
= of_clk_add_provider(client
->dev
.of_node
, of_clk_src_onecell_get
,
1592 dev_err(&client
->dev
, "unable to add clk provider\n");
1599 if (!IS_ERR(drvdata
->pxtal
))
1600 clk_disable_unprepare(drvdata
->pxtal
);
1601 if (!IS_ERR(drvdata
->pclkin
))
1602 clk_disable_unprepare(drvdata
->pclkin
);
1606 static const struct i2c_device_id si5351_i2c_ids
[] = {
1607 { "si5351a", SI5351_VARIANT_A
},
1608 { "si5351a-msop", SI5351_VARIANT_A3
},
1609 { "si5351b", SI5351_VARIANT_B
},
1610 { "si5351c", SI5351_VARIANT_C
},
1613 MODULE_DEVICE_TABLE(i2c
, si5351_i2c_ids
);
1615 static struct i2c_driver si5351_driver
= {
1618 .of_match_table
= of_match_ptr(si5351_dt_ids
),
1620 .probe
= si5351_i2c_probe
,
1621 .id_table
= si5351_i2c_ids
,
1623 module_i2c_driver(si5351_driver
);
1625 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
1626 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
1627 MODULE_LICENSE("GPL");