drivers/clk/clk-wm831x.c

   1 /*
   2  * WM831x clock control
   3  *
   4  * Copyright 2011-2 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/module.h>
  18 #include <linux/slab.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/mfd/wm831x/core.h>
  21
  22 struct wm831x_clk {
  23         struct wm831x *wm831x;
  24         struct clk_hw xtal_hw;
  25         struct clk_hw fll_hw;
  26         struct clk_hw clkout_hw;
  27         struct clk *xtal;
  28         struct clk *fll;
  29         struct clk *clkout;
  30         bool xtal_ena;
  31 };
  32
  33 static int wm831x_xtal_is_prepared(struct clk_hw *hw)
  34 {
  35         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  36                                                   xtal_hw);
  37
  38         return clkdata->xtal_ena;
  39 }
  40
  41 static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
  42                                              unsigned long parent_rate)
  43 {
  44         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  45                                                   xtal_hw);
  46
  47         if (clkdata->xtal_ena)
  48                 return 32768;
  49         else
  50                 return 0;
  51 }
  52
  53 static const struct clk_ops wm831x_xtal_ops = {
  54         .is_prepared = wm831x_xtal_is_prepared,
  55         .recalc_rate = wm831x_xtal_recalc_rate,
  56 };
  57
  58 static struct clk_init_data wm831x_xtal_init = {
  59         .name = "xtal",
  60         .ops = &wm831x_xtal_ops,
  61 };
  62
  63 static const unsigned long wm831x_fll_auto_rates[] = {
  64          2048000,
  65         11289600,
  66         12000000,
  67         12288000,
  68         19200000,
  69         22579600,
  70         24000000,
  71         24576000,
  72 };
  73
  74 static int wm831x_fll_is_prepared(struct clk_hw *hw)
  75 {
  76         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  77                                                   fll_hw);
  78         struct wm831x *wm831x = clkdata->wm831x;
  79         int ret;
  80
  81         ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
  82         if (ret < 0) {
  83                 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
  84                         ret);
  85                 return true;
  86         }
  87
  88         return (ret & WM831X_FLL_ENA) != 0;
  89 }
  90
  91 static int wm831x_fll_prepare(struct clk_hw *hw)
  92 {
  93         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  94                                                   fll_hw);
  95         struct wm831x *wm831x = clkdata->wm831x;
  96         int ret;
  97
  98         ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
  99                               WM831X_FLL_ENA, WM831X_FLL_ENA);
 100         if (ret != 0)
 101                 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
 102
 103         usleep_range(2000, 2000);
 104
 105         return ret;
 106 }
 107
 108 static void wm831x_fll_unprepare(struct clk_hw *hw)
 109 {
 110         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 111                                                   fll_hw);
 112         struct wm831x *wm831x = clkdata->wm831x;
 113         int ret;
 114
 115         ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
 116         if (ret != 0)
 117                 dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
 118 }
 119
 120 static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
 121                                             unsigned long parent_rate)
 122 {
 123         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 124                                                   fll_hw);
 125         struct wm831x *wm831x = clkdata->wm831x;
 126         int ret;
 127
 128         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
 129         if (ret < 0) {
 130                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
 131                         ret);
 132                 return 0;
 133         }
 134
 135         if (ret & WM831X_FLL_AUTO)
 136                 return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
 137
 138         dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
 139
 140         return 0;
 141 }
 142
 143 static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
 144                                   unsigned long *unused)
 145 {
 146         int best = 0;
 147         int i;
 148
 149         for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
 150                 if (abs(wm831x_fll_auto_rates[i] - rate) <
 151                     abs(wm831x_fll_auto_rates[best] - rate))
 152                         best = i;
 153
 154         return wm831x_fll_auto_rates[best];
 155 }
 156
 157 static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
 158                                unsigned long parent_rate)
 159 {
 160         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 161                                                   fll_hw);
 162         struct wm831x *wm831x = clkdata->wm831x;
 163         int i;
 164
 165         for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
 166                 if (wm831x_fll_auto_rates[i] == rate)
 167                         break;
 168         if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
 169                 return -EINVAL;
 170
 171         if (wm831x_fll_is_prepared(hw))
 172                 return -EPERM;
 173
 174         return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
 175                                WM831X_FLL_AUTO_FREQ_MASK, i);
 176 }
 177
 178 static const char *wm831x_fll_parents[] = {
 179         "xtal",
 180         "clkin",
 181 };
 182
 183 static u8 wm831x_fll_get_parent(struct clk_hw *hw)
 184 {
 185         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 186                                                   fll_hw);
 187         struct wm831x *wm831x = clkdata->wm831x;
 188         int ret;
 189
 190         /* AUTO mode is always clocked from the crystal */
 191         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
 192         if (ret < 0) {
 193                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
 194                         ret);
 195                 return 0;
 196         }
 197
 198         if (ret & WM831X_FLL_AUTO)
 199                 return 0;
 200
 201         ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
 202         if (ret < 0) {
 203                 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
 204                         ret);
 205                 return 0;
 206         }
 207
 208         switch (ret & WM831X_FLL_CLK_SRC_MASK) {
 209         case 0:
 210                 return 0;
 211         case 1:
 212                 return 1;
 213         default:
 214                 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
 215                         ret & WM831X_FLL_CLK_SRC_MASK);
 216                 return 0;
 217         }
 218 }
 219
 220 static const struct clk_ops wm831x_fll_ops = {
 221         .is_prepared = wm831x_fll_is_prepared,
 222         .prepare = wm831x_fll_prepare,
 223         .unprepare = wm831x_fll_unprepare,
 224         .round_rate = wm831x_fll_round_rate,
 225         .recalc_rate = wm831x_fll_recalc_rate,
 226         .set_rate = wm831x_fll_set_rate,
 227         .get_parent = wm831x_fll_get_parent,
 228 };
 229
 230 static struct clk_init_data wm831x_fll_init = {
 231         .name = "fll",
 232         .ops = &wm831x_fll_ops,
 233         .parent_names = wm831x_fll_parents,
 234         .num_parents = ARRAY_SIZE(wm831x_fll_parents),
 235         .flags = CLK_SET_RATE_GATE,
 236 };
 237
 238 static int wm831x_clkout_is_prepared(struct clk_hw *hw)
 239 {
 240         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 241                                                   clkout_hw);
 242         struct wm831x *wm831x = clkdata->wm831x;
 243         int ret;
 244
 245         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
 246         if (ret < 0) {
 247                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
 248                         ret);
 249                 return true;
 250         }
 251
 252         return (ret & WM831X_CLKOUT_ENA) != 0;
 253 }
 254
 255 static int wm831x_clkout_prepare(struct clk_hw *hw)
 256 {
 257         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 258                                                   clkout_hw);
 259         struct wm831x *wm831x = clkdata->wm831x;
 260         int ret;
 261
 262         ret = wm831x_reg_unlock(wm831x);
 263         if (ret != 0) {
 264                 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
 265                 return ret;
 266         }
 267
 268         ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
 269                               WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
 270         if (ret != 0)
 271                 dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
 272
 273         wm831x_reg_lock(wm831x);
 274
 275         return ret;
 276 }
 277
 278 static void wm831x_clkout_unprepare(struct clk_hw *hw)
 279 {
 280         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 281                                                   clkout_hw);
 282         struct wm831x *wm831x = clkdata->wm831x;
 283         int ret;
 284
 285         ret = wm831x_reg_unlock(wm831x);
 286         if (ret != 0) {
 287                 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
 288                 return;
 289         }
 290
 291         ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
 292                               WM831X_CLKOUT_ENA, 0);
 293         if (ret != 0)
 294                 dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
 295
 296         wm831x_reg_lock(wm831x);
 297 }
 298
 299 static const char *wm831x_clkout_parents[] = {
 300         "fll",
 301         "xtal",
 302 };
 303
 304 static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
 305 {
 306         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 307                                                   clkout_hw);
 308         struct wm831x *wm831x = clkdata->wm831x;
 309         int ret;
 310
 311         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
 312         if (ret < 0) {
 313                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
 314                         ret);
 315                 return 0;
 316         }
 317
 318         if (ret & WM831X_CLKOUT_SRC)
 319                 return 1;
 320         else
 321                 return 0;
 322 }
 323
 324 static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
 325 {
 326         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
 327                                                   clkout_hw);
 328         struct wm831x *wm831x = clkdata->wm831x;
 329
 330         return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
 331                                WM831X_CLKOUT_SRC,
 332                                parent << WM831X_CLKOUT_SRC_SHIFT);
 333 }
 334
 335 static const struct clk_ops wm831x_clkout_ops = {
 336         .is_prepared = wm831x_clkout_is_prepared,
 337         .prepare = wm831x_clkout_prepare,
 338         .unprepare = wm831x_clkout_unprepare,
 339         .get_parent = wm831x_clkout_get_parent,
 340         .set_parent = wm831x_clkout_set_parent,
 341 };
 342
 343 static struct clk_init_data wm831x_clkout_init = {
 344         .name = "clkout",
 345         .ops = &wm831x_clkout_ops,
 346         .parent_names = wm831x_clkout_parents,
 347         .num_parents = ARRAY_SIZE(wm831x_clkout_parents),
 348         .flags = CLK_SET_RATE_PARENT,
 349 };
 350
 351 static int wm831x_clk_probe(struct platform_device *pdev)
 352 {
 353         struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
 354         struct wm831x_clk *clkdata;
 355         int ret;
 356
 357         clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
 358         if (!clkdata)
 359                 return -ENOMEM;
 360
 361         clkdata->wm831x = wm831x;
 362
 363         /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
 364         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
 365         if (ret < 0) {
 366                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
 367                         ret);
 368                 return ret;
 369         }
 370         clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
 371
 372         clkdata->xtal_hw.init = &wm831x_xtal_init;
 373         clkdata->xtal = devm_clk_register(&pdev->dev, &clkdata->xtal_hw);
 374         if (IS_ERR(clkdata->xtal))
 375                 return PTR_ERR(clkdata->xtal);
 376
 377         clkdata->fll_hw.init = &wm831x_fll_init;
 378         clkdata->fll = devm_clk_register(&pdev->dev, &clkdata->fll_hw);
 379         if (IS_ERR(clkdata->fll))
 380                 return PTR_ERR(clkdata->fll);
 381
 382         clkdata->clkout_hw.init = &wm831x_clkout_init;
 383         clkdata->clkout = devm_clk_register(&pdev->dev, &clkdata->clkout_hw);
 384         if (IS_ERR(clkdata->clkout))
 385                 return PTR_ERR(clkdata->clkout);
 386
 387         platform_set_drvdata(pdev, clkdata);
 388
 389         return 0;
 390 }
 391
 392 static struct platform_driver wm831x_clk_driver = {
 393         .probe = wm831x_clk_probe,
 394         .driver         = {
 395                 .name   = "wm831x-clk",
 396         },
 397 };
 398
 399 module_platform_driver(wm831x_clk_driver);
 400
 401 /* Module information */
 402 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 403 MODULE_DESCRIPTION("WM831x clock driver");
 404 MODULE_LICENSE("GPL");
 405 MODULE_ALIAS("platform:wm831x-clk");