2 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
4 * Copyright (c) 2013, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
27 #include <linux/clkdev.h>
28 #include <linux/clk-provider.h>
29 #include <linux/of_address.h>
30 #include <asm/setup.h>
32 /* Register SCU_PCPPLL bit fields */
33 #define N_DIV_RD(src) (((src) & 0x000001ff))
35 /* Register SCU_SOCPLL bit fields */
36 #define CLKR_RD(src) (((src) & 0x07000000)>>24)
37 #define CLKOD_RD(src) (((src) & 0x00300000)>>20)
38 #define REGSPEC_RESET_F1_MASK 0x00010000
39 #define CLKF_RD(src) (((src) & 0x000001ff))
41 #define XGENE_CLK_DRIVER_VER "0.1"
43 static DEFINE_SPINLOCK(clk_lock
);
45 static inline u32
xgene_clk_read(void __iomem
*csr
)
47 return readl_relaxed(csr
);
50 static inline void xgene_clk_write(u32 data
, void __iomem
*csr
)
52 return writel_relaxed(data
, csr
);
61 struct xgene_clk_pll
{
66 enum xgene_pll_type type
;
69 #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
71 static int xgene_clk_pll_is_enabled(struct clk_hw
*hw
)
73 struct xgene_clk_pll
*pllclk
= to_xgene_clk_pll(hw
);
76 data
= xgene_clk_read(pllclk
->reg
+ pllclk
->pll_offset
);
77 pr_debug("%s pll %s\n", clk_hw_get_name(hw
),
78 data
& REGSPEC_RESET_F1_MASK
? "disabled" : "enabled");
80 return data
& REGSPEC_RESET_F1_MASK
? 0 : 1;
83 static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw
*hw
,
84 unsigned long parent_rate
)
86 struct xgene_clk_pll
*pllclk
= to_xgene_clk_pll(hw
);
94 pll
= xgene_clk_read(pllclk
->reg
+ pllclk
->pll_offset
);
96 if (pllclk
->type
== PLL_TYPE_PCP
) {
98 * PLL VCO = Reference clock * NF
99 * PCP PLL = PLL_VCO / 2
102 fvco
= parent_rate
* (N_DIV_RD(pll
) + 4);
105 * Fref = Reference Clock / NREF;
107 * Fout = Fvco / NOUT;
109 nref
= CLKR_RD(pll
) + 1;
110 nout
= CLKOD_RD(pll
) + 1;
112 fref
= parent_rate
/ nref
;
115 pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw
),
116 fvco
/ nout
, parent_rate
);
121 static const struct clk_ops xgene_clk_pll_ops
= {
122 .is_enabled
= xgene_clk_pll_is_enabled
,
123 .recalc_rate
= xgene_clk_pll_recalc_rate
,
126 static struct clk
*xgene_register_clk_pll(struct device
*dev
,
127 const char *name
, const char *parent_name
,
128 unsigned long flags
, void __iomem
*reg
, u32 pll_offset
,
129 u32 type
, spinlock_t
*lock
)
131 struct xgene_clk_pll
*apmclk
;
133 struct clk_init_data init
;
135 /* allocate the APM clock structure */
136 apmclk
= kzalloc(sizeof(*apmclk
), GFP_KERNEL
);
138 pr_err("%s: could not allocate APM clk\n", __func__
);
139 return ERR_PTR(-ENOMEM
);
143 init
.ops
= &xgene_clk_pll_ops
;
145 init
.parent_names
= parent_name
? &parent_name
: NULL
;
146 init
.num_parents
= parent_name
? 1 : 0;
150 apmclk
->pll_offset
= pll_offset
;
152 apmclk
->hw
.init
= &init
;
154 /* Register the clock */
155 clk
= clk_register(dev
, &apmclk
->hw
);
157 pr_err("%s: could not register clk %s\n", __func__
, name
);
164 static void xgene_pllclk_init(struct device_node
*np
, enum xgene_pll_type pll_type
)
166 const char *clk_name
= np
->full_name
;
170 reg
= of_iomap(np
, 0);
172 pr_err("Unable to map CSR register for %s\n", np
->full_name
);
175 of_property_read_string(np
, "clock-output-names", &clk_name
);
176 clk
= xgene_register_clk_pll(NULL
,
177 clk_name
, of_clk_get_parent_name(np
, 0),
178 CLK_IS_ROOT
, reg
, 0, pll_type
, &clk_lock
);
180 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
181 clk_register_clkdev(clk
, clk_name
, NULL
);
182 pr_debug("Add %s clock PLL\n", clk_name
);
186 static void xgene_socpllclk_init(struct device_node
*np
)
188 xgene_pllclk_init(np
, PLL_TYPE_SOC
);
191 static void xgene_pcppllclk_init(struct device_node
*np
)
193 xgene_pllclk_init(np
, PLL_TYPE_PCP
);
197 struct xgene_dev_parameters
{
198 void __iomem
*csr_reg
; /* CSR for IP clock */
199 u32 reg_clk_offset
; /* Offset to clock enable CSR */
200 u32 reg_clk_mask
; /* Mask bit for clock enable */
201 u32 reg_csr_offset
; /* Offset to CSR reset */
202 u32 reg_csr_mask
; /* Mask bit for disable CSR reset */
203 void __iomem
*divider_reg
; /* CSR for divider */
204 u32 reg_divider_offset
; /* Offset to divider register */
205 u32 reg_divider_shift
; /* Bit shift to divider field */
206 u32 reg_divider_width
; /* Width of the bit to divider field */
212 struct xgene_dev_parameters param
;
215 #define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)
217 static int xgene_clk_enable(struct clk_hw
*hw
)
219 struct xgene_clk
*pclk
= to_xgene_clk(hw
);
220 unsigned long flags
= 0;
225 spin_lock_irqsave(pclk
->lock
, flags
);
227 if (pclk
->param
.csr_reg
!= NULL
) {
228 pr_debug("%s clock enabled\n", clk_hw_get_name(hw
));
229 reg
= __pa(pclk
->param
.csr_reg
);
230 /* First enable the clock */
231 data
= xgene_clk_read(pclk
->param
.csr_reg
+
232 pclk
->param
.reg_clk_offset
);
233 data
|= pclk
->param
.reg_clk_mask
;
234 xgene_clk_write(data
, pclk
->param
.csr_reg
+
235 pclk
->param
.reg_clk_offset
);
236 pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
237 clk_hw_get_name(hw
), ®
,
238 pclk
->param
.reg_clk_offset
, pclk
->param
.reg_clk_mask
,
241 /* Second enable the CSR */
242 data
= xgene_clk_read(pclk
->param
.csr_reg
+
243 pclk
->param
.reg_csr_offset
);
244 data
&= ~pclk
->param
.reg_csr_mask
;
245 xgene_clk_write(data
, pclk
->param
.csr_reg
+
246 pclk
->param
.reg_csr_offset
);
247 pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
248 clk_hw_get_name(hw
), ®
,
249 pclk
->param
.reg_csr_offset
, pclk
->param
.reg_csr_mask
,
254 spin_unlock_irqrestore(pclk
->lock
, flags
);
259 static void xgene_clk_disable(struct clk_hw
*hw
)
261 struct xgene_clk
*pclk
= to_xgene_clk(hw
);
262 unsigned long flags
= 0;
266 spin_lock_irqsave(pclk
->lock
, flags
);
268 if (pclk
->param
.csr_reg
!= NULL
) {
269 pr_debug("%s clock disabled\n", clk_hw_get_name(hw
));
270 /* First put the CSR in reset */
271 data
= xgene_clk_read(pclk
->param
.csr_reg
+
272 pclk
->param
.reg_csr_offset
);
273 data
|= pclk
->param
.reg_csr_mask
;
274 xgene_clk_write(data
, pclk
->param
.csr_reg
+
275 pclk
->param
.reg_csr_offset
);
277 /* Second disable the clock */
278 data
= xgene_clk_read(pclk
->param
.csr_reg
+
279 pclk
->param
.reg_clk_offset
);
280 data
&= ~pclk
->param
.reg_clk_mask
;
281 xgene_clk_write(data
, pclk
->param
.csr_reg
+
282 pclk
->param
.reg_clk_offset
);
286 spin_unlock_irqrestore(pclk
->lock
, flags
);
289 static int xgene_clk_is_enabled(struct clk_hw
*hw
)
291 struct xgene_clk
*pclk
= to_xgene_clk(hw
);
294 if (pclk
->param
.csr_reg
!= NULL
) {
295 pr_debug("%s clock checking\n", clk_hw_get_name(hw
));
296 data
= xgene_clk_read(pclk
->param
.csr_reg
+
297 pclk
->param
.reg_clk_offset
);
298 pr_debug("%s clock is %s\n", clk_hw_get_name(hw
),
299 data
& pclk
->param
.reg_clk_mask
? "enabled" :
303 if (pclk
->param
.csr_reg
== NULL
)
305 return data
& pclk
->param
.reg_clk_mask
? 1 : 0;
308 static unsigned long xgene_clk_recalc_rate(struct clk_hw
*hw
,
309 unsigned long parent_rate
)
311 struct xgene_clk
*pclk
= to_xgene_clk(hw
);
314 if (pclk
->param
.divider_reg
) {
315 data
= xgene_clk_read(pclk
->param
.divider_reg
+
316 pclk
->param
.reg_divider_offset
);
317 data
>>= pclk
->param
.reg_divider_shift
;
318 data
&= (1 << pclk
->param
.reg_divider_width
) - 1;
320 pr_debug("%s clock recalc rate %ld parent %ld\n",
322 parent_rate
/ data
, parent_rate
);
324 return parent_rate
/ data
;
326 pr_debug("%s clock recalc rate %ld parent %ld\n",
327 clk_hw_get_name(hw
), parent_rate
, parent_rate
);
332 static int xgene_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
333 unsigned long parent_rate
)
335 struct xgene_clk
*pclk
= to_xgene_clk(hw
);
336 unsigned long flags
= 0;
342 spin_lock_irqsave(pclk
->lock
, flags
);
344 if (pclk
->param
.divider_reg
) {
345 /* Let's compute the divider */
346 if (rate
> parent_rate
)
348 divider_save
= divider
= parent_rate
/ rate
; /* Rounded down */
349 divider
&= (1 << pclk
->param
.reg_divider_width
) - 1;
350 divider
<<= pclk
->param
.reg_divider_shift
;
352 /* Set new divider */
353 data
= xgene_clk_read(pclk
->param
.divider_reg
+
354 pclk
->param
.reg_divider_offset
);
355 data
&= ~((1 << pclk
->param
.reg_divider_width
) - 1);
357 xgene_clk_write(data
, pclk
->param
.divider_reg
+
358 pclk
->param
.reg_divider_offset
);
359 pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw
),
360 parent_rate
/ divider_save
);
366 spin_unlock_irqrestore(pclk
->lock
, flags
);
368 return parent_rate
/ divider_save
;
371 static long xgene_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
372 unsigned long *prate
)
374 struct xgene_clk
*pclk
= to_xgene_clk(hw
);
375 unsigned long parent_rate
= *prate
;
378 if (pclk
->param
.divider_reg
) {
379 /* Let's compute the divider */
380 if (rate
> parent_rate
)
382 divider
= parent_rate
/ rate
; /* Rounded down */
387 return parent_rate
/ divider
;
390 static const struct clk_ops xgene_clk_ops
= {
391 .enable
= xgene_clk_enable
,
392 .disable
= xgene_clk_disable
,
393 .is_enabled
= xgene_clk_is_enabled
,
394 .recalc_rate
= xgene_clk_recalc_rate
,
395 .set_rate
= xgene_clk_set_rate
,
396 .round_rate
= xgene_clk_round_rate
,
399 static struct clk
*xgene_register_clk(struct device
*dev
,
400 const char *name
, const char *parent_name
,
401 struct xgene_dev_parameters
*parameters
, spinlock_t
*lock
)
403 struct xgene_clk
*apmclk
;
405 struct clk_init_data init
;
408 /* allocate the APM clock structure */
409 apmclk
= kzalloc(sizeof(*apmclk
), GFP_KERNEL
);
411 pr_err("%s: could not allocate APM clk\n", __func__
);
412 return ERR_PTR(-ENOMEM
);
416 init
.ops
= &xgene_clk_ops
;
418 init
.parent_names
= parent_name
? &parent_name
: NULL
;
419 init
.num_parents
= parent_name
? 1 : 0;
422 apmclk
->hw
.init
= &init
;
423 apmclk
->param
= *parameters
;
425 /* Register the clock */
426 clk
= clk_register(dev
, &apmclk
->hw
);
428 pr_err("%s: could not register clk %s\n", __func__
, name
);
433 /* Register the clock for lookup */
434 rc
= clk_register_clkdev(clk
, name
, NULL
);
436 pr_err("%s: could not register lookup clk %s\n",
442 static void __init
xgene_devclk_init(struct device_node
*np
)
444 const char *clk_name
= np
->full_name
;
448 struct xgene_dev_parameters parameters
;
451 /* Check if the entry is disabled */
452 if (!of_device_is_available(np
))
455 /* Parse the DTS register for resource */
456 parameters
.csr_reg
= NULL
;
457 parameters
.divider_reg
= NULL
;
458 for (i
= 0; i
< 2; i
++) {
459 void __iomem
*map_res
;
460 rc
= of_address_to_resource(np
, i
, &res
);
463 pr_err("no DTS register for %s\n",
469 map_res
= of_iomap(np
, i
);
470 if (map_res
== NULL
) {
471 pr_err("Unable to map resource %d for %s\n",
475 if (strcmp(res
.name
, "div-reg") == 0)
476 parameters
.divider_reg
= map_res
;
477 else /* if (strcmp(res->name, "csr-reg") == 0) */
478 parameters
.csr_reg
= map_res
;
480 if (of_property_read_u32(np
, "csr-offset", ¶meters
.reg_csr_offset
))
481 parameters
.reg_csr_offset
= 0;
482 if (of_property_read_u32(np
, "csr-mask", ¶meters
.reg_csr_mask
))
483 parameters
.reg_csr_mask
= 0xF;
484 if (of_property_read_u32(np
, "enable-offset",
485 ¶meters
.reg_clk_offset
))
486 parameters
.reg_clk_offset
= 0x8;
487 if (of_property_read_u32(np
, "enable-mask", ¶meters
.reg_clk_mask
))
488 parameters
.reg_clk_mask
= 0xF;
489 if (of_property_read_u32(np
, "divider-offset",
490 ¶meters
.reg_divider_offset
))
491 parameters
.reg_divider_offset
= 0;
492 if (of_property_read_u32(np
, "divider-width",
493 ¶meters
.reg_divider_width
))
494 parameters
.reg_divider_width
= 0;
495 if (of_property_read_u32(np
, "divider-shift",
496 ¶meters
.reg_divider_shift
))
497 parameters
.reg_divider_shift
= 0;
498 of_property_read_string(np
, "clock-output-names", &clk_name
);
500 clk
= xgene_register_clk(NULL
, clk_name
,
501 of_clk_get_parent_name(np
, 0), ¶meters
, &clk_lock
);
504 pr_debug("Add %s clock\n", clk_name
);
505 rc
= of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
507 pr_err("%s: could register provider clk %s\n", __func__
,
513 if (parameters
.csr_reg
)
514 iounmap(parameters
.csr_reg
);
515 if (parameters
.divider_reg
)
516 iounmap(parameters
.divider_reg
);
519 CLK_OF_DECLARE(xgene_socpll_clock
, "apm,xgene-socpll-clock", xgene_socpllclk_init
);
520 CLK_OF_DECLARE(xgene_pcppll_clock
, "apm,xgene-pcppll-clock", xgene_pcppllclk_init
);
521 CLK_OF_DECLARE(xgene_dev_clock
, "apm,xgene-device-clock", xgene_devclk_init
);