drivers/clk/keystone/gate.c

   1 /*
   2  * Clock driver for Keystone 2 based devices
   3  *
   4  * Copyright (C) 2013 Texas Instruments.
   5  *      Murali Karicheri <m-karicheri2@ti.com>
   6  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13 #include <linux/clk-provider.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/slab.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of.h>
  19 #include <linux/module.h>
  20
  21 /* PSC register offsets */
  22 #define PTCMD                   0x120
  23 #define PTSTAT                  0x128
  24 #define PDSTAT                  0x200
  25 #define PDCTL                   0x300
  26 #define MDSTAT                  0x800
  27 #define MDCTL                   0xa00
  28
  29 /* PSC module states */
  30 #define PSC_STATE_SWRSTDISABLE  0
  31 #define PSC_STATE_SYNCRST       1
  32 #define PSC_STATE_DISABLE       2
  33 #define PSC_STATE_ENABLE        3
  34
  35 #define MDSTAT_STATE_MASK       0x3f
  36 #define MDSTAT_MCKOUT           BIT(12)
  37 #define PDSTAT_STATE_MASK       0x1f
  38 #define MDCTL_FORCE             BIT(31)
  39 #define MDCTL_LRESET            BIT(8)
  40 #define PDCTL_NEXT              BIT(0)
  41
  42 /* Maximum timeout to bail out state transition for module */
  43 #define STATE_TRANS_MAX_COUNT   0xffff
  44
  45 static void __iomem *domain_transition_base;
  46
  47 /**
  48  * struct clk_psc_data - PSC data
  49  * @control_base: Base address for a PSC control
  50  * @domain_base: Base address for a PSC domain
  51  * @domain_id: PSC domain id number
  52  */
  53 struct clk_psc_data {
  54         void __iomem *control_base;
  55         void __iomem *domain_base;
  56         u32 domain_id;
  57 };
  58
  59 /**
  60  * struct clk_psc - PSC clock structure
  61  * @hw: clk_hw for the psc
  62  * @psc_data: PSC driver specific data
  63  * @lock: Spinlock used by the driver
  64  */
  65 struct clk_psc {
  66         struct clk_hw hw;
  67         struct clk_psc_data *psc_data;
  68         spinlock_t *lock;
  69 };
  70
  71 static DEFINE_SPINLOCK(psc_lock);
  72
  73 #define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw)
  74
  75 static void psc_config(void __iomem *control_base, void __iomem *domain_base,
  76                                                 u32 next_state, u32 domain_id)
  77 {
  78         u32 ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat;
  79         u32 count = STATE_TRANS_MAX_COUNT;
  80
  81         mdctl = readl(control_base + MDCTL);
  82         mdctl &= ~MDSTAT_STATE_MASK;
  83         mdctl |= next_state;
  84         /* For disable, we always put the module in local reset */
  85         if (next_state == PSC_STATE_DISABLE)
  86                 mdctl &= ~MDCTL_LRESET;
  87         writel(mdctl, control_base + MDCTL);
  88
  89         pdstat = readl(domain_base + PDSTAT);
  90         if (!(pdstat & PDSTAT_STATE_MASK)) {
  91                 pdctl = readl(domain_base + PDCTL);
  92                 pdctl |= PDCTL_NEXT;
  93                 writel(pdctl, domain_base + PDCTL);
  94         }
  95
  96         ptcmd = 1 << domain_id;
  97         writel(ptcmd, domain_transition_base + PTCMD);
  98         do {
  99                 ptstat = readl(domain_transition_base + PTSTAT);
 100         } while (((ptstat >> domain_id) & 1) && count--);
 101
 102         count = STATE_TRANS_MAX_COUNT;
 103         do {
 104                 mdstat = readl(control_base + MDSTAT);
 105         } while (!((mdstat & MDSTAT_STATE_MASK) == next_state) && count--);
 106 }
 107
 108 static int keystone_clk_is_enabled(struct clk_hw *hw)
 109 {
 110         struct clk_psc *psc = to_clk_psc(hw);
 111         struct clk_psc_data *data = psc->psc_data;
 112         u32 mdstat = readl(data->control_base + MDSTAT);
 113
 114         return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
 115 }
 116
 117 static int keystone_clk_enable(struct clk_hw *hw)
 118 {
 119         struct clk_psc *psc = to_clk_psc(hw);
 120         struct clk_psc_data *data = psc->psc_data;
 121         unsigned long flags = 0;
 122
 123         if (psc->lock)
 124                 spin_lock_irqsave(psc->lock, flags);
 125
 126         psc_config(data->control_base, data->domain_base,
 127                                 PSC_STATE_ENABLE, data->domain_id);
 128
 129         if (psc->lock)
 130                 spin_unlock_irqrestore(psc->lock, flags);
 131
 132         return 0;
 133 }
 134
 135 static void keystone_clk_disable(struct clk_hw *hw)
 136 {
 137         struct clk_psc *psc = to_clk_psc(hw);
 138         struct clk_psc_data *data = psc->psc_data;
 139         unsigned long flags = 0;
 140
 141         if (psc->lock)
 142                 spin_lock_irqsave(psc->lock, flags);
 143
 144         psc_config(data->control_base, data->domain_base,
 145                                 PSC_STATE_DISABLE, data->domain_id);
 146
 147         if (psc->lock)
 148                 spin_unlock_irqrestore(psc->lock, flags);
 149 }
 150
 151 static const struct clk_ops clk_psc_ops = {
 152         .enable = keystone_clk_enable,
 153         .disable = keystone_clk_disable,
 154         .is_enabled = keystone_clk_is_enabled,
 155 };
 156
 157 /**
 158  * clk_register_psc - register psc clock
 159  * @dev: device that is registering this clock
 160  * @name: name of this clock
 161  * @parent_name: name of clock's parent
 162  * @psc_data: platform data to configure this clock
 163  * @lock: spinlock used by this clock
 164  */
 165 static struct clk *clk_register_psc(struct device *dev,
 166                         const char *name,
 167                         const char *parent_name,
 168                         struct clk_psc_data *psc_data,
 169                         spinlock_t *lock)
 170 {
 171         struct clk_init_data init;
 172         struct clk_psc *psc;
 173         struct clk *clk;
 174
 175         psc = kzalloc(sizeof(*psc), GFP_KERNEL);
 176         if (!psc)
 177                 return ERR_PTR(-ENOMEM);
 178
 179         init.name = name;
 180         init.ops = &clk_psc_ops;
 181         init.flags = 0;
 182         init.parent_names = (parent_name ? &parent_name : NULL);
 183         init.num_parents = (parent_name ? 1 : 0);
 184
 185         psc->psc_data = psc_data;
 186         psc->lock = lock;
 187         psc->hw.init = &init;
 188
 189         clk = clk_register(NULL, &psc->hw);
 190         if (IS_ERR(clk))
 191                 kfree(psc);
 192
 193         return clk;
 194 }
 195
 196 /**
 197  * of_psc_clk_init - initialize psc clock through DT
 198  * @node: device tree node for this clock
 199  * @lock: spinlock used by this clock
 200  */
 201 static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
 202 {
 203         const char *clk_name = node->name;
 204         const char *parent_name;
 205         struct clk_psc_data *data;
 206         struct clk *clk;
 207         int i;
 208
 209         data = kzalloc(sizeof(*data), GFP_KERNEL);
 210         if (!data) {
 211                 pr_err("%s: Out of memory\n", __func__);
 212                 return;
 213         }
 214
 215         i = of_property_match_string(node, "reg-names", "control");
 216         data->control_base = of_iomap(node, i);
 217         if (!data->control_base) {
 218                 pr_err("%s: control ioremap failed\n", __func__);
 219                 goto out;
 220         }
 221
 222         i = of_property_match_string(node, "reg-names", "domain");
 223         data->domain_base = of_iomap(node, i);
 224         if (!data->domain_base) {
 225                 pr_err("%s: domain ioremap failed\n", __func__);
 226                 goto unmap_ctrl;
 227         }
 228
 229         of_property_read_u32(node, "domain-id", &data->domain_id);
 230
 231         /* Domain transition registers at fixed address space of domain_id 0 */
 232         if (!domain_transition_base && !data->domain_id)
 233                 domain_transition_base = data->domain_base;
 234
 235         of_property_read_string(node, "clock-output-names", &clk_name);
 236         parent_name = of_clk_get_parent_name(node, 0);
 237         if (!parent_name) {
 238                 pr_err("%s: Parent clock not found\n", __func__);
 239                 goto unmap_domain;
 240         }
 241
 242         clk = clk_register_psc(NULL, clk_name, parent_name, data, lock);
 243         if (!IS_ERR(clk)) {
 244                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 245                 return;
 246         }
 247
 248         pr_err("%s: error registering clk %s\n", __func__, node->name);
 249
 250 unmap_domain:
 251         iounmap(data->domain_base);
 252 unmap_ctrl:
 253         iounmap(data->control_base);
 254 out:
 255         kfree(data);
 256         return;
 257 }
 258
 259 /**
 260  * of_keystone_psc_clk_init - initialize psc clock through DT
 261  * @node: device tree node for this clock
 262  */
 263 static void __init of_keystone_psc_clk_init(struct device_node *node)
 264 {
 265         of_psc_clk_init(node, &psc_lock);
 266 }
 267 CLK_OF_DECLARE(keystone_gate_clk, "ti,keystone,psc-clock",
 268                                         of_keystone_psc_clk_init);