drivers/clk/meson/meson8b-clkc.c

   1 /*
   2  * Copyright (c) 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/kernel.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/slab.h>
  23 #include <dt-bindings/clock/meson8b-clkc.h>
  24
  25 #include "clkc.h"
  26
  27 #define MESON8B_REG_CTL0_ADDR           0x0000
  28 #define MESON8B_REG_SYS_CPU_CNTL1       0x015c
  29 #define MESON8B_REG_HHI_MPEG            0x0174
  30 #define MESON8B_REG_MALI                0x01b0
  31 #define MESON8B_REG_PLL_FIXED           0x0280
  32 #define MESON8B_REG_PLL_SYS             0x0300
  33 #define MESON8B_REG_PLL_VID             0x0320
  34
  35 static const struct pll_rate_table sys_pll_rate_table[] = {
  36         PLL_RATE(312000000, 52, 1, 2),
  37         PLL_RATE(336000000, 56, 1, 2),
  38         PLL_RATE(360000000, 60, 1, 2),
  39         PLL_RATE(384000000, 64, 1, 2),
  40         PLL_RATE(408000000, 68, 1, 2),
  41         PLL_RATE(432000000, 72, 1, 2),
  42         PLL_RATE(456000000, 76, 1, 2),
  43         PLL_RATE(480000000, 80, 1, 2),
  44         PLL_RATE(504000000, 84, 1, 2),
  45         PLL_RATE(528000000, 88, 1, 2),
  46         PLL_RATE(552000000, 92, 1, 2),
  47         PLL_RATE(576000000, 96, 1, 2),
  48         PLL_RATE(600000000, 50, 1, 1),
  49         PLL_RATE(624000000, 52, 1, 1),
  50         PLL_RATE(648000000, 54, 1, 1),
  51         PLL_RATE(672000000, 56, 1, 1),
  52         PLL_RATE(696000000, 58, 1, 1),
  53         PLL_RATE(720000000, 60, 1, 1),
  54         PLL_RATE(744000000, 62, 1, 1),
  55         PLL_RATE(768000000, 64, 1, 1),
  56         PLL_RATE(792000000, 66, 1, 1),
  57         PLL_RATE(816000000, 68, 1, 1),
  58         PLL_RATE(840000000, 70, 1, 1),
  59         PLL_RATE(864000000, 72, 1, 1),
  60         PLL_RATE(888000000, 74, 1, 1),
  61         PLL_RATE(912000000, 76, 1, 1),
  62         PLL_RATE(936000000, 78, 1, 1),
  63         PLL_RATE(960000000, 80, 1, 1),
  64         PLL_RATE(984000000, 82, 1, 1),
  65         PLL_RATE(1008000000, 84, 1, 1),
  66         PLL_RATE(1032000000, 86, 1, 1),
  67         PLL_RATE(1056000000, 88, 1, 1),
  68         PLL_RATE(1080000000, 90, 1, 1),
  69         PLL_RATE(1104000000, 92, 1, 1),
  70         PLL_RATE(1128000000, 94, 1, 1),
  71         PLL_RATE(1152000000, 96, 1, 1),
  72         PLL_RATE(1176000000, 98, 1, 1),
  73         PLL_RATE(1200000000, 50, 1, 0),
  74         PLL_RATE(1224000000, 51, 1, 0),
  75         PLL_RATE(1248000000, 52, 1, 0),
  76         PLL_RATE(1272000000, 53, 1, 0),
  77         PLL_RATE(1296000000, 54, 1, 0),
  78         PLL_RATE(1320000000, 55, 1, 0),
  79         PLL_RATE(1344000000, 56, 1, 0),
  80         PLL_RATE(1368000000, 57, 1, 0),
  81         PLL_RATE(1392000000, 58, 1, 0),
  82         PLL_RATE(1416000000, 59, 1, 0),
  83         PLL_RATE(1440000000, 60, 1, 0),
  84         PLL_RATE(1464000000, 61, 1, 0),
  85         PLL_RATE(1488000000, 62, 1, 0),
  86         PLL_RATE(1512000000, 63, 1, 0),
  87         PLL_RATE(1536000000, 64, 1, 0),
  88         { /* sentinel */ },
  89 };
  90
  91 static const struct clk_div_table cpu_div_table[] = {
  92         { .val = 1, .div = 1 },
  93         { .val = 2, .div = 2 },
  94         { .val = 3, .div = 3 },
  95         { .val = 2, .div = 4 },
  96         { .val = 3, .div = 6 },
  97         { .val = 4, .div = 8 },
  98         { .val = 5, .div = 10 },
  99         { .val = 6, .div = 12 },
 100         { .val = 7, .div = 14 },
 101         { .val = 8, .div = 16 },
 102         { /* sentinel */ },
 103 };
 104
 105 PNAME(p_xtal)           = { "xtal" };
 106 PNAME(p_fclk_div)       = { "fixed_pll" };
 107 PNAME(p_cpu_clk)        = { "sys_pll" };
 108 PNAME(p_clk81)          = { "fclk_div3", "fclk_div4", "fclk_div5" };
 109 PNAME(p_mali)           = { "fclk_div3", "fclk_div4", "fclk_div5",
 110                             "fclk_div7", "zero" };
 111
 112 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 113 static u32 mux_table_mali[]     = { 6, 5, 7, 4, 0 };
 114
 115 static struct pll_conf pll_confs = {
 116         .m              = PARM(0x00, 0,  9),
 117         .n              = PARM(0x00, 9,  5),
 118         .od             = PARM(0x00, 16, 2),
 119 };
 120
 121 static struct pll_conf sys_pll_conf = {
 122         .m              = PARM(0x00, 0,  9),
 123         .n              = PARM(0x00, 9,  5),
 124         .od             = PARM(0x00, 16, 2),
 125         .rate_table     = sys_pll_rate_table,
 126 };
 127
 128 static const struct composite_conf clk81_conf __initconst = {
 129         .mux_table              = mux_table_clk81,
 130         .mux_flags              = CLK_MUX_READ_ONLY,
 131         .mux_parm               = PARM(0x00, 12, 3),
 132         .div_parm               = PARM(0x00, 0, 7),
 133         .gate_parm              = PARM(0x00, 7, 1),
 134 };
 135
 136 static const struct composite_conf mali_conf __initconst = {
 137         .mux_table              = mux_table_mali,
 138         .mux_parm               = PARM(0x00, 9, 3),
 139         .div_parm               = PARM(0x00, 0, 7),
 140         .gate_parm              = PARM(0x00, 8, 1),
 141 };
 142
 143 static const struct clk_conf meson8b_xtal_conf __initconst =
 144         FIXED_RATE_P(MESON8B_REG_CTL0_ADDR, CLKID_XTAL, "xtal",
 145                      CLK_IS_ROOT, PARM(0x00, 4, 7));
 146
 147 static const struct clk_conf meson8b_clk_confs[] __initconst = {
 148         FIXED_RATE(CLKID_ZERO, "zero", CLK_IS_ROOT, 0),
 149         PLL(MESON8B_REG_PLL_FIXED, CLKID_PLL_FIXED, "fixed_pll",
 150             p_xtal, 0, &pll_confs),
 151         PLL(MESON8B_REG_PLL_VID, CLKID_PLL_VID, "vid_pll",
 152             p_xtal, 0, &pll_confs),
 153         PLL(MESON8B_REG_PLL_SYS, CLKID_PLL_SYS, "sys_pll",
 154             p_xtal, 0, &sys_pll_conf),
 155         FIXED_FACTOR_DIV(CLKID_FCLK_DIV2, "fclk_div2", p_fclk_div, 0, 2),
 156         FIXED_FACTOR_DIV(CLKID_FCLK_DIV3, "fclk_div3", p_fclk_div, 0, 3),
 157         FIXED_FACTOR_DIV(CLKID_FCLK_DIV4, "fclk_div4", p_fclk_div, 0, 4),
 158         FIXED_FACTOR_DIV(CLKID_FCLK_DIV5, "fclk_div5", p_fclk_div, 0, 5),
 159         FIXED_FACTOR_DIV(CLKID_FCLK_DIV7, "fclk_div7", p_fclk_div, 0, 7),
 160         CPU(MESON8B_REG_SYS_CPU_CNTL1, CLKID_CPUCLK, "a5_clk", p_cpu_clk,
 161             cpu_div_table),
 162         COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81,
 163                   CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf),
 164         COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali,
 165                   CLK_IGNORE_UNUSED, &mali_conf),
 166 };
 167
 168 static void __init meson8b_clkc_init(struct device_node *np)
 169 {
 170         void __iomem *clk_base;
 171
 172         if (!meson_clk_init(np, CLK_NR_CLKS))
 173                 return;
 174
 175         /* XTAL */
 176         clk_base = of_iomap(np, 0);
 177         if (!clk_base) {
 178                 pr_err("%s: Unable to map xtal base\n", __func__);
 179                 return;
 180         }
 181
 182         meson_clk_register_clks(&meson8b_xtal_conf, 1, clk_base);
 183         iounmap(clk_base);
 184
 185         /*  Generic clocks and PLLs */
 186         clk_base = of_iomap(np, 1);
 187         if (!clk_base) {
 188                 pr_err("%s: Unable to map clk base\n", __func__);
 189                 return;
 190         }
 191
 192         meson_clk_register_clks(meson8b_clk_confs,
 193                                 ARRAY_SIZE(meson8b_clk_confs),
 194                                 clk_base);
 195 }
 196 CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init);