drivers/clk/mvebu/armada-39x.c

   1 /*
   2  * Marvell Armada 39x SoC clocks
   3  *
   4  * Copyright (C) 2015 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   8  * Andrew Lunn <andrew@lunn.ch>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/io.h>
  19 #include <linux/of.h>
  20 #include "common.h"
  21
  22 /*
  23  * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
  24  *
  25  * SARL[15]    : TCLK frequency
  26  *               0 = 250 MHz
  27  *               1 = 200 MHz
  28  *
  29  * SARH[0]     : Reference clock frequency
  30  *               0 = 25 Mhz
  31  *               1 = 40 Mhz
  32  */
  33
  34 #define SARL                                    0
  35 #define  SARL_A390_TCLK_FREQ_OPT                15
  36 #define  SARL_A390_TCLK_FREQ_OPT_MASK           0x1
  37 #define  SARL_A390_CPU_DDR_L2_FREQ_OPT          10
  38 #define  SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK     0x1F
  39 #define SARH                                    4
  40 #define  SARH_A390_REFCLK_FREQ                  BIT(0)
  41
  42 static const u32 armada_39x_tclk_frequencies[] __initconst = {
  43         250000000,
  44         200000000,
  45 };
  46
  47 static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
  48 {
  49         u8 tclk_freq_select;
  50
  51         tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
  52                             SARL_A390_TCLK_FREQ_OPT_MASK);
  53         return armada_39x_tclk_frequencies[tclk_freq_select];
  54 }
  55
  56 static const u32 armada_39x_cpu_frequencies[] __initconst = {
  57         [0x0] = 666 * 1000 * 1000,
  58         [0x2] = 800 * 1000 * 1000,
  59         [0x3] = 800 * 1000 * 1000,
  60         [0x4] = 1066 * 1000 * 1000,
  61         [0x5] = 1066 * 1000 * 1000,
  62         [0x6] = 1200 * 1000 * 1000,
  63         [0x8] = 1332 * 1000 * 1000,
  64         [0xB] = 1600 * 1000 * 1000,
  65         [0xC] = 1600 * 1000 * 1000,
  66         [0x12] = 1800 * 1000 * 1000,
  67         [0x1E] = 1800 * 1000 * 1000,
  68 };
  69
  70 static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
  71 {
  72         u8 cpu_freq_select;
  73
  74         cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
  75                            SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
  76         if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
  77                 pr_err("Selected CPU frequency (%d) unsupported\n",
  78                         cpu_freq_select);
  79                 return 0;
  80         }
  81
  82         return armada_39x_cpu_frequencies[cpu_freq_select];
  83 }
  84
  85 enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
  86
  87 static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
  88         { .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
  89         { .id = A390_CPU_TO_HCLK, .name = "hclk" },
  90         { .id = A390_CPU_TO_DCLK, .name = "dclk" },
  91 };
  92
  93 static void __init armada_39x_get_clk_ratio(
  94         void __iomem *sar, int id, int *mult, int *div)
  95 {
  96         switch (id) {
  97         case A390_CPU_TO_NBCLK:
  98                 *mult = 1;
  99                 *div = 2;
 100                 break;
 101         case A390_CPU_TO_HCLK:
 102                 *mult = 1;
 103                 *div = 4;
 104                 break;
 105         case A390_CPU_TO_DCLK:
 106                 *mult = 1;
 107                 *div = 2;
 108                 break;
 109         }
 110 }
 111
 112 static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
 113 {
 114         if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
 115                 return 40 * 1000 * 1000;
 116         else
 117                 return 25 * 1000 * 1000;
 118 }
 119
 120 static const struct coreclk_soc_desc armada_39x_coreclks = {
 121         .get_tclk_freq = armada_39x_get_tclk_freq,
 122         .get_cpu_freq = armada_39x_get_cpu_freq,
 123         .get_clk_ratio = armada_39x_get_clk_ratio,
 124         .get_refclk_freq = armada_39x_refclk_ratio,
 125         .ratios = armada_39x_coreclk_ratios,
 126         .num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
 127 };
 128
 129 static void __init armada_39x_coreclk_init(struct device_node *np)
 130 {
 131         mvebu_coreclk_setup(np, &armada_39x_coreclks);
 132 }
 133 CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
 134                armada_39x_coreclk_init);
 135
 136 /*
 137  * Clock Gating Control
 138  */
 139 static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
 140         { "pex1", NULL, 5 },
 141         { "pex2", NULL, 6 },
 142         { "pex3", NULL, 7 },
 143         { "pex0", NULL, 8 },
 144         { "usb3h0", NULL, 9 },
 145         { "sdio", NULL, 17 },
 146         { "xor0", NULL, 22 },
 147         { "xor1", NULL, 28 },
 148         { }
 149 };
 150
 151 static void __init armada_39x_clk_gating_init(struct device_node *np)
 152 {
 153         mvebu_clk_gating_setup(np, armada_39x_gating_desc);
 154 }
 155 CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
 156                armada_39x_clk_gating_init);