drivers/clk/mxs/clk-imx28.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/err.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <mach/common.h>
  18 #include <mach/mx28.h>
  19 #include "clk.h"
  20
  21 #define CLKCTRL                 MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
  22 #define PLL0CTRL0               (CLKCTRL + 0x0000)
  23 #define PLL1CTRL0               (CLKCTRL + 0x0020)
  24 #define PLL2CTRL0               (CLKCTRL + 0x0040)
  25 #define CPU                     (CLKCTRL + 0x0050)
  26 #define HBUS                    (CLKCTRL + 0x0060)
  27 #define XBUS                    (CLKCTRL + 0x0070)
  28 #define XTAL                    (CLKCTRL + 0x0080)
  29 #define SSP0                    (CLKCTRL + 0x0090)
  30 #define SSP1                    (CLKCTRL + 0x00a0)
  31 #define SSP2                    (CLKCTRL + 0x00b0)
  32 #define SSP3                    (CLKCTRL + 0x00c0)
  33 #define GPMI                    (CLKCTRL + 0x00d0)
  34 #define SPDIF                   (CLKCTRL + 0x00e0)
  35 #define EMI                     (CLKCTRL + 0x00f0)
  36 #define SAIF0                   (CLKCTRL + 0x0100)
  37 #define SAIF1                   (CLKCTRL + 0x0110)
  38 #define LCDIF                   (CLKCTRL + 0x0120)
  39 #define ETM                     (CLKCTRL + 0x0130)
  40 #define ENET                    (CLKCTRL + 0x0140)
  41 #define FLEXCAN                 (CLKCTRL + 0x0160)
  42 #define FRAC0                   (CLKCTRL + 0x01b0)
  43 #define FRAC1                   (CLKCTRL + 0x01c0)
  44 #define CLKSEQ                  (CLKCTRL + 0x01d0)
  45
  46 #define BP_CPU_INTERRUPT_WAIT   12
  47 #define BP_SAIF_DIV_FRAC_EN     16
  48 #define BP_ENET_DIV_TIME        21
  49 #define BP_ENET_SLEEP           31
  50 #define BP_CLKSEQ_BYPASS_SAIF0  0
  51 #define BP_CLKSEQ_BYPASS_SSP0   3
  52 #define BP_FRAC0_IO1FRAC        16
  53 #define BP_FRAC0_IO0FRAC        24
  54
  55 #define DIGCTRL                 MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
  56 #define BP_SAIF_CLKMUX          10
  57
  58 /*
  59  * HW_SAIF_CLKMUX_SEL:
  60  *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
  61  *              clock pins selected for SAIF1 input clocks.
  62  *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
  63  *              SAIF0 clock inputs selected for SAIF1 input clocks.
  64  *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
  65  *              clocks.
  66  *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
  67  *              clocks.
  68  */
  69 int mxs_saif_clkmux_select(unsigned int clkmux)
  70 {
  71         if (clkmux > 0x3)
  72                 return -EINVAL;
  73
  74         __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL);
  75         __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL);
  76
  77         return 0;
  78 }
  79
  80 static void __init clk_misc_init(void)
  81 {
  82         u32 val;
  83
  84         /* Gate off cpu clock in WFI for power saving */
  85         __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
  86
  87         /* 0 is a bad default value for a divider */
  88         __mxs_setl(1 << BP_ENET_DIV_TIME, ENET);
  89
  90         /* Clear BYPASS for SAIF */
  91         __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ);
  92
  93         /* SAIF has to use frac div for functional operation */
  94         val = readl_relaxed(SAIF0);
  95         val |= 1 << BP_SAIF_DIV_FRAC_EN;
  96         writel_relaxed(val, SAIF0);
  97
  98         val = readl_relaxed(SAIF1);
  99         val |= 1 << BP_SAIF_DIV_FRAC_EN;
 100         writel_relaxed(val, SAIF1);
 101
 102         /* Extra fec clock setting */
 103         val = readl_relaxed(ENET);
 104         val &= ~(1 << BP_ENET_SLEEP);
 105         writel_relaxed(val, ENET);
 106
 107         /*
 108          * Source ssp clock from ref_io than ref_xtal,
 109          * as ref_xtal only provides 24 MHz as maximum.
 110          */
 111         __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ);
 112
 113         /*
 114          * 480 MHz seems too high to be ssp clock source directly,
 115          * so set frac0 to get a 288 MHz ref_io0.
 116          */
 117         val = readl_relaxed(FRAC0);
 118         val &= ~(0x3f << BP_FRAC0_IO0FRAC);
 119         val |= 30 << BP_FRAC0_IO0FRAC;
 120         writel_relaxed(val, FRAC0);
 121 }
 122
 123 static struct clk_lookup uart_lookups[] = {
 124         { .dev_id = "duart", },
 125         { .dev_id = "mxs-auart.0", },
 126         { .dev_id = "mxs-auart.1", },
 127         { .dev_id = "mxs-auart.2", },
 128         { .dev_id = "mxs-auart.3", },
 129         { .dev_id = "mxs-auart.4", },
 130         { .dev_id = "8006a000.serial", },
 131         { .dev_id = "8006c000.serial", },
 132         { .dev_id = "8006e000.serial", },
 133         { .dev_id = "80070000.serial", },
 134         { .dev_id = "80072000.serial", },
 135         { .dev_id = "80074000.serial", },
 136 };
 137
 138 static struct clk_lookup hbus_lookups[] = {
 139         { .dev_id = "imx28-dma-apbh", },
 140         { .dev_id = "80004000.dma-apbh", },
 141 };
 142
 143 static struct clk_lookup xbus_lookups[] = {
 144         { .dev_id = "duart", .con_id = "apb_pclk"},
 145         { .dev_id = "80074000.serial", .con_id = "apb_pclk"},
 146         { .dev_id = "imx28-dma-apbx", },
 147         { .dev_id = "80024000.dma-apbx", },
 148 };
 149
 150 static struct clk_lookup ssp0_lookups[] = {
 151         { .dev_id = "imx28-mmc.0", },
 152         { .dev_id = "80010000.ssp", },
 153 };
 154
 155 static struct clk_lookup ssp1_lookups[] = {
 156         { .dev_id = "imx28-mmc.1", },
 157         { .dev_id = "80012000.ssp", },
 158 };
 159
 160 static struct clk_lookup ssp2_lookups[] = {
 161         { .dev_id = "imx28-mmc.2", },
 162         { .dev_id = "80014000.ssp", },
 163 };
 164
 165 static struct clk_lookup ssp3_lookups[] = {
 166         { .dev_id = "imx28-mmc.3", },
 167         { .dev_id = "80016000.ssp", },
 168 };
 169
 170 static struct clk_lookup lcdif_lookups[] = {
 171         { .dev_id = "imx28-fb", },
 172         { .dev_id = "80030000.lcdif", },
 173 };
 174
 175 static struct clk_lookup gpmi_lookups[] = {
 176         { .dev_id = "imx28-gpmi-nand", },
 177         { .dev_id = "8000c000.gpmi", },
 178 };
 179
 180 static struct clk_lookup fec_lookups[] = {
 181         { .dev_id = "imx28-fec.0", },
 182         { .dev_id = "imx28-fec.1", },
 183         { .dev_id = "800f0000.ethernet", },
 184         { .dev_id = "800f4000.ethernet", },
 185 };
 186
 187 static struct clk_lookup can0_lookups[] = {
 188         { .dev_id = "flexcan.0", },
 189         { .dev_id = "80032000.can", },
 190 };
 191
 192 static struct clk_lookup can1_lookups[] = {
 193         { .dev_id = "flexcan.1", },
 194         { .dev_id = "80034000.can", },
 195 };
 196
 197 static struct clk_lookup saif0_lookups[] = {
 198         { .dev_id = "mxs-saif.0", },
 199         { .dev_id = "80042000.saif", },
 200 };
 201
 202 static struct clk_lookup saif1_lookups[] = {
 203         { .dev_id = "mxs-saif.1", },
 204         { .dev_id = "80046000.saif", },
 205 };
 206
 207 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 208 static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
 209 static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
 210 static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
 211 static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
 212 static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", };
 213 static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
 214 static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
 215 static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", };
 216
 217 enum imx28_clk {
 218         ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
 219         ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
 220         ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
 221         lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
 222         ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
 223         emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
 224         clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
 225         ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
 226         fec, can0, can1, usb0, usb1, usb0_pwr, usb1_pwr, enet_out,
 227         clk_max
 228 };
 229
 230 static struct clk *clks[clk_max];
 231
 232 static enum imx28_clk clks_init_on[] __initdata = {
 233         cpu, hbus, xbus, emi, uart,
 234 };
 235
 236 int __init mx28_clocks_init(void)
 237 {
 238         int i;
 239
 240         clk_misc_init();
 241
 242         clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
 243         clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
 244         clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
 245         clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
 246         clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
 247         clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
 248         clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
 249         clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
 250         clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
 251         clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
 252         clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
 253         clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
 254         clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
 255         clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
 256         clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
 257         clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
 258         clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
 259         clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
 260         clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
 261         clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
 262         clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
 263         clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
 264         clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
 265         clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
 266         clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
 267         clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
 268         clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
 269         clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
 270         clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
 271         clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
 272         clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
 273         clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
 274         clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
 275         clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
 276         clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
 277         clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
 278         clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
 279         clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
 280         clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
 281         clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
 282         clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
 283         clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
 284         clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
 285         clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
 286         clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
 287         clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
 288         clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
 289         clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
 290         clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
 291         clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
 292         clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
 293         clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
 294         clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
 295         clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
 296         clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
 297         clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
 298         clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
 299         clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
 300         clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
 301         clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
 302         clks[usb0] = mxs_clk_gate("usb0", "usb0_pwr", DIGCTRL, 2);
 303         clks[usb1] = mxs_clk_gate("usb1", "usb1_pwr", DIGCTRL, 16);
 304         clks[usb0_pwr] = clk_register_gate(NULL, "usb0_pwr", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
 305         clks[usb1_pwr] = clk_register_gate(NULL, "usb1_pwr", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
 306         clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
 307
 308         for (i = 0; i < ARRAY_SIZE(clks); i++)
 309                 if (IS_ERR(clks[i])) {
 310                         pr_err("i.MX28 clk %d: register failed with %ld\n",
 311                                 i, PTR_ERR(clks[i]));
 312                         return PTR_ERR(clks[i]);
 313                 }
 314
 315         clk_register_clkdev(clks[clk32k], NULL, "timrot");
 316         clk_register_clkdev(clks[enet_out], NULL, "enet_out");
 317         clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
 318         clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
 319         clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
 320         clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups));
 321         clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups));
 322         clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups));
 323         clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups));
 324         clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
 325         clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups));
 326         clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups));
 327         clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
 328         clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
 329         clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
 330         clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
 331
 332         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 333                 clk_prepare_enable(clks[clks_init_on[i]]);
 334
 335         mxs_timer_init(MX28_INT_TIMER0);
 336
 337         return 0;
 338 }