2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
35 static struct clk_pll pll3
= {
43 .clkr
.hw
.init
= &(struct clk_init_data
){
45 .parent_names
= (const char *[]){ "pxo" },
51 static struct clk_regmap pll4_vote
= {
53 .enable_mask
= BIT(4),
54 .hw
.init
= &(struct clk_init_data
){
56 .parent_names
= (const char *[]){ "pll4" },
58 .ops
= &clk_pll_vote_ops
,
62 static struct clk_pll pll8
= {
70 .clkr
.hw
.init
= &(struct clk_init_data
){
72 .parent_names
= (const char *[]){ "pxo" },
78 static struct clk_regmap pll8_vote
= {
80 .enable_mask
= BIT(8),
81 .hw
.init
= &(struct clk_init_data
){
83 .parent_names
= (const char *[]){ "pll8" },
85 .ops
= &clk_pll_vote_ops
,
89 static struct clk_pll pll14
= {
97 .clkr
.hw
.init
= &(struct clk_init_data
){
99 .parent_names
= (const char *[]){ "pxo" },
105 static struct clk_regmap pll14_vote
= {
106 .enable_reg
= 0x34c0,
107 .enable_mask
= BIT(14),
108 .hw
.init
= &(struct clk_init_data
){
109 .name
= "pll14_vote",
110 .parent_names
= (const char *[]){ "pll14" },
112 .ops
= &clk_pll_vote_ops
,
121 static const u8 gcc_pxo_pll8_map
[] = {
126 static const char *gcc_pxo_pll8
[] = {
131 static const u8 gcc_pxo_pll8_cxo_map
[] = {
137 static const char *gcc_pxo_pll8_cxo
[] = {
143 static const u8 gcc_pxo_pll8_pll3_map
[] = {
149 static const char *gcc_pxo_pll8_pll3
[] = {
155 static struct freq_tbl clk_tbl_gsbi_uart
[] = {
156 { 1843200, P_PLL8
, 2, 6, 625 },
157 { 3686400, P_PLL8
, 2, 12, 625 },
158 { 7372800, P_PLL8
, 2, 24, 625 },
159 { 14745600, P_PLL8
, 2, 48, 625 },
160 { 16000000, P_PLL8
, 4, 1, 6 },
161 { 24000000, P_PLL8
, 4, 1, 4 },
162 { 32000000, P_PLL8
, 4, 1, 3 },
163 { 40000000, P_PLL8
, 1, 5, 48 },
164 { 46400000, P_PLL8
, 1, 29, 240 },
165 { 48000000, P_PLL8
, 4, 1, 2 },
166 { 51200000, P_PLL8
, 1, 2, 15 },
167 { 56000000, P_PLL8
, 1, 7, 48 },
168 { 58982400, P_PLL8
, 1, 96, 625 },
169 { 64000000, P_PLL8
, 2, 1, 3 },
173 static struct clk_rcg gsbi1_uart_src
= {
178 .mnctr_reset_bit
= 7,
179 .mnctr_mode_shift
= 5,
190 .parent_map
= gcc_pxo_pll8_map
,
192 .freq_tbl
= clk_tbl_gsbi_uart
,
194 .enable_reg
= 0x29d4,
195 .enable_mask
= BIT(11),
196 .hw
.init
= &(struct clk_init_data
){
197 .name
= "gsbi1_uart_src",
198 .parent_names
= gcc_pxo_pll8
,
201 .flags
= CLK_SET_PARENT_GATE
,
206 static struct clk_branch gsbi1_uart_clk
= {
210 .enable_reg
= 0x29d4,
211 .enable_mask
= BIT(9),
212 .hw
.init
= &(struct clk_init_data
){
213 .name
= "gsbi1_uart_clk",
214 .parent_names
= (const char *[]){
218 .ops
= &clk_branch_ops
,
219 .flags
= CLK_SET_RATE_PARENT
,
224 static struct clk_rcg gsbi2_uart_src
= {
229 .mnctr_reset_bit
= 7,
230 .mnctr_mode_shift
= 5,
241 .parent_map
= gcc_pxo_pll8_map
,
243 .freq_tbl
= clk_tbl_gsbi_uart
,
245 .enable_reg
= 0x29f4,
246 .enable_mask
= BIT(11),
247 .hw
.init
= &(struct clk_init_data
){
248 .name
= "gsbi2_uart_src",
249 .parent_names
= gcc_pxo_pll8
,
252 .flags
= CLK_SET_PARENT_GATE
,
257 static struct clk_branch gsbi2_uart_clk
= {
261 .enable_reg
= 0x29f4,
262 .enable_mask
= BIT(9),
263 .hw
.init
= &(struct clk_init_data
){
264 .name
= "gsbi2_uart_clk",
265 .parent_names
= (const char *[]){
269 .ops
= &clk_branch_ops
,
270 .flags
= CLK_SET_RATE_PARENT
,
275 static struct clk_rcg gsbi3_uart_src
= {
280 .mnctr_reset_bit
= 7,
281 .mnctr_mode_shift
= 5,
292 .parent_map
= gcc_pxo_pll8_map
,
294 .freq_tbl
= clk_tbl_gsbi_uart
,
296 .enable_reg
= 0x2a14,
297 .enable_mask
= BIT(11),
298 .hw
.init
= &(struct clk_init_data
){
299 .name
= "gsbi3_uart_src",
300 .parent_names
= gcc_pxo_pll8
,
303 .flags
= CLK_SET_PARENT_GATE
,
308 static struct clk_branch gsbi3_uart_clk
= {
312 .enable_reg
= 0x2a14,
313 .enable_mask
= BIT(9),
314 .hw
.init
= &(struct clk_init_data
){
315 .name
= "gsbi3_uart_clk",
316 .parent_names
= (const char *[]){
320 .ops
= &clk_branch_ops
,
321 .flags
= CLK_SET_RATE_PARENT
,
326 static struct clk_rcg gsbi4_uart_src
= {
331 .mnctr_reset_bit
= 7,
332 .mnctr_mode_shift
= 5,
343 .parent_map
= gcc_pxo_pll8_map
,
345 .freq_tbl
= clk_tbl_gsbi_uart
,
347 .enable_reg
= 0x2a34,
348 .enable_mask
= BIT(11),
349 .hw
.init
= &(struct clk_init_data
){
350 .name
= "gsbi4_uart_src",
351 .parent_names
= gcc_pxo_pll8
,
354 .flags
= CLK_SET_PARENT_GATE
,
359 static struct clk_branch gsbi4_uart_clk
= {
363 .enable_reg
= 0x2a34,
364 .enable_mask
= BIT(9),
365 .hw
.init
= &(struct clk_init_data
){
366 .name
= "gsbi4_uart_clk",
367 .parent_names
= (const char *[]){
371 .ops
= &clk_branch_ops
,
372 .flags
= CLK_SET_RATE_PARENT
,
377 static struct clk_rcg gsbi5_uart_src
= {
382 .mnctr_reset_bit
= 7,
383 .mnctr_mode_shift
= 5,
394 .parent_map
= gcc_pxo_pll8_map
,
396 .freq_tbl
= clk_tbl_gsbi_uart
,
398 .enable_reg
= 0x2a54,
399 .enable_mask
= BIT(11),
400 .hw
.init
= &(struct clk_init_data
){
401 .name
= "gsbi5_uart_src",
402 .parent_names
= gcc_pxo_pll8
,
405 .flags
= CLK_SET_PARENT_GATE
,
410 static struct clk_branch gsbi5_uart_clk
= {
414 .enable_reg
= 0x2a54,
415 .enable_mask
= BIT(9),
416 .hw
.init
= &(struct clk_init_data
){
417 .name
= "gsbi5_uart_clk",
418 .parent_names
= (const char *[]){
422 .ops
= &clk_branch_ops
,
423 .flags
= CLK_SET_RATE_PARENT
,
428 static struct clk_rcg gsbi6_uart_src
= {
433 .mnctr_reset_bit
= 7,
434 .mnctr_mode_shift
= 5,
445 .parent_map
= gcc_pxo_pll8_map
,
447 .freq_tbl
= clk_tbl_gsbi_uart
,
449 .enable_reg
= 0x2a74,
450 .enable_mask
= BIT(11),
451 .hw
.init
= &(struct clk_init_data
){
452 .name
= "gsbi6_uart_src",
453 .parent_names
= gcc_pxo_pll8
,
456 .flags
= CLK_SET_PARENT_GATE
,
461 static struct clk_branch gsbi6_uart_clk
= {
465 .enable_reg
= 0x2a74,
466 .enable_mask
= BIT(9),
467 .hw
.init
= &(struct clk_init_data
){
468 .name
= "gsbi6_uart_clk",
469 .parent_names
= (const char *[]){
473 .ops
= &clk_branch_ops
,
474 .flags
= CLK_SET_RATE_PARENT
,
479 static struct clk_rcg gsbi7_uart_src
= {
484 .mnctr_reset_bit
= 7,
485 .mnctr_mode_shift
= 5,
496 .parent_map
= gcc_pxo_pll8_map
,
498 .freq_tbl
= clk_tbl_gsbi_uart
,
500 .enable_reg
= 0x2a94,
501 .enable_mask
= BIT(11),
502 .hw
.init
= &(struct clk_init_data
){
503 .name
= "gsbi7_uart_src",
504 .parent_names
= gcc_pxo_pll8
,
507 .flags
= CLK_SET_PARENT_GATE
,
512 static struct clk_branch gsbi7_uart_clk
= {
516 .enable_reg
= 0x2a94,
517 .enable_mask
= BIT(9),
518 .hw
.init
= &(struct clk_init_data
){
519 .name
= "gsbi7_uart_clk",
520 .parent_names
= (const char *[]){
524 .ops
= &clk_branch_ops
,
525 .flags
= CLK_SET_RATE_PARENT
,
530 static struct clk_rcg gsbi8_uart_src
= {
535 .mnctr_reset_bit
= 7,
536 .mnctr_mode_shift
= 5,
547 .parent_map
= gcc_pxo_pll8_map
,
549 .freq_tbl
= clk_tbl_gsbi_uart
,
551 .enable_reg
= 0x2ab4,
552 .enable_mask
= BIT(11),
553 .hw
.init
= &(struct clk_init_data
){
554 .name
= "gsbi8_uart_src",
555 .parent_names
= gcc_pxo_pll8
,
558 .flags
= CLK_SET_PARENT_GATE
,
563 static struct clk_branch gsbi8_uart_clk
= {
567 .enable_reg
= 0x2ab4,
568 .enable_mask
= BIT(9),
569 .hw
.init
= &(struct clk_init_data
){
570 .name
= "gsbi8_uart_clk",
571 .parent_names
= (const char *[]){ "gsbi8_uart_src" },
573 .ops
= &clk_branch_ops
,
574 .flags
= CLK_SET_RATE_PARENT
,
579 static struct clk_rcg gsbi9_uart_src
= {
584 .mnctr_reset_bit
= 7,
585 .mnctr_mode_shift
= 5,
596 .parent_map
= gcc_pxo_pll8_map
,
598 .freq_tbl
= clk_tbl_gsbi_uart
,
600 .enable_reg
= 0x2ad4,
601 .enable_mask
= BIT(11),
602 .hw
.init
= &(struct clk_init_data
){
603 .name
= "gsbi9_uart_src",
604 .parent_names
= gcc_pxo_pll8
,
607 .flags
= CLK_SET_PARENT_GATE
,
612 static struct clk_branch gsbi9_uart_clk
= {
616 .enable_reg
= 0x2ad4,
617 .enable_mask
= BIT(9),
618 .hw
.init
= &(struct clk_init_data
){
619 .name
= "gsbi9_uart_clk",
620 .parent_names
= (const char *[]){ "gsbi9_uart_src" },
622 .ops
= &clk_branch_ops
,
623 .flags
= CLK_SET_RATE_PARENT
,
628 static struct clk_rcg gsbi10_uart_src
= {
633 .mnctr_reset_bit
= 7,
634 .mnctr_mode_shift
= 5,
645 .parent_map
= gcc_pxo_pll8_map
,
647 .freq_tbl
= clk_tbl_gsbi_uart
,
649 .enable_reg
= 0x2af4,
650 .enable_mask
= BIT(11),
651 .hw
.init
= &(struct clk_init_data
){
652 .name
= "gsbi10_uart_src",
653 .parent_names
= gcc_pxo_pll8
,
656 .flags
= CLK_SET_PARENT_GATE
,
661 static struct clk_branch gsbi10_uart_clk
= {
665 .enable_reg
= 0x2af4,
666 .enable_mask
= BIT(9),
667 .hw
.init
= &(struct clk_init_data
){
668 .name
= "gsbi10_uart_clk",
669 .parent_names
= (const char *[]){ "gsbi10_uart_src" },
671 .ops
= &clk_branch_ops
,
672 .flags
= CLK_SET_RATE_PARENT
,
677 static struct clk_rcg gsbi11_uart_src
= {
682 .mnctr_reset_bit
= 7,
683 .mnctr_mode_shift
= 5,
694 .parent_map
= gcc_pxo_pll8_map
,
696 .freq_tbl
= clk_tbl_gsbi_uart
,
698 .enable_reg
= 0x2b14,
699 .enable_mask
= BIT(11),
700 .hw
.init
= &(struct clk_init_data
){
701 .name
= "gsbi11_uart_src",
702 .parent_names
= gcc_pxo_pll8
,
705 .flags
= CLK_SET_PARENT_GATE
,
710 static struct clk_branch gsbi11_uart_clk
= {
714 .enable_reg
= 0x2b14,
715 .enable_mask
= BIT(9),
716 .hw
.init
= &(struct clk_init_data
){
717 .name
= "gsbi11_uart_clk",
718 .parent_names
= (const char *[]){ "gsbi11_uart_src" },
720 .ops
= &clk_branch_ops
,
721 .flags
= CLK_SET_RATE_PARENT
,
726 static struct clk_rcg gsbi12_uart_src
= {
731 .mnctr_reset_bit
= 7,
732 .mnctr_mode_shift
= 5,
743 .parent_map
= gcc_pxo_pll8_map
,
745 .freq_tbl
= clk_tbl_gsbi_uart
,
747 .enable_reg
= 0x2b34,
748 .enable_mask
= BIT(11),
749 .hw
.init
= &(struct clk_init_data
){
750 .name
= "gsbi12_uart_src",
751 .parent_names
= gcc_pxo_pll8
,
754 .flags
= CLK_SET_PARENT_GATE
,
759 static struct clk_branch gsbi12_uart_clk
= {
763 .enable_reg
= 0x2b34,
764 .enable_mask
= BIT(9),
765 .hw
.init
= &(struct clk_init_data
){
766 .name
= "gsbi12_uart_clk",
767 .parent_names
= (const char *[]){ "gsbi12_uart_src" },
769 .ops
= &clk_branch_ops
,
770 .flags
= CLK_SET_RATE_PARENT
,
775 static struct freq_tbl clk_tbl_gsbi_qup
[] = {
776 { 1100000, P_PXO
, 1, 2, 49 },
777 { 5400000, P_PXO
, 1, 1, 5 },
778 { 10800000, P_PXO
, 1, 2, 5 },
779 { 15060000, P_PLL8
, 1, 2, 51 },
780 { 24000000, P_PLL8
, 4, 1, 4 },
781 { 25600000, P_PLL8
, 1, 1, 15 },
782 { 27000000, P_PXO
, 1, 0, 0 },
783 { 48000000, P_PLL8
, 4, 1, 2 },
784 { 51200000, P_PLL8
, 1, 2, 15 },
788 static struct clk_rcg gsbi1_qup_src
= {
793 .mnctr_reset_bit
= 7,
794 .mnctr_mode_shift
= 5,
805 .parent_map
= gcc_pxo_pll8_map
,
807 .freq_tbl
= clk_tbl_gsbi_qup
,
809 .enable_reg
= 0x29cc,
810 .enable_mask
= BIT(11),
811 .hw
.init
= &(struct clk_init_data
){
812 .name
= "gsbi1_qup_src",
813 .parent_names
= gcc_pxo_pll8
,
816 .flags
= CLK_SET_PARENT_GATE
,
821 static struct clk_branch gsbi1_qup_clk
= {
825 .enable_reg
= 0x29cc,
826 .enable_mask
= BIT(9),
827 .hw
.init
= &(struct clk_init_data
){
828 .name
= "gsbi1_qup_clk",
829 .parent_names
= (const char *[]){ "gsbi1_qup_src" },
831 .ops
= &clk_branch_ops
,
832 .flags
= CLK_SET_RATE_PARENT
,
837 static struct clk_rcg gsbi2_qup_src
= {
842 .mnctr_reset_bit
= 7,
843 .mnctr_mode_shift
= 5,
854 .parent_map
= gcc_pxo_pll8_map
,
856 .freq_tbl
= clk_tbl_gsbi_qup
,
858 .enable_reg
= 0x29ec,
859 .enable_mask
= BIT(11),
860 .hw
.init
= &(struct clk_init_data
){
861 .name
= "gsbi2_qup_src",
862 .parent_names
= gcc_pxo_pll8
,
865 .flags
= CLK_SET_PARENT_GATE
,
870 static struct clk_branch gsbi2_qup_clk
= {
874 .enable_reg
= 0x29ec,
875 .enable_mask
= BIT(9),
876 .hw
.init
= &(struct clk_init_data
){
877 .name
= "gsbi2_qup_clk",
878 .parent_names
= (const char *[]){ "gsbi2_qup_src" },
880 .ops
= &clk_branch_ops
,
881 .flags
= CLK_SET_RATE_PARENT
,
886 static struct clk_rcg gsbi3_qup_src
= {
891 .mnctr_reset_bit
= 7,
892 .mnctr_mode_shift
= 5,
903 .parent_map
= gcc_pxo_pll8_map
,
905 .freq_tbl
= clk_tbl_gsbi_qup
,
907 .enable_reg
= 0x2a0c,
908 .enable_mask
= BIT(11),
909 .hw
.init
= &(struct clk_init_data
){
910 .name
= "gsbi3_qup_src",
911 .parent_names
= gcc_pxo_pll8
,
914 .flags
= CLK_SET_PARENT_GATE
,
919 static struct clk_branch gsbi3_qup_clk
= {
923 .enable_reg
= 0x2a0c,
924 .enable_mask
= BIT(9),
925 .hw
.init
= &(struct clk_init_data
){
926 .name
= "gsbi3_qup_clk",
927 .parent_names
= (const char *[]){ "gsbi3_qup_src" },
929 .ops
= &clk_branch_ops
,
930 .flags
= CLK_SET_RATE_PARENT
,
935 static struct clk_rcg gsbi4_qup_src
= {
940 .mnctr_reset_bit
= 7,
941 .mnctr_mode_shift
= 5,
952 .parent_map
= gcc_pxo_pll8_map
,
954 .freq_tbl
= clk_tbl_gsbi_qup
,
956 .enable_reg
= 0x2a2c,
957 .enable_mask
= BIT(11),
958 .hw
.init
= &(struct clk_init_data
){
959 .name
= "gsbi4_qup_src",
960 .parent_names
= gcc_pxo_pll8
,
963 .flags
= CLK_SET_PARENT_GATE
,
968 static struct clk_branch gsbi4_qup_clk
= {
972 .enable_reg
= 0x2a2c,
973 .enable_mask
= BIT(9),
974 .hw
.init
= &(struct clk_init_data
){
975 .name
= "gsbi4_qup_clk",
976 .parent_names
= (const char *[]){ "gsbi4_qup_src" },
978 .ops
= &clk_branch_ops
,
979 .flags
= CLK_SET_RATE_PARENT
,
984 static struct clk_rcg gsbi5_qup_src
= {
989 .mnctr_reset_bit
= 7,
990 .mnctr_mode_shift
= 5,
1001 .parent_map
= gcc_pxo_pll8_map
,
1003 .freq_tbl
= clk_tbl_gsbi_qup
,
1005 .enable_reg
= 0x2a4c,
1006 .enable_mask
= BIT(11),
1007 .hw
.init
= &(struct clk_init_data
){
1008 .name
= "gsbi5_qup_src",
1009 .parent_names
= gcc_pxo_pll8
,
1011 .ops
= &clk_rcg_ops
,
1012 .flags
= CLK_SET_PARENT_GATE
,
1017 static struct clk_branch gsbi5_qup_clk
= {
1021 .enable_reg
= 0x2a4c,
1022 .enable_mask
= BIT(9),
1023 .hw
.init
= &(struct clk_init_data
){
1024 .name
= "gsbi5_qup_clk",
1025 .parent_names
= (const char *[]){ "gsbi5_qup_src" },
1027 .ops
= &clk_branch_ops
,
1028 .flags
= CLK_SET_RATE_PARENT
,
1033 static struct clk_rcg gsbi6_qup_src
= {
1038 .mnctr_reset_bit
= 7,
1039 .mnctr_mode_shift
= 5,
1050 .parent_map
= gcc_pxo_pll8_map
,
1052 .freq_tbl
= clk_tbl_gsbi_qup
,
1054 .enable_reg
= 0x2a6c,
1055 .enable_mask
= BIT(11),
1056 .hw
.init
= &(struct clk_init_data
){
1057 .name
= "gsbi6_qup_src",
1058 .parent_names
= gcc_pxo_pll8
,
1060 .ops
= &clk_rcg_ops
,
1061 .flags
= CLK_SET_PARENT_GATE
,
1066 static struct clk_branch gsbi6_qup_clk
= {
1070 .enable_reg
= 0x2a6c,
1071 .enable_mask
= BIT(9),
1072 .hw
.init
= &(struct clk_init_data
){
1073 .name
= "gsbi6_qup_clk",
1074 .parent_names
= (const char *[]){ "gsbi6_qup_src" },
1076 .ops
= &clk_branch_ops
,
1077 .flags
= CLK_SET_RATE_PARENT
,
1082 static struct clk_rcg gsbi7_qup_src
= {
1087 .mnctr_reset_bit
= 7,
1088 .mnctr_mode_shift
= 5,
1099 .parent_map
= gcc_pxo_pll8_map
,
1101 .freq_tbl
= clk_tbl_gsbi_qup
,
1103 .enable_reg
= 0x2a8c,
1104 .enable_mask
= BIT(11),
1105 .hw
.init
= &(struct clk_init_data
){
1106 .name
= "gsbi7_qup_src",
1107 .parent_names
= gcc_pxo_pll8
,
1109 .ops
= &clk_rcg_ops
,
1110 .flags
= CLK_SET_PARENT_GATE
,
1115 static struct clk_branch gsbi7_qup_clk
= {
1119 .enable_reg
= 0x2a8c,
1120 .enable_mask
= BIT(9),
1121 .hw
.init
= &(struct clk_init_data
){
1122 .name
= "gsbi7_qup_clk",
1123 .parent_names
= (const char *[]){ "gsbi7_qup_src" },
1125 .ops
= &clk_branch_ops
,
1126 .flags
= CLK_SET_RATE_PARENT
,
1131 static struct clk_rcg gsbi8_qup_src
= {
1136 .mnctr_reset_bit
= 7,
1137 .mnctr_mode_shift
= 5,
1148 .parent_map
= gcc_pxo_pll8_map
,
1150 .freq_tbl
= clk_tbl_gsbi_qup
,
1152 .enable_reg
= 0x2aac,
1153 .enable_mask
= BIT(11),
1154 .hw
.init
= &(struct clk_init_data
){
1155 .name
= "gsbi8_qup_src",
1156 .parent_names
= gcc_pxo_pll8
,
1158 .ops
= &clk_rcg_ops
,
1159 .flags
= CLK_SET_PARENT_GATE
,
1164 static struct clk_branch gsbi8_qup_clk
= {
1168 .enable_reg
= 0x2aac,
1169 .enable_mask
= BIT(9),
1170 .hw
.init
= &(struct clk_init_data
){
1171 .name
= "gsbi8_qup_clk",
1172 .parent_names
= (const char *[]){ "gsbi8_qup_src" },
1174 .ops
= &clk_branch_ops
,
1175 .flags
= CLK_SET_RATE_PARENT
,
1180 static struct clk_rcg gsbi9_qup_src
= {
1185 .mnctr_reset_bit
= 7,
1186 .mnctr_mode_shift
= 5,
1197 .parent_map
= gcc_pxo_pll8_map
,
1199 .freq_tbl
= clk_tbl_gsbi_qup
,
1201 .enable_reg
= 0x2acc,
1202 .enable_mask
= BIT(11),
1203 .hw
.init
= &(struct clk_init_data
){
1204 .name
= "gsbi9_qup_src",
1205 .parent_names
= gcc_pxo_pll8
,
1207 .ops
= &clk_rcg_ops
,
1208 .flags
= CLK_SET_PARENT_GATE
,
1213 static struct clk_branch gsbi9_qup_clk
= {
1217 .enable_reg
= 0x2acc,
1218 .enable_mask
= BIT(9),
1219 .hw
.init
= &(struct clk_init_data
){
1220 .name
= "gsbi9_qup_clk",
1221 .parent_names
= (const char *[]){ "gsbi9_qup_src" },
1223 .ops
= &clk_branch_ops
,
1224 .flags
= CLK_SET_RATE_PARENT
,
1229 static struct clk_rcg gsbi10_qup_src
= {
1234 .mnctr_reset_bit
= 7,
1235 .mnctr_mode_shift
= 5,
1246 .parent_map
= gcc_pxo_pll8_map
,
1248 .freq_tbl
= clk_tbl_gsbi_qup
,
1250 .enable_reg
= 0x2aec,
1251 .enable_mask
= BIT(11),
1252 .hw
.init
= &(struct clk_init_data
){
1253 .name
= "gsbi10_qup_src",
1254 .parent_names
= gcc_pxo_pll8
,
1256 .ops
= &clk_rcg_ops
,
1257 .flags
= CLK_SET_PARENT_GATE
,
1262 static struct clk_branch gsbi10_qup_clk
= {
1266 .enable_reg
= 0x2aec,
1267 .enable_mask
= BIT(9),
1268 .hw
.init
= &(struct clk_init_data
){
1269 .name
= "gsbi10_qup_clk",
1270 .parent_names
= (const char *[]){ "gsbi10_qup_src" },
1272 .ops
= &clk_branch_ops
,
1273 .flags
= CLK_SET_RATE_PARENT
,
1278 static struct clk_rcg gsbi11_qup_src
= {
1283 .mnctr_reset_bit
= 7,
1284 .mnctr_mode_shift
= 5,
1295 .parent_map
= gcc_pxo_pll8_map
,
1297 .freq_tbl
= clk_tbl_gsbi_qup
,
1299 .enable_reg
= 0x2b0c,
1300 .enable_mask
= BIT(11),
1301 .hw
.init
= &(struct clk_init_data
){
1302 .name
= "gsbi11_qup_src",
1303 .parent_names
= gcc_pxo_pll8
,
1305 .ops
= &clk_rcg_ops
,
1306 .flags
= CLK_SET_PARENT_GATE
,
1311 static struct clk_branch gsbi11_qup_clk
= {
1315 .enable_reg
= 0x2b0c,
1316 .enable_mask
= BIT(9),
1317 .hw
.init
= &(struct clk_init_data
){
1318 .name
= "gsbi11_qup_clk",
1319 .parent_names
= (const char *[]){ "gsbi11_qup_src" },
1321 .ops
= &clk_branch_ops
,
1322 .flags
= CLK_SET_RATE_PARENT
,
1327 static struct clk_rcg gsbi12_qup_src
= {
1332 .mnctr_reset_bit
= 7,
1333 .mnctr_mode_shift
= 5,
1344 .parent_map
= gcc_pxo_pll8_map
,
1346 .freq_tbl
= clk_tbl_gsbi_qup
,
1348 .enable_reg
= 0x2b2c,
1349 .enable_mask
= BIT(11),
1350 .hw
.init
= &(struct clk_init_data
){
1351 .name
= "gsbi12_qup_src",
1352 .parent_names
= gcc_pxo_pll8
,
1354 .ops
= &clk_rcg_ops
,
1355 .flags
= CLK_SET_PARENT_GATE
,
1360 static struct clk_branch gsbi12_qup_clk
= {
1364 .enable_reg
= 0x2b2c,
1365 .enable_mask
= BIT(9),
1366 .hw
.init
= &(struct clk_init_data
){
1367 .name
= "gsbi12_qup_clk",
1368 .parent_names
= (const char *[]){ "gsbi12_qup_src" },
1370 .ops
= &clk_branch_ops
,
1371 .flags
= CLK_SET_RATE_PARENT
,
1376 static const struct freq_tbl clk_tbl_gp
[] = {
1377 { 9600000, P_CXO
, 2, 0, 0 },
1378 { 13500000, P_PXO
, 2, 0, 0 },
1379 { 19200000, P_CXO
, 1, 0, 0 },
1380 { 27000000, P_PXO
, 1, 0, 0 },
1381 { 64000000, P_PLL8
, 2, 1, 3 },
1382 { 76800000, P_PLL8
, 1, 1, 5 },
1383 { 96000000, P_PLL8
, 4, 0, 0 },
1384 { 128000000, P_PLL8
, 3, 0, 0 },
1385 { 192000000, P_PLL8
, 2, 0, 0 },
1389 static struct clk_rcg gp0_src
= {
1394 .mnctr_reset_bit
= 7,
1395 .mnctr_mode_shift
= 5,
1406 .parent_map
= gcc_pxo_pll8_cxo_map
,
1408 .freq_tbl
= clk_tbl_gp
,
1410 .enable_reg
= 0x2d24,
1411 .enable_mask
= BIT(11),
1412 .hw
.init
= &(struct clk_init_data
){
1414 .parent_names
= gcc_pxo_pll8_cxo
,
1416 .ops
= &clk_rcg_ops
,
1417 .flags
= CLK_SET_PARENT_GATE
,
1422 static struct clk_branch gp0_clk
= {
1426 .enable_reg
= 0x2d24,
1427 .enable_mask
= BIT(9),
1428 .hw
.init
= &(struct clk_init_data
){
1430 .parent_names
= (const char *[]){ "gp0_src" },
1432 .ops
= &clk_branch_ops
,
1433 .flags
= CLK_SET_RATE_PARENT
,
1438 static struct clk_rcg gp1_src
= {
1443 .mnctr_reset_bit
= 7,
1444 .mnctr_mode_shift
= 5,
1455 .parent_map
= gcc_pxo_pll8_cxo_map
,
1457 .freq_tbl
= clk_tbl_gp
,
1459 .enable_reg
= 0x2d44,
1460 .enable_mask
= BIT(11),
1461 .hw
.init
= &(struct clk_init_data
){
1463 .parent_names
= gcc_pxo_pll8_cxo
,
1465 .ops
= &clk_rcg_ops
,
1466 .flags
= CLK_SET_RATE_GATE
,
1471 static struct clk_branch gp1_clk
= {
1475 .enable_reg
= 0x2d44,
1476 .enable_mask
= BIT(9),
1477 .hw
.init
= &(struct clk_init_data
){
1479 .parent_names
= (const char *[]){ "gp1_src" },
1481 .ops
= &clk_branch_ops
,
1482 .flags
= CLK_SET_RATE_PARENT
,
1487 static struct clk_rcg gp2_src
= {
1492 .mnctr_reset_bit
= 7,
1493 .mnctr_mode_shift
= 5,
1504 .parent_map
= gcc_pxo_pll8_cxo_map
,
1506 .freq_tbl
= clk_tbl_gp
,
1508 .enable_reg
= 0x2d64,
1509 .enable_mask
= BIT(11),
1510 .hw
.init
= &(struct clk_init_data
){
1512 .parent_names
= gcc_pxo_pll8_cxo
,
1514 .ops
= &clk_rcg_ops
,
1515 .flags
= CLK_SET_RATE_GATE
,
1520 static struct clk_branch gp2_clk
= {
1524 .enable_reg
= 0x2d64,
1525 .enable_mask
= BIT(9),
1526 .hw
.init
= &(struct clk_init_data
){
1528 .parent_names
= (const char *[]){ "gp2_src" },
1530 .ops
= &clk_branch_ops
,
1531 .flags
= CLK_SET_RATE_PARENT
,
1536 static struct clk_branch pmem_clk
= {
1542 .enable_reg
= 0x25a0,
1543 .enable_mask
= BIT(4),
1544 .hw
.init
= &(struct clk_init_data
){
1546 .ops
= &clk_branch_ops
,
1547 .flags
= CLK_IS_ROOT
,
1552 static struct clk_rcg prng_src
= {
1560 .parent_map
= gcc_pxo_pll8_map
,
1563 .hw
.init
= &(struct clk_init_data
){
1565 .parent_names
= gcc_pxo_pll8
,
1567 .ops
= &clk_rcg_ops
,
1572 static struct clk_branch prng_clk
= {
1574 .halt_check
= BRANCH_HALT_VOTED
,
1577 .enable_reg
= 0x3080,
1578 .enable_mask
= BIT(10),
1579 .hw
.init
= &(struct clk_init_data
){
1581 .parent_names
= (const char *[]){ "prng_src" },
1583 .ops
= &clk_branch_ops
,
1588 static const struct freq_tbl clk_tbl_sdc
[] = {
1589 { 144000, P_PXO
, 3, 2, 125 },
1590 { 400000, P_PLL8
, 4, 1, 240 },
1591 { 16000000, P_PLL8
, 4, 1, 6 },
1592 { 17070000, P_PLL8
, 1, 2, 45 },
1593 { 20210000, P_PLL8
, 1, 1, 19 },
1594 { 24000000, P_PLL8
, 4, 1, 4 },
1595 { 48000000, P_PLL8
, 4, 1, 2 },
1596 { 64000000, P_PLL8
, 3, 1, 2 },
1597 { 96000000, P_PLL8
, 4, 0, 0 },
1598 { 192000000, P_PLL8
, 2, 0, 0 },
1602 static struct clk_rcg sdc1_src
= {
1607 .mnctr_reset_bit
= 7,
1608 .mnctr_mode_shift
= 5,
1619 .parent_map
= gcc_pxo_pll8_map
,
1621 .freq_tbl
= clk_tbl_sdc
,
1623 .enable_reg
= 0x282c,
1624 .enable_mask
= BIT(11),
1625 .hw
.init
= &(struct clk_init_data
){
1627 .parent_names
= gcc_pxo_pll8
,
1629 .ops
= &clk_rcg_ops
,
1630 .flags
= CLK_SET_RATE_GATE
,
1635 static struct clk_branch sdc1_clk
= {
1639 .enable_reg
= 0x282c,
1640 .enable_mask
= BIT(9),
1641 .hw
.init
= &(struct clk_init_data
){
1643 .parent_names
= (const char *[]){ "sdc1_src" },
1645 .ops
= &clk_branch_ops
,
1646 .flags
= CLK_SET_RATE_PARENT
,
1651 static struct clk_rcg sdc2_src
= {
1656 .mnctr_reset_bit
= 7,
1657 .mnctr_mode_shift
= 5,
1668 .parent_map
= gcc_pxo_pll8_map
,
1670 .freq_tbl
= clk_tbl_sdc
,
1672 .enable_reg
= 0x284c,
1673 .enable_mask
= BIT(11),
1674 .hw
.init
= &(struct clk_init_data
){
1676 .parent_names
= gcc_pxo_pll8
,
1678 .ops
= &clk_rcg_ops
,
1679 .flags
= CLK_SET_RATE_GATE
,
1684 static struct clk_branch sdc2_clk
= {
1688 .enable_reg
= 0x284c,
1689 .enable_mask
= BIT(9),
1690 .hw
.init
= &(struct clk_init_data
){
1692 .parent_names
= (const char *[]){ "sdc2_src" },
1694 .ops
= &clk_branch_ops
,
1695 .flags
= CLK_SET_RATE_PARENT
,
1700 static struct clk_rcg sdc3_src
= {
1705 .mnctr_reset_bit
= 7,
1706 .mnctr_mode_shift
= 5,
1717 .parent_map
= gcc_pxo_pll8_map
,
1719 .freq_tbl
= clk_tbl_sdc
,
1721 .enable_reg
= 0x286c,
1722 .enable_mask
= BIT(11),
1723 .hw
.init
= &(struct clk_init_data
){
1725 .parent_names
= gcc_pxo_pll8
,
1727 .ops
= &clk_rcg_ops
,
1728 .flags
= CLK_SET_RATE_GATE
,
1733 static struct clk_branch sdc3_clk
= {
1737 .enable_reg
= 0x286c,
1738 .enable_mask
= BIT(9),
1739 .hw
.init
= &(struct clk_init_data
){
1741 .parent_names
= (const char *[]){ "sdc3_src" },
1743 .ops
= &clk_branch_ops
,
1744 .flags
= CLK_SET_RATE_PARENT
,
1749 static struct clk_rcg sdc4_src
= {
1754 .mnctr_reset_bit
= 7,
1755 .mnctr_mode_shift
= 5,
1766 .parent_map
= gcc_pxo_pll8_map
,
1768 .freq_tbl
= clk_tbl_sdc
,
1770 .enable_reg
= 0x288c,
1771 .enable_mask
= BIT(11),
1772 .hw
.init
= &(struct clk_init_data
){
1774 .parent_names
= gcc_pxo_pll8
,
1776 .ops
= &clk_rcg_ops
,
1777 .flags
= CLK_SET_RATE_GATE
,
1782 static struct clk_branch sdc4_clk
= {
1786 .enable_reg
= 0x288c,
1787 .enable_mask
= BIT(9),
1788 .hw
.init
= &(struct clk_init_data
){
1790 .parent_names
= (const char *[]){ "sdc4_src" },
1792 .ops
= &clk_branch_ops
,
1793 .flags
= CLK_SET_RATE_PARENT
,
1798 static struct clk_rcg sdc5_src
= {
1803 .mnctr_reset_bit
= 7,
1804 .mnctr_mode_shift
= 5,
1815 .parent_map
= gcc_pxo_pll8_map
,
1817 .freq_tbl
= clk_tbl_sdc
,
1819 .enable_reg
= 0x28ac,
1820 .enable_mask
= BIT(11),
1821 .hw
.init
= &(struct clk_init_data
){
1823 .parent_names
= gcc_pxo_pll8
,
1825 .ops
= &clk_rcg_ops
,
1826 .flags
= CLK_SET_RATE_GATE
,
1831 static struct clk_branch sdc5_clk
= {
1835 .enable_reg
= 0x28ac,
1836 .enable_mask
= BIT(9),
1837 .hw
.init
= &(struct clk_init_data
){
1839 .parent_names
= (const char *[]){ "sdc5_src" },
1841 .ops
= &clk_branch_ops
,
1842 .flags
= CLK_SET_RATE_PARENT
,
1847 static const struct freq_tbl clk_tbl_tsif_ref
[] = {
1848 { 105000, P_PXO
, 1, 1, 256 },
1852 static struct clk_rcg tsif_ref_src
= {
1857 .mnctr_reset_bit
= 7,
1858 .mnctr_mode_shift
= 5,
1869 .parent_map
= gcc_pxo_pll8_map
,
1871 .freq_tbl
= clk_tbl_tsif_ref
,
1873 .enable_reg
= 0x2710,
1874 .enable_mask
= BIT(11),
1875 .hw
.init
= &(struct clk_init_data
){
1876 .name
= "tsif_ref_src",
1877 .parent_names
= gcc_pxo_pll8
,
1879 .ops
= &clk_rcg_ops
,
1880 .flags
= CLK_SET_RATE_GATE
,
1885 static struct clk_branch tsif_ref_clk
= {
1889 .enable_reg
= 0x2710,
1890 .enable_mask
= BIT(9),
1891 .hw
.init
= &(struct clk_init_data
){
1892 .name
= "tsif_ref_clk",
1893 .parent_names
= (const char *[]){ "tsif_ref_src" },
1895 .ops
= &clk_branch_ops
,
1896 .flags
= CLK_SET_RATE_PARENT
,
1901 static const struct freq_tbl clk_tbl_usb
[] = {
1902 { 60000000, P_PLL8
, 1, 5, 32 },
1906 static struct clk_rcg usb_hs1_xcvr_src
= {
1911 .mnctr_reset_bit
= 7,
1912 .mnctr_mode_shift
= 5,
1923 .parent_map
= gcc_pxo_pll8_map
,
1925 .freq_tbl
= clk_tbl_usb
,
1927 .enable_reg
= 0x290c,
1928 .enable_mask
= BIT(11),
1929 .hw
.init
= &(struct clk_init_data
){
1930 .name
= "usb_hs1_xcvr_src",
1931 .parent_names
= gcc_pxo_pll8
,
1933 .ops
= &clk_rcg_ops
,
1934 .flags
= CLK_SET_RATE_GATE
,
1939 static struct clk_branch usb_hs1_xcvr_clk
= {
1943 .enable_reg
= 0x290c,
1944 .enable_mask
= BIT(9),
1945 .hw
.init
= &(struct clk_init_data
){
1946 .name
= "usb_hs1_xcvr_clk",
1947 .parent_names
= (const char *[]){ "usb_hs1_xcvr_src" },
1949 .ops
= &clk_branch_ops
,
1950 .flags
= CLK_SET_RATE_PARENT
,
1955 static struct clk_rcg usb_hs3_xcvr_src
= {
1960 .mnctr_reset_bit
= 7,
1961 .mnctr_mode_shift
= 5,
1972 .parent_map
= gcc_pxo_pll8_map
,
1974 .freq_tbl
= clk_tbl_usb
,
1976 .enable_reg
= 0x370c,
1977 .enable_mask
= BIT(11),
1978 .hw
.init
= &(struct clk_init_data
){
1979 .name
= "usb_hs3_xcvr_src",
1980 .parent_names
= gcc_pxo_pll8
,
1982 .ops
= &clk_rcg_ops
,
1983 .flags
= CLK_SET_RATE_GATE
,
1988 static struct clk_branch usb_hs3_xcvr_clk
= {
1992 .enable_reg
= 0x370c,
1993 .enable_mask
= BIT(9),
1994 .hw
.init
= &(struct clk_init_data
){
1995 .name
= "usb_hs3_xcvr_clk",
1996 .parent_names
= (const char *[]){ "usb_hs3_xcvr_src" },
1998 .ops
= &clk_branch_ops
,
1999 .flags
= CLK_SET_RATE_PARENT
,
2004 static struct clk_rcg usb_hs4_xcvr_src
= {
2009 .mnctr_reset_bit
= 7,
2010 .mnctr_mode_shift
= 5,
2021 .parent_map
= gcc_pxo_pll8_map
,
2023 .freq_tbl
= clk_tbl_usb
,
2025 .enable_reg
= 0x372c,
2026 .enable_mask
= BIT(11),
2027 .hw
.init
= &(struct clk_init_data
){
2028 .name
= "usb_hs4_xcvr_src",
2029 .parent_names
= gcc_pxo_pll8
,
2031 .ops
= &clk_rcg_ops
,
2032 .flags
= CLK_SET_RATE_GATE
,
2037 static struct clk_branch usb_hs4_xcvr_clk
= {
2041 .enable_reg
= 0x372c,
2042 .enable_mask
= BIT(9),
2043 .hw
.init
= &(struct clk_init_data
){
2044 .name
= "usb_hs4_xcvr_clk",
2045 .parent_names
= (const char *[]){ "usb_hs4_xcvr_src" },
2047 .ops
= &clk_branch_ops
,
2048 .flags
= CLK_SET_RATE_PARENT
,
2053 static struct clk_rcg usb_hsic_xcvr_fs_src
= {
2058 .mnctr_reset_bit
= 7,
2059 .mnctr_mode_shift
= 5,
2070 .parent_map
= gcc_pxo_pll8_map
,
2072 .freq_tbl
= clk_tbl_usb
,
2074 .enable_reg
= 0x2928,
2075 .enable_mask
= BIT(11),
2076 .hw
.init
= &(struct clk_init_data
){
2077 .name
= "usb_hsic_xcvr_fs_src",
2078 .parent_names
= gcc_pxo_pll8
,
2080 .ops
= &clk_rcg_ops
,
2081 .flags
= CLK_SET_RATE_GATE
,
2086 static const char *usb_hsic_xcvr_fs_src_p
[] = { "usb_hsic_xcvr_fs_src" };
2088 static struct clk_branch usb_hsic_xcvr_fs_clk
= {
2092 .enable_reg
= 0x2928,
2093 .enable_mask
= BIT(9),
2094 .hw
.init
= &(struct clk_init_data
){
2095 .name
= "usb_hsic_xcvr_fs_clk",
2096 .parent_names
= usb_hsic_xcvr_fs_src_p
,
2098 .ops
= &clk_branch_ops
,
2099 .flags
= CLK_SET_RATE_PARENT
,
2104 static struct clk_branch usb_hsic_system_clk
= {
2108 .enable_reg
= 0x292c,
2109 .enable_mask
= BIT(4),
2110 .hw
.init
= &(struct clk_init_data
){
2111 .parent_names
= usb_hsic_xcvr_fs_src_p
,
2113 .name
= "usb_hsic_system_clk",
2114 .ops
= &clk_branch_ops
,
2115 .flags
= CLK_SET_RATE_PARENT
,
2120 static struct clk_branch usb_hsic_hsic_clk
= {
2124 .enable_reg
= 0x2b44,
2125 .enable_mask
= BIT(0),
2126 .hw
.init
= &(struct clk_init_data
){
2127 .parent_names
= (const char *[]){ "pll14_vote" },
2129 .name
= "usb_hsic_hsic_clk",
2130 .ops
= &clk_branch_ops
,
2135 static struct clk_branch usb_hsic_hsio_cal_clk
= {
2139 .enable_reg
= 0x2b48,
2140 .enable_mask
= BIT(0),
2141 .hw
.init
= &(struct clk_init_data
){
2142 .name
= "usb_hsic_hsio_cal_clk",
2143 .ops
= &clk_branch_ops
,
2144 .flags
= CLK_IS_ROOT
,
2149 static struct clk_rcg usb_fs1_xcvr_fs_src
= {
2154 .mnctr_reset_bit
= 7,
2155 .mnctr_mode_shift
= 5,
2166 .parent_map
= gcc_pxo_pll8_map
,
2168 .freq_tbl
= clk_tbl_usb
,
2170 .enable_reg
= 0x2968,
2171 .enable_mask
= BIT(11),
2172 .hw
.init
= &(struct clk_init_data
){
2173 .name
= "usb_fs1_xcvr_fs_src",
2174 .parent_names
= gcc_pxo_pll8
,
2176 .ops
= &clk_rcg_ops
,
2177 .flags
= CLK_SET_RATE_GATE
,
2182 static const char *usb_fs1_xcvr_fs_src_p
[] = { "usb_fs1_xcvr_fs_src" };
2184 static struct clk_branch usb_fs1_xcvr_fs_clk
= {
2188 .enable_reg
= 0x2968,
2189 .enable_mask
= BIT(9),
2190 .hw
.init
= &(struct clk_init_data
){
2191 .name
= "usb_fs1_xcvr_fs_clk",
2192 .parent_names
= usb_fs1_xcvr_fs_src_p
,
2194 .ops
= &clk_branch_ops
,
2195 .flags
= CLK_SET_RATE_PARENT
,
2200 static struct clk_branch usb_fs1_system_clk
= {
2204 .enable_reg
= 0x296c,
2205 .enable_mask
= BIT(4),
2206 .hw
.init
= &(struct clk_init_data
){
2207 .parent_names
= usb_fs1_xcvr_fs_src_p
,
2209 .name
= "usb_fs1_system_clk",
2210 .ops
= &clk_branch_ops
,
2211 .flags
= CLK_SET_RATE_PARENT
,
2216 static struct clk_rcg usb_fs2_xcvr_fs_src
= {
2221 .mnctr_reset_bit
= 7,
2222 .mnctr_mode_shift
= 5,
2233 .parent_map
= gcc_pxo_pll8_map
,
2235 .freq_tbl
= clk_tbl_usb
,
2237 .enable_reg
= 0x2988,
2238 .enable_mask
= BIT(11),
2239 .hw
.init
= &(struct clk_init_data
){
2240 .name
= "usb_fs2_xcvr_fs_src",
2241 .parent_names
= gcc_pxo_pll8
,
2243 .ops
= &clk_rcg_ops
,
2244 .flags
= CLK_SET_RATE_GATE
,
2249 static const char *usb_fs2_xcvr_fs_src_p
[] = { "usb_fs2_xcvr_fs_src" };
2251 static struct clk_branch usb_fs2_xcvr_fs_clk
= {
2255 .enable_reg
= 0x2988,
2256 .enable_mask
= BIT(9),
2257 .hw
.init
= &(struct clk_init_data
){
2258 .name
= "usb_fs2_xcvr_fs_clk",
2259 .parent_names
= usb_fs2_xcvr_fs_src_p
,
2261 .ops
= &clk_branch_ops
,
2262 .flags
= CLK_SET_RATE_PARENT
,
2267 static struct clk_branch usb_fs2_system_clk
= {
2271 .enable_reg
= 0x298c,
2272 .enable_mask
= BIT(4),
2273 .hw
.init
= &(struct clk_init_data
){
2274 .name
= "usb_fs2_system_clk",
2275 .parent_names
= usb_fs2_xcvr_fs_src_p
,
2277 .ops
= &clk_branch_ops
,
2278 .flags
= CLK_SET_RATE_PARENT
,
2283 static struct clk_branch ce1_core_clk
= {
2289 .enable_reg
= 0x2724,
2290 .enable_mask
= BIT(4),
2291 .hw
.init
= &(struct clk_init_data
){
2292 .name
= "ce1_core_clk",
2293 .ops
= &clk_branch_ops
,
2294 .flags
= CLK_IS_ROOT
,
2299 static struct clk_branch ce1_h_clk
= {
2303 .enable_reg
= 0x2720,
2304 .enable_mask
= BIT(4),
2305 .hw
.init
= &(struct clk_init_data
){
2306 .name
= "ce1_h_clk",
2307 .ops
= &clk_branch_ops
,
2308 .flags
= CLK_IS_ROOT
,
2313 static struct clk_branch dma_bam_h_clk
= {
2319 .enable_reg
= 0x25c0,
2320 .enable_mask
= BIT(4),
2321 .hw
.init
= &(struct clk_init_data
){
2322 .name
= "dma_bam_h_clk",
2323 .ops
= &clk_branch_ops
,
2324 .flags
= CLK_IS_ROOT
,
2329 static struct clk_branch gsbi1_h_clk
= {
2335 .enable_reg
= 0x29c0,
2336 .enable_mask
= BIT(4),
2337 .hw
.init
= &(struct clk_init_data
){
2338 .name
= "gsbi1_h_clk",
2339 .ops
= &clk_branch_ops
,
2340 .flags
= CLK_IS_ROOT
,
2345 static struct clk_branch gsbi2_h_clk
= {
2351 .enable_reg
= 0x29e0,
2352 .enable_mask
= BIT(4),
2353 .hw
.init
= &(struct clk_init_data
){
2354 .name
= "gsbi2_h_clk",
2355 .ops
= &clk_branch_ops
,
2356 .flags
= CLK_IS_ROOT
,
2361 static struct clk_branch gsbi3_h_clk
= {
2367 .enable_reg
= 0x2a00,
2368 .enable_mask
= BIT(4),
2369 .hw
.init
= &(struct clk_init_data
){
2370 .name
= "gsbi3_h_clk",
2371 .ops
= &clk_branch_ops
,
2372 .flags
= CLK_IS_ROOT
,
2377 static struct clk_branch gsbi4_h_clk
= {
2383 .enable_reg
= 0x2a20,
2384 .enable_mask
= BIT(4),
2385 .hw
.init
= &(struct clk_init_data
){
2386 .name
= "gsbi4_h_clk",
2387 .ops
= &clk_branch_ops
,
2388 .flags
= CLK_IS_ROOT
,
2393 static struct clk_branch gsbi5_h_clk
= {
2399 .enable_reg
= 0x2a40,
2400 .enable_mask
= BIT(4),
2401 .hw
.init
= &(struct clk_init_data
){
2402 .name
= "gsbi5_h_clk",
2403 .ops
= &clk_branch_ops
,
2404 .flags
= CLK_IS_ROOT
,
2409 static struct clk_branch gsbi6_h_clk
= {
2415 .enable_reg
= 0x2a60,
2416 .enable_mask
= BIT(4),
2417 .hw
.init
= &(struct clk_init_data
){
2418 .name
= "gsbi6_h_clk",
2419 .ops
= &clk_branch_ops
,
2420 .flags
= CLK_IS_ROOT
,
2425 static struct clk_branch gsbi7_h_clk
= {
2431 .enable_reg
= 0x2a80,
2432 .enable_mask
= BIT(4),
2433 .hw
.init
= &(struct clk_init_data
){
2434 .name
= "gsbi7_h_clk",
2435 .ops
= &clk_branch_ops
,
2436 .flags
= CLK_IS_ROOT
,
2441 static struct clk_branch gsbi8_h_clk
= {
2447 .enable_reg
= 0x2aa0,
2448 .enable_mask
= BIT(4),
2449 .hw
.init
= &(struct clk_init_data
){
2450 .name
= "gsbi8_h_clk",
2451 .ops
= &clk_branch_ops
,
2452 .flags
= CLK_IS_ROOT
,
2457 static struct clk_branch gsbi9_h_clk
= {
2463 .enable_reg
= 0x2ac0,
2464 .enable_mask
= BIT(4),
2465 .hw
.init
= &(struct clk_init_data
){
2466 .name
= "gsbi9_h_clk",
2467 .ops
= &clk_branch_ops
,
2468 .flags
= CLK_IS_ROOT
,
2473 static struct clk_branch gsbi10_h_clk
= {
2479 .enable_reg
= 0x2ae0,
2480 .enable_mask
= BIT(4),
2481 .hw
.init
= &(struct clk_init_data
){
2482 .name
= "gsbi10_h_clk",
2483 .ops
= &clk_branch_ops
,
2484 .flags
= CLK_IS_ROOT
,
2489 static struct clk_branch gsbi11_h_clk
= {
2495 .enable_reg
= 0x2b00,
2496 .enable_mask
= BIT(4),
2497 .hw
.init
= &(struct clk_init_data
){
2498 .name
= "gsbi11_h_clk",
2499 .ops
= &clk_branch_ops
,
2500 .flags
= CLK_IS_ROOT
,
2505 static struct clk_branch gsbi12_h_clk
= {
2511 .enable_reg
= 0x2b20,
2512 .enable_mask
= BIT(4),
2513 .hw
.init
= &(struct clk_init_data
){
2514 .name
= "gsbi12_h_clk",
2515 .ops
= &clk_branch_ops
,
2516 .flags
= CLK_IS_ROOT
,
2521 static struct clk_branch tsif_h_clk
= {
2527 .enable_reg
= 0x2700,
2528 .enable_mask
= BIT(4),
2529 .hw
.init
= &(struct clk_init_data
){
2530 .name
= "tsif_h_clk",
2531 .ops
= &clk_branch_ops
,
2532 .flags
= CLK_IS_ROOT
,
2537 static struct clk_branch usb_fs1_h_clk
= {
2541 .enable_reg
= 0x2960,
2542 .enable_mask
= BIT(4),
2543 .hw
.init
= &(struct clk_init_data
){
2544 .name
= "usb_fs1_h_clk",
2545 .ops
= &clk_branch_ops
,
2546 .flags
= CLK_IS_ROOT
,
2551 static struct clk_branch usb_fs2_h_clk
= {
2555 .enable_reg
= 0x2980,
2556 .enable_mask
= BIT(4),
2557 .hw
.init
= &(struct clk_init_data
){
2558 .name
= "usb_fs2_h_clk",
2559 .ops
= &clk_branch_ops
,
2560 .flags
= CLK_IS_ROOT
,
2565 static struct clk_branch usb_hs1_h_clk
= {
2571 .enable_reg
= 0x2900,
2572 .enable_mask
= BIT(4),
2573 .hw
.init
= &(struct clk_init_data
){
2574 .name
= "usb_hs1_h_clk",
2575 .ops
= &clk_branch_ops
,
2576 .flags
= CLK_IS_ROOT
,
2581 static struct clk_branch usb_hs3_h_clk
= {
2585 .enable_reg
= 0x3700,
2586 .enable_mask
= BIT(4),
2587 .hw
.init
= &(struct clk_init_data
){
2588 .name
= "usb_hs3_h_clk",
2589 .ops
= &clk_branch_ops
,
2590 .flags
= CLK_IS_ROOT
,
2595 static struct clk_branch usb_hs4_h_clk
= {
2599 .enable_reg
= 0x3720,
2600 .enable_mask
= BIT(4),
2601 .hw
.init
= &(struct clk_init_data
){
2602 .name
= "usb_hs4_h_clk",
2603 .ops
= &clk_branch_ops
,
2604 .flags
= CLK_IS_ROOT
,
2609 static struct clk_branch usb_hsic_h_clk
= {
2613 .enable_reg
= 0x2920,
2614 .enable_mask
= BIT(4),
2615 .hw
.init
= &(struct clk_init_data
){
2616 .name
= "usb_hsic_h_clk",
2617 .ops
= &clk_branch_ops
,
2618 .flags
= CLK_IS_ROOT
,
2623 static struct clk_branch sdc1_h_clk
= {
2629 .enable_reg
= 0x2820,
2630 .enable_mask
= BIT(4),
2631 .hw
.init
= &(struct clk_init_data
){
2632 .name
= "sdc1_h_clk",
2633 .ops
= &clk_branch_ops
,
2634 .flags
= CLK_IS_ROOT
,
2639 static struct clk_branch sdc2_h_clk
= {
2645 .enable_reg
= 0x2840,
2646 .enable_mask
= BIT(4),
2647 .hw
.init
= &(struct clk_init_data
){
2648 .name
= "sdc2_h_clk",
2649 .ops
= &clk_branch_ops
,
2650 .flags
= CLK_IS_ROOT
,
2655 static struct clk_branch sdc3_h_clk
= {
2661 .enable_reg
= 0x2860,
2662 .enable_mask
= BIT(4),
2663 .hw
.init
= &(struct clk_init_data
){
2664 .name
= "sdc3_h_clk",
2665 .ops
= &clk_branch_ops
,
2666 .flags
= CLK_IS_ROOT
,
2671 static struct clk_branch sdc4_h_clk
= {
2677 .enable_reg
= 0x2880,
2678 .enable_mask
= BIT(4),
2679 .hw
.init
= &(struct clk_init_data
){
2680 .name
= "sdc4_h_clk",
2681 .ops
= &clk_branch_ops
,
2682 .flags
= CLK_IS_ROOT
,
2687 static struct clk_branch sdc5_h_clk
= {
2693 .enable_reg
= 0x28a0,
2694 .enable_mask
= BIT(4),
2695 .hw
.init
= &(struct clk_init_data
){
2696 .name
= "sdc5_h_clk",
2697 .ops
= &clk_branch_ops
,
2698 .flags
= CLK_IS_ROOT
,
2703 static struct clk_branch adm0_clk
= {
2705 .halt_check
= BRANCH_HALT_VOTED
,
2708 .enable_reg
= 0x3080,
2709 .enable_mask
= BIT(2),
2710 .hw
.init
= &(struct clk_init_data
){
2712 .ops
= &clk_branch_ops
,
2713 .flags
= CLK_IS_ROOT
,
2718 static struct clk_branch adm0_pbus_clk
= {
2722 .halt_check
= BRANCH_HALT_VOTED
,
2725 .enable_reg
= 0x3080,
2726 .enable_mask
= BIT(3),
2727 .hw
.init
= &(struct clk_init_data
){
2728 .name
= "adm0_pbus_clk",
2729 .ops
= &clk_branch_ops
,
2730 .flags
= CLK_IS_ROOT
,
2735 static struct freq_tbl clk_tbl_ce3
[] = {
2736 { 48000000, P_PLL8
, 8 },
2737 { 100000000, P_PLL3
, 12 },
2738 { 120000000, P_PLL3
, 10 },
2742 static struct clk_rcg ce3_src
= {
2750 .parent_map
= gcc_pxo_pll8_pll3_map
,
2752 .freq_tbl
= clk_tbl_ce3
,
2754 .enable_reg
= 0x2c08,
2755 .enable_mask
= BIT(7),
2756 .hw
.init
= &(struct clk_init_data
){
2758 .parent_names
= gcc_pxo_pll8_pll3
,
2760 .ops
= &clk_rcg_ops
,
2761 .flags
= CLK_SET_RATE_GATE
,
2766 static struct clk_branch ce3_core_clk
= {
2770 .enable_reg
= 0x36c4,
2771 .enable_mask
= BIT(4),
2772 .hw
.init
= &(struct clk_init_data
){
2773 .name
= "ce3_core_clk",
2774 .parent_names
= (const char *[]){ "ce3_src" },
2776 .ops
= &clk_branch_ops
,
2777 .flags
= CLK_SET_RATE_PARENT
,
2782 static struct clk_branch ce3_h_clk
= {
2786 .enable_reg
= 0x36c4,
2787 .enable_mask
= BIT(4),
2788 .hw
.init
= &(struct clk_init_data
){
2789 .name
= "ce3_h_clk",
2790 .parent_names
= (const char *[]){ "ce3_src" },
2792 .ops
= &clk_branch_ops
,
2793 .flags
= CLK_SET_RATE_PARENT
,
2798 static const struct freq_tbl clk_tbl_sata_ref
[] = {
2799 { 48000000, P_PLL8
, 8, 0, 0 },
2800 { 100000000, P_PLL3
, 12, 0, 0 },
2804 static struct clk_rcg sata_clk_src
= {
2812 .parent_map
= gcc_pxo_pll8_pll3_map
,
2814 .freq_tbl
= clk_tbl_sata_ref
,
2816 .enable_reg
= 0x2c08,
2817 .enable_mask
= BIT(7),
2818 .hw
.init
= &(struct clk_init_data
){
2819 .name
= "sata_clk_src",
2820 .parent_names
= gcc_pxo_pll8_pll3
,
2822 .ops
= &clk_rcg_ops
,
2823 .flags
= CLK_SET_RATE_GATE
,
2828 static struct clk_branch sata_rxoob_clk
= {
2832 .enable_reg
= 0x2c0c,
2833 .enable_mask
= BIT(4),
2834 .hw
.init
= &(struct clk_init_data
){
2835 .name
= "sata_rxoob_clk",
2836 .parent_names
= (const char *[]){ "sata_clk_src" },
2838 .ops
= &clk_branch_ops
,
2839 .flags
= CLK_SET_RATE_PARENT
,
2844 static struct clk_branch sata_pmalive_clk
= {
2848 .enable_reg
= 0x2c10,
2849 .enable_mask
= BIT(4),
2850 .hw
.init
= &(struct clk_init_data
){
2851 .name
= "sata_pmalive_clk",
2852 .parent_names
= (const char *[]){ "sata_clk_src" },
2854 .ops
= &clk_branch_ops
,
2855 .flags
= CLK_SET_RATE_PARENT
,
2860 static struct clk_branch sata_phy_ref_clk
= {
2864 .enable_reg
= 0x2c14,
2865 .enable_mask
= BIT(4),
2866 .hw
.init
= &(struct clk_init_data
){
2867 .name
= "sata_phy_ref_clk",
2868 .parent_names
= (const char *[]){ "pxo" },
2870 .ops
= &clk_branch_ops
,
2875 static struct clk_branch sata_a_clk
= {
2879 .enable_reg
= 0x2c20,
2880 .enable_mask
= BIT(4),
2881 .hw
.init
= &(struct clk_init_data
){
2882 .name
= "sata_a_clk",
2883 .ops
= &clk_branch_ops
,
2884 .flags
= CLK_IS_ROOT
,
2889 static struct clk_branch sata_h_clk
= {
2893 .enable_reg
= 0x2c00,
2894 .enable_mask
= BIT(4),
2895 .hw
.init
= &(struct clk_init_data
){
2896 .name
= "sata_h_clk",
2897 .ops
= &clk_branch_ops
,
2898 .flags
= CLK_IS_ROOT
,
2903 static struct clk_branch sfab_sata_s_h_clk
= {
2907 .enable_reg
= 0x2480,
2908 .enable_mask
= BIT(4),
2909 .hw
.init
= &(struct clk_init_data
){
2910 .name
= "sfab_sata_s_h_clk",
2911 .ops
= &clk_branch_ops
,
2912 .flags
= CLK_IS_ROOT
,
2917 static struct clk_branch sata_phy_cfg_clk
= {
2921 .enable_reg
= 0x2c40,
2922 .enable_mask
= BIT(4),
2923 .hw
.init
= &(struct clk_init_data
){
2924 .name
= "sata_phy_cfg_clk",
2925 .ops
= &clk_branch_ops
,
2926 .flags
= CLK_IS_ROOT
,
2931 static struct clk_branch pcie_phy_ref_clk
= {
2935 .enable_reg
= 0x22d0,
2936 .enable_mask
= BIT(4),
2937 .hw
.init
= &(struct clk_init_data
){
2938 .name
= "pcie_phy_ref_clk",
2939 .ops
= &clk_branch_ops
,
2940 .flags
= CLK_IS_ROOT
,
2945 static struct clk_branch pcie_h_clk
= {
2949 .enable_reg
= 0x22cc,
2950 .enable_mask
= BIT(4),
2951 .hw
.init
= &(struct clk_init_data
){
2952 .name
= "pcie_h_clk",
2953 .ops
= &clk_branch_ops
,
2954 .flags
= CLK_IS_ROOT
,
2959 static struct clk_branch pcie_a_clk
= {
2963 .enable_reg
= 0x22c0,
2964 .enable_mask
= BIT(4),
2965 .hw
.init
= &(struct clk_init_data
){
2966 .name
= "pcie_a_clk",
2967 .ops
= &clk_branch_ops
,
2968 .flags
= CLK_IS_ROOT
,
2973 static struct clk_branch pmic_arb0_h_clk
= {
2975 .halt_check
= BRANCH_HALT_VOTED
,
2978 .enable_reg
= 0x3080,
2979 .enable_mask
= BIT(8),
2980 .hw
.init
= &(struct clk_init_data
){
2981 .name
= "pmic_arb0_h_clk",
2982 .ops
= &clk_branch_ops
,
2983 .flags
= CLK_IS_ROOT
,
2988 static struct clk_branch pmic_arb1_h_clk
= {
2990 .halt_check
= BRANCH_HALT_VOTED
,
2993 .enable_reg
= 0x3080,
2994 .enable_mask
= BIT(9),
2995 .hw
.init
= &(struct clk_init_data
){
2996 .name
= "pmic_arb1_h_clk",
2997 .ops
= &clk_branch_ops
,
2998 .flags
= CLK_IS_ROOT
,
3003 static struct clk_branch pmic_ssbi2_clk
= {
3005 .halt_check
= BRANCH_HALT_VOTED
,
3008 .enable_reg
= 0x3080,
3009 .enable_mask
= BIT(7),
3010 .hw
.init
= &(struct clk_init_data
){
3011 .name
= "pmic_ssbi2_clk",
3012 .ops
= &clk_branch_ops
,
3013 .flags
= CLK_IS_ROOT
,
3018 static struct clk_branch rpm_msg_ram_h_clk
= {
3022 .halt_check
= BRANCH_HALT_VOTED
,
3025 .enable_reg
= 0x3080,
3026 .enable_mask
= BIT(6),
3027 .hw
.init
= &(struct clk_init_data
){
3028 .name
= "rpm_msg_ram_h_clk",
3029 .ops
= &clk_branch_ops
,
3030 .flags
= CLK_IS_ROOT
,
3035 static struct clk_regmap
*gcc_msm8960_clks
[] = {
3036 [PLL3
] = &pll3
.clkr
,
3037 [PLL4_VOTE
] = &pll4_vote
,
3038 [PLL8
] = &pll8
.clkr
,
3039 [PLL8_VOTE
] = &pll8_vote
,
3040 [PLL14
] = &pll14
.clkr
,
3041 [PLL14_VOTE
] = &pll14_vote
,
3042 [GSBI1_UART_SRC
] = &gsbi1_uart_src
.clkr
,
3043 [GSBI1_UART_CLK
] = &gsbi1_uart_clk
.clkr
,
3044 [GSBI2_UART_SRC
] = &gsbi2_uart_src
.clkr
,
3045 [GSBI2_UART_CLK
] = &gsbi2_uart_clk
.clkr
,
3046 [GSBI3_UART_SRC
] = &gsbi3_uart_src
.clkr
,
3047 [GSBI3_UART_CLK
] = &gsbi3_uart_clk
.clkr
,
3048 [GSBI4_UART_SRC
] = &gsbi4_uart_src
.clkr
,
3049 [GSBI4_UART_CLK
] = &gsbi4_uart_clk
.clkr
,
3050 [GSBI5_UART_SRC
] = &gsbi5_uart_src
.clkr
,
3051 [GSBI5_UART_CLK
] = &gsbi5_uart_clk
.clkr
,
3052 [GSBI6_UART_SRC
] = &gsbi6_uart_src
.clkr
,
3053 [GSBI6_UART_CLK
] = &gsbi6_uart_clk
.clkr
,
3054 [GSBI7_UART_SRC
] = &gsbi7_uart_src
.clkr
,
3055 [GSBI7_UART_CLK
] = &gsbi7_uart_clk
.clkr
,
3056 [GSBI8_UART_SRC
] = &gsbi8_uart_src
.clkr
,
3057 [GSBI8_UART_CLK
] = &gsbi8_uart_clk
.clkr
,
3058 [GSBI9_UART_SRC
] = &gsbi9_uart_src
.clkr
,
3059 [GSBI9_UART_CLK
] = &gsbi9_uart_clk
.clkr
,
3060 [GSBI10_UART_SRC
] = &gsbi10_uart_src
.clkr
,
3061 [GSBI10_UART_CLK
] = &gsbi10_uart_clk
.clkr
,
3062 [GSBI11_UART_SRC
] = &gsbi11_uart_src
.clkr
,
3063 [GSBI11_UART_CLK
] = &gsbi11_uart_clk
.clkr
,
3064 [GSBI12_UART_SRC
] = &gsbi12_uart_src
.clkr
,
3065 [GSBI12_UART_CLK
] = &gsbi12_uart_clk
.clkr
,
3066 [GSBI1_QUP_SRC
] = &gsbi1_qup_src
.clkr
,
3067 [GSBI1_QUP_CLK
] = &gsbi1_qup_clk
.clkr
,
3068 [GSBI2_QUP_SRC
] = &gsbi2_qup_src
.clkr
,
3069 [GSBI2_QUP_CLK
] = &gsbi2_qup_clk
.clkr
,
3070 [GSBI3_QUP_SRC
] = &gsbi3_qup_src
.clkr
,
3071 [GSBI3_QUP_CLK
] = &gsbi3_qup_clk
.clkr
,
3072 [GSBI4_QUP_SRC
] = &gsbi4_qup_src
.clkr
,
3073 [GSBI4_QUP_CLK
] = &gsbi4_qup_clk
.clkr
,
3074 [GSBI5_QUP_SRC
] = &gsbi5_qup_src
.clkr
,
3075 [GSBI5_QUP_CLK
] = &gsbi5_qup_clk
.clkr
,
3076 [GSBI6_QUP_SRC
] = &gsbi6_qup_src
.clkr
,
3077 [GSBI6_QUP_CLK
] = &gsbi6_qup_clk
.clkr
,
3078 [GSBI7_QUP_SRC
] = &gsbi7_qup_src
.clkr
,
3079 [GSBI7_QUP_CLK
] = &gsbi7_qup_clk
.clkr
,
3080 [GSBI8_QUP_SRC
] = &gsbi8_qup_src
.clkr
,
3081 [GSBI8_QUP_CLK
] = &gsbi8_qup_clk
.clkr
,
3082 [GSBI9_QUP_SRC
] = &gsbi9_qup_src
.clkr
,
3083 [GSBI9_QUP_CLK
] = &gsbi9_qup_clk
.clkr
,
3084 [GSBI10_QUP_SRC
] = &gsbi10_qup_src
.clkr
,
3085 [GSBI10_QUP_CLK
] = &gsbi10_qup_clk
.clkr
,
3086 [GSBI11_QUP_SRC
] = &gsbi11_qup_src
.clkr
,
3087 [GSBI11_QUP_CLK
] = &gsbi11_qup_clk
.clkr
,
3088 [GSBI12_QUP_SRC
] = &gsbi12_qup_src
.clkr
,
3089 [GSBI12_QUP_CLK
] = &gsbi12_qup_clk
.clkr
,
3090 [GP0_SRC
] = &gp0_src
.clkr
,
3091 [GP0_CLK
] = &gp0_clk
.clkr
,
3092 [GP1_SRC
] = &gp1_src
.clkr
,
3093 [GP1_CLK
] = &gp1_clk
.clkr
,
3094 [GP2_SRC
] = &gp2_src
.clkr
,
3095 [GP2_CLK
] = &gp2_clk
.clkr
,
3096 [PMEM_A_CLK
] = &pmem_clk
.clkr
,
3097 [PRNG_SRC
] = &prng_src
.clkr
,
3098 [PRNG_CLK
] = &prng_clk
.clkr
,
3099 [SDC1_SRC
] = &sdc1_src
.clkr
,
3100 [SDC1_CLK
] = &sdc1_clk
.clkr
,
3101 [SDC2_SRC
] = &sdc2_src
.clkr
,
3102 [SDC2_CLK
] = &sdc2_clk
.clkr
,
3103 [SDC3_SRC
] = &sdc3_src
.clkr
,
3104 [SDC3_CLK
] = &sdc3_clk
.clkr
,
3105 [SDC4_SRC
] = &sdc4_src
.clkr
,
3106 [SDC4_CLK
] = &sdc4_clk
.clkr
,
3107 [SDC5_SRC
] = &sdc5_src
.clkr
,
3108 [SDC5_CLK
] = &sdc5_clk
.clkr
,
3109 [TSIF_REF_SRC
] = &tsif_ref_src
.clkr
,
3110 [TSIF_REF_CLK
] = &tsif_ref_clk
.clkr
,
3111 [USB_HS1_XCVR_SRC
] = &usb_hs1_xcvr_src
.clkr
,
3112 [USB_HS1_XCVR_CLK
] = &usb_hs1_xcvr_clk
.clkr
,
3113 [USB_HSIC_XCVR_FS_SRC
] = &usb_hsic_xcvr_fs_src
.clkr
,
3114 [USB_HSIC_XCVR_FS_CLK
] = &usb_hsic_xcvr_fs_clk
.clkr
,
3115 [USB_HSIC_SYSTEM_CLK
] = &usb_hsic_system_clk
.clkr
,
3116 [USB_HSIC_HSIC_CLK
] = &usb_hsic_hsic_clk
.clkr
,
3117 [USB_HSIC_HSIO_CAL_CLK
] = &usb_hsic_hsio_cal_clk
.clkr
,
3118 [USB_FS1_XCVR_FS_SRC
] = &usb_fs1_xcvr_fs_src
.clkr
,
3119 [USB_FS1_XCVR_FS_CLK
] = &usb_fs1_xcvr_fs_clk
.clkr
,
3120 [USB_FS1_SYSTEM_CLK
] = &usb_fs1_system_clk
.clkr
,
3121 [USB_FS2_XCVR_FS_SRC
] = &usb_fs2_xcvr_fs_src
.clkr
,
3122 [USB_FS2_XCVR_FS_CLK
] = &usb_fs2_xcvr_fs_clk
.clkr
,
3123 [USB_FS2_SYSTEM_CLK
] = &usb_fs2_system_clk
.clkr
,
3124 [CE1_CORE_CLK
] = &ce1_core_clk
.clkr
,
3125 [CE1_H_CLK
] = &ce1_h_clk
.clkr
,
3126 [DMA_BAM_H_CLK
] = &dma_bam_h_clk
.clkr
,
3127 [GSBI1_H_CLK
] = &gsbi1_h_clk
.clkr
,
3128 [GSBI2_H_CLK
] = &gsbi2_h_clk
.clkr
,
3129 [GSBI3_H_CLK
] = &gsbi3_h_clk
.clkr
,
3130 [GSBI4_H_CLK
] = &gsbi4_h_clk
.clkr
,
3131 [GSBI5_H_CLK
] = &gsbi5_h_clk
.clkr
,
3132 [GSBI6_H_CLK
] = &gsbi6_h_clk
.clkr
,
3133 [GSBI7_H_CLK
] = &gsbi7_h_clk
.clkr
,
3134 [GSBI8_H_CLK
] = &gsbi8_h_clk
.clkr
,
3135 [GSBI9_H_CLK
] = &gsbi9_h_clk
.clkr
,
3136 [GSBI10_H_CLK
] = &gsbi10_h_clk
.clkr
,
3137 [GSBI11_H_CLK
] = &gsbi11_h_clk
.clkr
,
3138 [GSBI12_H_CLK
] = &gsbi12_h_clk
.clkr
,
3139 [TSIF_H_CLK
] = &tsif_h_clk
.clkr
,
3140 [USB_FS1_H_CLK
] = &usb_fs1_h_clk
.clkr
,
3141 [USB_FS2_H_CLK
] = &usb_fs2_h_clk
.clkr
,
3142 [USB_HS1_H_CLK
] = &usb_hs1_h_clk
.clkr
,
3143 [USB_HSIC_H_CLK
] = &usb_hsic_h_clk
.clkr
,
3144 [SDC1_H_CLK
] = &sdc1_h_clk
.clkr
,
3145 [SDC2_H_CLK
] = &sdc2_h_clk
.clkr
,
3146 [SDC3_H_CLK
] = &sdc3_h_clk
.clkr
,
3147 [SDC4_H_CLK
] = &sdc4_h_clk
.clkr
,
3148 [SDC5_H_CLK
] = &sdc5_h_clk
.clkr
,
3149 [ADM0_CLK
] = &adm0_clk
.clkr
,
3150 [ADM0_PBUS_CLK
] = &adm0_pbus_clk
.clkr
,
3151 [PMIC_ARB0_H_CLK
] = &pmic_arb0_h_clk
.clkr
,
3152 [PMIC_ARB1_H_CLK
] = &pmic_arb1_h_clk
.clkr
,
3153 [PMIC_SSBI2_CLK
] = &pmic_ssbi2_clk
.clkr
,
3154 [RPM_MSG_RAM_H_CLK
] = &rpm_msg_ram_h_clk
.clkr
,
3157 static const struct qcom_reset_map gcc_msm8960_resets
[] = {
3158 [SFAB_MSS_Q6_SW_RESET
] = { 0x2040, 7 },
3159 [SFAB_MSS_Q6_FW_RESET
] = { 0x2044, 7 },
3160 [QDSS_STM_RESET
] = { 0x2060, 6 },
3161 [AFAB_SMPSS_S_RESET
] = { 0x20b8, 2 },
3162 [AFAB_SMPSS_M1_RESET
] = { 0x20b8, 1 },
3163 [AFAB_SMPSS_M0_RESET
] = { 0x20b8 },
3164 [AFAB_EBI1_CH0_RESET
] = { 0x20c0, 7 },
3165 [AFAB_EBI1_CH1_RESET
] = { 0x20c4, 7},
3166 [SFAB_ADM0_M0_RESET
] = { 0x21e0, 7 },
3167 [SFAB_ADM0_M1_RESET
] = { 0x21e4, 7 },
3168 [SFAB_ADM0_M2_RESET
] = { 0x21e8, 7 },
3169 [ADM0_C2_RESET
] = { 0x220c, 4},
3170 [ADM0_C1_RESET
] = { 0x220c, 3},
3171 [ADM0_C0_RESET
] = { 0x220c, 2},
3172 [ADM0_PBUS_RESET
] = { 0x220c, 1 },
3173 [ADM0_RESET
] = { 0x220c },
3174 [QDSS_CLKS_SW_RESET
] = { 0x2260, 5 },
3175 [QDSS_POR_RESET
] = { 0x2260, 4 },
3176 [QDSS_TSCTR_RESET
] = { 0x2260, 3 },
3177 [QDSS_HRESET_RESET
] = { 0x2260, 2 },
3178 [QDSS_AXI_RESET
] = { 0x2260, 1 },
3179 [QDSS_DBG_RESET
] = { 0x2260 },
3180 [PCIE_A_RESET
] = { 0x22c0, 7 },
3181 [PCIE_AUX_RESET
] = { 0x22c8, 7 },
3182 [PCIE_H_RESET
] = { 0x22d0, 7 },
3183 [SFAB_PCIE_M_RESET
] = { 0x22d4, 1 },
3184 [SFAB_PCIE_S_RESET
] = { 0x22d4 },
3185 [SFAB_MSS_M_RESET
] = { 0x2340, 7 },
3186 [SFAB_USB3_M_RESET
] = { 0x2360, 7 },
3187 [SFAB_RIVA_M_RESET
] = { 0x2380, 7 },
3188 [SFAB_LPASS_RESET
] = { 0x23a0, 7 },
3189 [SFAB_AFAB_M_RESET
] = { 0x23e0, 7 },
3190 [AFAB_SFAB_M0_RESET
] = { 0x2420, 7 },
3191 [AFAB_SFAB_M1_RESET
] = { 0x2424, 7 },
3192 [SFAB_SATA_S_RESET
] = { 0x2480, 7 },
3193 [SFAB_DFAB_M_RESET
] = { 0x2500, 7 },
3194 [DFAB_SFAB_M_RESET
] = { 0x2520, 7 },
3195 [DFAB_SWAY0_RESET
] = { 0x2540, 7 },
3196 [DFAB_SWAY1_RESET
] = { 0x2544, 7 },
3197 [DFAB_ARB0_RESET
] = { 0x2560, 7 },
3198 [DFAB_ARB1_RESET
] = { 0x2564, 7 },
3199 [PPSS_PROC_RESET
] = { 0x2594, 1 },
3200 [PPSS_RESET
] = { 0x2594},
3201 [DMA_BAM_RESET
] = { 0x25c0, 7 },
3202 [SPS_TIC_H_RESET
] = { 0x2600, 7 },
3203 [SLIMBUS_H_RESET
] = { 0x2620, 7 },
3204 [SFAB_CFPB_M_RESET
] = { 0x2680, 7 },
3205 [SFAB_CFPB_S_RESET
] = { 0x26c0, 7 },
3206 [TSIF_H_RESET
] = { 0x2700, 7 },
3207 [CE1_H_RESET
] = { 0x2720, 7 },
3208 [CE1_CORE_RESET
] = { 0x2724, 7 },
3209 [CE1_SLEEP_RESET
] = { 0x2728, 7 },
3210 [CE2_H_RESET
] = { 0x2740, 7 },
3211 [CE2_CORE_RESET
] = { 0x2744, 7 },
3212 [SFAB_SFPB_M_RESET
] = { 0x2780, 7 },
3213 [SFAB_SFPB_S_RESET
] = { 0x27a0, 7 },
3214 [RPM_PROC_RESET
] = { 0x27c0, 7 },
3215 [PMIC_SSBI2_RESET
] = { 0x280c, 12 },
3216 [SDC1_RESET
] = { 0x2830 },
3217 [SDC2_RESET
] = { 0x2850 },
3218 [SDC3_RESET
] = { 0x2870 },
3219 [SDC4_RESET
] = { 0x2890 },
3220 [SDC5_RESET
] = { 0x28b0 },
3221 [DFAB_A2_RESET
] = { 0x28c0, 7 },
3222 [USB_HS1_RESET
] = { 0x2910 },
3223 [USB_HSIC_RESET
] = { 0x2934 },
3224 [USB_FS1_XCVR_RESET
] = { 0x2974, 1 },
3225 [USB_FS1_RESET
] = { 0x2974 },
3226 [USB_FS2_XCVR_RESET
] = { 0x2994, 1 },
3227 [USB_FS2_RESET
] = { 0x2994 },
3228 [GSBI1_RESET
] = { 0x29dc },
3229 [GSBI2_RESET
] = { 0x29fc },
3230 [GSBI3_RESET
] = { 0x2a1c },
3231 [GSBI4_RESET
] = { 0x2a3c },
3232 [GSBI5_RESET
] = { 0x2a5c },
3233 [GSBI6_RESET
] = { 0x2a7c },
3234 [GSBI7_RESET
] = { 0x2a9c },
3235 [GSBI8_RESET
] = { 0x2abc },
3236 [GSBI9_RESET
] = { 0x2adc },
3237 [GSBI10_RESET
] = { 0x2afc },
3238 [GSBI11_RESET
] = { 0x2b1c },
3239 [GSBI12_RESET
] = { 0x2b3c },
3240 [SPDM_RESET
] = { 0x2b6c },
3241 [TLMM_H_RESET
] = { 0x2ba0, 7 },
3242 [SFAB_MSS_S_RESET
] = { 0x2c00, 7 },
3243 [MSS_SLP_RESET
] = { 0x2c60, 7 },
3244 [MSS_Q6SW_JTAG_RESET
] = { 0x2c68, 7 },
3245 [MSS_Q6FW_JTAG_RESET
] = { 0x2c6c, 7 },
3246 [MSS_RESET
] = { 0x2c64 },
3247 [SATA_H_RESET
] = { 0x2c80, 7 },
3248 [SATA_RXOOB_RESE
] = { 0x2c8c, 7 },
3249 [SATA_PMALIVE_RESET
] = { 0x2c90, 7 },
3250 [SATA_SFAB_M_RESET
] = { 0x2c98, 7 },
3251 [TSSC_RESET
] = { 0x2ca0, 7 },
3252 [PDM_RESET
] = { 0x2cc0, 12 },
3253 [MPM_H_RESET
] = { 0x2da0, 7 },
3254 [MPM_RESET
] = { 0x2da4 },
3255 [SFAB_SMPSS_S_RESET
] = { 0x2e00, 7 },
3256 [PRNG_RESET
] = { 0x2e80, 12 },
3257 [RIVA_RESET
] = { 0x35e0 },
3260 static struct clk_regmap
*gcc_apq8064_clks
[] = {
3261 [PLL3
] = &pll3
.clkr
,
3262 [PLL4_VOTE
] = &pll4_vote
,
3263 [PLL8
] = &pll8
.clkr
,
3264 [PLL8_VOTE
] = &pll8_vote
,
3265 [PLL14
] = &pll14
.clkr
,
3266 [PLL14_VOTE
] = &pll14_vote
,
3267 [GSBI1_UART_SRC
] = &gsbi1_uart_src
.clkr
,
3268 [GSBI1_UART_CLK
] = &gsbi1_uart_clk
.clkr
,
3269 [GSBI2_UART_SRC
] = &gsbi2_uart_src
.clkr
,
3270 [GSBI2_UART_CLK
] = &gsbi2_uart_clk
.clkr
,
3271 [GSBI3_UART_SRC
] = &gsbi3_uart_src
.clkr
,
3272 [GSBI3_UART_CLK
] = &gsbi3_uart_clk
.clkr
,
3273 [GSBI4_UART_SRC
] = &gsbi4_uart_src
.clkr
,
3274 [GSBI4_UART_CLK
] = &gsbi4_uart_clk
.clkr
,
3275 [GSBI5_UART_SRC
] = &gsbi5_uart_src
.clkr
,
3276 [GSBI5_UART_CLK
] = &gsbi5_uart_clk
.clkr
,
3277 [GSBI6_UART_SRC
] = &gsbi6_uart_src
.clkr
,
3278 [GSBI6_UART_CLK
] = &gsbi6_uart_clk
.clkr
,
3279 [GSBI7_UART_SRC
] = &gsbi7_uart_src
.clkr
,
3280 [GSBI7_UART_CLK
] = &gsbi7_uart_clk
.clkr
,
3281 [GSBI1_QUP_SRC
] = &gsbi1_qup_src
.clkr
,
3282 [GSBI1_QUP_CLK
] = &gsbi1_qup_clk
.clkr
,
3283 [GSBI2_QUP_SRC
] = &gsbi2_qup_src
.clkr
,
3284 [GSBI2_QUP_CLK
] = &gsbi2_qup_clk
.clkr
,
3285 [GSBI3_QUP_SRC
] = &gsbi3_qup_src
.clkr
,
3286 [GSBI3_QUP_CLK
] = &gsbi3_qup_clk
.clkr
,
3287 [GSBI4_QUP_SRC
] = &gsbi4_qup_src
.clkr
,
3288 [GSBI4_QUP_CLK
] = &gsbi4_qup_clk
.clkr
,
3289 [GSBI5_QUP_SRC
] = &gsbi5_qup_src
.clkr
,
3290 [GSBI5_QUP_CLK
] = &gsbi5_qup_clk
.clkr
,
3291 [GSBI6_QUP_SRC
] = &gsbi6_qup_src
.clkr
,
3292 [GSBI6_QUP_CLK
] = &gsbi6_qup_clk
.clkr
,
3293 [GSBI7_QUP_SRC
] = &gsbi7_qup_src
.clkr
,
3294 [GSBI7_QUP_CLK
] = &gsbi7_qup_clk
.clkr
,
3295 [GP0_SRC
] = &gp0_src
.clkr
,
3296 [GP0_CLK
] = &gp0_clk
.clkr
,
3297 [GP1_SRC
] = &gp1_src
.clkr
,
3298 [GP1_CLK
] = &gp1_clk
.clkr
,
3299 [GP2_SRC
] = &gp2_src
.clkr
,
3300 [GP2_CLK
] = &gp2_clk
.clkr
,
3301 [PMEM_A_CLK
] = &pmem_clk
.clkr
,
3302 [PRNG_SRC
] = &prng_src
.clkr
,
3303 [PRNG_CLK
] = &prng_clk
.clkr
,
3304 [SDC1_SRC
] = &sdc1_src
.clkr
,
3305 [SDC1_CLK
] = &sdc1_clk
.clkr
,
3306 [SDC2_SRC
] = &sdc2_src
.clkr
,
3307 [SDC2_CLK
] = &sdc2_clk
.clkr
,
3308 [SDC3_SRC
] = &sdc3_src
.clkr
,
3309 [SDC3_CLK
] = &sdc3_clk
.clkr
,
3310 [SDC4_SRC
] = &sdc4_src
.clkr
,
3311 [SDC4_CLK
] = &sdc4_clk
.clkr
,
3312 [TSIF_REF_SRC
] = &tsif_ref_src
.clkr
,
3313 [TSIF_REF_CLK
] = &tsif_ref_clk
.clkr
,
3314 [USB_HS1_XCVR_SRC
] = &usb_hs1_xcvr_src
.clkr
,
3315 [USB_HS1_XCVR_CLK
] = &usb_hs1_xcvr_clk
.clkr
,
3316 [USB_HS3_XCVR_SRC
] = &usb_hs3_xcvr_src
.clkr
,
3317 [USB_HS3_XCVR_CLK
] = &usb_hs3_xcvr_clk
.clkr
,
3318 [USB_HS4_XCVR_SRC
] = &usb_hs4_xcvr_src
.clkr
,
3319 [USB_HS4_XCVR_CLK
] = &usb_hs4_xcvr_clk
.clkr
,
3320 [USB_HSIC_XCVR_FS_SRC
] = &usb_hsic_xcvr_fs_src
.clkr
,
3321 [USB_HSIC_XCVR_FS_CLK
] = &usb_hsic_xcvr_fs_clk
.clkr
,
3322 [USB_HSIC_SYSTEM_CLK
] = &usb_hsic_system_clk
.clkr
,
3323 [USB_HSIC_HSIC_CLK
] = &usb_hsic_hsic_clk
.clkr
,
3324 [USB_HSIC_HSIO_CAL_CLK
] = &usb_hsic_hsio_cal_clk
.clkr
,
3325 [USB_FS1_XCVR_FS_SRC
] = &usb_fs1_xcvr_fs_src
.clkr
,
3326 [USB_FS1_XCVR_FS_CLK
] = &usb_fs1_xcvr_fs_clk
.clkr
,
3327 [USB_FS1_SYSTEM_CLK
] = &usb_fs1_system_clk
.clkr
,
3328 [SATA_H_CLK
] = &sata_h_clk
.clkr
,
3329 [SATA_CLK_SRC
] = &sata_clk_src
.clkr
,
3330 [SATA_RXOOB_CLK
] = &sata_rxoob_clk
.clkr
,
3331 [SATA_PMALIVE_CLK
] = &sata_pmalive_clk
.clkr
,
3332 [SATA_PHY_REF_CLK
] = &sata_phy_ref_clk
.clkr
,
3333 [SATA_PHY_CFG_CLK
] = &sata_phy_cfg_clk
.clkr
,
3334 [SATA_A_CLK
] = &sata_a_clk
.clkr
,
3335 [SFAB_SATA_S_H_CLK
] = &sfab_sata_s_h_clk
.clkr
,
3336 [CE3_SRC
] = &ce3_src
.clkr
,
3337 [CE3_CORE_CLK
] = &ce3_core_clk
.clkr
,
3338 [CE3_H_CLK
] = &ce3_h_clk
.clkr
,
3339 [DMA_BAM_H_CLK
] = &dma_bam_h_clk
.clkr
,
3340 [GSBI1_H_CLK
] = &gsbi1_h_clk
.clkr
,
3341 [GSBI2_H_CLK
] = &gsbi2_h_clk
.clkr
,
3342 [GSBI3_H_CLK
] = &gsbi3_h_clk
.clkr
,
3343 [GSBI4_H_CLK
] = &gsbi4_h_clk
.clkr
,
3344 [GSBI5_H_CLK
] = &gsbi5_h_clk
.clkr
,
3345 [GSBI6_H_CLK
] = &gsbi6_h_clk
.clkr
,
3346 [GSBI7_H_CLK
] = &gsbi7_h_clk
.clkr
,
3347 [TSIF_H_CLK
] = &tsif_h_clk
.clkr
,
3348 [USB_FS1_H_CLK
] = &usb_fs1_h_clk
.clkr
,
3349 [USB_HS1_H_CLK
] = &usb_hs1_h_clk
.clkr
,
3350 [USB_HSIC_H_CLK
] = &usb_hsic_h_clk
.clkr
,
3351 [USB_HS3_H_CLK
] = &usb_hs3_h_clk
.clkr
,
3352 [USB_HS4_H_CLK
] = &usb_hs4_h_clk
.clkr
,
3353 [SDC1_H_CLK
] = &sdc1_h_clk
.clkr
,
3354 [SDC2_H_CLK
] = &sdc2_h_clk
.clkr
,
3355 [SDC3_H_CLK
] = &sdc3_h_clk
.clkr
,
3356 [SDC4_H_CLK
] = &sdc4_h_clk
.clkr
,
3357 [ADM0_CLK
] = &adm0_clk
.clkr
,
3358 [ADM0_PBUS_CLK
] = &adm0_pbus_clk
.clkr
,
3359 [PCIE_A_CLK
] = &pcie_a_clk
.clkr
,
3360 [PCIE_PHY_REF_CLK
] = &pcie_phy_ref_clk
.clkr
,
3361 [PCIE_H_CLK
] = &pcie_h_clk
.clkr
,
3362 [PMIC_ARB0_H_CLK
] = &pmic_arb0_h_clk
.clkr
,
3363 [PMIC_ARB1_H_CLK
] = &pmic_arb1_h_clk
.clkr
,
3364 [PMIC_SSBI2_CLK
] = &pmic_ssbi2_clk
.clkr
,
3365 [RPM_MSG_RAM_H_CLK
] = &rpm_msg_ram_h_clk
.clkr
,
3368 static const struct qcom_reset_map gcc_apq8064_resets
[] = {
3369 [QDSS_STM_RESET
] = { 0x2060, 6 },
3370 [AFAB_SMPSS_S_RESET
] = { 0x20b8, 2 },
3371 [AFAB_SMPSS_M1_RESET
] = { 0x20b8, 1 },
3372 [AFAB_SMPSS_M0_RESET
] = { 0x20b8 },
3373 [AFAB_EBI1_CH0_RESET
] = { 0x20c0, 7 },
3374 [AFAB_EBI1_CH1_RESET
] = { 0x20c4, 7},
3375 [SFAB_ADM0_M0_RESET
] = { 0x21e0, 7 },
3376 [SFAB_ADM0_M1_RESET
] = { 0x21e4, 7 },
3377 [SFAB_ADM0_M2_RESET
] = { 0x21e8, 7 },
3378 [ADM0_C2_RESET
] = { 0x220c, 4},
3379 [ADM0_C1_RESET
] = { 0x220c, 3},
3380 [ADM0_C0_RESET
] = { 0x220c, 2},
3381 [ADM0_PBUS_RESET
] = { 0x220c, 1 },
3382 [ADM0_RESET
] = { 0x220c },
3383 [QDSS_CLKS_SW_RESET
] = { 0x2260, 5 },
3384 [QDSS_POR_RESET
] = { 0x2260, 4 },
3385 [QDSS_TSCTR_RESET
] = { 0x2260, 3 },
3386 [QDSS_HRESET_RESET
] = { 0x2260, 2 },
3387 [QDSS_AXI_RESET
] = { 0x2260, 1 },
3388 [QDSS_DBG_RESET
] = { 0x2260 },
3389 [SFAB_PCIE_M_RESET
] = { 0x22d8, 1 },
3390 [SFAB_PCIE_S_RESET
] = { 0x22d8 },
3391 [PCIE_EXT_PCI_RESET
] = { 0x22dc, 6 },
3392 [PCIE_PHY_RESET
] = { 0x22dc, 5 },
3393 [PCIE_PCI_RESET
] = { 0x22dc, 4 },
3394 [PCIE_POR_RESET
] = { 0x22dc, 3 },
3395 [PCIE_HCLK_RESET
] = { 0x22dc, 2 },
3396 [PCIE_ACLK_RESET
] = { 0x22dc },
3397 [SFAB_USB3_M_RESET
] = { 0x2360, 7 },
3398 [SFAB_RIVA_M_RESET
] = { 0x2380, 7 },
3399 [SFAB_LPASS_RESET
] = { 0x23a0, 7 },
3400 [SFAB_AFAB_M_RESET
] = { 0x23e0, 7 },
3401 [AFAB_SFAB_M0_RESET
] = { 0x2420, 7 },
3402 [AFAB_SFAB_M1_RESET
] = { 0x2424, 7 },
3403 [SFAB_SATA_S_RESET
] = { 0x2480, 7 },
3404 [SFAB_DFAB_M_RESET
] = { 0x2500, 7 },
3405 [DFAB_SFAB_M_RESET
] = { 0x2520, 7 },
3406 [DFAB_SWAY0_RESET
] = { 0x2540, 7 },
3407 [DFAB_SWAY1_RESET
] = { 0x2544, 7 },
3408 [DFAB_ARB0_RESET
] = { 0x2560, 7 },
3409 [DFAB_ARB1_RESET
] = { 0x2564, 7 },
3410 [PPSS_PROC_RESET
] = { 0x2594, 1 },
3411 [PPSS_RESET
] = { 0x2594},
3412 [DMA_BAM_RESET
] = { 0x25c0, 7 },
3413 [SPS_TIC_H_RESET
] = { 0x2600, 7 },
3414 [SFAB_CFPB_M_RESET
] = { 0x2680, 7 },
3415 [SFAB_CFPB_S_RESET
] = { 0x26c0, 7 },
3416 [TSIF_H_RESET
] = { 0x2700, 7 },
3417 [CE1_H_RESET
] = { 0x2720, 7 },
3418 [CE1_CORE_RESET
] = { 0x2724, 7 },
3419 [CE1_SLEEP_RESET
] = { 0x2728, 7 },
3420 [CE2_H_RESET
] = { 0x2740, 7 },
3421 [CE2_CORE_RESET
] = { 0x2744, 7 },
3422 [SFAB_SFPB_M_RESET
] = { 0x2780, 7 },
3423 [SFAB_SFPB_S_RESET
] = { 0x27a0, 7 },
3424 [RPM_PROC_RESET
] = { 0x27c0, 7 },
3425 [PMIC_SSBI2_RESET
] = { 0x280c, 12 },
3426 [SDC1_RESET
] = { 0x2830 },
3427 [SDC2_RESET
] = { 0x2850 },
3428 [SDC3_RESET
] = { 0x2870 },
3429 [SDC4_RESET
] = { 0x2890 },
3430 [USB_HS1_RESET
] = { 0x2910 },
3431 [USB_HSIC_RESET
] = { 0x2934 },
3432 [USB_FS1_XCVR_RESET
] = { 0x2974, 1 },
3433 [USB_FS1_RESET
] = { 0x2974 },
3434 [GSBI1_RESET
] = { 0x29dc },
3435 [GSBI2_RESET
] = { 0x29fc },
3436 [GSBI3_RESET
] = { 0x2a1c },
3437 [GSBI4_RESET
] = { 0x2a3c },
3438 [GSBI5_RESET
] = { 0x2a5c },
3439 [GSBI6_RESET
] = { 0x2a7c },
3440 [GSBI7_RESET
] = { 0x2a9c },
3441 [SPDM_RESET
] = { 0x2b6c },
3442 [TLMM_H_RESET
] = { 0x2ba0, 7 },
3443 [SATA_SFAB_M_RESET
] = { 0x2c18 },
3444 [SATA_RESET
] = { 0x2c1c },
3445 [GSS_SLP_RESET
] = { 0x2c60, 7 },
3446 [GSS_RESET
] = { 0x2c64 },
3447 [TSSC_RESET
] = { 0x2ca0, 7 },
3448 [PDM_RESET
] = { 0x2cc0, 12 },
3449 [MPM_H_RESET
] = { 0x2da0, 7 },
3450 [MPM_RESET
] = { 0x2da4 },
3451 [SFAB_SMPSS_S_RESET
] = { 0x2e00, 7 },
3452 [PRNG_RESET
] = { 0x2e80, 12 },
3453 [RIVA_RESET
] = { 0x35e0 },
3454 [CE3_H_RESET
] = { 0x36c4, 7 },
3455 [SFAB_CE3_M_RESET
] = { 0x36c8, 1 },
3456 [SFAB_CE3_S_RESET
] = { 0x36c8 },
3457 [CE3_RESET
] = { 0x36cc, 7 },
3458 [CE3_SLEEP_RESET
] = { 0x36d0, 7 },
3459 [USB_HS3_RESET
] = { 0x3710 },
3460 [USB_HS4_RESET
] = { 0x3730 },
3463 static const struct regmap_config gcc_msm8960_regmap_config
= {
3467 .max_register
= 0x3660,
3471 static const struct regmap_config gcc_apq8064_regmap_config
= {
3475 .max_register
= 0x3880,
3479 static const struct qcom_cc_desc gcc_msm8960_desc
= {
3480 .config
= &gcc_msm8960_regmap_config
,
3481 .clks
= gcc_msm8960_clks
,
3482 .num_clks
= ARRAY_SIZE(gcc_msm8960_clks
),
3483 .resets
= gcc_msm8960_resets
,
3484 .num_resets
= ARRAY_SIZE(gcc_msm8960_resets
),
3487 static const struct qcom_cc_desc gcc_apq8064_desc
= {
3488 .config
= &gcc_apq8064_regmap_config
,
3489 .clks
= gcc_apq8064_clks
,
3490 .num_clks
= ARRAY_SIZE(gcc_apq8064_clks
),
3491 .resets
= gcc_apq8064_resets
,
3492 .num_resets
= ARRAY_SIZE(gcc_apq8064_resets
),
3495 static const struct of_device_id gcc_msm8960_match_table
[] = {
3496 { .compatible
= "qcom,gcc-msm8960", .data
= &gcc_msm8960_desc
},
3497 { .compatible
= "qcom,gcc-apq8064", .data
= &gcc_apq8064_desc
},
3500 MODULE_DEVICE_TABLE(of
, gcc_msm8960_match_table
);
3502 static int gcc_msm8960_probe(struct platform_device
*pdev
)
3505 struct device
*dev
= &pdev
->dev
;
3506 const struct of_device_id
*match
;
3508 match
= of_match_device(gcc_msm8960_match_table
, &pdev
->dev
);
3512 /* Temporary until RPM clocks supported */
3513 clk
= clk_register_fixed_rate(dev
, "cxo", NULL
, CLK_IS_ROOT
, 19200000);
3515 return PTR_ERR(clk
);
3517 clk
= clk_register_fixed_rate(dev
, "pxo", NULL
, CLK_IS_ROOT
, 27000000);
3519 return PTR_ERR(clk
);
3521 return qcom_cc_probe(pdev
, match
->data
);
3524 static int gcc_msm8960_remove(struct platform_device
*pdev
)
3526 qcom_cc_remove(pdev
);
3530 static struct platform_driver gcc_msm8960_driver
= {
3531 .probe
= gcc_msm8960_probe
,
3532 .remove
= gcc_msm8960_remove
,
3534 .name
= "gcc-msm8960",
3535 .of_match_table
= gcc_msm8960_match_table
,
3539 static int __init
gcc_msm8960_init(void)
3541 return platform_driver_register(&gcc_msm8960_driver
);
3543 core_initcall(gcc_msm8960_init
);
3545 static void __exit
gcc_msm8960_exit(void)
3547 platform_driver_unregister(&gcc_msm8960_driver
);
3549 module_exit(gcc_msm8960_exit
);
3551 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3552 MODULE_LICENSE("GPL v2");
3553 MODULE_ALIAS("platform:gcc-msm8960");