drivers/clk/qcom/gdsc.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/kernel.h>
  19 #include <linux/pm_domain.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include "gdsc.h"
  23
  24 #define PWR_ON_MASK             BIT(31)
  25 #define EN_REST_WAIT_MASK       GENMASK_ULL(23, 20)
  26 #define EN_FEW_WAIT_MASK        GENMASK_ULL(19, 16)
  27 #define CLK_DIS_WAIT_MASK       GENMASK_ULL(15, 12)
  28 #define SW_OVERRIDE_MASK        BIT(2)
  29 #define HW_CONTROL_MASK         BIT(1)
  30 #define SW_COLLAPSE_MASK        BIT(0)
  31
  32 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
  33 #define EN_REST_WAIT_VAL        (0x2 << 20)
  34 #define EN_FEW_WAIT_VAL         (0x8 << 16)
  35 #define CLK_DIS_WAIT_VAL        (0x2 << 12)
  36
  37 #define TIMEOUT_US              100
  38
  39 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  40
  41 static int gdsc_is_enabled(struct gdsc *sc)
  42 {
  43         u32 val;
  44         int ret;
  45
  46         ret = regmap_read(sc->regmap, sc->gdscr, &val);
  47         if (ret)
  48                 return ret;
  49
  50         return !!(val & PWR_ON_MASK);
  51 }
  52
  53 static int gdsc_toggle_logic(struct gdsc *sc, bool en)
  54 {
  55         int ret;
  56         u32 val = en ? 0 : SW_COLLAPSE_MASK;
  57         u32 check = en ? PWR_ON_MASK : 0;
  58         unsigned long timeout;
  59
  60         ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
  61         if (ret)
  62                 return ret;
  63
  64         timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
  65         do {
  66                 ret = regmap_read(sc->regmap, sc->gdscr, &val);
  67                 if (ret)
  68                         return ret;
  69
  70                 if ((val & PWR_ON_MASK) == check)
  71                         return 0;
  72         } while (time_before(jiffies, timeout));
  73
  74         ret = regmap_read(sc->regmap, sc->gdscr, &val);
  75         if (ret)
  76                 return ret;
  77
  78         if ((val & PWR_ON_MASK) == check)
  79                 return 0;
  80
  81         return -ETIMEDOUT;
  82 }
  83
  84 static int gdsc_enable(struct generic_pm_domain *domain)
  85 {
  86         struct gdsc *sc = domain_to_gdsc(domain);
  87         int ret;
  88
  89         ret = gdsc_toggle_logic(sc, true);
  90         if (ret)
  91                 return ret;
  92         /*
  93          * If clocks to this power domain were already on, they will take an
  94          * additional 4 clock cycles to re-enable after the power domain is
  95          * enabled. Delay to account for this. A delay is also needed to ensure
  96          * clocks are not enabled within 400ns of enabling power to the
  97          * memories.
  98          */
  99         udelay(1);
 100
 101         return 0;
 102 }
 103
 104 static int gdsc_disable(struct generic_pm_domain *domain)
 105 {
 106         struct gdsc *sc = domain_to_gdsc(domain);
 107
 108         return gdsc_toggle_logic(sc, false);
 109 }
 110
 111 static int gdsc_init(struct gdsc *sc)
 112 {
 113         u32 mask, val;
 114         int on, ret;
 115
 116         /*
 117          * Disable HW trigger: collapse/restore occur based on registers writes.
 118          * Disable SW override: Use hardware state-machine for sequencing.
 119          * Configure wait time between states.
 120          */
 121         mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
 122                EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
 123         val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
 124         ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
 125         if (ret)
 126                 return ret;
 127
 128         on = gdsc_is_enabled(sc);
 129         if (on < 0)
 130                 return on;
 131
 132         sc->pd.power_off = gdsc_disable;
 133         sc->pd.power_on = gdsc_enable;
 134         pm_genpd_init(&sc->pd, NULL, !on);
 135
 136         return 0;
 137 }
 138
 139 int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
 140                   struct regmap *regmap)
 141 {
 142         int i, ret;
 143         struct genpd_onecell_data *data;
 144
 145         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 146         if (!data)
 147                 return -ENOMEM;
 148
 149         data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
 150                                      GFP_KERNEL);
 151         if (!data->domains)
 152                 return -ENOMEM;
 153
 154         data->num_domains = num;
 155         for (i = 0; i < num; i++) {
 156                 if (!scs[i])
 157                         continue;
 158                 scs[i]->regmap = regmap;
 159                 ret = gdsc_init(scs[i]);
 160                 if (ret)
 161                         return ret;
 162                 data->domains[i] = &scs[i]->pd;
 163         }
 164
 165         return of_genpd_add_provider_onecell(dev->of_node, data);
 166 }
 167
 168 void gdsc_unregister(struct device *dev)
 169 {
 170         of_genpd_del_provider(dev->of_node);
 171 }