2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
24 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
27 #include "clk-regmap.h"
30 #include "clk-branch.h"
31 #include "clk-regmap-divider.h"
32 #include "clk-regmap-mux.h"
34 static struct clk_pll pll4
= {
42 .clkr
.hw
.init
= &(struct clk_init_data
){
44 .parent_names
= (const char *[]){ "pxo" },
53 static const u8 lcc_pxo_pll4_map
[] = {
58 static const char *lcc_pxo_pll4
[] = {
63 static struct freq_tbl clk_tbl_aif_osr_492
[] = {
64 { 512000, P_PLL4
, 4, 1, 240 },
65 { 768000, P_PLL4
, 4, 1, 160 },
66 { 1024000, P_PLL4
, 4, 1, 120 },
67 { 1536000, P_PLL4
, 4, 1, 80 },
68 { 2048000, P_PLL4
, 4, 1, 60 },
69 { 3072000, P_PLL4
, 4, 1, 40 },
70 { 4096000, P_PLL4
, 4, 1, 30 },
71 { 6144000, P_PLL4
, 4, 1, 20 },
72 { 8192000, P_PLL4
, 4, 1, 15 },
73 { 12288000, P_PLL4
, 4, 1, 10 },
74 { 24576000, P_PLL4
, 4, 1, 5 },
75 { 27000000, P_PXO
, 1, 0, 0 },
79 static struct freq_tbl clk_tbl_aif_osr_393
[] = {
80 { 512000, P_PLL4
, 4, 1, 192 },
81 { 768000, P_PLL4
, 4, 1, 128 },
82 { 1024000, P_PLL4
, 4, 1, 96 },
83 { 1536000, P_PLL4
, 4, 1, 64 },
84 { 2048000, P_PLL4
, 4, 1, 48 },
85 { 3072000, P_PLL4
, 4, 1, 32 },
86 { 4096000, P_PLL4
, 4, 1, 24 },
87 { 6144000, P_PLL4
, 4, 1, 16 },
88 { 8192000, P_PLL4
, 4, 1, 12 },
89 { 12288000, P_PLL4
, 4, 1, 8 },
90 { 24576000, P_PLL4
, 4, 1, 4 },
91 { 27000000, P_PXO
, 1, 0, 0 },
95 static struct clk_rcg mi2s_osr_src
= {
100 .mnctr_reset_bit
= 7,
101 .mnctr_mode_shift
= 5,
112 .parent_map
= lcc_pxo_pll4_map
,
114 .freq_tbl
= clk_tbl_aif_osr_393
,
117 .enable_mask
= BIT(9),
118 .hw
.init
= &(struct clk_init_data
){
119 .name
= "mi2s_osr_src",
120 .parent_names
= lcc_pxo_pll4
,
123 .flags
= CLK_SET_RATE_GATE
,
128 static const char *lcc_mi2s_parents
[] = {
132 static struct clk_branch mi2s_osr_clk
= {
135 .halt_check
= BRANCH_HALT_ENABLE
,
138 .enable_mask
= BIT(17),
139 .hw
.init
= &(struct clk_init_data
){
140 .name
= "mi2s_osr_clk",
141 .parent_names
= lcc_mi2s_parents
,
143 .ops
= &clk_branch_ops
,
144 .flags
= CLK_SET_RATE_PARENT
,
149 static struct clk_regmap_div mi2s_div_clk
= {
155 .enable_mask
= BIT(15),
156 .hw
.init
= &(struct clk_init_data
){
157 .name
= "mi2s_div_clk",
158 .parent_names
= lcc_mi2s_parents
,
160 .ops
= &clk_regmap_div_ops
,
165 static struct clk_branch mi2s_bit_div_clk
= {
168 .halt_check
= BRANCH_HALT_ENABLE
,
171 .enable_mask
= BIT(15),
172 .hw
.init
= &(struct clk_init_data
){
173 .name
= "mi2s_bit_div_clk",
174 .parent_names
= (const char *[]){ "mi2s_div_clk" },
176 .ops
= &clk_branch_ops
,
177 .flags
= CLK_SET_RATE_PARENT
,
182 static struct clk_regmap_mux mi2s_bit_clk
= {
187 .hw
.init
= &(struct clk_init_data
){
188 .name
= "mi2s_bit_clk",
189 .parent_names
= (const char *[]){
194 .ops
= &clk_regmap_mux_closest_ops
,
195 .flags
= CLK_SET_RATE_PARENT
,
200 #define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
201 static struct clk_rcg prefix##_osr_src = { \
206 .mnctr_reset_bit = 7, \
207 .mnctr_mode_shift = 5, \
213 .pre_div_shift = 3, \
214 .pre_div_width = 2, \
217 .src_sel_shift = 0, \
218 .parent_map = lcc_pxo_pll4_map, \
220 .freq_tbl = clk_tbl_aif_osr_393, \
223 .enable_mask = BIT(9), \
224 .hw.init = &(struct clk_init_data){ \
225 .name = #prefix "_osr_src", \
226 .parent_names = lcc_pxo_pll4, \
228 .ops = &clk_rcg_ops, \
229 .flags = CLK_SET_RATE_GATE, \
234 static const char *lcc_##prefix##_parents[] = { \
235 #prefix "_osr_src", \
238 static struct clk_branch prefix##_osr_clk = { \
241 .halt_check = BRANCH_HALT_ENABLE, \
244 .enable_mask = BIT(21), \
245 .hw.init = &(struct clk_init_data){ \
246 .name = #prefix "_osr_clk", \
247 .parent_names = lcc_##prefix##_parents, \
249 .ops = &clk_branch_ops, \
250 .flags = CLK_SET_RATE_PARENT, \
255 static struct clk_regmap_div prefix##_div_clk = { \
260 .hw.init = &(struct clk_init_data){ \
261 .name = #prefix "_div_clk", \
262 .parent_names = lcc_##prefix##_parents, \
264 .ops = &clk_regmap_div_ops, \
269 static struct clk_branch prefix##_bit_div_clk = { \
272 .halt_check = BRANCH_HALT_ENABLE, \
275 .enable_mask = BIT(19), \
276 .hw.init = &(struct clk_init_data){ \
277 .name = #prefix "_bit_div_clk", \
278 .parent_names = (const char *[]){ \
282 .ops = &clk_branch_ops, \
283 .flags = CLK_SET_RATE_PARENT, \
288 static struct clk_regmap_mux prefix##_bit_clk = { \
293 .hw.init = &(struct clk_init_data){ \
294 .name = #prefix "_bit_clk", \
295 .parent_names = (const char *[]){ \
296 #prefix "_bit_div_clk", \
297 #prefix "_codec_clk", \
300 .ops = &clk_regmap_mux_closest_ops, \
301 .flags = CLK_SET_RATE_PARENT, \
306 CLK_AIF_OSR_DIV(codec_i2s_mic
, 0x60, 0x64, 0x68);
307 CLK_AIF_OSR_DIV(spare_i2s_mic
, 0x78, 0x7c, 0x80);
308 CLK_AIF_OSR_DIV(codec_i2s_spkr
, 0x6c, 0x70, 0x74);
309 CLK_AIF_OSR_DIV(spare_i2s_spkr
, 0x84, 0x88, 0x8c);
311 static struct freq_tbl clk_tbl_pcm_492
[] = {
312 { 256000, P_PLL4
, 4, 1, 480 },
313 { 512000, P_PLL4
, 4, 1, 240 },
314 { 768000, P_PLL4
, 4, 1, 160 },
315 { 1024000, P_PLL4
, 4, 1, 120 },
316 { 1536000, P_PLL4
, 4, 1, 80 },
317 { 2048000, P_PLL4
, 4, 1, 60 },
318 { 3072000, P_PLL4
, 4, 1, 40 },
319 { 4096000, P_PLL4
, 4, 1, 30 },
320 { 6144000, P_PLL4
, 4, 1, 20 },
321 { 8192000, P_PLL4
, 4, 1, 15 },
322 { 12288000, P_PLL4
, 4, 1, 10 },
323 { 24576000, P_PLL4
, 4, 1, 5 },
324 { 27000000, P_PXO
, 1, 0, 0 },
328 static struct freq_tbl clk_tbl_pcm_393
[] = {
329 { 256000, P_PLL4
, 4, 1, 384 },
330 { 512000, P_PLL4
, 4, 1, 192 },
331 { 768000, P_PLL4
, 4, 1, 128 },
332 { 1024000, P_PLL4
, 4, 1, 96 },
333 { 1536000, P_PLL4
, 4, 1, 64 },
334 { 2048000, P_PLL4
, 4, 1, 48 },
335 { 3072000, P_PLL4
, 4, 1, 32 },
336 { 4096000, P_PLL4
, 4, 1, 24 },
337 { 6144000, P_PLL4
, 4, 1, 16 },
338 { 8192000, P_PLL4
, 4, 1, 12 },
339 { 12288000, P_PLL4
, 4, 1, 8 },
340 { 24576000, P_PLL4
, 4, 1, 4 },
341 { 27000000, P_PXO
, 1, 0, 0 },
345 static struct clk_rcg pcm_src
= {
350 .mnctr_reset_bit
= 7,
351 .mnctr_mode_shift
= 5,
362 .parent_map
= lcc_pxo_pll4_map
,
364 .freq_tbl
= clk_tbl_pcm_393
,
367 .enable_mask
= BIT(9),
368 .hw
.init
= &(struct clk_init_data
){
370 .parent_names
= lcc_pxo_pll4
,
373 .flags
= CLK_SET_RATE_GATE
,
378 static struct clk_branch pcm_clk_out
= {
381 .halt_check
= BRANCH_HALT_ENABLE
,
384 .enable_mask
= BIT(11),
385 .hw
.init
= &(struct clk_init_data
){
386 .name
= "pcm_clk_out",
387 .parent_names
= (const char *[]){ "pcm_src" },
389 .ops
= &clk_branch_ops
,
390 .flags
= CLK_SET_RATE_PARENT
,
395 static struct clk_regmap_mux pcm_clk
= {
400 .hw
.init
= &(struct clk_init_data
){
402 .parent_names
= (const char *[]){
407 .ops
= &clk_regmap_mux_closest_ops
,
408 .flags
= CLK_SET_RATE_PARENT
,
413 static struct clk_rcg slimbus_src
= {
418 .mnctr_reset_bit
= 7,
419 .mnctr_mode_shift
= 5,
430 .parent_map
= lcc_pxo_pll4_map
,
432 .freq_tbl
= clk_tbl_aif_osr_393
,
435 .enable_mask
= BIT(9),
436 .hw
.init
= &(struct clk_init_data
){
437 .name
= "slimbus_src",
438 .parent_names
= lcc_pxo_pll4
,
441 .flags
= CLK_SET_RATE_GATE
,
446 static const char *lcc_slimbus_parents
[] = {
450 static struct clk_branch audio_slimbus_clk
= {
453 .halt_check
= BRANCH_HALT_ENABLE
,
456 .enable_mask
= BIT(10),
457 .hw
.init
= &(struct clk_init_data
){
458 .name
= "audio_slimbus_clk",
459 .parent_names
= lcc_slimbus_parents
,
461 .ops
= &clk_branch_ops
,
462 .flags
= CLK_SET_RATE_PARENT
,
467 static struct clk_branch sps_slimbus_clk
= {
470 .halt_check
= BRANCH_HALT_ENABLE
,
473 .enable_mask
= BIT(12),
474 .hw
.init
= &(struct clk_init_data
){
475 .name
= "sps_slimbus_clk",
476 .parent_names
= lcc_slimbus_parents
,
478 .ops
= &clk_branch_ops
,
479 .flags
= CLK_SET_RATE_PARENT
,
484 static struct clk_regmap
*lcc_msm8960_clks
[] = {
486 [MI2S_OSR_SRC
] = &mi2s_osr_src
.clkr
,
487 [MI2S_OSR_CLK
] = &mi2s_osr_clk
.clkr
,
488 [MI2S_DIV_CLK
] = &mi2s_div_clk
.clkr
,
489 [MI2S_BIT_DIV_CLK
] = &mi2s_bit_div_clk
.clkr
,
490 [MI2S_BIT_CLK
] = &mi2s_bit_clk
.clkr
,
491 [PCM_SRC
] = &pcm_src
.clkr
,
492 [PCM_CLK_OUT
] = &pcm_clk_out
.clkr
,
493 [PCM_CLK
] = &pcm_clk
.clkr
,
494 [SLIMBUS_SRC
] = &slimbus_src
.clkr
,
495 [AUDIO_SLIMBUS_CLK
] = &audio_slimbus_clk
.clkr
,
496 [SPS_SLIMBUS_CLK
] = &sps_slimbus_clk
.clkr
,
497 [CODEC_I2S_MIC_OSR_SRC
] = &codec_i2s_mic_osr_src
.clkr
,
498 [CODEC_I2S_MIC_OSR_CLK
] = &codec_i2s_mic_osr_clk
.clkr
,
499 [CODEC_I2S_MIC_DIV_CLK
] = &codec_i2s_mic_div_clk
.clkr
,
500 [CODEC_I2S_MIC_BIT_DIV_CLK
] = &codec_i2s_mic_bit_div_clk
.clkr
,
501 [CODEC_I2S_MIC_BIT_CLK
] = &codec_i2s_mic_bit_clk
.clkr
,
502 [SPARE_I2S_MIC_OSR_SRC
] = &spare_i2s_mic_osr_src
.clkr
,
503 [SPARE_I2S_MIC_OSR_CLK
] = &spare_i2s_mic_osr_clk
.clkr
,
504 [SPARE_I2S_MIC_DIV_CLK
] = &spare_i2s_mic_div_clk
.clkr
,
505 [SPARE_I2S_MIC_BIT_DIV_CLK
] = &spare_i2s_mic_bit_div_clk
.clkr
,
506 [SPARE_I2S_MIC_BIT_CLK
] = &spare_i2s_mic_bit_clk
.clkr
,
507 [CODEC_I2S_SPKR_OSR_SRC
] = &codec_i2s_spkr_osr_src
.clkr
,
508 [CODEC_I2S_SPKR_OSR_CLK
] = &codec_i2s_spkr_osr_clk
.clkr
,
509 [CODEC_I2S_SPKR_DIV_CLK
] = &codec_i2s_spkr_div_clk
.clkr
,
510 [CODEC_I2S_SPKR_BIT_DIV_CLK
] = &codec_i2s_spkr_bit_div_clk
.clkr
,
511 [CODEC_I2S_SPKR_BIT_CLK
] = &codec_i2s_spkr_bit_clk
.clkr
,
512 [SPARE_I2S_SPKR_OSR_SRC
] = &spare_i2s_spkr_osr_src
.clkr
,
513 [SPARE_I2S_SPKR_OSR_CLK
] = &spare_i2s_spkr_osr_clk
.clkr
,
514 [SPARE_I2S_SPKR_DIV_CLK
] = &spare_i2s_spkr_div_clk
.clkr
,
515 [SPARE_I2S_SPKR_BIT_DIV_CLK
] = &spare_i2s_spkr_bit_div_clk
.clkr
,
516 [SPARE_I2S_SPKR_BIT_CLK
] = &spare_i2s_spkr_bit_clk
.clkr
,
519 static const struct regmap_config lcc_msm8960_regmap_config
= {
523 .max_register
= 0xfc,
527 static const struct qcom_cc_desc lcc_msm8960_desc
= {
528 .config
= &lcc_msm8960_regmap_config
,
529 .clks
= lcc_msm8960_clks
,
530 .num_clks
= ARRAY_SIZE(lcc_msm8960_clks
),
533 static const struct of_device_id lcc_msm8960_match_table
[] = {
534 { .compatible
= "qcom,lcc-msm8960" },
535 { .compatible
= "qcom,lcc-apq8064" },
538 MODULE_DEVICE_TABLE(of
, lcc_msm8960_match_table
);
540 static int lcc_msm8960_probe(struct platform_device
*pdev
)
543 struct regmap
*regmap
;
545 regmap
= qcom_cc_map(pdev
, &lcc_msm8960_desc
);
547 return PTR_ERR(regmap
);
549 /* Use the correct frequency plan depending on speed of PLL4 */
550 val
= regmap_read(regmap
, 0x4, &val
);
552 slimbus_src
.freq_tbl
= clk_tbl_aif_osr_492
;
553 mi2s_osr_src
.freq_tbl
= clk_tbl_aif_osr_492
;
554 codec_i2s_mic_osr_src
.freq_tbl
= clk_tbl_aif_osr_492
;
555 spare_i2s_mic_osr_src
.freq_tbl
= clk_tbl_aif_osr_492
;
556 codec_i2s_spkr_osr_src
.freq_tbl
= clk_tbl_aif_osr_492
;
557 spare_i2s_spkr_osr_src
.freq_tbl
= clk_tbl_aif_osr_492
;
558 pcm_src
.freq_tbl
= clk_tbl_pcm_492
;
560 /* Enable PLL4 source on the LPASS Primary PLL Mux */
561 regmap_write(regmap
, 0xc4, 0x1);
563 return qcom_cc_really_probe(pdev
, &lcc_msm8960_desc
, regmap
);
566 static int lcc_msm8960_remove(struct platform_device
*pdev
)
568 qcom_cc_remove(pdev
);
572 static struct platform_driver lcc_msm8960_driver
= {
573 .probe
= lcc_msm8960_probe
,
574 .remove
= lcc_msm8960_remove
,
576 .name
= "lcc-msm8960",
577 .owner
= THIS_MODULE
,
578 .of_match_table
= lcc_msm8960_match_table
,
581 module_platform_driver(lcc_msm8960_driver
);
583 MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver");
584 MODULE_LICENSE("GPL v2");
585 MODULE_ALIAS("platform:lcc-msm8960");