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Merge branch 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[deliverable/linux.git] / drivers / clk / qcom / mmcc-msm8960.c
1 /*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/clk.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
25 #include <linux/reset-controller.h>
26
27 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
28 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
29
30 #include "common.h"
31 #include "clk-regmap.h"
32 #include "clk-pll.h"
33 #include "clk-rcg.h"
34 #include "clk-branch.h"
35 #include "reset.h"
36
37 enum {
38 P_PXO,
39 P_PLL8,
40 P_PLL2,
41 P_PLL3,
42 P_PLL15,
43 P_HDMI_PLL,
44 P_DSI1_PLL_DSICLK,
45 P_DSI2_PLL_DSICLK,
46 P_DSI1_PLL_BYTECLK,
47 P_DSI2_PLL_BYTECLK,
48 };
49
50 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
51
52 static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
53 { P_PXO, 0 },
54 { P_PLL8, 2 },
55 { P_PLL2, 1 }
56 };
57
58 static const char * const mmcc_pxo_pll8_pll2[] = {
59 "pxo",
60 "pll8_vote",
61 "pll2",
62 };
63
64 static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
65 { P_PXO, 0 },
66 { P_PLL8, 2 },
67 { P_PLL2, 1 },
68 { P_PLL3, 3 }
69 };
70
71 static const char * const mmcc_pxo_pll8_pll2_pll15[] = {
72 "pxo",
73 "pll8_vote",
74 "pll2",
75 "pll15",
76 };
77
78 static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
79 { P_PXO, 0 },
80 { P_PLL8, 2 },
81 { P_PLL2, 1 },
82 { P_PLL15, 3 }
83 };
84
85 static const char * const mmcc_pxo_pll8_pll2_pll3[] = {
86 "pxo",
87 "pll8_vote",
88 "pll2",
89 "pll3",
90 };
91
92 static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
93 { P_PXO, 0 },
94 { P_DSI2_PLL_DSICLK, 1 },
95 { P_DSI1_PLL_DSICLK, 3 },
96 };
97
98 static const char * const mmcc_pxo_dsi2_dsi1[] = {
99 "pxo",
100 "dsi2pll",
101 "dsi1pll",
102 };
103
104 static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
105 { P_PXO, 0 },
106 { P_DSI1_PLL_BYTECLK, 1 },
107 { P_DSI2_PLL_BYTECLK, 2 },
108 };
109
110 static const char * const mmcc_pxo_dsi1_dsi2_byte[] = {
111 "pxo",
112 "dsi1pllbyte",
113 "dsi2pllbyte",
114 };
115
116 static struct clk_pll pll2 = {
117 .l_reg = 0x320,
118 .m_reg = 0x324,
119 .n_reg = 0x328,
120 .config_reg = 0x32c,
121 .mode_reg = 0x31c,
122 .status_reg = 0x334,
123 .status_bit = 16,
124 .clkr.hw.init = &(struct clk_init_data){
125 .name = "pll2",
126 .parent_names = (const char *[]){ "pxo" },
127 .num_parents = 1,
128 .ops = &clk_pll_ops,
129 },
130 };
131
132 static struct clk_pll pll15 = {
133 .l_reg = 0x33c,
134 .m_reg = 0x340,
135 .n_reg = 0x344,
136 .config_reg = 0x348,
137 .mode_reg = 0x338,
138 .status_reg = 0x350,
139 .status_bit = 16,
140 .clkr.hw.init = &(struct clk_init_data){
141 .name = "pll15",
142 .parent_names = (const char *[]){ "pxo" },
143 .num_parents = 1,
144 .ops = &clk_pll_ops,
145 },
146 };
147
148 static const struct pll_config pll15_config = {
149 .l = 33,
150 .m = 1,
151 .n = 3,
152 .vco_val = 0x2 << 16,
153 .vco_mask = 0x3 << 16,
154 .pre_div_val = 0x0,
155 .pre_div_mask = BIT(19),
156 .post_div_val = 0x0,
157 .post_div_mask = 0x3 << 20,
158 .mn_ena_mask = BIT(22),
159 .main_output_mask = BIT(23),
160 };
161
162 static struct freq_tbl clk_tbl_cam[] = {
163 { 6000000, P_PLL8, 4, 1, 16 },
164 { 8000000, P_PLL8, 4, 1, 12 },
165 { 12000000, P_PLL8, 4, 1, 8 },
166 { 16000000, P_PLL8, 4, 1, 6 },
167 { 19200000, P_PLL8, 4, 1, 5 },
168 { 24000000, P_PLL8, 4, 1, 4 },
169 { 32000000, P_PLL8, 4, 1, 3 },
170 { 48000000, P_PLL8, 4, 1, 2 },
171 { 64000000, P_PLL8, 3, 1, 2 },
172 { 96000000, P_PLL8, 4, 0, 0 },
173 { 128000000, P_PLL8, 3, 0, 0 },
174 { }
175 };
176
177 static struct clk_rcg camclk0_src = {
178 .ns_reg = 0x0148,
179 .md_reg = 0x0144,
180 .mn = {
181 .mnctr_en_bit = 5,
182 .mnctr_reset_bit = 8,
183 .reset_in_cc = true,
184 .mnctr_mode_shift = 6,
185 .n_val_shift = 24,
186 .m_val_shift = 8,
187 .width = 8,
188 },
189 .p = {
190 .pre_div_shift = 14,
191 .pre_div_width = 2,
192 },
193 .s = {
194 .src_sel_shift = 0,
195 .parent_map = mmcc_pxo_pll8_pll2_map,
196 },
197 .freq_tbl = clk_tbl_cam,
198 .clkr = {
199 .enable_reg = 0x0140,
200 .enable_mask = BIT(2),
201 .hw.init = &(struct clk_init_data){
202 .name = "camclk0_src",
203 .parent_names = mmcc_pxo_pll8_pll2,
204 .num_parents = 3,
205 .ops = &clk_rcg_ops,
206 },
207 },
208 };
209
210 static struct clk_branch camclk0_clk = {
211 .halt_reg = 0x01e8,
212 .halt_bit = 15,
213 .clkr = {
214 .enable_reg = 0x0140,
215 .enable_mask = BIT(0),
216 .hw.init = &(struct clk_init_data){
217 .name = "camclk0_clk",
218 .parent_names = (const char *[]){ "camclk0_src" },
219 .num_parents = 1,
220 .ops = &clk_branch_ops,
221 },
222 },
223
224 };
225
226 static struct clk_rcg camclk1_src = {
227 .ns_reg = 0x015c,
228 .md_reg = 0x0158,
229 .mn = {
230 .mnctr_en_bit = 5,
231 .mnctr_reset_bit = 8,
232 .reset_in_cc = true,
233 .mnctr_mode_shift = 6,
234 .n_val_shift = 24,
235 .m_val_shift = 8,
236 .width = 8,
237 },
238 .p = {
239 .pre_div_shift = 14,
240 .pre_div_width = 2,
241 },
242 .s = {
243 .src_sel_shift = 0,
244 .parent_map = mmcc_pxo_pll8_pll2_map,
245 },
246 .freq_tbl = clk_tbl_cam,
247 .clkr = {
248 .enable_reg = 0x0154,
249 .enable_mask = BIT(2),
250 .hw.init = &(struct clk_init_data){
251 .name = "camclk1_src",
252 .parent_names = mmcc_pxo_pll8_pll2,
253 .num_parents = 3,
254 .ops = &clk_rcg_ops,
255 },
256 },
257 };
258
259 static struct clk_branch camclk1_clk = {
260 .halt_reg = 0x01e8,
261 .halt_bit = 16,
262 .clkr = {
263 .enable_reg = 0x0154,
264 .enable_mask = BIT(0),
265 .hw.init = &(struct clk_init_data){
266 .name = "camclk1_clk",
267 .parent_names = (const char *[]){ "camclk1_src" },
268 .num_parents = 1,
269 .ops = &clk_branch_ops,
270 },
271 },
272
273 };
274
275 static struct clk_rcg camclk2_src = {
276 .ns_reg = 0x0228,
277 .md_reg = 0x0224,
278 .mn = {
279 .mnctr_en_bit = 5,
280 .mnctr_reset_bit = 8,
281 .reset_in_cc = true,
282 .mnctr_mode_shift = 6,
283 .n_val_shift = 24,
284 .m_val_shift = 8,
285 .width = 8,
286 },
287 .p = {
288 .pre_div_shift = 14,
289 .pre_div_width = 2,
290 },
291 .s = {
292 .src_sel_shift = 0,
293 .parent_map = mmcc_pxo_pll8_pll2_map,
294 },
295 .freq_tbl = clk_tbl_cam,
296 .clkr = {
297 .enable_reg = 0x0220,
298 .enable_mask = BIT(2),
299 .hw.init = &(struct clk_init_data){
300 .name = "camclk2_src",
301 .parent_names = mmcc_pxo_pll8_pll2,
302 .num_parents = 3,
303 .ops = &clk_rcg_ops,
304 },
305 },
306 };
307
308 static struct clk_branch camclk2_clk = {
309 .halt_reg = 0x01e8,
310 .halt_bit = 16,
311 .clkr = {
312 .enable_reg = 0x0220,
313 .enable_mask = BIT(0),
314 .hw.init = &(struct clk_init_data){
315 .name = "camclk2_clk",
316 .parent_names = (const char *[]){ "camclk2_src" },
317 .num_parents = 1,
318 .ops = &clk_branch_ops,
319 },
320 },
321
322 };
323
324 static struct freq_tbl clk_tbl_csi[] = {
325 { 27000000, P_PXO, 1, 0, 0 },
326 { 85330000, P_PLL8, 1, 2, 9 },
327 { 177780000, P_PLL2, 1, 2, 9 },
328 { }
329 };
330
331 static struct clk_rcg csi0_src = {
332 .ns_reg = 0x0048,
333 .md_reg = 0x0044,
334 .mn = {
335 .mnctr_en_bit = 5,
336 .mnctr_reset_bit = 7,
337 .mnctr_mode_shift = 6,
338 .n_val_shift = 24,
339 .m_val_shift = 8,
340 .width = 8,
341 },
342 .p = {
343 .pre_div_shift = 14,
344 .pre_div_width = 2,
345 },
346 .s = {
347 .src_sel_shift = 0,
348 .parent_map = mmcc_pxo_pll8_pll2_map,
349 },
350 .freq_tbl = clk_tbl_csi,
351 .clkr = {
352 .enable_reg = 0x0040,
353 .enable_mask = BIT(2),
354 .hw.init = &(struct clk_init_data){
355 .name = "csi0_src",
356 .parent_names = mmcc_pxo_pll8_pll2,
357 .num_parents = 3,
358 .ops = &clk_rcg_ops,
359 },
360 },
361 };
362
363 static struct clk_branch csi0_clk = {
364 .halt_reg = 0x01cc,
365 .halt_bit = 13,
366 .clkr = {
367 .enable_reg = 0x0040,
368 .enable_mask = BIT(0),
369 .hw.init = &(struct clk_init_data){
370 .parent_names = (const char *[]){ "csi0_src" },
371 .num_parents = 1,
372 .name = "csi0_clk",
373 .ops = &clk_branch_ops,
374 .flags = CLK_SET_RATE_PARENT,
375 },
376 },
377 };
378
379 static struct clk_branch csi0_phy_clk = {
380 .halt_reg = 0x01e8,
381 .halt_bit = 9,
382 .clkr = {
383 .enable_reg = 0x0040,
384 .enable_mask = BIT(8),
385 .hw.init = &(struct clk_init_data){
386 .parent_names = (const char *[]){ "csi0_src" },
387 .num_parents = 1,
388 .name = "csi0_phy_clk",
389 .ops = &clk_branch_ops,
390 .flags = CLK_SET_RATE_PARENT,
391 },
392 },
393 };
394
395 static struct clk_rcg csi1_src = {
396 .ns_reg = 0x0010,
397 .md_reg = 0x0028,
398 .mn = {
399 .mnctr_en_bit = 5,
400 .mnctr_reset_bit = 7,
401 .mnctr_mode_shift = 6,
402 .n_val_shift = 24,
403 .m_val_shift = 8,
404 .width = 8,
405 },
406 .p = {
407 .pre_div_shift = 14,
408 .pre_div_width = 2,
409 },
410 .s = {
411 .src_sel_shift = 0,
412 .parent_map = mmcc_pxo_pll8_pll2_map,
413 },
414 .freq_tbl = clk_tbl_csi,
415 .clkr = {
416 .enable_reg = 0x0024,
417 .enable_mask = BIT(2),
418 .hw.init = &(struct clk_init_data){
419 .name = "csi1_src",
420 .parent_names = mmcc_pxo_pll8_pll2,
421 .num_parents = 3,
422 .ops = &clk_rcg_ops,
423 },
424 },
425 };
426
427 static struct clk_branch csi1_clk = {
428 .halt_reg = 0x01cc,
429 .halt_bit = 14,
430 .clkr = {
431 .enable_reg = 0x0024,
432 .enable_mask = BIT(0),
433 .hw.init = &(struct clk_init_data){
434 .parent_names = (const char *[]){ "csi1_src" },
435 .num_parents = 1,
436 .name = "csi1_clk",
437 .ops = &clk_branch_ops,
438 .flags = CLK_SET_RATE_PARENT,
439 },
440 },
441 };
442
443 static struct clk_branch csi1_phy_clk = {
444 .halt_reg = 0x01e8,
445 .halt_bit = 10,
446 .clkr = {
447 .enable_reg = 0x0024,
448 .enable_mask = BIT(8),
449 .hw.init = &(struct clk_init_data){
450 .parent_names = (const char *[]){ "csi1_src" },
451 .num_parents = 1,
452 .name = "csi1_phy_clk",
453 .ops = &clk_branch_ops,
454 .flags = CLK_SET_RATE_PARENT,
455 },
456 },
457 };
458
459 static struct clk_rcg csi2_src = {
460 .ns_reg = 0x0234,
461 .md_reg = 0x022c,
462 .mn = {
463 .mnctr_en_bit = 5,
464 .mnctr_reset_bit = 7,
465 .mnctr_mode_shift = 6,
466 .n_val_shift = 24,
467 .m_val_shift = 8,
468 .width = 8,
469 },
470 .p = {
471 .pre_div_shift = 14,
472 .pre_div_width = 2,
473 },
474 .s = {
475 .src_sel_shift = 0,
476 .parent_map = mmcc_pxo_pll8_pll2_map,
477 },
478 .freq_tbl = clk_tbl_csi,
479 .clkr = {
480 .enable_reg = 0x022c,
481 .enable_mask = BIT(2),
482 .hw.init = &(struct clk_init_data){
483 .name = "csi2_src",
484 .parent_names = mmcc_pxo_pll8_pll2,
485 .num_parents = 3,
486 .ops = &clk_rcg_ops,
487 },
488 },
489 };
490
491 static struct clk_branch csi2_clk = {
492 .halt_reg = 0x01cc,
493 .halt_bit = 29,
494 .clkr = {
495 .enable_reg = 0x022c,
496 .enable_mask = BIT(0),
497 .hw.init = &(struct clk_init_data){
498 .parent_names = (const char *[]){ "csi2_src" },
499 .num_parents = 1,
500 .name = "csi2_clk",
501 .ops = &clk_branch_ops,
502 .flags = CLK_SET_RATE_PARENT,
503 },
504 },
505 };
506
507 static struct clk_branch csi2_phy_clk = {
508 .halt_reg = 0x01e8,
509 .halt_bit = 29,
510 .clkr = {
511 .enable_reg = 0x022c,
512 .enable_mask = BIT(8),
513 .hw.init = &(struct clk_init_data){
514 .parent_names = (const char *[]){ "csi2_src" },
515 .num_parents = 1,
516 .name = "csi2_phy_clk",
517 .ops = &clk_branch_ops,
518 .flags = CLK_SET_RATE_PARENT,
519 },
520 },
521 };
522
523 struct clk_pix_rdi {
524 u32 s_reg;
525 u32 s_mask;
526 u32 s2_reg;
527 u32 s2_mask;
528 struct clk_regmap clkr;
529 };
530
531 #define to_clk_pix_rdi(_hw) \
532 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
533
534 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
535 {
536 int i;
537 int ret = 0;
538 u32 val;
539 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
540 int num_parents = clk_hw_get_num_parents(hw);
541
542 /*
543 * These clocks select three inputs via two muxes. One mux selects
544 * between csi0 and csi1 and the second mux selects between that mux's
545 * output and csi2. The source and destination selections for each
546 * mux must be clocking for the switch to succeed so just turn on
547 * all three sources because it's easier than figuring out what source
548 * needs to be on at what time.
549 */
550 for (i = 0; i < num_parents; i++) {
551 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
552 ret = clk_prepare_enable(p->clk);
553 if (ret)
554 goto err;
555 }
556
557 if (index == 2)
558 val = rdi->s2_mask;
559 else
560 val = 0;
561 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
562 /*
563 * Wait at least 6 cycles of slowest clock
564 * for the glitch-free MUX to fully switch sources.
565 */
566 udelay(1);
567
568 if (index == 1)
569 val = rdi->s_mask;
570 else
571 val = 0;
572 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
573 /*
574 * Wait at least 6 cycles of slowest clock
575 * for the glitch-free MUX to fully switch sources.
576 */
577 udelay(1);
578
579 err:
580 for (i--; i >= 0; i--) {
581 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
582 clk_disable_unprepare(p->clk);
583 }
584
585 return ret;
586 }
587
588 static u8 pix_rdi_get_parent(struct clk_hw *hw)
589 {
590 u32 val;
591 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
592
593
594 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
595 if (val & rdi->s2_mask)
596 return 2;
597
598 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
599 if (val & rdi->s_mask)
600 return 1;
601
602 return 0;
603 }
604
605 static const struct clk_ops clk_ops_pix_rdi = {
606 .enable = clk_enable_regmap,
607 .disable = clk_disable_regmap,
608 .set_parent = pix_rdi_set_parent,
609 .get_parent = pix_rdi_get_parent,
610 .determine_rate = __clk_mux_determine_rate,
611 };
612
613 static const char * const pix_rdi_parents[] = {
614 "csi0_clk",
615 "csi1_clk",
616 "csi2_clk",
617 };
618
619 static struct clk_pix_rdi csi_pix_clk = {
620 .s_reg = 0x0058,
621 .s_mask = BIT(25),
622 .s2_reg = 0x0238,
623 .s2_mask = BIT(13),
624 .clkr = {
625 .enable_reg = 0x0058,
626 .enable_mask = BIT(26),
627 .hw.init = &(struct clk_init_data){
628 .name = "csi_pix_clk",
629 .parent_names = pix_rdi_parents,
630 .num_parents = 3,
631 .ops = &clk_ops_pix_rdi,
632 },
633 },
634 };
635
636 static struct clk_pix_rdi csi_pix1_clk = {
637 .s_reg = 0x0238,
638 .s_mask = BIT(8),
639 .s2_reg = 0x0238,
640 .s2_mask = BIT(9),
641 .clkr = {
642 .enable_reg = 0x0238,
643 .enable_mask = BIT(10),
644 .hw.init = &(struct clk_init_data){
645 .name = "csi_pix1_clk",
646 .parent_names = pix_rdi_parents,
647 .num_parents = 3,
648 .ops = &clk_ops_pix_rdi,
649 },
650 },
651 };
652
653 static struct clk_pix_rdi csi_rdi_clk = {
654 .s_reg = 0x0058,
655 .s_mask = BIT(12),
656 .s2_reg = 0x0238,
657 .s2_mask = BIT(12),
658 .clkr = {
659 .enable_reg = 0x0058,
660 .enable_mask = BIT(13),
661 .hw.init = &(struct clk_init_data){
662 .name = "csi_rdi_clk",
663 .parent_names = pix_rdi_parents,
664 .num_parents = 3,
665 .ops = &clk_ops_pix_rdi,
666 },
667 },
668 };
669
670 static struct clk_pix_rdi csi_rdi1_clk = {
671 .s_reg = 0x0238,
672 .s_mask = BIT(0),
673 .s2_reg = 0x0238,
674 .s2_mask = BIT(1),
675 .clkr = {
676 .enable_reg = 0x0238,
677 .enable_mask = BIT(2),
678 .hw.init = &(struct clk_init_data){
679 .name = "csi_rdi1_clk",
680 .parent_names = pix_rdi_parents,
681 .num_parents = 3,
682 .ops = &clk_ops_pix_rdi,
683 },
684 },
685 };
686
687 static struct clk_pix_rdi csi_rdi2_clk = {
688 .s_reg = 0x0238,
689 .s_mask = BIT(4),
690 .s2_reg = 0x0238,
691 .s2_mask = BIT(5),
692 .clkr = {
693 .enable_reg = 0x0238,
694 .enable_mask = BIT(6),
695 .hw.init = &(struct clk_init_data){
696 .name = "csi_rdi2_clk",
697 .parent_names = pix_rdi_parents,
698 .num_parents = 3,
699 .ops = &clk_ops_pix_rdi,
700 },
701 },
702 };
703
704 static struct freq_tbl clk_tbl_csiphytimer[] = {
705 { 85330000, P_PLL8, 1, 2, 9 },
706 { 177780000, P_PLL2, 1, 2, 9 },
707 { }
708 };
709
710 static struct clk_rcg csiphytimer_src = {
711 .ns_reg = 0x0168,
712 .md_reg = 0x0164,
713 .mn = {
714 .mnctr_en_bit = 5,
715 .mnctr_reset_bit = 8,
716 .reset_in_cc = true,
717 .mnctr_mode_shift = 6,
718 .n_val_shift = 24,
719 .m_val_shift = 8,
720 .width = 8,
721 },
722 .p = {
723 .pre_div_shift = 14,
724 .pre_div_width = 2,
725 },
726 .s = {
727 .src_sel_shift = 0,
728 .parent_map = mmcc_pxo_pll8_pll2_map,
729 },
730 .freq_tbl = clk_tbl_csiphytimer,
731 .clkr = {
732 .enable_reg = 0x0160,
733 .enable_mask = BIT(2),
734 .hw.init = &(struct clk_init_data){
735 .name = "csiphytimer_src",
736 .parent_names = mmcc_pxo_pll8_pll2,
737 .num_parents = 3,
738 .ops = &clk_rcg_ops,
739 },
740 },
741 };
742
743 static const char * const csixphy_timer_src[] = { "csiphytimer_src" };
744
745 static struct clk_branch csiphy0_timer_clk = {
746 .halt_reg = 0x01e8,
747 .halt_bit = 17,
748 .clkr = {
749 .enable_reg = 0x0160,
750 .enable_mask = BIT(0),
751 .hw.init = &(struct clk_init_data){
752 .parent_names = csixphy_timer_src,
753 .num_parents = 1,
754 .name = "csiphy0_timer_clk",
755 .ops = &clk_branch_ops,
756 .flags = CLK_SET_RATE_PARENT,
757 },
758 },
759 };
760
761 static struct clk_branch csiphy1_timer_clk = {
762 .halt_reg = 0x01e8,
763 .halt_bit = 18,
764 .clkr = {
765 .enable_reg = 0x0160,
766 .enable_mask = BIT(9),
767 .hw.init = &(struct clk_init_data){
768 .parent_names = csixphy_timer_src,
769 .num_parents = 1,
770 .name = "csiphy1_timer_clk",
771 .ops = &clk_branch_ops,
772 .flags = CLK_SET_RATE_PARENT,
773 },
774 },
775 };
776
777 static struct clk_branch csiphy2_timer_clk = {
778 .halt_reg = 0x01e8,
779 .halt_bit = 30,
780 .clkr = {
781 .enable_reg = 0x0160,
782 .enable_mask = BIT(11),
783 .hw.init = &(struct clk_init_data){
784 .parent_names = csixphy_timer_src,
785 .num_parents = 1,
786 .name = "csiphy2_timer_clk",
787 .ops = &clk_branch_ops,
788 .flags = CLK_SET_RATE_PARENT,
789 },
790 },
791 };
792
793 static struct freq_tbl clk_tbl_gfx2d[] = {
794 F_MN( 27000000, P_PXO, 1, 0),
795 F_MN( 48000000, P_PLL8, 1, 8),
796 F_MN( 54857000, P_PLL8, 1, 7),
797 F_MN( 64000000, P_PLL8, 1, 6),
798 F_MN( 76800000, P_PLL8, 1, 5),
799 F_MN( 96000000, P_PLL8, 1, 4),
800 F_MN(128000000, P_PLL8, 1, 3),
801 F_MN(145455000, P_PLL2, 2, 11),
802 F_MN(160000000, P_PLL2, 1, 5),
803 F_MN(177778000, P_PLL2, 2, 9),
804 F_MN(200000000, P_PLL2, 1, 4),
805 F_MN(228571000, P_PLL2, 2, 7),
806 { }
807 };
808
809 static struct clk_dyn_rcg gfx2d0_src = {
810 .ns_reg[0] = 0x0070,
811 .ns_reg[1] = 0x0070,
812 .md_reg[0] = 0x0064,
813 .md_reg[1] = 0x0068,
814 .bank_reg = 0x0060,
815 .mn[0] = {
816 .mnctr_en_bit = 8,
817 .mnctr_reset_bit = 25,
818 .mnctr_mode_shift = 9,
819 .n_val_shift = 20,
820 .m_val_shift = 4,
821 .width = 4,
822 },
823 .mn[1] = {
824 .mnctr_en_bit = 5,
825 .mnctr_reset_bit = 24,
826 .mnctr_mode_shift = 6,
827 .n_val_shift = 16,
828 .m_val_shift = 4,
829 .width = 4,
830 },
831 .s[0] = {
832 .src_sel_shift = 3,
833 .parent_map = mmcc_pxo_pll8_pll2_map,
834 },
835 .s[1] = {
836 .src_sel_shift = 0,
837 .parent_map = mmcc_pxo_pll8_pll2_map,
838 },
839 .mux_sel_bit = 11,
840 .freq_tbl = clk_tbl_gfx2d,
841 .clkr = {
842 .enable_reg = 0x0060,
843 .enable_mask = BIT(2),
844 .hw.init = &(struct clk_init_data){
845 .name = "gfx2d0_src",
846 .parent_names = mmcc_pxo_pll8_pll2,
847 .num_parents = 3,
848 .ops = &clk_dyn_rcg_ops,
849 },
850 },
851 };
852
853 static struct clk_branch gfx2d0_clk = {
854 .halt_reg = 0x01c8,
855 .halt_bit = 9,
856 .clkr = {
857 .enable_reg = 0x0060,
858 .enable_mask = BIT(0),
859 .hw.init = &(struct clk_init_data){
860 .name = "gfx2d0_clk",
861 .parent_names = (const char *[]){ "gfx2d0_src" },
862 .num_parents = 1,
863 .ops = &clk_branch_ops,
864 .flags = CLK_SET_RATE_PARENT,
865 },
866 },
867 };
868
869 static struct clk_dyn_rcg gfx2d1_src = {
870 .ns_reg[0] = 0x007c,
871 .ns_reg[1] = 0x007c,
872 .md_reg[0] = 0x0078,
873 .md_reg[1] = 0x006c,
874 .bank_reg = 0x0074,
875 .mn[0] = {
876 .mnctr_en_bit = 8,
877 .mnctr_reset_bit = 25,
878 .mnctr_mode_shift = 9,
879 .n_val_shift = 20,
880 .m_val_shift = 4,
881 .width = 4,
882 },
883 .mn[1] = {
884 .mnctr_en_bit = 5,
885 .mnctr_reset_bit = 24,
886 .mnctr_mode_shift = 6,
887 .n_val_shift = 16,
888 .m_val_shift = 4,
889 .width = 4,
890 },
891 .s[0] = {
892 .src_sel_shift = 3,
893 .parent_map = mmcc_pxo_pll8_pll2_map,
894 },
895 .s[1] = {
896 .src_sel_shift = 0,
897 .parent_map = mmcc_pxo_pll8_pll2_map,
898 },
899 .mux_sel_bit = 11,
900 .freq_tbl = clk_tbl_gfx2d,
901 .clkr = {
902 .enable_reg = 0x0074,
903 .enable_mask = BIT(2),
904 .hw.init = &(struct clk_init_data){
905 .name = "gfx2d1_src",
906 .parent_names = mmcc_pxo_pll8_pll2,
907 .num_parents = 3,
908 .ops = &clk_dyn_rcg_ops,
909 },
910 },
911 };
912
913 static struct clk_branch gfx2d1_clk = {
914 .halt_reg = 0x01c8,
915 .halt_bit = 14,
916 .clkr = {
917 .enable_reg = 0x0074,
918 .enable_mask = BIT(0),
919 .hw.init = &(struct clk_init_data){
920 .name = "gfx2d1_clk",
921 .parent_names = (const char *[]){ "gfx2d1_src" },
922 .num_parents = 1,
923 .ops = &clk_branch_ops,
924 .flags = CLK_SET_RATE_PARENT,
925 },
926 },
927 };
928
929 static struct freq_tbl clk_tbl_gfx3d[] = {
930 F_MN( 27000000, P_PXO, 1, 0),
931 F_MN( 48000000, P_PLL8, 1, 8),
932 F_MN( 54857000, P_PLL8, 1, 7),
933 F_MN( 64000000, P_PLL8, 1, 6),
934 F_MN( 76800000, P_PLL8, 1, 5),
935 F_MN( 96000000, P_PLL8, 1, 4),
936 F_MN(128000000, P_PLL8, 1, 3),
937 F_MN(145455000, P_PLL2, 2, 11),
938 F_MN(160000000, P_PLL2, 1, 5),
939 F_MN(177778000, P_PLL2, 2, 9),
940 F_MN(200000000, P_PLL2, 1, 4),
941 F_MN(228571000, P_PLL2, 2, 7),
942 F_MN(266667000, P_PLL2, 1, 3),
943 F_MN(300000000, P_PLL3, 1, 4),
944 F_MN(320000000, P_PLL2, 2, 5),
945 F_MN(400000000, P_PLL2, 1, 2),
946 { }
947 };
948
949 static struct freq_tbl clk_tbl_gfx3d_8064[] = {
950 F_MN( 27000000, P_PXO, 0, 0),
951 F_MN( 48000000, P_PLL8, 1, 8),
952 F_MN( 54857000, P_PLL8, 1, 7),
953 F_MN( 64000000, P_PLL8, 1, 6),
954 F_MN( 76800000, P_PLL8, 1, 5),
955 F_MN( 96000000, P_PLL8, 1, 4),
956 F_MN(128000000, P_PLL8, 1, 3),
957 F_MN(145455000, P_PLL2, 2, 11),
958 F_MN(160000000, P_PLL2, 1, 5),
959 F_MN(177778000, P_PLL2, 2, 9),
960 F_MN(192000000, P_PLL8, 1, 2),
961 F_MN(200000000, P_PLL2, 1, 4),
962 F_MN(228571000, P_PLL2, 2, 7),
963 F_MN(266667000, P_PLL2, 1, 3),
964 F_MN(320000000, P_PLL2, 2, 5),
965 F_MN(400000000, P_PLL2, 1, 2),
966 F_MN(450000000, P_PLL15, 1, 2),
967 { }
968 };
969
970 static struct clk_dyn_rcg gfx3d_src = {
971 .ns_reg[0] = 0x008c,
972 .ns_reg[1] = 0x008c,
973 .md_reg[0] = 0x0084,
974 .md_reg[1] = 0x0088,
975 .bank_reg = 0x0080,
976 .mn[0] = {
977 .mnctr_en_bit = 8,
978 .mnctr_reset_bit = 25,
979 .mnctr_mode_shift = 9,
980 .n_val_shift = 18,
981 .m_val_shift = 4,
982 .width = 4,
983 },
984 .mn[1] = {
985 .mnctr_en_bit = 5,
986 .mnctr_reset_bit = 24,
987 .mnctr_mode_shift = 6,
988 .n_val_shift = 14,
989 .m_val_shift = 4,
990 .width = 4,
991 },
992 .s[0] = {
993 .src_sel_shift = 3,
994 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
995 },
996 .s[1] = {
997 .src_sel_shift = 0,
998 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
999 },
1000 .mux_sel_bit = 11,
1001 .freq_tbl = clk_tbl_gfx3d,
1002 .clkr = {
1003 .enable_reg = 0x0080,
1004 .enable_mask = BIT(2),
1005 .hw.init = &(struct clk_init_data){
1006 .name = "gfx3d_src",
1007 .parent_names = mmcc_pxo_pll8_pll2_pll3,
1008 .num_parents = 4,
1009 .ops = &clk_dyn_rcg_ops,
1010 },
1011 },
1012 };
1013
1014 static const struct clk_init_data gfx3d_8064_init = {
1015 .name = "gfx3d_src",
1016 .parent_names = mmcc_pxo_pll8_pll2_pll15,
1017 .num_parents = 4,
1018 .ops = &clk_dyn_rcg_ops,
1019 };
1020
1021 static struct clk_branch gfx3d_clk = {
1022 .halt_reg = 0x01c8,
1023 .halt_bit = 4,
1024 .clkr = {
1025 .enable_reg = 0x0080,
1026 .enable_mask = BIT(0),
1027 .hw.init = &(struct clk_init_data){
1028 .name = "gfx3d_clk",
1029 .parent_names = (const char *[]){ "gfx3d_src" },
1030 .num_parents = 1,
1031 .ops = &clk_branch_ops,
1032 .flags = CLK_SET_RATE_PARENT,
1033 },
1034 },
1035 };
1036
1037 static struct freq_tbl clk_tbl_vcap[] = {
1038 F_MN( 27000000, P_PXO, 0, 0),
1039 F_MN( 54860000, P_PLL8, 1, 7),
1040 F_MN( 64000000, P_PLL8, 1, 6),
1041 F_MN( 76800000, P_PLL8, 1, 5),
1042 F_MN(128000000, P_PLL8, 1, 3),
1043 F_MN(160000000, P_PLL2, 1, 5),
1044 F_MN(200000000, P_PLL2, 1, 4),
1045 { }
1046 };
1047
1048 static struct clk_dyn_rcg vcap_src = {
1049 .ns_reg[0] = 0x021c,
1050 .ns_reg[1] = 0x021c,
1051 .md_reg[0] = 0x01ec,
1052 .md_reg[1] = 0x0218,
1053 .bank_reg = 0x0178,
1054 .mn[0] = {
1055 .mnctr_en_bit = 8,
1056 .mnctr_reset_bit = 23,
1057 .mnctr_mode_shift = 9,
1058 .n_val_shift = 18,
1059 .m_val_shift = 4,
1060 .width = 4,
1061 },
1062 .mn[1] = {
1063 .mnctr_en_bit = 5,
1064 .mnctr_reset_bit = 22,
1065 .mnctr_mode_shift = 6,
1066 .n_val_shift = 14,
1067 .m_val_shift = 4,
1068 .width = 4,
1069 },
1070 .s[0] = {
1071 .src_sel_shift = 3,
1072 .parent_map = mmcc_pxo_pll8_pll2_map,
1073 },
1074 .s[1] = {
1075 .src_sel_shift = 0,
1076 .parent_map = mmcc_pxo_pll8_pll2_map,
1077 },
1078 .mux_sel_bit = 11,
1079 .freq_tbl = clk_tbl_vcap,
1080 .clkr = {
1081 .enable_reg = 0x0178,
1082 .enable_mask = BIT(2),
1083 .hw.init = &(struct clk_init_data){
1084 .name = "vcap_src",
1085 .parent_names = mmcc_pxo_pll8_pll2,
1086 .num_parents = 3,
1087 .ops = &clk_dyn_rcg_ops,
1088 },
1089 },
1090 };
1091
1092 static struct clk_branch vcap_clk = {
1093 .halt_reg = 0x0240,
1094 .halt_bit = 15,
1095 .clkr = {
1096 .enable_reg = 0x0178,
1097 .enable_mask = BIT(0),
1098 .hw.init = &(struct clk_init_data){
1099 .name = "vcap_clk",
1100 .parent_names = (const char *[]){ "vcap_src" },
1101 .num_parents = 1,
1102 .ops = &clk_branch_ops,
1103 .flags = CLK_SET_RATE_PARENT,
1104 },
1105 },
1106 };
1107
1108 static struct clk_branch vcap_npl_clk = {
1109 .halt_reg = 0x0240,
1110 .halt_bit = 25,
1111 .clkr = {
1112 .enable_reg = 0x0178,
1113 .enable_mask = BIT(13),
1114 .hw.init = &(struct clk_init_data){
1115 .name = "vcap_npl_clk",
1116 .parent_names = (const char *[]){ "vcap_src" },
1117 .num_parents = 1,
1118 .ops = &clk_branch_ops,
1119 .flags = CLK_SET_RATE_PARENT,
1120 },
1121 },
1122 };
1123
1124 static struct freq_tbl clk_tbl_ijpeg[] = {
1125 { 27000000, P_PXO, 1, 0, 0 },
1126 { 36570000, P_PLL8, 1, 2, 21 },
1127 { 54860000, P_PLL8, 7, 0, 0 },
1128 { 96000000, P_PLL8, 4, 0, 0 },
1129 { 109710000, P_PLL8, 1, 2, 7 },
1130 { 128000000, P_PLL8, 3, 0, 0 },
1131 { 153600000, P_PLL8, 1, 2, 5 },
1132 { 200000000, P_PLL2, 4, 0, 0 },
1133 { 228571000, P_PLL2, 1, 2, 7 },
1134 { 266667000, P_PLL2, 1, 1, 3 },
1135 { 320000000, P_PLL2, 1, 2, 5 },
1136 { }
1137 };
1138
1139 static struct clk_rcg ijpeg_src = {
1140 .ns_reg = 0x00a0,
1141 .md_reg = 0x009c,
1142 .mn = {
1143 .mnctr_en_bit = 5,
1144 .mnctr_reset_bit = 7,
1145 .mnctr_mode_shift = 6,
1146 .n_val_shift = 16,
1147 .m_val_shift = 8,
1148 .width = 8,
1149 },
1150 .p = {
1151 .pre_div_shift = 12,
1152 .pre_div_width = 2,
1153 },
1154 .s = {
1155 .src_sel_shift = 0,
1156 .parent_map = mmcc_pxo_pll8_pll2_map,
1157 },
1158 .freq_tbl = clk_tbl_ijpeg,
1159 .clkr = {
1160 .enable_reg = 0x0098,
1161 .enable_mask = BIT(2),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "ijpeg_src",
1164 .parent_names = mmcc_pxo_pll8_pll2,
1165 .num_parents = 3,
1166 .ops = &clk_rcg_ops,
1167 },
1168 },
1169 };
1170
1171 static struct clk_branch ijpeg_clk = {
1172 .halt_reg = 0x01c8,
1173 .halt_bit = 24,
1174 .clkr = {
1175 .enable_reg = 0x0098,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "ijpeg_clk",
1179 .parent_names = (const char *[]){ "ijpeg_src" },
1180 .num_parents = 1,
1181 .ops = &clk_branch_ops,
1182 .flags = CLK_SET_RATE_PARENT,
1183 },
1184 },
1185 };
1186
1187 static struct freq_tbl clk_tbl_jpegd[] = {
1188 { 64000000, P_PLL8, 6 },
1189 { 76800000, P_PLL8, 5 },
1190 { 96000000, P_PLL8, 4 },
1191 { 160000000, P_PLL2, 5 },
1192 { 200000000, P_PLL2, 4 },
1193 { }
1194 };
1195
1196 static struct clk_rcg jpegd_src = {
1197 .ns_reg = 0x00ac,
1198 .p = {
1199 .pre_div_shift = 12,
1200 .pre_div_width = 4,
1201 },
1202 .s = {
1203 .src_sel_shift = 0,
1204 .parent_map = mmcc_pxo_pll8_pll2_map,
1205 },
1206 .freq_tbl = clk_tbl_jpegd,
1207 .clkr = {
1208 .enable_reg = 0x00a4,
1209 .enable_mask = BIT(2),
1210 .hw.init = &(struct clk_init_data){
1211 .name = "jpegd_src",
1212 .parent_names = mmcc_pxo_pll8_pll2,
1213 .num_parents = 3,
1214 .ops = &clk_rcg_ops,
1215 },
1216 },
1217 };
1218
1219 static struct clk_branch jpegd_clk = {
1220 .halt_reg = 0x01c8,
1221 .halt_bit = 19,
1222 .clkr = {
1223 .enable_reg = 0x00a4,
1224 .enable_mask = BIT(0),
1225 .hw.init = &(struct clk_init_data){
1226 .name = "jpegd_clk",
1227 .parent_names = (const char *[]){ "jpegd_src" },
1228 .num_parents = 1,
1229 .ops = &clk_branch_ops,
1230 .flags = CLK_SET_RATE_PARENT,
1231 },
1232 },
1233 };
1234
1235 static struct freq_tbl clk_tbl_mdp[] = {
1236 { 9600000, P_PLL8, 1, 1, 40 },
1237 { 13710000, P_PLL8, 1, 1, 28 },
1238 { 27000000, P_PXO, 1, 0, 0 },
1239 { 29540000, P_PLL8, 1, 1, 13 },
1240 { 34910000, P_PLL8, 1, 1, 11 },
1241 { 38400000, P_PLL8, 1, 1, 10 },
1242 { 59080000, P_PLL8, 1, 2, 13 },
1243 { 76800000, P_PLL8, 1, 1, 5 },
1244 { 85330000, P_PLL8, 1, 2, 9 },
1245 { 96000000, P_PLL8, 1, 1, 4 },
1246 { 128000000, P_PLL8, 1, 1, 3 },
1247 { 160000000, P_PLL2, 1, 1, 5 },
1248 { 177780000, P_PLL2, 1, 2, 9 },
1249 { 200000000, P_PLL2, 1, 1, 4 },
1250 { 228571000, P_PLL2, 1, 2, 7 },
1251 { 266667000, P_PLL2, 1, 1, 3 },
1252 { }
1253 };
1254
1255 static struct clk_dyn_rcg mdp_src = {
1256 .ns_reg[0] = 0x00d0,
1257 .ns_reg[1] = 0x00d0,
1258 .md_reg[0] = 0x00c4,
1259 .md_reg[1] = 0x00c8,
1260 .bank_reg = 0x00c0,
1261 .mn[0] = {
1262 .mnctr_en_bit = 8,
1263 .mnctr_reset_bit = 31,
1264 .mnctr_mode_shift = 9,
1265 .n_val_shift = 22,
1266 .m_val_shift = 8,
1267 .width = 8,
1268 },
1269 .mn[1] = {
1270 .mnctr_en_bit = 5,
1271 .mnctr_reset_bit = 30,
1272 .mnctr_mode_shift = 6,
1273 .n_val_shift = 14,
1274 .m_val_shift = 8,
1275 .width = 8,
1276 },
1277 .s[0] = {
1278 .src_sel_shift = 3,
1279 .parent_map = mmcc_pxo_pll8_pll2_map,
1280 },
1281 .s[1] = {
1282 .src_sel_shift = 0,
1283 .parent_map = mmcc_pxo_pll8_pll2_map,
1284 },
1285 .mux_sel_bit = 11,
1286 .freq_tbl = clk_tbl_mdp,
1287 .clkr = {
1288 .enable_reg = 0x00c0,
1289 .enable_mask = BIT(2),
1290 .hw.init = &(struct clk_init_data){
1291 .name = "mdp_src",
1292 .parent_names = mmcc_pxo_pll8_pll2,
1293 .num_parents = 3,
1294 .ops = &clk_dyn_rcg_ops,
1295 },
1296 },
1297 };
1298
1299 static struct clk_branch mdp_clk = {
1300 .halt_reg = 0x01d0,
1301 .halt_bit = 10,
1302 .clkr = {
1303 .enable_reg = 0x00c0,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "mdp_clk",
1307 .parent_names = (const char *[]){ "mdp_src" },
1308 .num_parents = 1,
1309 .ops = &clk_branch_ops,
1310 .flags = CLK_SET_RATE_PARENT,
1311 },
1312 },
1313 };
1314
1315 static struct clk_branch mdp_lut_clk = {
1316 .halt_reg = 0x01e8,
1317 .halt_bit = 13,
1318 .clkr = {
1319 .enable_reg = 0x016c,
1320 .enable_mask = BIT(0),
1321 .hw.init = &(struct clk_init_data){
1322 .parent_names = (const char *[]){ "mdp_src" },
1323 .num_parents = 1,
1324 .name = "mdp_lut_clk",
1325 .ops = &clk_branch_ops,
1326 .flags = CLK_SET_RATE_PARENT,
1327 },
1328 },
1329 };
1330
1331 static struct clk_branch mdp_vsync_clk = {
1332 .halt_reg = 0x01cc,
1333 .halt_bit = 22,
1334 .clkr = {
1335 .enable_reg = 0x0058,
1336 .enable_mask = BIT(6),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "mdp_vsync_clk",
1339 .parent_names = (const char *[]){ "pxo" },
1340 .num_parents = 1,
1341 .ops = &clk_branch_ops
1342 },
1343 },
1344 };
1345
1346 static struct freq_tbl clk_tbl_rot[] = {
1347 { 27000000, P_PXO, 1 },
1348 { 29540000, P_PLL8, 13 },
1349 { 32000000, P_PLL8, 12 },
1350 { 38400000, P_PLL8, 10 },
1351 { 48000000, P_PLL8, 8 },
1352 { 54860000, P_PLL8, 7 },
1353 { 64000000, P_PLL8, 6 },
1354 { 76800000, P_PLL8, 5 },
1355 { 96000000, P_PLL8, 4 },
1356 { 100000000, P_PLL2, 8 },
1357 { 114290000, P_PLL2, 7 },
1358 { 133330000, P_PLL2, 6 },
1359 { 160000000, P_PLL2, 5 },
1360 { 200000000, P_PLL2, 4 },
1361 { }
1362 };
1363
1364 static struct clk_dyn_rcg rot_src = {
1365 .ns_reg[0] = 0x00e8,
1366 .ns_reg[1] = 0x00e8,
1367 .bank_reg = 0x00e8,
1368 .p[0] = {
1369 .pre_div_shift = 22,
1370 .pre_div_width = 4,
1371 },
1372 .p[1] = {
1373 .pre_div_shift = 26,
1374 .pre_div_width = 4,
1375 },
1376 .s[0] = {
1377 .src_sel_shift = 16,
1378 .parent_map = mmcc_pxo_pll8_pll2_map,
1379 },
1380 .s[1] = {
1381 .src_sel_shift = 19,
1382 .parent_map = mmcc_pxo_pll8_pll2_map,
1383 },
1384 .mux_sel_bit = 30,
1385 .freq_tbl = clk_tbl_rot,
1386 .clkr = {
1387 .enable_reg = 0x00e0,
1388 .enable_mask = BIT(2),
1389 .hw.init = &(struct clk_init_data){
1390 .name = "rot_src",
1391 .parent_names = mmcc_pxo_pll8_pll2,
1392 .num_parents = 3,
1393 .ops = &clk_dyn_rcg_ops,
1394 },
1395 },
1396 };
1397
1398 static struct clk_branch rot_clk = {
1399 .halt_reg = 0x01d0,
1400 .halt_bit = 15,
1401 .clkr = {
1402 .enable_reg = 0x00e0,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "rot_clk",
1406 .parent_names = (const char *[]){ "rot_src" },
1407 .num_parents = 1,
1408 .ops = &clk_branch_ops,
1409 .flags = CLK_SET_RATE_PARENT,
1410 },
1411 },
1412 };
1413
1414 static const struct parent_map mmcc_pxo_hdmi_map[] = {
1415 { P_PXO, 0 },
1416 { P_HDMI_PLL, 3 }
1417 };
1418
1419 static const char * const mmcc_pxo_hdmi[] = {
1420 "pxo",
1421 "hdmi_pll",
1422 };
1423
1424 static struct freq_tbl clk_tbl_tv[] = {
1425 { .src = P_HDMI_PLL, .pre_div = 1 },
1426 { }
1427 };
1428
1429 static struct clk_rcg tv_src = {
1430 .ns_reg = 0x00f4,
1431 .md_reg = 0x00f0,
1432 .mn = {
1433 .mnctr_en_bit = 5,
1434 .mnctr_reset_bit = 7,
1435 .mnctr_mode_shift = 6,
1436 .n_val_shift = 16,
1437 .m_val_shift = 8,
1438 .width = 8,
1439 },
1440 .p = {
1441 .pre_div_shift = 14,
1442 .pre_div_width = 2,
1443 },
1444 .s = {
1445 .src_sel_shift = 0,
1446 .parent_map = mmcc_pxo_hdmi_map,
1447 },
1448 .freq_tbl = clk_tbl_tv,
1449 .clkr = {
1450 .enable_reg = 0x00ec,
1451 .enable_mask = BIT(2),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "tv_src",
1454 .parent_names = mmcc_pxo_hdmi,
1455 .num_parents = 2,
1456 .ops = &clk_rcg_bypass_ops,
1457 .flags = CLK_SET_RATE_PARENT,
1458 },
1459 },
1460 };
1461
1462 static const char * const tv_src_name[] = { "tv_src" };
1463
1464 static struct clk_branch tv_enc_clk = {
1465 .halt_reg = 0x01d4,
1466 .halt_bit = 9,
1467 .clkr = {
1468 .enable_reg = 0x00ec,
1469 .enable_mask = BIT(8),
1470 .hw.init = &(struct clk_init_data){
1471 .parent_names = tv_src_name,
1472 .num_parents = 1,
1473 .name = "tv_enc_clk",
1474 .ops = &clk_branch_ops,
1475 .flags = CLK_SET_RATE_PARENT,
1476 },
1477 },
1478 };
1479
1480 static struct clk_branch tv_dac_clk = {
1481 .halt_reg = 0x01d4,
1482 .halt_bit = 10,
1483 .clkr = {
1484 .enable_reg = 0x00ec,
1485 .enable_mask = BIT(10),
1486 .hw.init = &(struct clk_init_data){
1487 .parent_names = tv_src_name,
1488 .num_parents = 1,
1489 .name = "tv_dac_clk",
1490 .ops = &clk_branch_ops,
1491 .flags = CLK_SET_RATE_PARENT,
1492 },
1493 },
1494 };
1495
1496 static struct clk_branch mdp_tv_clk = {
1497 .halt_reg = 0x01d4,
1498 .halt_bit = 12,
1499 .clkr = {
1500 .enable_reg = 0x00ec,
1501 .enable_mask = BIT(0),
1502 .hw.init = &(struct clk_init_data){
1503 .parent_names = tv_src_name,
1504 .num_parents = 1,
1505 .name = "mdp_tv_clk",
1506 .ops = &clk_branch_ops,
1507 .flags = CLK_SET_RATE_PARENT,
1508 },
1509 },
1510 };
1511
1512 static struct clk_branch hdmi_tv_clk = {
1513 .halt_reg = 0x01d4,
1514 .halt_bit = 11,
1515 .clkr = {
1516 .enable_reg = 0x00ec,
1517 .enable_mask = BIT(12),
1518 .hw.init = &(struct clk_init_data){
1519 .parent_names = tv_src_name,
1520 .num_parents = 1,
1521 .name = "hdmi_tv_clk",
1522 .ops = &clk_branch_ops,
1523 .flags = CLK_SET_RATE_PARENT,
1524 },
1525 },
1526 };
1527
1528 static struct clk_branch rgb_tv_clk = {
1529 .halt_reg = 0x0240,
1530 .halt_bit = 27,
1531 .clkr = {
1532 .enable_reg = 0x0124,
1533 .enable_mask = BIT(14),
1534 .hw.init = &(struct clk_init_data){
1535 .parent_names = tv_src_name,
1536 .num_parents = 1,
1537 .name = "rgb_tv_clk",
1538 .ops = &clk_branch_ops,
1539 .flags = CLK_SET_RATE_PARENT,
1540 },
1541 },
1542 };
1543
1544 static struct clk_branch npl_tv_clk = {
1545 .halt_reg = 0x0240,
1546 .halt_bit = 26,
1547 .clkr = {
1548 .enable_reg = 0x0124,
1549 .enable_mask = BIT(16),
1550 .hw.init = &(struct clk_init_data){
1551 .parent_names = tv_src_name,
1552 .num_parents = 1,
1553 .name = "npl_tv_clk",
1554 .ops = &clk_branch_ops,
1555 .flags = CLK_SET_RATE_PARENT,
1556 },
1557 },
1558 };
1559
1560 static struct clk_branch hdmi_app_clk = {
1561 .halt_reg = 0x01cc,
1562 .halt_bit = 25,
1563 .clkr = {
1564 .enable_reg = 0x005c,
1565 .enable_mask = BIT(11),
1566 .hw.init = &(struct clk_init_data){
1567 .parent_names = (const char *[]){ "pxo" },
1568 .num_parents = 1,
1569 .name = "hdmi_app_clk",
1570 .ops = &clk_branch_ops,
1571 },
1572 },
1573 };
1574
1575 static struct freq_tbl clk_tbl_vcodec[] = {
1576 F_MN( 27000000, P_PXO, 1, 0),
1577 F_MN( 32000000, P_PLL8, 1, 12),
1578 F_MN( 48000000, P_PLL8, 1, 8),
1579 F_MN( 54860000, P_PLL8, 1, 7),
1580 F_MN( 96000000, P_PLL8, 1, 4),
1581 F_MN(133330000, P_PLL2, 1, 6),
1582 F_MN(200000000, P_PLL2, 1, 4),
1583 F_MN(228570000, P_PLL2, 2, 7),
1584 F_MN(266670000, P_PLL2, 1, 3),
1585 { }
1586 };
1587
1588 static struct clk_dyn_rcg vcodec_src = {
1589 .ns_reg[0] = 0x0100,
1590 .ns_reg[1] = 0x0100,
1591 .md_reg[0] = 0x00fc,
1592 .md_reg[1] = 0x0128,
1593 .bank_reg = 0x00f8,
1594 .mn[0] = {
1595 .mnctr_en_bit = 5,
1596 .mnctr_reset_bit = 31,
1597 .mnctr_mode_shift = 6,
1598 .n_val_shift = 11,
1599 .m_val_shift = 8,
1600 .width = 8,
1601 },
1602 .mn[1] = {
1603 .mnctr_en_bit = 10,
1604 .mnctr_reset_bit = 30,
1605 .mnctr_mode_shift = 11,
1606 .n_val_shift = 19,
1607 .m_val_shift = 8,
1608 .width = 8,
1609 },
1610 .s[0] = {
1611 .src_sel_shift = 27,
1612 .parent_map = mmcc_pxo_pll8_pll2_map,
1613 },
1614 .s[1] = {
1615 .src_sel_shift = 0,
1616 .parent_map = mmcc_pxo_pll8_pll2_map,
1617 },
1618 .mux_sel_bit = 13,
1619 .freq_tbl = clk_tbl_vcodec,
1620 .clkr = {
1621 .enable_reg = 0x00f8,
1622 .enable_mask = BIT(2),
1623 .hw.init = &(struct clk_init_data){
1624 .name = "vcodec_src",
1625 .parent_names = mmcc_pxo_pll8_pll2,
1626 .num_parents = 3,
1627 .ops = &clk_dyn_rcg_ops,
1628 },
1629 },
1630 };
1631
1632 static struct clk_branch vcodec_clk = {
1633 .halt_reg = 0x01d0,
1634 .halt_bit = 29,
1635 .clkr = {
1636 .enable_reg = 0x00f8,
1637 .enable_mask = BIT(0),
1638 .hw.init = &(struct clk_init_data){
1639 .name = "vcodec_clk",
1640 .parent_names = (const char *[]){ "vcodec_src" },
1641 .num_parents = 1,
1642 .ops = &clk_branch_ops,
1643 .flags = CLK_SET_RATE_PARENT,
1644 },
1645 },
1646 };
1647
1648 static struct freq_tbl clk_tbl_vpe[] = {
1649 { 27000000, P_PXO, 1 },
1650 { 34909000, P_PLL8, 11 },
1651 { 38400000, P_PLL8, 10 },
1652 { 64000000, P_PLL8, 6 },
1653 { 76800000, P_PLL8, 5 },
1654 { 96000000, P_PLL8, 4 },
1655 { 100000000, P_PLL2, 8 },
1656 { 160000000, P_PLL2, 5 },
1657 { }
1658 };
1659
1660 static struct clk_rcg vpe_src = {
1661 .ns_reg = 0x0118,
1662 .p = {
1663 .pre_div_shift = 12,
1664 .pre_div_width = 4,
1665 },
1666 .s = {
1667 .src_sel_shift = 0,
1668 .parent_map = mmcc_pxo_pll8_pll2_map,
1669 },
1670 .freq_tbl = clk_tbl_vpe,
1671 .clkr = {
1672 .enable_reg = 0x0110,
1673 .enable_mask = BIT(2),
1674 .hw.init = &(struct clk_init_data){
1675 .name = "vpe_src",
1676 .parent_names = mmcc_pxo_pll8_pll2,
1677 .num_parents = 3,
1678 .ops = &clk_rcg_ops,
1679 },
1680 },
1681 };
1682
1683 static struct clk_branch vpe_clk = {
1684 .halt_reg = 0x01c8,
1685 .halt_bit = 28,
1686 .clkr = {
1687 .enable_reg = 0x0110,
1688 .enable_mask = BIT(0),
1689 .hw.init = &(struct clk_init_data){
1690 .name = "vpe_clk",
1691 .parent_names = (const char *[]){ "vpe_src" },
1692 .num_parents = 1,
1693 .ops = &clk_branch_ops,
1694 .flags = CLK_SET_RATE_PARENT,
1695 },
1696 },
1697 };
1698
1699 static struct freq_tbl clk_tbl_vfe[] = {
1700 { 13960000, P_PLL8, 1, 2, 55 },
1701 { 27000000, P_PXO, 1, 0, 0 },
1702 { 36570000, P_PLL8, 1, 2, 21 },
1703 { 38400000, P_PLL8, 2, 1, 5 },
1704 { 45180000, P_PLL8, 1, 2, 17 },
1705 { 48000000, P_PLL8, 2, 1, 4 },
1706 { 54860000, P_PLL8, 1, 1, 7 },
1707 { 64000000, P_PLL8, 2, 1, 3 },
1708 { 76800000, P_PLL8, 1, 1, 5 },
1709 { 96000000, P_PLL8, 2, 1, 2 },
1710 { 109710000, P_PLL8, 1, 2, 7 },
1711 { 128000000, P_PLL8, 1, 1, 3 },
1712 { 153600000, P_PLL8, 1, 2, 5 },
1713 { 200000000, P_PLL2, 2, 1, 2 },
1714 { 228570000, P_PLL2, 1, 2, 7 },
1715 { 266667000, P_PLL2, 1, 1, 3 },
1716 { 320000000, P_PLL2, 1, 2, 5 },
1717 { }
1718 };
1719
1720 static struct clk_rcg vfe_src = {
1721 .ns_reg = 0x0108,
1722 .mn = {
1723 .mnctr_en_bit = 5,
1724 .mnctr_reset_bit = 7,
1725 .mnctr_mode_shift = 6,
1726 .n_val_shift = 16,
1727 .m_val_shift = 8,
1728 .width = 8,
1729 },
1730 .p = {
1731 .pre_div_shift = 10,
1732 .pre_div_width = 1,
1733 },
1734 .s = {
1735 .src_sel_shift = 0,
1736 .parent_map = mmcc_pxo_pll8_pll2_map,
1737 },
1738 .freq_tbl = clk_tbl_vfe,
1739 .clkr = {
1740 .enable_reg = 0x0104,
1741 .enable_mask = BIT(2),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "vfe_src",
1744 .parent_names = mmcc_pxo_pll8_pll2,
1745 .num_parents = 3,
1746 .ops = &clk_rcg_ops,
1747 },
1748 },
1749 };
1750
1751 static struct clk_branch vfe_clk = {
1752 .halt_reg = 0x01cc,
1753 .halt_bit = 6,
1754 .clkr = {
1755 .enable_reg = 0x0104,
1756 .enable_mask = BIT(0),
1757 .hw.init = &(struct clk_init_data){
1758 .name = "vfe_clk",
1759 .parent_names = (const char *[]){ "vfe_src" },
1760 .num_parents = 1,
1761 .ops = &clk_branch_ops,
1762 .flags = CLK_SET_RATE_PARENT,
1763 },
1764 },
1765 };
1766
1767 static struct clk_branch vfe_csi_clk = {
1768 .halt_reg = 0x01cc,
1769 .halt_bit = 8,
1770 .clkr = {
1771 .enable_reg = 0x0104,
1772 .enable_mask = BIT(12),
1773 .hw.init = &(struct clk_init_data){
1774 .parent_names = (const char *[]){ "vfe_src" },
1775 .num_parents = 1,
1776 .name = "vfe_csi_clk",
1777 .ops = &clk_branch_ops,
1778 .flags = CLK_SET_RATE_PARENT,
1779 },
1780 },
1781 };
1782
1783 static struct clk_branch gmem_axi_clk = {
1784 .halt_reg = 0x01d8,
1785 .halt_bit = 6,
1786 .clkr = {
1787 .enable_reg = 0x0018,
1788 .enable_mask = BIT(24),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "gmem_axi_clk",
1791 .ops = &clk_branch_ops,
1792 .flags = CLK_IS_ROOT,
1793 },
1794 },
1795 };
1796
1797 static struct clk_branch ijpeg_axi_clk = {
1798 .hwcg_reg = 0x0018,
1799 .hwcg_bit = 11,
1800 .halt_reg = 0x01d8,
1801 .halt_bit = 4,
1802 .clkr = {
1803 .enable_reg = 0x0018,
1804 .enable_mask = BIT(21),
1805 .hw.init = &(struct clk_init_data){
1806 .name = "ijpeg_axi_clk",
1807 .ops = &clk_branch_ops,
1808 .flags = CLK_IS_ROOT,
1809 },
1810 },
1811 };
1812
1813 static struct clk_branch mmss_imem_axi_clk = {
1814 .hwcg_reg = 0x0018,
1815 .hwcg_bit = 15,
1816 .halt_reg = 0x01d8,
1817 .halt_bit = 7,
1818 .clkr = {
1819 .enable_reg = 0x0018,
1820 .enable_mask = BIT(22),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "mmss_imem_axi_clk",
1823 .ops = &clk_branch_ops,
1824 .flags = CLK_IS_ROOT,
1825 },
1826 },
1827 };
1828
1829 static struct clk_branch jpegd_axi_clk = {
1830 .halt_reg = 0x01d8,
1831 .halt_bit = 5,
1832 .clkr = {
1833 .enable_reg = 0x0018,
1834 .enable_mask = BIT(25),
1835 .hw.init = &(struct clk_init_data){
1836 .name = "jpegd_axi_clk",
1837 .ops = &clk_branch_ops,
1838 .flags = CLK_IS_ROOT,
1839 },
1840 },
1841 };
1842
1843 static struct clk_branch vcodec_axi_b_clk = {
1844 .hwcg_reg = 0x0114,
1845 .hwcg_bit = 22,
1846 .halt_reg = 0x01e8,
1847 .halt_bit = 25,
1848 .clkr = {
1849 .enable_reg = 0x0114,
1850 .enable_mask = BIT(23),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "vcodec_axi_b_clk",
1853 .ops = &clk_branch_ops,
1854 .flags = CLK_IS_ROOT,
1855 },
1856 },
1857 };
1858
1859 static struct clk_branch vcodec_axi_a_clk = {
1860 .hwcg_reg = 0x0114,
1861 .hwcg_bit = 24,
1862 .halt_reg = 0x01e8,
1863 .halt_bit = 26,
1864 .clkr = {
1865 .enable_reg = 0x0114,
1866 .enable_mask = BIT(25),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "vcodec_axi_a_clk",
1869 .ops = &clk_branch_ops,
1870 .flags = CLK_IS_ROOT,
1871 },
1872 },
1873 };
1874
1875 static struct clk_branch vcodec_axi_clk = {
1876 .hwcg_reg = 0x0018,
1877 .hwcg_bit = 13,
1878 .halt_reg = 0x01d8,
1879 .halt_bit = 3,
1880 .clkr = {
1881 .enable_reg = 0x0018,
1882 .enable_mask = BIT(19),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "vcodec_axi_clk",
1885 .ops = &clk_branch_ops,
1886 .flags = CLK_IS_ROOT,
1887 },
1888 },
1889 };
1890
1891 static struct clk_branch vfe_axi_clk = {
1892 .halt_reg = 0x01d8,
1893 .halt_bit = 0,
1894 .clkr = {
1895 .enable_reg = 0x0018,
1896 .enable_mask = BIT(18),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "vfe_axi_clk",
1899 .ops = &clk_branch_ops,
1900 .flags = CLK_IS_ROOT,
1901 },
1902 },
1903 };
1904
1905 static struct clk_branch mdp_axi_clk = {
1906 .hwcg_reg = 0x0018,
1907 .hwcg_bit = 16,
1908 .halt_reg = 0x01d8,
1909 .halt_bit = 8,
1910 .clkr = {
1911 .enable_reg = 0x0018,
1912 .enable_mask = BIT(23),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "mdp_axi_clk",
1915 .ops = &clk_branch_ops,
1916 .flags = CLK_IS_ROOT,
1917 },
1918 },
1919 };
1920
1921 static struct clk_branch rot_axi_clk = {
1922 .hwcg_reg = 0x0020,
1923 .hwcg_bit = 25,
1924 .halt_reg = 0x01d8,
1925 .halt_bit = 2,
1926 .clkr = {
1927 .enable_reg = 0x0020,
1928 .enable_mask = BIT(24),
1929 .hw.init = &(struct clk_init_data){
1930 .name = "rot_axi_clk",
1931 .ops = &clk_branch_ops,
1932 .flags = CLK_IS_ROOT,
1933 },
1934 },
1935 };
1936
1937 static struct clk_branch vcap_axi_clk = {
1938 .halt_reg = 0x0240,
1939 .halt_bit = 20,
1940 .hwcg_reg = 0x0244,
1941 .hwcg_bit = 11,
1942 .clkr = {
1943 .enable_reg = 0x0244,
1944 .enable_mask = BIT(12),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "vcap_axi_clk",
1947 .ops = &clk_branch_ops,
1948 .flags = CLK_IS_ROOT,
1949 },
1950 },
1951 };
1952
1953 static struct clk_branch vpe_axi_clk = {
1954 .hwcg_reg = 0x0020,
1955 .hwcg_bit = 27,
1956 .halt_reg = 0x01d8,
1957 .halt_bit = 1,
1958 .clkr = {
1959 .enable_reg = 0x0020,
1960 .enable_mask = BIT(26),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "vpe_axi_clk",
1963 .ops = &clk_branch_ops,
1964 .flags = CLK_IS_ROOT,
1965 },
1966 },
1967 };
1968
1969 static struct clk_branch gfx3d_axi_clk = {
1970 .hwcg_reg = 0x0244,
1971 .hwcg_bit = 24,
1972 .halt_reg = 0x0240,
1973 .halt_bit = 30,
1974 .clkr = {
1975 .enable_reg = 0x0244,
1976 .enable_mask = BIT(25),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "gfx3d_axi_clk",
1979 .ops = &clk_branch_ops,
1980 .flags = CLK_IS_ROOT,
1981 },
1982 },
1983 };
1984
1985 static struct clk_branch amp_ahb_clk = {
1986 .halt_reg = 0x01dc,
1987 .halt_bit = 18,
1988 .clkr = {
1989 .enable_reg = 0x0008,
1990 .enable_mask = BIT(24),
1991 .hw.init = &(struct clk_init_data){
1992 .name = "amp_ahb_clk",
1993 .ops = &clk_branch_ops,
1994 .flags = CLK_IS_ROOT,
1995 },
1996 },
1997 };
1998
1999 static struct clk_branch csi_ahb_clk = {
2000 .halt_reg = 0x01dc,
2001 .halt_bit = 16,
2002 .clkr = {
2003 .enable_reg = 0x0008,
2004 .enable_mask = BIT(7),
2005 .hw.init = &(struct clk_init_data){
2006 .name = "csi_ahb_clk",
2007 .ops = &clk_branch_ops,
2008 .flags = CLK_IS_ROOT
2009 },
2010 },
2011 };
2012
2013 static struct clk_branch dsi_m_ahb_clk = {
2014 .halt_reg = 0x01dc,
2015 .halt_bit = 19,
2016 .clkr = {
2017 .enable_reg = 0x0008,
2018 .enable_mask = BIT(9),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "dsi_m_ahb_clk",
2021 .ops = &clk_branch_ops,
2022 .flags = CLK_IS_ROOT,
2023 },
2024 },
2025 };
2026
2027 static struct clk_branch dsi_s_ahb_clk = {
2028 .hwcg_reg = 0x0038,
2029 .hwcg_bit = 20,
2030 .halt_reg = 0x01dc,
2031 .halt_bit = 21,
2032 .clkr = {
2033 .enable_reg = 0x0008,
2034 .enable_mask = BIT(18),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "dsi_s_ahb_clk",
2037 .ops = &clk_branch_ops,
2038 .flags = CLK_IS_ROOT,
2039 },
2040 },
2041 };
2042
2043 static struct clk_branch dsi2_m_ahb_clk = {
2044 .halt_reg = 0x01d8,
2045 .halt_bit = 18,
2046 .clkr = {
2047 .enable_reg = 0x0008,
2048 .enable_mask = BIT(17),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "dsi2_m_ahb_clk",
2051 .ops = &clk_branch_ops,
2052 .flags = CLK_IS_ROOT
2053 },
2054 },
2055 };
2056
2057 static struct clk_branch dsi2_s_ahb_clk = {
2058 .hwcg_reg = 0x0038,
2059 .hwcg_bit = 15,
2060 .halt_reg = 0x01dc,
2061 .halt_bit = 20,
2062 .clkr = {
2063 .enable_reg = 0x0008,
2064 .enable_mask = BIT(22),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "dsi2_s_ahb_clk",
2067 .ops = &clk_branch_ops,
2068 .flags = CLK_IS_ROOT,
2069 },
2070 },
2071 };
2072
2073 static struct clk_rcg dsi1_src = {
2074 .ns_reg = 0x0054,
2075 .md_reg = 0x0050,
2076 .mn = {
2077 .mnctr_en_bit = 5,
2078 .mnctr_reset_bit = 7,
2079 .mnctr_mode_shift = 6,
2080 .n_val_shift = 24,
2081 .m_val_shift = 8,
2082 .width = 8,
2083 },
2084 .p = {
2085 .pre_div_shift = 14,
2086 .pre_div_width = 2,
2087 },
2088 .s = {
2089 .src_sel_shift = 0,
2090 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2091 },
2092 .clkr = {
2093 .enable_reg = 0x004c,
2094 .enable_mask = BIT(2),
2095 .hw.init = &(struct clk_init_data){
2096 .name = "dsi1_src",
2097 .parent_names = mmcc_pxo_dsi2_dsi1,
2098 .num_parents = 3,
2099 .ops = &clk_rcg_bypass2_ops,
2100 .flags = CLK_SET_RATE_PARENT,
2101 },
2102 },
2103 };
2104
2105 static struct clk_branch dsi1_clk = {
2106 .halt_reg = 0x01d0,
2107 .halt_bit = 2,
2108 .clkr = {
2109 .enable_reg = 0x004c,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "dsi1_clk",
2113 .parent_names = (const char *[]){ "dsi1_src" },
2114 .num_parents = 1,
2115 .ops = &clk_branch_ops,
2116 .flags = CLK_SET_RATE_PARENT,
2117 },
2118 },
2119 };
2120
2121 static struct clk_rcg dsi2_src = {
2122 .ns_reg = 0x012c,
2123 .md_reg = 0x00a8,
2124 .mn = {
2125 .mnctr_en_bit = 5,
2126 .mnctr_reset_bit = 7,
2127 .mnctr_mode_shift = 6,
2128 .n_val_shift = 24,
2129 .m_val_shift = 8,
2130 .width = 8,
2131 },
2132 .p = {
2133 .pre_div_shift = 14,
2134 .pre_div_width = 2,
2135 },
2136 .s = {
2137 .src_sel_shift = 0,
2138 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2139 },
2140 .clkr = {
2141 .enable_reg = 0x003c,
2142 .enable_mask = BIT(2),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "dsi2_src",
2145 .parent_names = mmcc_pxo_dsi2_dsi1,
2146 .num_parents = 3,
2147 .ops = &clk_rcg_bypass2_ops,
2148 .flags = CLK_SET_RATE_PARENT,
2149 },
2150 },
2151 };
2152
2153 static struct clk_branch dsi2_clk = {
2154 .halt_reg = 0x01d0,
2155 .halt_bit = 20,
2156 .clkr = {
2157 .enable_reg = 0x003c,
2158 .enable_mask = BIT(0),
2159 .hw.init = &(struct clk_init_data){
2160 .name = "dsi2_clk",
2161 .parent_names = (const char *[]){ "dsi2_src" },
2162 .num_parents = 1,
2163 .ops = &clk_branch_ops,
2164 .flags = CLK_SET_RATE_PARENT,
2165 },
2166 },
2167 };
2168
2169 static struct clk_rcg dsi1_byte_src = {
2170 .ns_reg = 0x00b0,
2171 .p = {
2172 .pre_div_shift = 12,
2173 .pre_div_width = 4,
2174 },
2175 .s = {
2176 .src_sel_shift = 0,
2177 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2178 },
2179 .clkr = {
2180 .enable_reg = 0x0090,
2181 .enable_mask = BIT(2),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "dsi1_byte_src",
2184 .parent_names = mmcc_pxo_dsi1_dsi2_byte,
2185 .num_parents = 3,
2186 .ops = &clk_rcg_bypass2_ops,
2187 .flags = CLK_SET_RATE_PARENT,
2188 },
2189 },
2190 };
2191
2192 static struct clk_branch dsi1_byte_clk = {
2193 .halt_reg = 0x01cc,
2194 .halt_bit = 21,
2195 .clkr = {
2196 .enable_reg = 0x0090,
2197 .enable_mask = BIT(0),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "dsi1_byte_clk",
2200 .parent_names = (const char *[]){ "dsi1_byte_src" },
2201 .num_parents = 1,
2202 .ops = &clk_branch_ops,
2203 .flags = CLK_SET_RATE_PARENT,
2204 },
2205 },
2206 };
2207
2208 static struct clk_rcg dsi2_byte_src = {
2209 .ns_reg = 0x012c,
2210 .p = {
2211 .pre_div_shift = 12,
2212 .pre_div_width = 4,
2213 },
2214 .s = {
2215 .src_sel_shift = 0,
2216 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2217 },
2218 .clkr = {
2219 .enable_reg = 0x0130,
2220 .enable_mask = BIT(2),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "dsi2_byte_src",
2223 .parent_names = mmcc_pxo_dsi1_dsi2_byte,
2224 .num_parents = 3,
2225 .ops = &clk_rcg_bypass2_ops,
2226 .flags = CLK_SET_RATE_PARENT,
2227 },
2228 },
2229 };
2230
2231 static struct clk_branch dsi2_byte_clk = {
2232 .halt_reg = 0x01cc,
2233 .halt_bit = 20,
2234 .clkr = {
2235 .enable_reg = 0x00b4,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "dsi2_byte_clk",
2239 .parent_names = (const char *[]){ "dsi2_byte_src" },
2240 .num_parents = 1,
2241 .ops = &clk_branch_ops,
2242 .flags = CLK_SET_RATE_PARENT,
2243 },
2244 },
2245 };
2246
2247 static struct clk_rcg dsi1_esc_src = {
2248 .ns_reg = 0x0011c,
2249 .p = {
2250 .pre_div_shift = 12,
2251 .pre_div_width = 4,
2252 },
2253 .s = {
2254 .src_sel_shift = 0,
2255 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2256 },
2257 .clkr = {
2258 .enable_reg = 0x00cc,
2259 .enable_mask = BIT(2),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "dsi1_esc_src",
2262 .parent_names = mmcc_pxo_dsi1_dsi2_byte,
2263 .num_parents = 3,
2264 .ops = &clk_rcg_esc_ops,
2265 },
2266 },
2267 };
2268
2269 static struct clk_branch dsi1_esc_clk = {
2270 .halt_reg = 0x01e8,
2271 .halt_bit = 1,
2272 .clkr = {
2273 .enable_reg = 0x00cc,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "dsi1_esc_clk",
2277 .parent_names = (const char *[]){ "dsi1_esc_src" },
2278 .num_parents = 1,
2279 .ops = &clk_branch_ops,
2280 .flags = CLK_SET_RATE_PARENT,
2281 },
2282 },
2283 };
2284
2285 static struct clk_rcg dsi2_esc_src = {
2286 .ns_reg = 0x0150,
2287 .p = {
2288 .pre_div_shift = 12,
2289 .pre_div_width = 4,
2290 },
2291 .s = {
2292 .src_sel_shift = 0,
2293 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2294 },
2295 .clkr = {
2296 .enable_reg = 0x013c,
2297 .enable_mask = BIT(2),
2298 .hw.init = &(struct clk_init_data){
2299 .name = "dsi2_esc_src",
2300 .parent_names = mmcc_pxo_dsi1_dsi2_byte,
2301 .num_parents = 3,
2302 .ops = &clk_rcg_esc_ops,
2303 },
2304 },
2305 };
2306
2307 static struct clk_branch dsi2_esc_clk = {
2308 .halt_reg = 0x01e8,
2309 .halt_bit = 3,
2310 .clkr = {
2311 .enable_reg = 0x013c,
2312 .enable_mask = BIT(0),
2313 .hw.init = &(struct clk_init_data){
2314 .name = "dsi2_esc_clk",
2315 .parent_names = (const char *[]){ "dsi2_esc_src" },
2316 .num_parents = 1,
2317 .ops = &clk_branch_ops,
2318 .flags = CLK_SET_RATE_PARENT,
2319 },
2320 },
2321 };
2322
2323 static struct clk_rcg dsi1_pixel_src = {
2324 .ns_reg = 0x0138,
2325 .md_reg = 0x0134,
2326 .mn = {
2327 .mnctr_en_bit = 5,
2328 .mnctr_reset_bit = 7,
2329 .mnctr_mode_shift = 6,
2330 .n_val_shift = 16,
2331 .m_val_shift = 8,
2332 .width = 8,
2333 },
2334 .p = {
2335 .pre_div_shift = 12,
2336 .pre_div_width = 4,
2337 },
2338 .s = {
2339 .src_sel_shift = 0,
2340 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2341 },
2342 .clkr = {
2343 .enable_reg = 0x0130,
2344 .enable_mask = BIT(2),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "dsi1_pixel_src",
2347 .parent_names = mmcc_pxo_dsi2_dsi1,
2348 .num_parents = 3,
2349 .ops = &clk_rcg_pixel_ops,
2350 },
2351 },
2352 };
2353
2354 static struct clk_branch dsi1_pixel_clk = {
2355 .halt_reg = 0x01d0,
2356 .halt_bit = 6,
2357 .clkr = {
2358 .enable_reg = 0x0130,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(struct clk_init_data){
2361 .name = "mdp_pclk1_clk",
2362 .parent_names = (const char *[]){ "dsi1_pixel_src" },
2363 .num_parents = 1,
2364 .ops = &clk_branch_ops,
2365 .flags = CLK_SET_RATE_PARENT,
2366 },
2367 },
2368 };
2369
2370 static struct clk_rcg dsi2_pixel_src = {
2371 .ns_reg = 0x00e4,
2372 .md_reg = 0x00b8,
2373 .mn = {
2374 .mnctr_en_bit = 5,
2375 .mnctr_reset_bit = 7,
2376 .mnctr_mode_shift = 6,
2377 .n_val_shift = 16,
2378 .m_val_shift = 8,
2379 .width = 8,
2380 },
2381 .p = {
2382 .pre_div_shift = 12,
2383 .pre_div_width = 4,
2384 },
2385 .s = {
2386 .src_sel_shift = 0,
2387 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2388 },
2389 .clkr = {
2390 .enable_reg = 0x0094,
2391 .enable_mask = BIT(2),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "dsi2_pixel_src",
2394 .parent_names = mmcc_pxo_dsi2_dsi1,
2395 .num_parents = 3,
2396 .ops = &clk_rcg_pixel_ops,
2397 },
2398 },
2399 };
2400
2401 static struct clk_branch dsi2_pixel_clk = {
2402 .halt_reg = 0x01d0,
2403 .halt_bit = 19,
2404 .clkr = {
2405 .enable_reg = 0x0094,
2406 .enable_mask = BIT(0),
2407 .hw.init = &(struct clk_init_data){
2408 .name = "mdp_pclk2_clk",
2409 .parent_names = (const char *[]){ "dsi2_pixel_src" },
2410 .num_parents = 1,
2411 .ops = &clk_branch_ops,
2412 .flags = CLK_SET_RATE_PARENT,
2413 },
2414 },
2415 };
2416
2417 static struct clk_branch gfx2d0_ahb_clk = {
2418 .hwcg_reg = 0x0038,
2419 .hwcg_bit = 28,
2420 .halt_reg = 0x01dc,
2421 .halt_bit = 2,
2422 .clkr = {
2423 .enable_reg = 0x0008,
2424 .enable_mask = BIT(19),
2425 .hw.init = &(struct clk_init_data){
2426 .name = "gfx2d0_ahb_clk",
2427 .ops = &clk_branch_ops,
2428 .flags = CLK_IS_ROOT,
2429 },
2430 },
2431 };
2432
2433 static struct clk_branch gfx2d1_ahb_clk = {
2434 .hwcg_reg = 0x0038,
2435 .hwcg_bit = 29,
2436 .halt_reg = 0x01dc,
2437 .halt_bit = 3,
2438 .clkr = {
2439 .enable_reg = 0x0008,
2440 .enable_mask = BIT(2),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "gfx2d1_ahb_clk",
2443 .ops = &clk_branch_ops,
2444 .flags = CLK_IS_ROOT,
2445 },
2446 },
2447 };
2448
2449 static struct clk_branch gfx3d_ahb_clk = {
2450 .hwcg_reg = 0x0038,
2451 .hwcg_bit = 27,
2452 .halt_reg = 0x01dc,
2453 .halt_bit = 4,
2454 .clkr = {
2455 .enable_reg = 0x0008,
2456 .enable_mask = BIT(3),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gfx3d_ahb_clk",
2459 .ops = &clk_branch_ops,
2460 .flags = CLK_IS_ROOT,
2461 },
2462 },
2463 };
2464
2465 static struct clk_branch hdmi_m_ahb_clk = {
2466 .hwcg_reg = 0x0038,
2467 .hwcg_bit = 21,
2468 .halt_reg = 0x01dc,
2469 .halt_bit = 5,
2470 .clkr = {
2471 .enable_reg = 0x0008,
2472 .enable_mask = BIT(14),
2473 .hw.init = &(struct clk_init_data){
2474 .name = "hdmi_m_ahb_clk",
2475 .ops = &clk_branch_ops,
2476 .flags = CLK_IS_ROOT,
2477 },
2478 },
2479 };
2480
2481 static struct clk_branch hdmi_s_ahb_clk = {
2482 .hwcg_reg = 0x0038,
2483 .hwcg_bit = 22,
2484 .halt_reg = 0x01dc,
2485 .halt_bit = 6,
2486 .clkr = {
2487 .enable_reg = 0x0008,
2488 .enable_mask = BIT(4),
2489 .hw.init = &(struct clk_init_data){
2490 .name = "hdmi_s_ahb_clk",
2491 .ops = &clk_branch_ops,
2492 .flags = CLK_IS_ROOT,
2493 },
2494 },
2495 };
2496
2497 static struct clk_branch ijpeg_ahb_clk = {
2498 .halt_reg = 0x01dc,
2499 .halt_bit = 9,
2500 .clkr = {
2501 .enable_reg = 0x0008,
2502 .enable_mask = BIT(5),
2503 .hw.init = &(struct clk_init_data){
2504 .name = "ijpeg_ahb_clk",
2505 .ops = &clk_branch_ops,
2506 .flags = CLK_IS_ROOT
2507 },
2508 },
2509 };
2510
2511 static struct clk_branch mmss_imem_ahb_clk = {
2512 .hwcg_reg = 0x0038,
2513 .hwcg_bit = 12,
2514 .halt_reg = 0x01dc,
2515 .halt_bit = 10,
2516 .clkr = {
2517 .enable_reg = 0x0008,
2518 .enable_mask = BIT(6),
2519 .hw.init = &(struct clk_init_data){
2520 .name = "mmss_imem_ahb_clk",
2521 .ops = &clk_branch_ops,
2522 .flags = CLK_IS_ROOT
2523 },
2524 },
2525 };
2526
2527 static struct clk_branch jpegd_ahb_clk = {
2528 .halt_reg = 0x01dc,
2529 .halt_bit = 7,
2530 .clkr = {
2531 .enable_reg = 0x0008,
2532 .enable_mask = BIT(21),
2533 .hw.init = &(struct clk_init_data){
2534 .name = "jpegd_ahb_clk",
2535 .ops = &clk_branch_ops,
2536 .flags = CLK_IS_ROOT,
2537 },
2538 },
2539 };
2540
2541 static struct clk_branch mdp_ahb_clk = {
2542 .halt_reg = 0x01dc,
2543 .halt_bit = 11,
2544 .clkr = {
2545 .enable_reg = 0x0008,
2546 .enable_mask = BIT(10),
2547 .hw.init = &(struct clk_init_data){
2548 .name = "mdp_ahb_clk",
2549 .ops = &clk_branch_ops,
2550 .flags = CLK_IS_ROOT,
2551 },
2552 },
2553 };
2554
2555 static struct clk_branch rot_ahb_clk = {
2556 .halt_reg = 0x01dc,
2557 .halt_bit = 13,
2558 .clkr = {
2559 .enable_reg = 0x0008,
2560 .enable_mask = BIT(12),
2561 .hw.init = &(struct clk_init_data){
2562 .name = "rot_ahb_clk",
2563 .ops = &clk_branch_ops,
2564 .flags = CLK_IS_ROOT
2565 },
2566 },
2567 };
2568
2569 static struct clk_branch smmu_ahb_clk = {
2570 .hwcg_reg = 0x0008,
2571 .hwcg_bit = 26,
2572 .halt_reg = 0x01dc,
2573 .halt_bit = 22,
2574 .clkr = {
2575 .enable_reg = 0x0008,
2576 .enable_mask = BIT(15),
2577 .hw.init = &(struct clk_init_data){
2578 .name = "smmu_ahb_clk",
2579 .ops = &clk_branch_ops,
2580 .flags = CLK_IS_ROOT,
2581 },
2582 },
2583 };
2584
2585 static struct clk_branch tv_enc_ahb_clk = {
2586 .halt_reg = 0x01dc,
2587 .halt_bit = 23,
2588 .clkr = {
2589 .enable_reg = 0x0008,
2590 .enable_mask = BIT(25),
2591 .hw.init = &(struct clk_init_data){
2592 .name = "tv_enc_ahb_clk",
2593 .ops = &clk_branch_ops,
2594 .flags = CLK_IS_ROOT,
2595 },
2596 },
2597 };
2598
2599 static struct clk_branch vcap_ahb_clk = {
2600 .halt_reg = 0x0240,
2601 .halt_bit = 23,
2602 .clkr = {
2603 .enable_reg = 0x0248,
2604 .enable_mask = BIT(1),
2605 .hw.init = &(struct clk_init_data){
2606 .name = "vcap_ahb_clk",
2607 .ops = &clk_branch_ops,
2608 .flags = CLK_IS_ROOT,
2609 },
2610 },
2611 };
2612
2613 static struct clk_branch vcodec_ahb_clk = {
2614 .hwcg_reg = 0x0038,
2615 .hwcg_bit = 26,
2616 .halt_reg = 0x01dc,
2617 .halt_bit = 12,
2618 .clkr = {
2619 .enable_reg = 0x0008,
2620 .enable_mask = BIT(11),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "vcodec_ahb_clk",
2623 .ops = &clk_branch_ops,
2624 .flags = CLK_IS_ROOT,
2625 },
2626 },
2627 };
2628
2629 static struct clk_branch vfe_ahb_clk = {
2630 .halt_reg = 0x01dc,
2631 .halt_bit = 14,
2632 .clkr = {
2633 .enable_reg = 0x0008,
2634 .enable_mask = BIT(13),
2635 .hw.init = &(struct clk_init_data){
2636 .name = "vfe_ahb_clk",
2637 .ops = &clk_branch_ops,
2638 .flags = CLK_IS_ROOT,
2639 },
2640 },
2641 };
2642
2643 static struct clk_branch vpe_ahb_clk = {
2644 .halt_reg = 0x01dc,
2645 .halt_bit = 15,
2646 .clkr = {
2647 .enable_reg = 0x0008,
2648 .enable_mask = BIT(16),
2649 .hw.init = &(struct clk_init_data){
2650 .name = "vpe_ahb_clk",
2651 .ops = &clk_branch_ops,
2652 .flags = CLK_IS_ROOT,
2653 },
2654 },
2655 };
2656
2657 static struct clk_regmap *mmcc_msm8960_clks[] = {
2658 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2659 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2660 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2661 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2662 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2663 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2664 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2665 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2666 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2667 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2668 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2669 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2670 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2671 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2672 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2673 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2674 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2675 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2676 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2677 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2678 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2679 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2680 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2681 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2682 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2683 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2684 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2685 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2686 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2687 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2688 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2689 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2690 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2691 [CSI0_SRC] = &csi0_src.clkr,
2692 [CSI0_CLK] = &csi0_clk.clkr,
2693 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2694 [CSI1_SRC] = &csi1_src.clkr,
2695 [CSI1_CLK] = &csi1_clk.clkr,
2696 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2697 [CSI2_SRC] = &csi2_src.clkr,
2698 [CSI2_CLK] = &csi2_clk.clkr,
2699 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2700 [DSI_SRC] = &dsi1_src.clkr,
2701 [DSI_CLK] = &dsi1_clk.clkr,
2702 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2703 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2704 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2705 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2706 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2707 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2708 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2709 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2710 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2711 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2712 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2713 [GFX3D_SRC] = &gfx3d_src.clkr,
2714 [GFX3D_CLK] = &gfx3d_clk.clkr,
2715 [IJPEG_SRC] = &ijpeg_src.clkr,
2716 [IJPEG_CLK] = &ijpeg_clk.clkr,
2717 [JPEGD_SRC] = &jpegd_src.clkr,
2718 [JPEGD_CLK] = &jpegd_clk.clkr,
2719 [MDP_SRC] = &mdp_src.clkr,
2720 [MDP_CLK] = &mdp_clk.clkr,
2721 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2722 [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2723 [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2724 [DSI2_SRC] = &dsi2_src.clkr,
2725 [DSI2_CLK] = &dsi2_clk.clkr,
2726 [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2727 [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2728 [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2729 [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2730 [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
2731 [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
2732 [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
2733 [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
2734 [ROT_SRC] = &rot_src.clkr,
2735 [ROT_CLK] = &rot_clk.clkr,
2736 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2737 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2738 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2739 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2740 [TV_SRC] = &tv_src.clkr,
2741 [VCODEC_SRC] = &vcodec_src.clkr,
2742 [VCODEC_CLK] = &vcodec_clk.clkr,
2743 [VFE_SRC] = &vfe_src.clkr,
2744 [VFE_CLK] = &vfe_clk.clkr,
2745 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2746 [VPE_SRC] = &vpe_src.clkr,
2747 [VPE_CLK] = &vpe_clk.clkr,
2748 [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
2749 [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
2750 [CAMCLK0_SRC] = &camclk0_src.clkr,
2751 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2752 [CAMCLK1_SRC] = &camclk1_src.clkr,
2753 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2754 [CAMCLK2_SRC] = &camclk2_src.clkr,
2755 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2756 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2757 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2758 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2759 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2760 [PLL2] = &pll2.clkr,
2761 };
2762
2763 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2764 [VPE_AXI_RESET] = { 0x0208, 15 },
2765 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2766 [MPD_AXI_RESET] = { 0x0208, 13 },
2767 [VFE_AXI_RESET] = { 0x0208, 9 },
2768 [SP_AXI_RESET] = { 0x0208, 8 },
2769 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2770 [ROT_AXI_RESET] = { 0x0208, 6 },
2771 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2772 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2773 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2774 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2775 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2776 [FAB_S0_AXI_RESET] = { 0x0208 },
2777 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2778 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2779 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2780 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2781 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2782 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2783 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2784 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2785 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2786 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2787 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2788 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2789 [APU_AHB_RESET] = { 0x020c, 18 },
2790 [CSI_AHB_RESET] = { 0x020c, 17 },
2791 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2792 [VPE_AHB_RESET] = { 0x020c, 14 },
2793 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2794 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2795 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2796 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2797 [HDMI_AHB_RESET] = { 0x020c, 9 },
2798 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2799 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2800 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2801 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2802 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2803 [MDP_AHB_RESET] = { 0x020c, 3 },
2804 [ROT_AHB_RESET] = { 0x020c, 2 },
2805 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2806 [VFE_AHB_RESET] = { 0x020c, 0 },
2807 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2808 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2809 [CSIPHY2_RESET] = { 0x0210, 29 },
2810 [CSI_PIX1_RESET] = { 0x0210, 28 },
2811 [CSIPHY0_RESET] = { 0x0210, 27 },
2812 [CSIPHY1_RESET] = { 0x0210, 26 },
2813 [DSI2_RESET] = { 0x0210, 25 },
2814 [VFE_CSI_RESET] = { 0x0210, 24 },
2815 [MDP_RESET] = { 0x0210, 21 },
2816 [AMP_RESET] = { 0x0210, 20 },
2817 [JPEGD_RESET] = { 0x0210, 19 },
2818 [CSI1_RESET] = { 0x0210, 18 },
2819 [VPE_RESET] = { 0x0210, 17 },
2820 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2821 [VFE_RESET] = { 0x0210, 15 },
2822 [GFX2D0_RESET] = { 0x0210, 14 },
2823 [GFX2D1_RESET] = { 0x0210, 13 },
2824 [GFX3D_RESET] = { 0x0210, 12 },
2825 [HDMI_RESET] = { 0x0210, 11 },
2826 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2827 [IJPEG_RESET] = { 0x0210, 9 },
2828 [CSI0_RESET] = { 0x0210, 8 },
2829 [DSI_RESET] = { 0x0210, 7 },
2830 [VCODEC_RESET] = { 0x0210, 6 },
2831 [MDP_TV_RESET] = { 0x0210, 4 },
2832 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2833 [ROT_RESET] = { 0x0210, 2 },
2834 [TV_HDMI_RESET] = { 0x0210, 1 },
2835 [TV_ENC_RESET] = { 0x0210 },
2836 [CSI2_RESET] = { 0x0214, 2 },
2837 [CSI_RDI1_RESET] = { 0x0214, 1 },
2838 [CSI_RDI2_RESET] = { 0x0214 },
2839 };
2840
2841 static struct clk_regmap *mmcc_apq8064_clks[] = {
2842 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2843 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2844 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2845 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2846 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2847 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2848 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2849 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2850 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2851 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2852 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2853 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2854 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2855 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2856 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2857 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2858 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2859 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2860 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2861 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2862 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2863 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2864 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2865 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2866 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2867 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2868 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2869 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2870 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2871 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2872 [CSI0_SRC] = &csi0_src.clkr,
2873 [CSI0_CLK] = &csi0_clk.clkr,
2874 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2875 [CSI1_SRC] = &csi1_src.clkr,
2876 [CSI1_CLK] = &csi1_clk.clkr,
2877 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2878 [CSI2_SRC] = &csi2_src.clkr,
2879 [CSI2_CLK] = &csi2_clk.clkr,
2880 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2881 [DSI_SRC] = &dsi1_src.clkr,
2882 [DSI_CLK] = &dsi1_clk.clkr,
2883 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2884 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2885 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2886 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2887 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2888 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2889 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2890 [GFX3D_SRC] = &gfx3d_src.clkr,
2891 [GFX3D_CLK] = &gfx3d_clk.clkr,
2892 [IJPEG_SRC] = &ijpeg_src.clkr,
2893 [IJPEG_CLK] = &ijpeg_clk.clkr,
2894 [JPEGD_SRC] = &jpegd_src.clkr,
2895 [JPEGD_CLK] = &jpegd_clk.clkr,
2896 [MDP_SRC] = &mdp_src.clkr,
2897 [MDP_CLK] = &mdp_clk.clkr,
2898 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2899 [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2900 [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2901 [DSI2_SRC] = &dsi2_src.clkr,
2902 [DSI2_CLK] = &dsi2_clk.clkr,
2903 [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2904 [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2905 [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2906 [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2907 [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
2908 [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
2909 [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
2910 [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
2911 [ROT_SRC] = &rot_src.clkr,
2912 [ROT_CLK] = &rot_clk.clkr,
2913 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2914 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2915 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2916 [TV_SRC] = &tv_src.clkr,
2917 [VCODEC_SRC] = &vcodec_src.clkr,
2918 [VCODEC_CLK] = &vcodec_clk.clkr,
2919 [VFE_SRC] = &vfe_src.clkr,
2920 [VFE_CLK] = &vfe_clk.clkr,
2921 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2922 [VPE_SRC] = &vpe_src.clkr,
2923 [VPE_CLK] = &vpe_clk.clkr,
2924 [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
2925 [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
2926 [CAMCLK0_SRC] = &camclk0_src.clkr,
2927 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2928 [CAMCLK1_SRC] = &camclk1_src.clkr,
2929 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2930 [CAMCLK2_SRC] = &camclk2_src.clkr,
2931 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2932 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2933 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2934 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2935 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2936 [PLL2] = &pll2.clkr,
2937 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2938 [NPL_TV_CLK] = &npl_tv_clk.clkr,
2939 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2940 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2941 [VCAP_SRC] = &vcap_src.clkr,
2942 [VCAP_CLK] = &vcap_clk.clkr,
2943 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2944 [PLL15] = &pll15.clkr,
2945 };
2946
2947 static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2948 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2949 [VCAP_AXI_RESET] = { 0x0208, 16 },
2950 [VPE_AXI_RESET] = { 0x0208, 15 },
2951 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2952 [MPD_AXI_RESET] = { 0x0208, 13 },
2953 [VFE_AXI_RESET] = { 0x0208, 9 },
2954 [SP_AXI_RESET] = { 0x0208, 8 },
2955 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2956 [ROT_AXI_RESET] = { 0x0208, 6 },
2957 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2958 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2959 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2960 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2961 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2962 [FAB_S0_AXI_RESET] = { 0x0208 },
2963 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2964 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2965 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2966 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2967 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2968 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2969 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2970 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2971 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2972 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2973 [APU_AHB_RESET] = { 0x020c, 18 },
2974 [CSI_AHB_RESET] = { 0x020c, 17 },
2975 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2976 [VPE_AHB_RESET] = { 0x020c, 14 },
2977 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2978 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2979 [HDMI_AHB_RESET] = { 0x020c, 9 },
2980 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2981 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2982 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2983 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2984 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2985 [MDP_AHB_RESET] = { 0x020c, 3 },
2986 [ROT_AHB_RESET] = { 0x020c, 2 },
2987 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2988 [VFE_AHB_RESET] = { 0x020c, 0 },
2989 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2990 [VCAP_AHB_RESET] = { 0x0200, 2 },
2991 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2992 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2993 [CSIPHY2_RESET] = { 0x0210, 31 },
2994 [CSI_PIX1_RESET] = { 0x0210, 30 },
2995 [CSIPHY0_RESET] = { 0x0210, 29 },
2996 [CSIPHY1_RESET] = { 0x0210, 28 },
2997 [CSI_RDI_RESET] = { 0x0210, 27 },
2998 [CSI_PIX_RESET] = { 0x0210, 26 },
2999 [DSI2_RESET] = { 0x0210, 25 },
3000 [VFE_CSI_RESET] = { 0x0210, 24 },
3001 [MDP_RESET] = { 0x0210, 21 },
3002 [AMP_RESET] = { 0x0210, 20 },
3003 [JPEGD_RESET] = { 0x0210, 19 },
3004 [CSI1_RESET] = { 0x0210, 18 },
3005 [VPE_RESET] = { 0x0210, 17 },
3006 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
3007 [VFE_RESET] = { 0x0210, 15 },
3008 [GFX3D_RESET] = { 0x0210, 12 },
3009 [HDMI_RESET] = { 0x0210, 11 },
3010 [MMSS_IMEM_RESET] = { 0x0210, 10 },
3011 [IJPEG_RESET] = { 0x0210, 9 },
3012 [CSI0_RESET] = { 0x0210, 8 },
3013 [DSI_RESET] = { 0x0210, 7 },
3014 [VCODEC_RESET] = { 0x0210, 6 },
3015 [MDP_TV_RESET] = { 0x0210, 4 },
3016 [MDP_VSYNC_RESET] = { 0x0210, 3 },
3017 [ROT_RESET] = { 0x0210, 2 },
3018 [TV_HDMI_RESET] = { 0x0210, 1 },
3019 [VCAP_NPL_RESET] = { 0x0214, 4 },
3020 [VCAP_RESET] = { 0x0214, 3 },
3021 [CSI2_RESET] = { 0x0214, 2 },
3022 [CSI_RDI1_RESET] = { 0x0214, 1 },
3023 [CSI_RDI2_RESET] = { 0x0214 },
3024 };
3025
3026 static const struct regmap_config mmcc_msm8960_regmap_config = {
3027 .reg_bits = 32,
3028 .reg_stride = 4,
3029 .val_bits = 32,
3030 .max_register = 0x334,
3031 .fast_io = true,
3032 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3033 };
3034
3035 static const struct regmap_config mmcc_apq8064_regmap_config = {
3036 .reg_bits = 32,
3037 .reg_stride = 4,
3038 .val_bits = 32,
3039 .max_register = 0x350,
3040 .fast_io = true,
3041 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3042 };
3043
3044 static const struct qcom_cc_desc mmcc_msm8960_desc = {
3045 .config = &mmcc_msm8960_regmap_config,
3046 .clks = mmcc_msm8960_clks,
3047 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
3048 .resets = mmcc_msm8960_resets,
3049 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
3050 };
3051
3052 static const struct qcom_cc_desc mmcc_apq8064_desc = {
3053 .config = &mmcc_apq8064_regmap_config,
3054 .clks = mmcc_apq8064_clks,
3055 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
3056 .resets = mmcc_apq8064_resets,
3057 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
3058 };
3059
3060 static const struct of_device_id mmcc_msm8960_match_table[] = {
3061 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
3062 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
3063 { }
3064 };
3065 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
3066
3067 static int mmcc_msm8960_probe(struct platform_device *pdev)
3068 {
3069 const struct of_device_id *match;
3070 struct regmap *regmap;
3071 bool is_8064;
3072 struct device *dev = &pdev->dev;
3073
3074 match = of_match_device(mmcc_msm8960_match_table, dev);
3075 if (!match)
3076 return -EINVAL;
3077
3078 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
3079 if (is_8064) {
3080 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
3081 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
3082 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3083 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3084 }
3085
3086 regmap = qcom_cc_map(pdev, match->data);
3087 if (IS_ERR(regmap))
3088 return PTR_ERR(regmap);
3089
3090 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
3091
3092 return qcom_cc_really_probe(pdev, match->data, regmap);
3093 }
3094
3095 static struct platform_driver mmcc_msm8960_driver = {
3096 .probe = mmcc_msm8960_probe,
3097 .driver = {
3098 .name = "mmcc-msm8960",
3099 .of_match_table = mmcc_msm8960_match_table,
3100 },
3101 };
3102
3103 module_platform_driver(mmcc_msm8960_driver);
3104
3105 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
3106 MODULE_LICENSE("GPL v2");
3107 MODULE_ALIAS("platform:mmcc-msm8960");
Linux kernel - Deliverables
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