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Merge branch 'next' of git://git.infradead.org/users/pcmoore/selinux into next
[deliverable/linux.git] / drivers / clk / qcom / mmcc-msm8960.c
1 /*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/clk-provider.h>
23 #include <linux/regmap.h>
24 #include <linux/reset-controller.h>
25
26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
28
29 #include "common.h"
30 #include "clk-regmap.h"
31 #include "clk-pll.h"
32 #include "clk-rcg.h"
33 #include "clk-branch.h"
34 #include "reset.h"
35
36 #define P_PXO 0
37 #define P_PLL8 1
38 #define P_PLL2 2
39 #define P_PLL3 3
40 #define P_PLL15 3
41
42 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
43
44 static u8 mmcc_pxo_pll8_pll2_map[] = {
45 [P_PXO] = 0,
46 [P_PLL8] = 2,
47 [P_PLL2] = 1,
48 };
49
50 static const char *mmcc_pxo_pll8_pll2[] = {
51 "pxo",
52 "pll8_vote",
53 "pll2",
54 };
55
56 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
57 [P_PXO] = 0,
58 [P_PLL8] = 2,
59 [P_PLL2] = 1,
60 [P_PLL3] = 3,
61 };
62
63 static const char *mmcc_pxo_pll8_pll2_pll15[] = {
64 "pxo",
65 "pll8_vote",
66 "pll2",
67 "pll15",
68 };
69
70 static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
71 [P_PXO] = 0,
72 [P_PLL8] = 2,
73 [P_PLL2] = 1,
74 [P_PLL15] = 3,
75 };
76
77 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
78 "pxo",
79 "pll8_vote",
80 "pll2",
81 "pll3",
82 };
83
84 static struct clk_pll pll2 = {
85 .l_reg = 0x320,
86 .m_reg = 0x324,
87 .n_reg = 0x328,
88 .config_reg = 0x32c,
89 .mode_reg = 0x31c,
90 .status_reg = 0x334,
91 .status_bit = 16,
92 .clkr.hw.init = &(struct clk_init_data){
93 .name = "pll2",
94 .parent_names = (const char *[]){ "pxo" },
95 .num_parents = 1,
96 .ops = &clk_pll_ops,
97 },
98 };
99
100 static struct clk_pll pll15 = {
101 .l_reg = 0x33c,
102 .m_reg = 0x340,
103 .n_reg = 0x344,
104 .config_reg = 0x348,
105 .mode_reg = 0x338,
106 .status_reg = 0x350,
107 .status_bit = 16,
108 .clkr.hw.init = &(struct clk_init_data){
109 .name = "pll15",
110 .parent_names = (const char *[]){ "pxo" },
111 .num_parents = 1,
112 .ops = &clk_pll_ops,
113 },
114 };
115
116 static const struct pll_config pll15_config = {
117 .l = 33,
118 .m = 1,
119 .n = 3,
120 .vco_val = 0x2 << 16,
121 .vco_mask = 0x3 << 16,
122 .pre_div_val = 0x0,
123 .pre_div_mask = BIT(19),
124 .post_div_val = 0x0,
125 .post_div_mask = 0x3 << 20,
126 .mn_ena_mask = BIT(22),
127 .main_output_mask = BIT(23),
128 };
129
130 static struct freq_tbl clk_tbl_cam[] = {
131 { 6000000, P_PLL8, 4, 1, 16 },
132 { 8000000, P_PLL8, 4, 1, 12 },
133 { 12000000, P_PLL8, 4, 1, 8 },
134 { 16000000, P_PLL8, 4, 1, 6 },
135 { 19200000, P_PLL8, 4, 1, 5 },
136 { 24000000, P_PLL8, 4, 1, 4 },
137 { 32000000, P_PLL8, 4, 1, 3 },
138 { 48000000, P_PLL8, 4, 1, 2 },
139 { 64000000, P_PLL8, 3, 1, 2 },
140 { 96000000, P_PLL8, 4, 0, 0 },
141 { 128000000, P_PLL8, 3, 0, 0 },
142 { }
143 };
144
145 static struct clk_rcg camclk0_src = {
146 .ns_reg = 0x0148,
147 .md_reg = 0x0144,
148 .mn = {
149 .mnctr_en_bit = 5,
150 .mnctr_reset_bit = 8,
151 .reset_in_cc = true,
152 .mnctr_mode_shift = 6,
153 .n_val_shift = 24,
154 .m_val_shift = 8,
155 .width = 8,
156 },
157 .p = {
158 .pre_div_shift = 14,
159 .pre_div_width = 2,
160 },
161 .s = {
162 .src_sel_shift = 0,
163 .parent_map = mmcc_pxo_pll8_pll2_map,
164 },
165 .freq_tbl = clk_tbl_cam,
166 .clkr = {
167 .enable_reg = 0x0140,
168 .enable_mask = BIT(2),
169 .hw.init = &(struct clk_init_data){
170 .name = "camclk0_src",
171 .parent_names = mmcc_pxo_pll8_pll2,
172 .num_parents = 3,
173 .ops = &clk_rcg_ops,
174 },
175 },
176 };
177
178 static struct clk_branch camclk0_clk = {
179 .halt_reg = 0x01e8,
180 .halt_bit = 15,
181 .clkr = {
182 .enable_reg = 0x0140,
183 .enable_mask = BIT(0),
184 .hw.init = &(struct clk_init_data){
185 .name = "camclk0_clk",
186 .parent_names = (const char *[]){ "camclk0_src" },
187 .num_parents = 1,
188 .ops = &clk_branch_ops,
189 },
190 },
191
192 };
193
194 static struct clk_rcg camclk1_src = {
195 .ns_reg = 0x015c,
196 .md_reg = 0x0158,
197 .mn = {
198 .mnctr_en_bit = 5,
199 .mnctr_reset_bit = 8,
200 .reset_in_cc = true,
201 .mnctr_mode_shift = 6,
202 .n_val_shift = 24,
203 .m_val_shift = 8,
204 .width = 8,
205 },
206 .p = {
207 .pre_div_shift = 14,
208 .pre_div_width = 2,
209 },
210 .s = {
211 .src_sel_shift = 0,
212 .parent_map = mmcc_pxo_pll8_pll2_map,
213 },
214 .freq_tbl = clk_tbl_cam,
215 .clkr = {
216 .enable_reg = 0x0154,
217 .enable_mask = BIT(2),
218 .hw.init = &(struct clk_init_data){
219 .name = "camclk1_src",
220 .parent_names = mmcc_pxo_pll8_pll2,
221 .num_parents = 3,
222 .ops = &clk_rcg_ops,
223 },
224 },
225 };
226
227 static struct clk_branch camclk1_clk = {
228 .halt_reg = 0x01e8,
229 .halt_bit = 16,
230 .clkr = {
231 .enable_reg = 0x0154,
232 .enable_mask = BIT(0),
233 .hw.init = &(struct clk_init_data){
234 .name = "camclk1_clk",
235 .parent_names = (const char *[]){ "camclk1_src" },
236 .num_parents = 1,
237 .ops = &clk_branch_ops,
238 },
239 },
240
241 };
242
243 static struct clk_rcg camclk2_src = {
244 .ns_reg = 0x0228,
245 .md_reg = 0x0224,
246 .mn = {
247 .mnctr_en_bit = 5,
248 .mnctr_reset_bit = 8,
249 .reset_in_cc = true,
250 .mnctr_mode_shift = 6,
251 .n_val_shift = 24,
252 .m_val_shift = 8,
253 .width = 8,
254 },
255 .p = {
256 .pre_div_shift = 14,
257 .pre_div_width = 2,
258 },
259 .s = {
260 .src_sel_shift = 0,
261 .parent_map = mmcc_pxo_pll8_pll2_map,
262 },
263 .freq_tbl = clk_tbl_cam,
264 .clkr = {
265 .enable_reg = 0x0220,
266 .enable_mask = BIT(2),
267 .hw.init = &(struct clk_init_data){
268 .name = "camclk2_src",
269 .parent_names = mmcc_pxo_pll8_pll2,
270 .num_parents = 3,
271 .ops = &clk_rcg_ops,
272 },
273 },
274 };
275
276 static struct clk_branch camclk2_clk = {
277 .halt_reg = 0x01e8,
278 .halt_bit = 16,
279 .clkr = {
280 .enable_reg = 0x0220,
281 .enable_mask = BIT(0),
282 .hw.init = &(struct clk_init_data){
283 .name = "camclk2_clk",
284 .parent_names = (const char *[]){ "camclk2_src" },
285 .num_parents = 1,
286 .ops = &clk_branch_ops,
287 },
288 },
289
290 };
291
292 static struct freq_tbl clk_tbl_csi[] = {
293 { 27000000, P_PXO, 1, 0, 0 },
294 { 85330000, P_PLL8, 1, 2, 9 },
295 { 177780000, P_PLL2, 1, 2, 9 },
296 { }
297 };
298
299 static struct clk_rcg csi0_src = {
300 .ns_reg = 0x0048,
301 .md_reg = 0x0044,
302 .mn = {
303 .mnctr_en_bit = 5,
304 .mnctr_reset_bit = 7,
305 .mnctr_mode_shift = 6,
306 .n_val_shift = 24,
307 .m_val_shift = 8,
308 .width = 8,
309 },
310 .p = {
311 .pre_div_shift = 14,
312 .pre_div_width = 2,
313 },
314 .s = {
315 .src_sel_shift = 0,
316 .parent_map = mmcc_pxo_pll8_pll2_map,
317 },
318 .freq_tbl = clk_tbl_csi,
319 .clkr = {
320 .enable_reg = 0x0040,
321 .enable_mask = BIT(2),
322 .hw.init = &(struct clk_init_data){
323 .name = "csi0_src",
324 .parent_names = mmcc_pxo_pll8_pll2,
325 .num_parents = 3,
326 .ops = &clk_rcg_ops,
327 },
328 },
329 };
330
331 static struct clk_branch csi0_clk = {
332 .halt_reg = 0x01cc,
333 .halt_bit = 13,
334 .clkr = {
335 .enable_reg = 0x0040,
336 .enable_mask = BIT(0),
337 .hw.init = &(struct clk_init_data){
338 .parent_names = (const char *[]){ "csi0_src" },
339 .num_parents = 1,
340 .name = "csi0_clk",
341 .ops = &clk_branch_ops,
342 .flags = CLK_SET_RATE_PARENT,
343 },
344 },
345 };
346
347 static struct clk_branch csi0_phy_clk = {
348 .halt_reg = 0x01e8,
349 .halt_bit = 9,
350 .clkr = {
351 .enable_reg = 0x0040,
352 .enable_mask = BIT(8),
353 .hw.init = &(struct clk_init_data){
354 .parent_names = (const char *[]){ "csi0_src" },
355 .num_parents = 1,
356 .name = "csi0_phy_clk",
357 .ops = &clk_branch_ops,
358 .flags = CLK_SET_RATE_PARENT,
359 },
360 },
361 };
362
363 static struct clk_rcg csi1_src = {
364 .ns_reg = 0x0010,
365 .md_reg = 0x0028,
366 .mn = {
367 .mnctr_en_bit = 5,
368 .mnctr_reset_bit = 7,
369 .mnctr_mode_shift = 6,
370 .n_val_shift = 24,
371 .m_val_shift = 8,
372 .width = 8,
373 },
374 .p = {
375 .pre_div_shift = 14,
376 .pre_div_width = 2,
377 },
378 .s = {
379 .src_sel_shift = 0,
380 .parent_map = mmcc_pxo_pll8_pll2_map,
381 },
382 .freq_tbl = clk_tbl_csi,
383 .clkr = {
384 .enable_reg = 0x0024,
385 .enable_mask = BIT(2),
386 .hw.init = &(struct clk_init_data){
387 .name = "csi1_src",
388 .parent_names = mmcc_pxo_pll8_pll2,
389 .num_parents = 3,
390 .ops = &clk_rcg_ops,
391 },
392 },
393 };
394
395 static struct clk_branch csi1_clk = {
396 .halt_reg = 0x01cc,
397 .halt_bit = 14,
398 .clkr = {
399 .enable_reg = 0x0024,
400 .enable_mask = BIT(0),
401 .hw.init = &(struct clk_init_data){
402 .parent_names = (const char *[]){ "csi1_src" },
403 .num_parents = 1,
404 .name = "csi1_clk",
405 .ops = &clk_branch_ops,
406 .flags = CLK_SET_RATE_PARENT,
407 },
408 },
409 };
410
411 static struct clk_branch csi1_phy_clk = {
412 .halt_reg = 0x01e8,
413 .halt_bit = 10,
414 .clkr = {
415 .enable_reg = 0x0024,
416 .enable_mask = BIT(8),
417 .hw.init = &(struct clk_init_data){
418 .parent_names = (const char *[]){ "csi1_src" },
419 .num_parents = 1,
420 .name = "csi1_phy_clk",
421 .ops = &clk_branch_ops,
422 .flags = CLK_SET_RATE_PARENT,
423 },
424 },
425 };
426
427 static struct clk_rcg csi2_src = {
428 .ns_reg = 0x0234,
429 .md_reg = 0x022c,
430 .mn = {
431 .mnctr_en_bit = 5,
432 .mnctr_reset_bit = 7,
433 .mnctr_mode_shift = 6,
434 .n_val_shift = 24,
435 .m_val_shift = 8,
436 .width = 8,
437 },
438 .p = {
439 .pre_div_shift = 14,
440 .pre_div_width = 2,
441 },
442 .s = {
443 .src_sel_shift = 0,
444 .parent_map = mmcc_pxo_pll8_pll2_map,
445 },
446 .freq_tbl = clk_tbl_csi,
447 .clkr = {
448 .enable_reg = 0x022c,
449 .enable_mask = BIT(2),
450 .hw.init = &(struct clk_init_data){
451 .name = "csi2_src",
452 .parent_names = mmcc_pxo_pll8_pll2,
453 .num_parents = 3,
454 .ops = &clk_rcg_ops,
455 },
456 },
457 };
458
459 static struct clk_branch csi2_clk = {
460 .halt_reg = 0x01cc,
461 .halt_bit = 29,
462 .clkr = {
463 .enable_reg = 0x022c,
464 .enable_mask = BIT(0),
465 .hw.init = &(struct clk_init_data){
466 .parent_names = (const char *[]){ "csi2_src" },
467 .num_parents = 1,
468 .name = "csi2_clk",
469 .ops = &clk_branch_ops,
470 .flags = CLK_SET_RATE_PARENT,
471 },
472 },
473 };
474
475 static struct clk_branch csi2_phy_clk = {
476 .halt_reg = 0x01e8,
477 .halt_bit = 29,
478 .clkr = {
479 .enable_reg = 0x022c,
480 .enable_mask = BIT(8),
481 .hw.init = &(struct clk_init_data){
482 .parent_names = (const char *[]){ "csi2_src" },
483 .num_parents = 1,
484 .name = "csi2_phy_clk",
485 .ops = &clk_branch_ops,
486 .flags = CLK_SET_RATE_PARENT,
487 },
488 },
489 };
490
491 struct clk_pix_rdi {
492 u32 s_reg;
493 u32 s_mask;
494 u32 s2_reg;
495 u32 s2_mask;
496 struct clk_regmap clkr;
497 };
498
499 #define to_clk_pix_rdi(_hw) \
500 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
501
502 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
503 {
504 int i;
505 int ret = 0;
506 u32 val;
507 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
508 struct clk *clk = hw->clk;
509 int num_parents = __clk_get_num_parents(hw->clk);
510
511 /*
512 * These clocks select three inputs via two muxes. One mux selects
513 * between csi0 and csi1 and the second mux selects between that mux's
514 * output and csi2. The source and destination selections for each
515 * mux must be clocking for the switch to succeed so just turn on
516 * all three sources because it's easier than figuring out what source
517 * needs to be on at what time.
518 */
519 for (i = 0; i < num_parents; i++) {
520 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
521 if (ret)
522 goto err;
523 }
524
525 if (index == 2)
526 val = rdi->s2_mask;
527 else
528 val = 0;
529 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
530 /*
531 * Wait at least 6 cycles of slowest clock
532 * for the glitch-free MUX to fully switch sources.
533 */
534 udelay(1);
535
536 if (index == 1)
537 val = rdi->s_mask;
538 else
539 val = 0;
540 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
541 /*
542 * Wait at least 6 cycles of slowest clock
543 * for the glitch-free MUX to fully switch sources.
544 */
545 udelay(1);
546
547 err:
548 for (i--; i >= 0; i--)
549 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
550
551 return ret;
552 }
553
554 static u8 pix_rdi_get_parent(struct clk_hw *hw)
555 {
556 u32 val;
557 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
558
559
560 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
561 if (val & rdi->s2_mask)
562 return 2;
563
564 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
565 if (val & rdi->s_mask)
566 return 1;
567
568 return 0;
569 }
570
571 static const struct clk_ops clk_ops_pix_rdi = {
572 .enable = clk_enable_regmap,
573 .disable = clk_disable_regmap,
574 .set_parent = pix_rdi_set_parent,
575 .get_parent = pix_rdi_get_parent,
576 .determine_rate = __clk_mux_determine_rate,
577 };
578
579 static const char *pix_rdi_parents[] = {
580 "csi0_clk",
581 "csi1_clk",
582 "csi2_clk",
583 };
584
585 static struct clk_pix_rdi csi_pix_clk = {
586 .s_reg = 0x0058,
587 .s_mask = BIT(25),
588 .s2_reg = 0x0238,
589 .s2_mask = BIT(13),
590 .clkr = {
591 .enable_reg = 0x0058,
592 .enable_mask = BIT(26),
593 .hw.init = &(struct clk_init_data){
594 .name = "csi_pix_clk",
595 .parent_names = pix_rdi_parents,
596 .num_parents = 3,
597 .ops = &clk_ops_pix_rdi,
598 },
599 },
600 };
601
602 static struct clk_pix_rdi csi_pix1_clk = {
603 .s_reg = 0x0238,
604 .s_mask = BIT(8),
605 .s2_reg = 0x0238,
606 .s2_mask = BIT(9),
607 .clkr = {
608 .enable_reg = 0x0238,
609 .enable_mask = BIT(10),
610 .hw.init = &(struct clk_init_data){
611 .name = "csi_pix1_clk",
612 .parent_names = pix_rdi_parents,
613 .num_parents = 3,
614 .ops = &clk_ops_pix_rdi,
615 },
616 },
617 };
618
619 static struct clk_pix_rdi csi_rdi_clk = {
620 .s_reg = 0x0058,
621 .s_mask = BIT(12),
622 .s2_reg = 0x0238,
623 .s2_mask = BIT(12),
624 .clkr = {
625 .enable_reg = 0x0058,
626 .enable_mask = BIT(13),
627 .hw.init = &(struct clk_init_data){
628 .name = "csi_rdi_clk",
629 .parent_names = pix_rdi_parents,
630 .num_parents = 3,
631 .ops = &clk_ops_pix_rdi,
632 },
633 },
634 };
635
636 static struct clk_pix_rdi csi_rdi1_clk = {
637 .s_reg = 0x0238,
638 .s_mask = BIT(0),
639 .s2_reg = 0x0238,
640 .s2_mask = BIT(1),
641 .clkr = {
642 .enable_reg = 0x0238,
643 .enable_mask = BIT(2),
644 .hw.init = &(struct clk_init_data){
645 .name = "csi_rdi1_clk",
646 .parent_names = pix_rdi_parents,
647 .num_parents = 3,
648 .ops = &clk_ops_pix_rdi,
649 },
650 },
651 };
652
653 static struct clk_pix_rdi csi_rdi2_clk = {
654 .s_reg = 0x0238,
655 .s_mask = BIT(4),
656 .s2_reg = 0x0238,
657 .s2_mask = BIT(5),
658 .clkr = {
659 .enable_reg = 0x0238,
660 .enable_mask = BIT(6),
661 .hw.init = &(struct clk_init_data){
662 .name = "csi_rdi2_clk",
663 .parent_names = pix_rdi_parents,
664 .num_parents = 3,
665 .ops = &clk_ops_pix_rdi,
666 },
667 },
668 };
669
670 static struct freq_tbl clk_tbl_csiphytimer[] = {
671 { 85330000, P_PLL8, 1, 2, 9 },
672 { 177780000, P_PLL2, 1, 2, 9 },
673 { }
674 };
675
676 static struct clk_rcg csiphytimer_src = {
677 .ns_reg = 0x0168,
678 .md_reg = 0x0164,
679 .mn = {
680 .mnctr_en_bit = 5,
681 .mnctr_reset_bit = 8,
682 .reset_in_cc = true,
683 .mnctr_mode_shift = 6,
684 .n_val_shift = 24,
685 .m_val_shift = 8,
686 .width = 8,
687 },
688 .p = {
689 .pre_div_shift = 14,
690 .pre_div_width = 2,
691 },
692 .s = {
693 .src_sel_shift = 0,
694 .parent_map = mmcc_pxo_pll8_pll2_map,
695 },
696 .freq_tbl = clk_tbl_csiphytimer,
697 .clkr = {
698 .enable_reg = 0x0160,
699 .enable_mask = BIT(2),
700 .hw.init = &(struct clk_init_data){
701 .name = "csiphytimer_src",
702 .parent_names = mmcc_pxo_pll8_pll2,
703 .num_parents = 3,
704 .ops = &clk_rcg_ops,
705 },
706 },
707 };
708
709 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
710
711 static struct clk_branch csiphy0_timer_clk = {
712 .halt_reg = 0x01e8,
713 .halt_bit = 17,
714 .clkr = {
715 .enable_reg = 0x0160,
716 .enable_mask = BIT(0),
717 .hw.init = &(struct clk_init_data){
718 .parent_names = csixphy_timer_src,
719 .num_parents = 1,
720 .name = "csiphy0_timer_clk",
721 .ops = &clk_branch_ops,
722 .flags = CLK_SET_RATE_PARENT,
723 },
724 },
725 };
726
727 static struct clk_branch csiphy1_timer_clk = {
728 .halt_reg = 0x01e8,
729 .halt_bit = 18,
730 .clkr = {
731 .enable_reg = 0x0160,
732 .enable_mask = BIT(9),
733 .hw.init = &(struct clk_init_data){
734 .parent_names = csixphy_timer_src,
735 .num_parents = 1,
736 .name = "csiphy1_timer_clk",
737 .ops = &clk_branch_ops,
738 .flags = CLK_SET_RATE_PARENT,
739 },
740 },
741 };
742
743 static struct clk_branch csiphy2_timer_clk = {
744 .halt_reg = 0x01e8,
745 .halt_bit = 30,
746 .clkr = {
747 .enable_reg = 0x0160,
748 .enable_mask = BIT(11),
749 .hw.init = &(struct clk_init_data){
750 .parent_names = csixphy_timer_src,
751 .num_parents = 1,
752 .name = "csiphy2_timer_clk",
753 .ops = &clk_branch_ops,
754 .flags = CLK_SET_RATE_PARENT,
755 },
756 },
757 };
758
759 static struct freq_tbl clk_tbl_gfx2d[] = {
760 F_MN( 27000000, P_PXO, 1, 0),
761 F_MN( 48000000, P_PLL8, 1, 8),
762 F_MN( 54857000, P_PLL8, 1, 7),
763 F_MN( 64000000, P_PLL8, 1, 6),
764 F_MN( 76800000, P_PLL8, 1, 5),
765 F_MN( 96000000, P_PLL8, 1, 4),
766 F_MN(128000000, P_PLL8, 1, 3),
767 F_MN(145455000, P_PLL2, 2, 11),
768 F_MN(160000000, P_PLL2, 1, 5),
769 F_MN(177778000, P_PLL2, 2, 9),
770 F_MN(200000000, P_PLL2, 1, 4),
771 F_MN(228571000, P_PLL2, 2, 7),
772 { }
773 };
774
775 static struct clk_dyn_rcg gfx2d0_src = {
776 .ns_reg = 0x0070,
777 .md_reg[0] = 0x0064,
778 .md_reg[1] = 0x0068,
779 .mn[0] = {
780 .mnctr_en_bit = 8,
781 .mnctr_reset_bit = 25,
782 .mnctr_mode_shift = 9,
783 .n_val_shift = 20,
784 .m_val_shift = 4,
785 .width = 4,
786 },
787 .mn[1] = {
788 .mnctr_en_bit = 5,
789 .mnctr_reset_bit = 24,
790 .mnctr_mode_shift = 6,
791 .n_val_shift = 16,
792 .m_val_shift = 4,
793 .width = 4,
794 },
795 .s[0] = {
796 .src_sel_shift = 3,
797 .parent_map = mmcc_pxo_pll8_pll2_map,
798 },
799 .s[1] = {
800 .src_sel_shift = 0,
801 .parent_map = mmcc_pxo_pll8_pll2_map,
802 },
803 .mux_sel_bit = 11,
804 .freq_tbl = clk_tbl_gfx2d,
805 .clkr = {
806 .enable_reg = 0x0060,
807 .enable_mask = BIT(2),
808 .hw.init = &(struct clk_init_data){
809 .name = "gfx2d0_src",
810 .parent_names = mmcc_pxo_pll8_pll2,
811 .num_parents = 3,
812 .ops = &clk_dyn_rcg_ops,
813 },
814 },
815 };
816
817 static struct clk_branch gfx2d0_clk = {
818 .halt_reg = 0x01c8,
819 .halt_bit = 9,
820 .clkr = {
821 .enable_reg = 0x0060,
822 .enable_mask = BIT(0),
823 .hw.init = &(struct clk_init_data){
824 .name = "gfx2d0_clk",
825 .parent_names = (const char *[]){ "gfx2d0_src" },
826 .num_parents = 1,
827 .ops = &clk_branch_ops,
828 .flags = CLK_SET_RATE_PARENT,
829 },
830 },
831 };
832
833 static struct clk_dyn_rcg gfx2d1_src = {
834 .ns_reg = 0x007c,
835 .md_reg[0] = 0x0078,
836 .md_reg[1] = 0x006c,
837 .mn[0] = {
838 .mnctr_en_bit = 8,
839 .mnctr_reset_bit = 25,
840 .mnctr_mode_shift = 9,
841 .n_val_shift = 20,
842 .m_val_shift = 4,
843 .width = 4,
844 },
845 .mn[1] = {
846 .mnctr_en_bit = 5,
847 .mnctr_reset_bit = 24,
848 .mnctr_mode_shift = 6,
849 .n_val_shift = 16,
850 .m_val_shift = 4,
851 .width = 4,
852 },
853 .s[0] = {
854 .src_sel_shift = 3,
855 .parent_map = mmcc_pxo_pll8_pll2_map,
856 },
857 .s[1] = {
858 .src_sel_shift = 0,
859 .parent_map = mmcc_pxo_pll8_pll2_map,
860 },
861 .mux_sel_bit = 11,
862 .freq_tbl = clk_tbl_gfx2d,
863 .clkr = {
864 .enable_reg = 0x0074,
865 .enable_mask = BIT(2),
866 .hw.init = &(struct clk_init_data){
867 .name = "gfx2d1_src",
868 .parent_names = mmcc_pxo_pll8_pll2,
869 .num_parents = 3,
870 .ops = &clk_dyn_rcg_ops,
871 },
872 },
873 };
874
875 static struct clk_branch gfx2d1_clk = {
876 .halt_reg = 0x01c8,
877 .halt_bit = 14,
878 .clkr = {
879 .enable_reg = 0x0074,
880 .enable_mask = BIT(0),
881 .hw.init = &(struct clk_init_data){
882 .name = "gfx2d1_clk",
883 .parent_names = (const char *[]){ "gfx2d1_src" },
884 .num_parents = 1,
885 .ops = &clk_branch_ops,
886 .flags = CLK_SET_RATE_PARENT,
887 },
888 },
889 };
890
891 static struct freq_tbl clk_tbl_gfx3d[] = {
892 F_MN( 27000000, P_PXO, 1, 0),
893 F_MN( 48000000, P_PLL8, 1, 8),
894 F_MN( 54857000, P_PLL8, 1, 7),
895 F_MN( 64000000, P_PLL8, 1, 6),
896 F_MN( 76800000, P_PLL8, 1, 5),
897 F_MN( 96000000, P_PLL8, 1, 4),
898 F_MN(128000000, P_PLL8, 1, 3),
899 F_MN(145455000, P_PLL2, 2, 11),
900 F_MN(160000000, P_PLL2, 1, 5),
901 F_MN(177778000, P_PLL2, 2, 9),
902 F_MN(200000000, P_PLL2, 1, 4),
903 F_MN(228571000, P_PLL2, 2, 7),
904 F_MN(266667000, P_PLL2, 1, 3),
905 F_MN(300000000, P_PLL3, 1, 4),
906 F_MN(320000000, P_PLL2, 2, 5),
907 F_MN(400000000, P_PLL2, 1, 2),
908 { }
909 };
910
911 static struct freq_tbl clk_tbl_gfx3d_8064[] = {
912 F_MN( 27000000, P_PXO, 0, 0),
913 F_MN( 48000000, P_PLL8, 1, 8),
914 F_MN( 54857000, P_PLL8, 1, 7),
915 F_MN( 64000000, P_PLL8, 1, 6),
916 F_MN( 76800000, P_PLL8, 1, 5),
917 F_MN( 96000000, P_PLL8, 1, 4),
918 F_MN(128000000, P_PLL8, 1, 3),
919 F_MN(145455000, P_PLL2, 2, 11),
920 F_MN(160000000, P_PLL2, 1, 5),
921 F_MN(177778000, P_PLL2, 2, 9),
922 F_MN(192000000, P_PLL8, 1, 2),
923 F_MN(200000000, P_PLL2, 1, 4),
924 F_MN(228571000, P_PLL2, 2, 7),
925 F_MN(266667000, P_PLL2, 1, 3),
926 F_MN(320000000, P_PLL2, 2, 5),
927 F_MN(400000000, P_PLL2, 1, 2),
928 F_MN(450000000, P_PLL15, 1, 2),
929 { }
930 };
931
932 static struct clk_dyn_rcg gfx3d_src = {
933 .ns_reg = 0x008c,
934 .md_reg[0] = 0x0084,
935 .md_reg[1] = 0x0088,
936 .mn[0] = {
937 .mnctr_en_bit = 8,
938 .mnctr_reset_bit = 25,
939 .mnctr_mode_shift = 9,
940 .n_val_shift = 18,
941 .m_val_shift = 4,
942 .width = 4,
943 },
944 .mn[1] = {
945 .mnctr_en_bit = 5,
946 .mnctr_reset_bit = 24,
947 .mnctr_mode_shift = 6,
948 .n_val_shift = 14,
949 .m_val_shift = 4,
950 .width = 4,
951 },
952 .s[0] = {
953 .src_sel_shift = 3,
954 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
955 },
956 .s[1] = {
957 .src_sel_shift = 0,
958 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
959 },
960 .mux_sel_bit = 11,
961 .freq_tbl = clk_tbl_gfx3d,
962 .clkr = {
963 .enable_reg = 0x0080,
964 .enable_mask = BIT(2),
965 .hw.init = &(struct clk_init_data){
966 .name = "gfx3d_src",
967 .parent_names = mmcc_pxo_pll8_pll2_pll3,
968 .num_parents = 4,
969 .ops = &clk_dyn_rcg_ops,
970 },
971 },
972 };
973
974 static const struct clk_init_data gfx3d_8064_init = {
975 .name = "gfx3d_src",
976 .parent_names = mmcc_pxo_pll8_pll2_pll15,
977 .num_parents = 4,
978 .ops = &clk_dyn_rcg_ops,
979 };
980
981 static struct clk_branch gfx3d_clk = {
982 .halt_reg = 0x01c8,
983 .halt_bit = 4,
984 .clkr = {
985 .enable_reg = 0x0080,
986 .enable_mask = BIT(0),
987 .hw.init = &(struct clk_init_data){
988 .name = "gfx3d_clk",
989 .parent_names = (const char *[]){ "gfx3d_src" },
990 .num_parents = 1,
991 .ops = &clk_branch_ops,
992 .flags = CLK_SET_RATE_PARENT,
993 },
994 },
995 };
996
997 static struct freq_tbl clk_tbl_vcap[] = {
998 F_MN( 27000000, P_PXO, 0, 0),
999 F_MN( 54860000, P_PLL8, 1, 7),
1000 F_MN( 64000000, P_PLL8, 1, 6),
1001 F_MN( 76800000, P_PLL8, 1, 5),
1002 F_MN(128000000, P_PLL8, 1, 3),
1003 F_MN(160000000, P_PLL2, 1, 5),
1004 F_MN(200000000, P_PLL2, 1, 4),
1005 { }
1006 };
1007
1008 static struct clk_dyn_rcg vcap_src = {
1009 .ns_reg = 0x021c,
1010 .md_reg[0] = 0x01ec,
1011 .md_reg[1] = 0x0218,
1012 .mn[0] = {
1013 .mnctr_en_bit = 8,
1014 .mnctr_reset_bit = 23,
1015 .mnctr_mode_shift = 9,
1016 .n_val_shift = 18,
1017 .m_val_shift = 4,
1018 .width = 4,
1019 },
1020 .mn[1] = {
1021 .mnctr_en_bit = 5,
1022 .mnctr_reset_bit = 22,
1023 .mnctr_mode_shift = 6,
1024 .n_val_shift = 14,
1025 .m_val_shift = 4,
1026 .width = 4,
1027 },
1028 .s[0] = {
1029 .src_sel_shift = 3,
1030 .parent_map = mmcc_pxo_pll8_pll2_map,
1031 },
1032 .s[1] = {
1033 .src_sel_shift = 0,
1034 .parent_map = mmcc_pxo_pll8_pll2_map,
1035 },
1036 .mux_sel_bit = 11,
1037 .freq_tbl = clk_tbl_vcap,
1038 .clkr = {
1039 .enable_reg = 0x0178,
1040 .enable_mask = BIT(2),
1041 .hw.init = &(struct clk_init_data){
1042 .name = "vcap_src",
1043 .parent_names = mmcc_pxo_pll8_pll2,
1044 .num_parents = 3,
1045 .ops = &clk_dyn_rcg_ops,
1046 },
1047 },
1048 };
1049
1050 static struct clk_branch vcap_clk = {
1051 .halt_reg = 0x0240,
1052 .halt_bit = 15,
1053 .clkr = {
1054 .enable_reg = 0x0178,
1055 .enable_mask = BIT(0),
1056 .hw.init = &(struct clk_init_data){
1057 .name = "vcap_clk",
1058 .parent_names = (const char *[]){ "vcap_src" },
1059 .num_parents = 1,
1060 .ops = &clk_branch_ops,
1061 .flags = CLK_SET_RATE_PARENT,
1062 },
1063 },
1064 };
1065
1066 static struct clk_branch vcap_npl_clk = {
1067 .halt_reg = 0x0240,
1068 .halt_bit = 25,
1069 .clkr = {
1070 .enable_reg = 0x0178,
1071 .enable_mask = BIT(13),
1072 .hw.init = &(struct clk_init_data){
1073 .name = "vcap_npl_clk",
1074 .parent_names = (const char *[]){ "vcap_src" },
1075 .num_parents = 1,
1076 .ops = &clk_branch_ops,
1077 .flags = CLK_SET_RATE_PARENT,
1078 },
1079 },
1080 };
1081
1082 static struct freq_tbl clk_tbl_ijpeg[] = {
1083 { 27000000, P_PXO, 1, 0, 0 },
1084 { 36570000, P_PLL8, 1, 2, 21 },
1085 { 54860000, P_PLL8, 7, 0, 0 },
1086 { 96000000, P_PLL8, 4, 0, 0 },
1087 { 109710000, P_PLL8, 1, 2, 7 },
1088 { 128000000, P_PLL8, 3, 0, 0 },
1089 { 153600000, P_PLL8, 1, 2, 5 },
1090 { 200000000, P_PLL2, 4, 0, 0 },
1091 { 228571000, P_PLL2, 1, 2, 7 },
1092 { 266667000, P_PLL2, 1, 1, 3 },
1093 { 320000000, P_PLL2, 1, 2, 5 },
1094 { }
1095 };
1096
1097 static struct clk_rcg ijpeg_src = {
1098 .ns_reg = 0x00a0,
1099 .md_reg = 0x009c,
1100 .mn = {
1101 .mnctr_en_bit = 5,
1102 .mnctr_reset_bit = 7,
1103 .mnctr_mode_shift = 6,
1104 .n_val_shift = 16,
1105 .m_val_shift = 8,
1106 .width = 8,
1107 },
1108 .p = {
1109 .pre_div_shift = 12,
1110 .pre_div_width = 2,
1111 },
1112 .s = {
1113 .src_sel_shift = 0,
1114 .parent_map = mmcc_pxo_pll8_pll2_map,
1115 },
1116 .freq_tbl = clk_tbl_ijpeg,
1117 .clkr = {
1118 .enable_reg = 0x0098,
1119 .enable_mask = BIT(2),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "ijpeg_src",
1122 .parent_names = mmcc_pxo_pll8_pll2,
1123 .num_parents = 3,
1124 .ops = &clk_rcg_ops,
1125 },
1126 },
1127 };
1128
1129 static struct clk_branch ijpeg_clk = {
1130 .halt_reg = 0x01c8,
1131 .halt_bit = 24,
1132 .clkr = {
1133 .enable_reg = 0x0098,
1134 .enable_mask = BIT(0),
1135 .hw.init = &(struct clk_init_data){
1136 .name = "ijpeg_clk",
1137 .parent_names = (const char *[]){ "ijpeg_src" },
1138 .num_parents = 1,
1139 .ops = &clk_branch_ops,
1140 .flags = CLK_SET_RATE_PARENT,
1141 },
1142 },
1143 };
1144
1145 static struct freq_tbl clk_tbl_jpegd[] = {
1146 { 64000000, P_PLL8, 6 },
1147 { 76800000, P_PLL8, 5 },
1148 { 96000000, P_PLL8, 4 },
1149 { 160000000, P_PLL2, 5 },
1150 { 200000000, P_PLL2, 4 },
1151 { }
1152 };
1153
1154 static struct clk_rcg jpegd_src = {
1155 .ns_reg = 0x00ac,
1156 .p = {
1157 .pre_div_shift = 12,
1158 .pre_div_width = 4,
1159 },
1160 .s = {
1161 .src_sel_shift = 0,
1162 .parent_map = mmcc_pxo_pll8_pll2_map,
1163 },
1164 .freq_tbl = clk_tbl_jpegd,
1165 .clkr = {
1166 .enable_reg = 0x00a4,
1167 .enable_mask = BIT(2),
1168 .hw.init = &(struct clk_init_data){
1169 .name = "jpegd_src",
1170 .parent_names = mmcc_pxo_pll8_pll2,
1171 .num_parents = 3,
1172 .ops = &clk_rcg_ops,
1173 },
1174 },
1175 };
1176
1177 static struct clk_branch jpegd_clk = {
1178 .halt_reg = 0x01c8,
1179 .halt_bit = 19,
1180 .clkr = {
1181 .enable_reg = 0x00a4,
1182 .enable_mask = BIT(0),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "jpegd_clk",
1185 .parent_names = (const char *[]){ "jpegd_src" },
1186 .num_parents = 1,
1187 .ops = &clk_branch_ops,
1188 .flags = CLK_SET_RATE_PARENT,
1189 },
1190 },
1191 };
1192
1193 static struct freq_tbl clk_tbl_mdp[] = {
1194 { 9600000, P_PLL8, 1, 1, 40 },
1195 { 13710000, P_PLL8, 1, 1, 28 },
1196 { 27000000, P_PXO, 1, 0, 0 },
1197 { 29540000, P_PLL8, 1, 1, 13 },
1198 { 34910000, P_PLL8, 1, 1, 11 },
1199 { 38400000, P_PLL8, 1, 1, 10 },
1200 { 59080000, P_PLL8, 1, 2, 13 },
1201 { 76800000, P_PLL8, 1, 1, 5 },
1202 { 85330000, P_PLL8, 1, 2, 9 },
1203 { 96000000, P_PLL8, 1, 1, 4 },
1204 { 128000000, P_PLL8, 1, 1, 3 },
1205 { 160000000, P_PLL2, 1, 1, 5 },
1206 { 177780000, P_PLL2, 1, 2, 9 },
1207 { 200000000, P_PLL2, 1, 1, 4 },
1208 { 228571000, P_PLL2, 1, 2, 7 },
1209 { 266667000, P_PLL2, 1, 1, 3 },
1210 { }
1211 };
1212
1213 static struct clk_dyn_rcg mdp_src = {
1214 .ns_reg = 0x00d0,
1215 .md_reg[0] = 0x00c4,
1216 .md_reg[1] = 0x00c8,
1217 .mn[0] = {
1218 .mnctr_en_bit = 8,
1219 .mnctr_reset_bit = 31,
1220 .mnctr_mode_shift = 9,
1221 .n_val_shift = 22,
1222 .m_val_shift = 8,
1223 .width = 8,
1224 },
1225 .mn[1] = {
1226 .mnctr_en_bit = 5,
1227 .mnctr_reset_bit = 30,
1228 .mnctr_mode_shift = 6,
1229 .n_val_shift = 14,
1230 .m_val_shift = 8,
1231 .width = 8,
1232 },
1233 .s[0] = {
1234 .src_sel_shift = 3,
1235 .parent_map = mmcc_pxo_pll8_pll2_map,
1236 },
1237 .s[1] = {
1238 .src_sel_shift = 0,
1239 .parent_map = mmcc_pxo_pll8_pll2_map,
1240 },
1241 .mux_sel_bit = 11,
1242 .freq_tbl = clk_tbl_mdp,
1243 .clkr = {
1244 .enable_reg = 0x00c0,
1245 .enable_mask = BIT(2),
1246 .hw.init = &(struct clk_init_data){
1247 .name = "mdp_src",
1248 .parent_names = mmcc_pxo_pll8_pll2,
1249 .num_parents = 3,
1250 .ops = &clk_dyn_rcg_ops,
1251 },
1252 },
1253 };
1254
1255 static struct clk_branch mdp_clk = {
1256 .halt_reg = 0x01d0,
1257 .halt_bit = 10,
1258 .clkr = {
1259 .enable_reg = 0x00c0,
1260 .enable_mask = BIT(0),
1261 .hw.init = &(struct clk_init_data){
1262 .name = "mdp_clk",
1263 .parent_names = (const char *[]){ "mdp_src" },
1264 .num_parents = 1,
1265 .ops = &clk_branch_ops,
1266 .flags = CLK_SET_RATE_PARENT,
1267 },
1268 },
1269 };
1270
1271 static struct clk_branch mdp_lut_clk = {
1272 .halt_reg = 0x01e8,
1273 .halt_bit = 13,
1274 .clkr = {
1275 .enable_reg = 0x016c,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .parent_names = (const char *[]){ "mdp_src" },
1279 .num_parents = 1,
1280 .name = "mdp_lut_clk",
1281 .ops = &clk_branch_ops,
1282 .flags = CLK_SET_RATE_PARENT,
1283 },
1284 },
1285 };
1286
1287 static struct clk_branch mdp_vsync_clk = {
1288 .halt_reg = 0x01cc,
1289 .halt_bit = 22,
1290 .clkr = {
1291 .enable_reg = 0x0058,
1292 .enable_mask = BIT(6),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "mdp_vsync_clk",
1295 .parent_names = (const char *[]){ "pxo" },
1296 .num_parents = 1,
1297 .ops = &clk_branch_ops
1298 },
1299 },
1300 };
1301
1302 static struct freq_tbl clk_tbl_rot[] = {
1303 { 27000000, P_PXO, 1 },
1304 { 29540000, P_PLL8, 13 },
1305 { 32000000, P_PLL8, 12 },
1306 { 38400000, P_PLL8, 10 },
1307 { 48000000, P_PLL8, 8 },
1308 { 54860000, P_PLL8, 7 },
1309 { 64000000, P_PLL8, 6 },
1310 { 76800000, P_PLL8, 5 },
1311 { 96000000, P_PLL8, 4 },
1312 { 100000000, P_PLL2, 8 },
1313 { 114290000, P_PLL2, 7 },
1314 { 133330000, P_PLL2, 6 },
1315 { 160000000, P_PLL2, 5 },
1316 { 200000000, P_PLL2, 4 },
1317 { }
1318 };
1319
1320 static struct clk_dyn_rcg rot_src = {
1321 .ns_reg = 0x00e8,
1322 .p[0] = {
1323 .pre_div_shift = 22,
1324 .pre_div_width = 4,
1325 },
1326 .p[1] = {
1327 .pre_div_shift = 26,
1328 .pre_div_width = 4,
1329 },
1330 .s[0] = {
1331 .src_sel_shift = 16,
1332 .parent_map = mmcc_pxo_pll8_pll2_map,
1333 },
1334 .s[1] = {
1335 .src_sel_shift = 19,
1336 .parent_map = mmcc_pxo_pll8_pll2_map,
1337 },
1338 .mux_sel_bit = 30,
1339 .freq_tbl = clk_tbl_rot,
1340 .clkr = {
1341 .enable_reg = 0x00e0,
1342 .enable_mask = BIT(2),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "rot_src",
1345 .parent_names = mmcc_pxo_pll8_pll2,
1346 .num_parents = 3,
1347 .ops = &clk_dyn_rcg_ops,
1348 },
1349 },
1350 };
1351
1352 static struct clk_branch rot_clk = {
1353 .halt_reg = 0x01d0,
1354 .halt_bit = 15,
1355 .clkr = {
1356 .enable_reg = 0x00e0,
1357 .enable_mask = BIT(0),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "rot_clk",
1360 .parent_names = (const char *[]){ "rot_src" },
1361 .num_parents = 1,
1362 .ops = &clk_branch_ops,
1363 .flags = CLK_SET_RATE_PARENT,
1364 },
1365 },
1366 };
1367
1368 #define P_HDMI_PLL 1
1369
1370 static u8 mmcc_pxo_hdmi_map[] = {
1371 [P_PXO] = 0,
1372 [P_HDMI_PLL] = 3,
1373 };
1374
1375 static const char *mmcc_pxo_hdmi[] = {
1376 "pxo",
1377 "hdmi_pll",
1378 };
1379
1380 static struct freq_tbl clk_tbl_tv[] = {
1381 { .src = P_HDMI_PLL, .pre_div = 1 },
1382 { }
1383 };
1384
1385 static struct clk_rcg tv_src = {
1386 .ns_reg = 0x00f4,
1387 .md_reg = 0x00f0,
1388 .mn = {
1389 .mnctr_en_bit = 5,
1390 .mnctr_reset_bit = 7,
1391 .mnctr_mode_shift = 6,
1392 .n_val_shift = 16,
1393 .m_val_shift = 8,
1394 .width = 8,
1395 },
1396 .p = {
1397 .pre_div_shift = 14,
1398 .pre_div_width = 2,
1399 },
1400 .s = {
1401 .src_sel_shift = 0,
1402 .parent_map = mmcc_pxo_hdmi_map,
1403 },
1404 .freq_tbl = clk_tbl_tv,
1405 .clkr = {
1406 .enable_reg = 0x00ec,
1407 .enable_mask = BIT(2),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "tv_src",
1410 .parent_names = mmcc_pxo_hdmi,
1411 .num_parents = 2,
1412 .ops = &clk_rcg_bypass_ops,
1413 .flags = CLK_SET_RATE_PARENT,
1414 },
1415 },
1416 };
1417
1418 static const char *tv_src_name[] = { "tv_src" };
1419
1420 static struct clk_branch tv_enc_clk = {
1421 .halt_reg = 0x01d4,
1422 .halt_bit = 9,
1423 .clkr = {
1424 .enable_reg = 0x00ec,
1425 .enable_mask = BIT(8),
1426 .hw.init = &(struct clk_init_data){
1427 .parent_names = tv_src_name,
1428 .num_parents = 1,
1429 .name = "tv_enc_clk",
1430 .ops = &clk_branch_ops,
1431 .flags = CLK_SET_RATE_PARENT,
1432 },
1433 },
1434 };
1435
1436 static struct clk_branch tv_dac_clk = {
1437 .halt_reg = 0x01d4,
1438 .halt_bit = 10,
1439 .clkr = {
1440 .enable_reg = 0x00ec,
1441 .enable_mask = BIT(10),
1442 .hw.init = &(struct clk_init_data){
1443 .parent_names = tv_src_name,
1444 .num_parents = 1,
1445 .name = "tv_dac_clk",
1446 .ops = &clk_branch_ops,
1447 .flags = CLK_SET_RATE_PARENT,
1448 },
1449 },
1450 };
1451
1452 static struct clk_branch mdp_tv_clk = {
1453 .halt_reg = 0x01d4,
1454 .halt_bit = 12,
1455 .clkr = {
1456 .enable_reg = 0x00ec,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .parent_names = tv_src_name,
1460 .num_parents = 1,
1461 .name = "mdp_tv_clk",
1462 .ops = &clk_branch_ops,
1463 .flags = CLK_SET_RATE_PARENT,
1464 },
1465 },
1466 };
1467
1468 static struct clk_branch hdmi_tv_clk = {
1469 .halt_reg = 0x01d4,
1470 .halt_bit = 11,
1471 .clkr = {
1472 .enable_reg = 0x00ec,
1473 .enable_mask = BIT(12),
1474 .hw.init = &(struct clk_init_data){
1475 .parent_names = tv_src_name,
1476 .num_parents = 1,
1477 .name = "hdmi_tv_clk",
1478 .ops = &clk_branch_ops,
1479 .flags = CLK_SET_RATE_PARENT,
1480 },
1481 },
1482 };
1483
1484 static struct clk_branch rgb_tv_clk = {
1485 .halt_reg = 0x0240,
1486 .halt_bit = 27,
1487 .clkr = {
1488 .enable_reg = 0x0124,
1489 .enable_mask = BIT(14),
1490 .hw.init = &(struct clk_init_data){
1491 .parent_names = tv_src_name,
1492 .num_parents = 1,
1493 .name = "rgb_tv_clk",
1494 .ops = &clk_branch_ops,
1495 .flags = CLK_SET_RATE_PARENT,
1496 },
1497 },
1498 };
1499
1500 static struct clk_branch npl_tv_clk = {
1501 .halt_reg = 0x0240,
1502 .halt_bit = 26,
1503 .clkr = {
1504 .enable_reg = 0x0124,
1505 .enable_mask = BIT(16),
1506 .hw.init = &(struct clk_init_data){
1507 .parent_names = tv_src_name,
1508 .num_parents = 1,
1509 .name = "npl_tv_clk",
1510 .ops = &clk_branch_ops,
1511 .flags = CLK_SET_RATE_PARENT,
1512 },
1513 },
1514 };
1515
1516 static struct clk_branch hdmi_app_clk = {
1517 .halt_reg = 0x01cc,
1518 .halt_bit = 25,
1519 .clkr = {
1520 .enable_reg = 0x005c,
1521 .enable_mask = BIT(11),
1522 .hw.init = &(struct clk_init_data){
1523 .parent_names = (const char *[]){ "pxo" },
1524 .num_parents = 1,
1525 .name = "hdmi_app_clk",
1526 .ops = &clk_branch_ops,
1527 },
1528 },
1529 };
1530
1531 static struct freq_tbl clk_tbl_vcodec[] = {
1532 F_MN( 27000000, P_PXO, 1, 0),
1533 F_MN( 32000000, P_PLL8, 1, 12),
1534 F_MN( 48000000, P_PLL8, 1, 8),
1535 F_MN( 54860000, P_PLL8, 1, 7),
1536 F_MN( 96000000, P_PLL8, 1, 4),
1537 F_MN(133330000, P_PLL2, 1, 6),
1538 F_MN(200000000, P_PLL2, 1, 4),
1539 F_MN(228570000, P_PLL2, 2, 7),
1540 F_MN(266670000, P_PLL2, 1, 3),
1541 { }
1542 };
1543
1544 static struct clk_dyn_rcg vcodec_src = {
1545 .ns_reg = 0x0100,
1546 .md_reg[0] = 0x00fc,
1547 .md_reg[1] = 0x0128,
1548 .mn[0] = {
1549 .mnctr_en_bit = 5,
1550 .mnctr_reset_bit = 31,
1551 .mnctr_mode_shift = 6,
1552 .n_val_shift = 11,
1553 .m_val_shift = 8,
1554 .width = 8,
1555 },
1556 .mn[1] = {
1557 .mnctr_en_bit = 10,
1558 .mnctr_reset_bit = 30,
1559 .mnctr_mode_shift = 11,
1560 .n_val_shift = 19,
1561 .m_val_shift = 8,
1562 .width = 8,
1563 },
1564 .s[0] = {
1565 .src_sel_shift = 27,
1566 .parent_map = mmcc_pxo_pll8_pll2_map,
1567 },
1568 .s[1] = {
1569 .src_sel_shift = 0,
1570 .parent_map = mmcc_pxo_pll8_pll2_map,
1571 },
1572 .mux_sel_bit = 13,
1573 .freq_tbl = clk_tbl_vcodec,
1574 .clkr = {
1575 .enable_reg = 0x00f8,
1576 .enable_mask = BIT(2),
1577 .hw.init = &(struct clk_init_data){
1578 .name = "vcodec_src",
1579 .parent_names = mmcc_pxo_pll8_pll2,
1580 .num_parents = 3,
1581 .ops = &clk_dyn_rcg_ops,
1582 },
1583 },
1584 };
1585
1586 static struct clk_branch vcodec_clk = {
1587 .halt_reg = 0x01d0,
1588 .halt_bit = 29,
1589 .clkr = {
1590 .enable_reg = 0x00f8,
1591 .enable_mask = BIT(0),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "vcodec_clk",
1594 .parent_names = (const char *[]){ "vcodec_src" },
1595 .num_parents = 1,
1596 .ops = &clk_branch_ops,
1597 .flags = CLK_SET_RATE_PARENT,
1598 },
1599 },
1600 };
1601
1602 static struct freq_tbl clk_tbl_vpe[] = {
1603 { 27000000, P_PXO, 1 },
1604 { 34909000, P_PLL8, 11 },
1605 { 38400000, P_PLL8, 10 },
1606 { 64000000, P_PLL8, 6 },
1607 { 76800000, P_PLL8, 5 },
1608 { 96000000, P_PLL8, 4 },
1609 { 100000000, P_PLL2, 8 },
1610 { 160000000, P_PLL2, 5 },
1611 { }
1612 };
1613
1614 static struct clk_rcg vpe_src = {
1615 .ns_reg = 0x0118,
1616 .p = {
1617 .pre_div_shift = 12,
1618 .pre_div_width = 4,
1619 },
1620 .s = {
1621 .src_sel_shift = 0,
1622 .parent_map = mmcc_pxo_pll8_pll2_map,
1623 },
1624 .freq_tbl = clk_tbl_vpe,
1625 .clkr = {
1626 .enable_reg = 0x0110,
1627 .enable_mask = BIT(2),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "vpe_src",
1630 .parent_names = mmcc_pxo_pll8_pll2,
1631 .num_parents = 3,
1632 .ops = &clk_rcg_ops,
1633 },
1634 },
1635 };
1636
1637 static struct clk_branch vpe_clk = {
1638 .halt_reg = 0x01c8,
1639 .halt_bit = 28,
1640 .clkr = {
1641 .enable_reg = 0x0110,
1642 .enable_mask = BIT(0),
1643 .hw.init = &(struct clk_init_data){
1644 .name = "vpe_clk",
1645 .parent_names = (const char *[]){ "vpe_src" },
1646 .num_parents = 1,
1647 .ops = &clk_branch_ops,
1648 .flags = CLK_SET_RATE_PARENT,
1649 },
1650 },
1651 };
1652
1653 static struct freq_tbl clk_tbl_vfe[] = {
1654 { 13960000, P_PLL8, 1, 2, 55 },
1655 { 27000000, P_PXO, 1, 0, 0 },
1656 { 36570000, P_PLL8, 1, 2, 21 },
1657 { 38400000, P_PLL8, 2, 1, 5 },
1658 { 45180000, P_PLL8, 1, 2, 17 },
1659 { 48000000, P_PLL8, 2, 1, 4 },
1660 { 54860000, P_PLL8, 1, 1, 7 },
1661 { 64000000, P_PLL8, 2, 1, 3 },
1662 { 76800000, P_PLL8, 1, 1, 5 },
1663 { 96000000, P_PLL8, 2, 1, 2 },
1664 { 109710000, P_PLL8, 1, 2, 7 },
1665 { 128000000, P_PLL8, 1, 1, 3 },
1666 { 153600000, P_PLL8, 1, 2, 5 },
1667 { 200000000, P_PLL2, 2, 1, 2 },
1668 { 228570000, P_PLL2, 1, 2, 7 },
1669 { 266667000, P_PLL2, 1, 1, 3 },
1670 { 320000000, P_PLL2, 1, 2, 5 },
1671 { }
1672 };
1673
1674 static struct clk_rcg vfe_src = {
1675 .ns_reg = 0x0108,
1676 .mn = {
1677 .mnctr_en_bit = 5,
1678 .mnctr_reset_bit = 7,
1679 .mnctr_mode_shift = 6,
1680 .n_val_shift = 16,
1681 .m_val_shift = 8,
1682 .width = 8,
1683 },
1684 .p = {
1685 .pre_div_shift = 10,
1686 .pre_div_width = 1,
1687 },
1688 .s = {
1689 .src_sel_shift = 0,
1690 .parent_map = mmcc_pxo_pll8_pll2_map,
1691 },
1692 .freq_tbl = clk_tbl_vfe,
1693 .clkr = {
1694 .enable_reg = 0x0104,
1695 .enable_mask = BIT(2),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "vfe_src",
1698 .parent_names = mmcc_pxo_pll8_pll2,
1699 .num_parents = 3,
1700 .ops = &clk_rcg_ops,
1701 },
1702 },
1703 };
1704
1705 static struct clk_branch vfe_clk = {
1706 .halt_reg = 0x01cc,
1707 .halt_bit = 6,
1708 .clkr = {
1709 .enable_reg = 0x0104,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "vfe_clk",
1713 .parent_names = (const char *[]){ "vfe_src" },
1714 .num_parents = 1,
1715 .ops = &clk_branch_ops,
1716 .flags = CLK_SET_RATE_PARENT,
1717 },
1718 },
1719 };
1720
1721 static struct clk_branch vfe_csi_clk = {
1722 .halt_reg = 0x01cc,
1723 .halt_bit = 8,
1724 .clkr = {
1725 .enable_reg = 0x0104,
1726 .enable_mask = BIT(12),
1727 .hw.init = &(struct clk_init_data){
1728 .parent_names = (const char *[]){ "vfe_src" },
1729 .num_parents = 1,
1730 .name = "vfe_csi_clk",
1731 .ops = &clk_branch_ops,
1732 .flags = CLK_SET_RATE_PARENT,
1733 },
1734 },
1735 };
1736
1737 static struct clk_branch gmem_axi_clk = {
1738 .halt_reg = 0x01d8,
1739 .halt_bit = 6,
1740 .clkr = {
1741 .enable_reg = 0x0018,
1742 .enable_mask = BIT(24),
1743 .hw.init = &(struct clk_init_data){
1744 .name = "gmem_axi_clk",
1745 .ops = &clk_branch_ops,
1746 .flags = CLK_IS_ROOT,
1747 },
1748 },
1749 };
1750
1751 static struct clk_branch ijpeg_axi_clk = {
1752 .hwcg_reg = 0x0018,
1753 .hwcg_bit = 11,
1754 .halt_reg = 0x01d8,
1755 .halt_bit = 4,
1756 .clkr = {
1757 .enable_reg = 0x0018,
1758 .enable_mask = BIT(21),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "ijpeg_axi_clk",
1761 .ops = &clk_branch_ops,
1762 .flags = CLK_IS_ROOT,
1763 },
1764 },
1765 };
1766
1767 static struct clk_branch mmss_imem_axi_clk = {
1768 .hwcg_reg = 0x0018,
1769 .hwcg_bit = 15,
1770 .halt_reg = 0x01d8,
1771 .halt_bit = 7,
1772 .clkr = {
1773 .enable_reg = 0x0018,
1774 .enable_mask = BIT(22),
1775 .hw.init = &(struct clk_init_data){
1776 .name = "mmss_imem_axi_clk",
1777 .ops = &clk_branch_ops,
1778 .flags = CLK_IS_ROOT,
1779 },
1780 },
1781 };
1782
1783 static struct clk_branch jpegd_axi_clk = {
1784 .halt_reg = 0x01d8,
1785 .halt_bit = 5,
1786 .clkr = {
1787 .enable_reg = 0x0018,
1788 .enable_mask = BIT(25),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "jpegd_axi_clk",
1791 .ops = &clk_branch_ops,
1792 .flags = CLK_IS_ROOT,
1793 },
1794 },
1795 };
1796
1797 static struct clk_branch vcodec_axi_b_clk = {
1798 .hwcg_reg = 0x0114,
1799 .hwcg_bit = 22,
1800 .halt_reg = 0x01e8,
1801 .halt_bit = 25,
1802 .clkr = {
1803 .enable_reg = 0x0114,
1804 .enable_mask = BIT(23),
1805 .hw.init = &(struct clk_init_data){
1806 .name = "vcodec_axi_b_clk",
1807 .ops = &clk_branch_ops,
1808 .flags = CLK_IS_ROOT,
1809 },
1810 },
1811 };
1812
1813 static struct clk_branch vcodec_axi_a_clk = {
1814 .hwcg_reg = 0x0114,
1815 .hwcg_bit = 24,
1816 .halt_reg = 0x01e8,
1817 .halt_bit = 26,
1818 .clkr = {
1819 .enable_reg = 0x0114,
1820 .enable_mask = BIT(25),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "vcodec_axi_a_clk",
1823 .ops = &clk_branch_ops,
1824 .flags = CLK_IS_ROOT,
1825 },
1826 },
1827 };
1828
1829 static struct clk_branch vcodec_axi_clk = {
1830 .hwcg_reg = 0x0018,
1831 .hwcg_bit = 13,
1832 .halt_reg = 0x01d8,
1833 .halt_bit = 3,
1834 .clkr = {
1835 .enable_reg = 0x0018,
1836 .enable_mask = BIT(19),
1837 .hw.init = &(struct clk_init_data){
1838 .name = "vcodec_axi_clk",
1839 .ops = &clk_branch_ops,
1840 .flags = CLK_IS_ROOT,
1841 },
1842 },
1843 };
1844
1845 static struct clk_branch vfe_axi_clk = {
1846 .halt_reg = 0x01d8,
1847 .halt_bit = 0,
1848 .clkr = {
1849 .enable_reg = 0x0018,
1850 .enable_mask = BIT(18),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "vfe_axi_clk",
1853 .ops = &clk_branch_ops,
1854 .flags = CLK_IS_ROOT,
1855 },
1856 },
1857 };
1858
1859 static struct clk_branch mdp_axi_clk = {
1860 .hwcg_reg = 0x0018,
1861 .hwcg_bit = 16,
1862 .halt_reg = 0x01d8,
1863 .halt_bit = 8,
1864 .clkr = {
1865 .enable_reg = 0x0018,
1866 .enable_mask = BIT(23),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "mdp_axi_clk",
1869 .ops = &clk_branch_ops,
1870 .flags = CLK_IS_ROOT,
1871 },
1872 },
1873 };
1874
1875 static struct clk_branch rot_axi_clk = {
1876 .hwcg_reg = 0x0020,
1877 .hwcg_bit = 25,
1878 .halt_reg = 0x01d8,
1879 .halt_bit = 2,
1880 .clkr = {
1881 .enable_reg = 0x0020,
1882 .enable_mask = BIT(24),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "rot_axi_clk",
1885 .ops = &clk_branch_ops,
1886 .flags = CLK_IS_ROOT,
1887 },
1888 },
1889 };
1890
1891 static struct clk_branch vcap_axi_clk = {
1892 .halt_reg = 0x0240,
1893 .halt_bit = 20,
1894 .hwcg_reg = 0x0244,
1895 .hwcg_bit = 11,
1896 .clkr = {
1897 .enable_reg = 0x0244,
1898 .enable_mask = BIT(12),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "vcap_axi_clk",
1901 .ops = &clk_branch_ops,
1902 .flags = CLK_IS_ROOT,
1903 },
1904 },
1905 };
1906
1907 static struct clk_branch vpe_axi_clk = {
1908 .hwcg_reg = 0x0020,
1909 .hwcg_bit = 27,
1910 .halt_reg = 0x01d8,
1911 .halt_bit = 1,
1912 .clkr = {
1913 .enable_reg = 0x0020,
1914 .enable_mask = BIT(26),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "vpe_axi_clk",
1917 .ops = &clk_branch_ops,
1918 .flags = CLK_IS_ROOT,
1919 },
1920 },
1921 };
1922
1923 static struct clk_branch gfx3d_axi_clk = {
1924 .hwcg_reg = 0x0244,
1925 .hwcg_bit = 24,
1926 .halt_reg = 0x0240,
1927 .halt_bit = 30,
1928 .clkr = {
1929 .enable_reg = 0x0244,
1930 .enable_mask = BIT(25),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "gfx3d_axi_clk",
1933 .ops = &clk_branch_ops,
1934 .flags = CLK_IS_ROOT,
1935 },
1936 },
1937 };
1938
1939 static struct clk_branch amp_ahb_clk = {
1940 .halt_reg = 0x01dc,
1941 .halt_bit = 18,
1942 .clkr = {
1943 .enable_reg = 0x0008,
1944 .enable_mask = BIT(24),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "amp_ahb_clk",
1947 .ops = &clk_branch_ops,
1948 .flags = CLK_IS_ROOT,
1949 },
1950 },
1951 };
1952
1953 static struct clk_branch csi_ahb_clk = {
1954 .halt_reg = 0x01dc,
1955 .halt_bit = 16,
1956 .clkr = {
1957 .enable_reg = 0x0008,
1958 .enable_mask = BIT(7),
1959 .hw.init = &(struct clk_init_data){
1960 .name = "csi_ahb_clk",
1961 .ops = &clk_branch_ops,
1962 .flags = CLK_IS_ROOT
1963 },
1964 },
1965 };
1966
1967 static struct clk_branch dsi_m_ahb_clk = {
1968 .halt_reg = 0x01dc,
1969 .halt_bit = 19,
1970 .clkr = {
1971 .enable_reg = 0x0008,
1972 .enable_mask = BIT(9),
1973 .hw.init = &(struct clk_init_data){
1974 .name = "dsi_m_ahb_clk",
1975 .ops = &clk_branch_ops,
1976 .flags = CLK_IS_ROOT,
1977 },
1978 },
1979 };
1980
1981 static struct clk_branch dsi_s_ahb_clk = {
1982 .hwcg_reg = 0x0038,
1983 .hwcg_bit = 20,
1984 .halt_reg = 0x01dc,
1985 .halt_bit = 21,
1986 .clkr = {
1987 .enable_reg = 0x0008,
1988 .enable_mask = BIT(18),
1989 .hw.init = &(struct clk_init_data){
1990 .name = "dsi_s_ahb_clk",
1991 .ops = &clk_branch_ops,
1992 .flags = CLK_IS_ROOT,
1993 },
1994 },
1995 };
1996
1997 static struct clk_branch dsi2_m_ahb_clk = {
1998 .halt_reg = 0x01d8,
1999 .halt_bit = 18,
2000 .clkr = {
2001 .enable_reg = 0x0008,
2002 .enable_mask = BIT(17),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "dsi2_m_ahb_clk",
2005 .ops = &clk_branch_ops,
2006 .flags = CLK_IS_ROOT
2007 },
2008 },
2009 };
2010
2011 static struct clk_branch dsi2_s_ahb_clk = {
2012 .hwcg_reg = 0x0038,
2013 .hwcg_bit = 15,
2014 .halt_reg = 0x01dc,
2015 .halt_bit = 20,
2016 .clkr = {
2017 .enable_reg = 0x0008,
2018 .enable_mask = BIT(22),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "dsi2_s_ahb_clk",
2021 .ops = &clk_branch_ops,
2022 .flags = CLK_IS_ROOT,
2023 },
2024 },
2025 };
2026
2027 static struct clk_branch gfx2d0_ahb_clk = {
2028 .hwcg_reg = 0x0038,
2029 .hwcg_bit = 28,
2030 .halt_reg = 0x01dc,
2031 .halt_bit = 2,
2032 .clkr = {
2033 .enable_reg = 0x0008,
2034 .enable_mask = BIT(19),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "gfx2d0_ahb_clk",
2037 .ops = &clk_branch_ops,
2038 .flags = CLK_IS_ROOT,
2039 },
2040 },
2041 };
2042
2043 static struct clk_branch gfx2d1_ahb_clk = {
2044 .hwcg_reg = 0x0038,
2045 .hwcg_bit = 29,
2046 .halt_reg = 0x01dc,
2047 .halt_bit = 3,
2048 .clkr = {
2049 .enable_reg = 0x0008,
2050 .enable_mask = BIT(2),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "gfx2d1_ahb_clk",
2053 .ops = &clk_branch_ops,
2054 .flags = CLK_IS_ROOT,
2055 },
2056 },
2057 };
2058
2059 static struct clk_branch gfx3d_ahb_clk = {
2060 .hwcg_reg = 0x0038,
2061 .hwcg_bit = 27,
2062 .halt_reg = 0x01dc,
2063 .halt_bit = 4,
2064 .clkr = {
2065 .enable_reg = 0x0008,
2066 .enable_mask = BIT(3),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "gfx3d_ahb_clk",
2069 .ops = &clk_branch_ops,
2070 .flags = CLK_IS_ROOT,
2071 },
2072 },
2073 };
2074
2075 static struct clk_branch hdmi_m_ahb_clk = {
2076 .hwcg_reg = 0x0038,
2077 .hwcg_bit = 21,
2078 .halt_reg = 0x01dc,
2079 .halt_bit = 5,
2080 .clkr = {
2081 .enable_reg = 0x0008,
2082 .enable_mask = BIT(14),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "hdmi_m_ahb_clk",
2085 .ops = &clk_branch_ops,
2086 .flags = CLK_IS_ROOT,
2087 },
2088 },
2089 };
2090
2091 static struct clk_branch hdmi_s_ahb_clk = {
2092 .hwcg_reg = 0x0038,
2093 .hwcg_bit = 22,
2094 .halt_reg = 0x01dc,
2095 .halt_bit = 6,
2096 .clkr = {
2097 .enable_reg = 0x0008,
2098 .enable_mask = BIT(4),
2099 .hw.init = &(struct clk_init_data){
2100 .name = "hdmi_s_ahb_clk",
2101 .ops = &clk_branch_ops,
2102 .flags = CLK_IS_ROOT,
2103 },
2104 },
2105 };
2106
2107 static struct clk_branch ijpeg_ahb_clk = {
2108 .halt_reg = 0x01dc,
2109 .halt_bit = 9,
2110 .clkr = {
2111 .enable_reg = 0x0008,
2112 .enable_mask = BIT(5),
2113 .hw.init = &(struct clk_init_data){
2114 .name = "ijpeg_ahb_clk",
2115 .ops = &clk_branch_ops,
2116 .flags = CLK_IS_ROOT
2117 },
2118 },
2119 };
2120
2121 static struct clk_branch mmss_imem_ahb_clk = {
2122 .hwcg_reg = 0x0038,
2123 .hwcg_bit = 12,
2124 .halt_reg = 0x01dc,
2125 .halt_bit = 10,
2126 .clkr = {
2127 .enable_reg = 0x0008,
2128 .enable_mask = BIT(6),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "mmss_imem_ahb_clk",
2131 .ops = &clk_branch_ops,
2132 .flags = CLK_IS_ROOT
2133 },
2134 },
2135 };
2136
2137 static struct clk_branch jpegd_ahb_clk = {
2138 .halt_reg = 0x01dc,
2139 .halt_bit = 7,
2140 .clkr = {
2141 .enable_reg = 0x0008,
2142 .enable_mask = BIT(21),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "jpegd_ahb_clk",
2145 .ops = &clk_branch_ops,
2146 .flags = CLK_IS_ROOT,
2147 },
2148 },
2149 };
2150
2151 static struct clk_branch mdp_ahb_clk = {
2152 .halt_reg = 0x01dc,
2153 .halt_bit = 11,
2154 .clkr = {
2155 .enable_reg = 0x0008,
2156 .enable_mask = BIT(10),
2157 .hw.init = &(struct clk_init_data){
2158 .name = "mdp_ahb_clk",
2159 .ops = &clk_branch_ops,
2160 .flags = CLK_IS_ROOT,
2161 },
2162 },
2163 };
2164
2165 static struct clk_branch rot_ahb_clk = {
2166 .halt_reg = 0x01dc,
2167 .halt_bit = 13,
2168 .clkr = {
2169 .enable_reg = 0x0008,
2170 .enable_mask = BIT(12),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "rot_ahb_clk",
2173 .ops = &clk_branch_ops,
2174 .flags = CLK_IS_ROOT
2175 },
2176 },
2177 };
2178
2179 static struct clk_branch smmu_ahb_clk = {
2180 .hwcg_reg = 0x0008,
2181 .hwcg_bit = 26,
2182 .halt_reg = 0x01dc,
2183 .halt_bit = 22,
2184 .clkr = {
2185 .enable_reg = 0x0008,
2186 .enable_mask = BIT(15),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "smmu_ahb_clk",
2189 .ops = &clk_branch_ops,
2190 .flags = CLK_IS_ROOT,
2191 },
2192 },
2193 };
2194
2195 static struct clk_branch tv_enc_ahb_clk = {
2196 .halt_reg = 0x01dc,
2197 .halt_bit = 23,
2198 .clkr = {
2199 .enable_reg = 0x0008,
2200 .enable_mask = BIT(25),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "tv_enc_ahb_clk",
2203 .ops = &clk_branch_ops,
2204 .flags = CLK_IS_ROOT,
2205 },
2206 },
2207 };
2208
2209 static struct clk_branch vcap_ahb_clk = {
2210 .halt_reg = 0x0240,
2211 .halt_bit = 23,
2212 .clkr = {
2213 .enable_reg = 0x0248,
2214 .enable_mask = BIT(1),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "vcap_ahb_clk",
2217 .ops = &clk_branch_ops,
2218 .flags = CLK_IS_ROOT,
2219 },
2220 },
2221 };
2222
2223 static struct clk_branch vcodec_ahb_clk = {
2224 .hwcg_reg = 0x0038,
2225 .hwcg_bit = 26,
2226 .halt_reg = 0x01dc,
2227 .halt_bit = 12,
2228 .clkr = {
2229 .enable_reg = 0x0008,
2230 .enable_mask = BIT(11),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "vcodec_ahb_clk",
2233 .ops = &clk_branch_ops,
2234 .flags = CLK_IS_ROOT,
2235 },
2236 },
2237 };
2238
2239 static struct clk_branch vfe_ahb_clk = {
2240 .halt_reg = 0x01dc,
2241 .halt_bit = 14,
2242 .clkr = {
2243 .enable_reg = 0x0008,
2244 .enable_mask = BIT(13),
2245 .hw.init = &(struct clk_init_data){
2246 .name = "vfe_ahb_clk",
2247 .ops = &clk_branch_ops,
2248 .flags = CLK_IS_ROOT,
2249 },
2250 },
2251 };
2252
2253 static struct clk_branch vpe_ahb_clk = {
2254 .halt_reg = 0x01dc,
2255 .halt_bit = 15,
2256 .clkr = {
2257 .enable_reg = 0x0008,
2258 .enable_mask = BIT(16),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "vpe_ahb_clk",
2261 .ops = &clk_branch_ops,
2262 .flags = CLK_IS_ROOT,
2263 },
2264 },
2265 };
2266
2267 static struct clk_regmap *mmcc_msm8960_clks[] = {
2268 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2269 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2270 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2271 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2272 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2273 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2274 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2275 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2276 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2277 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2278 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2279 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2280 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2281 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2282 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2283 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2284 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2285 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2286 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2287 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2288 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2289 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2290 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2291 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2292 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2293 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2294 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2295 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2296 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2297 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2298 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2299 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2300 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2301 [CSI0_SRC] = &csi0_src.clkr,
2302 [CSI0_CLK] = &csi0_clk.clkr,
2303 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2304 [CSI1_SRC] = &csi1_src.clkr,
2305 [CSI1_CLK] = &csi1_clk.clkr,
2306 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2307 [CSI2_SRC] = &csi2_src.clkr,
2308 [CSI2_CLK] = &csi2_clk.clkr,
2309 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2310 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2311 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2312 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2313 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2314 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2315 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2316 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2317 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2318 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2319 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2320 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2321 [GFX3D_SRC] = &gfx3d_src.clkr,
2322 [GFX3D_CLK] = &gfx3d_clk.clkr,
2323 [IJPEG_SRC] = &ijpeg_src.clkr,
2324 [IJPEG_CLK] = &ijpeg_clk.clkr,
2325 [JPEGD_SRC] = &jpegd_src.clkr,
2326 [JPEGD_CLK] = &jpegd_clk.clkr,
2327 [MDP_SRC] = &mdp_src.clkr,
2328 [MDP_CLK] = &mdp_clk.clkr,
2329 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2330 [ROT_SRC] = &rot_src.clkr,
2331 [ROT_CLK] = &rot_clk.clkr,
2332 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2333 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2334 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2335 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2336 [TV_SRC] = &tv_src.clkr,
2337 [VCODEC_SRC] = &vcodec_src.clkr,
2338 [VCODEC_CLK] = &vcodec_clk.clkr,
2339 [VFE_SRC] = &vfe_src.clkr,
2340 [VFE_CLK] = &vfe_clk.clkr,
2341 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2342 [VPE_SRC] = &vpe_src.clkr,
2343 [VPE_CLK] = &vpe_clk.clkr,
2344 [CAMCLK0_SRC] = &camclk0_src.clkr,
2345 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2346 [CAMCLK1_SRC] = &camclk1_src.clkr,
2347 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2348 [CAMCLK2_SRC] = &camclk2_src.clkr,
2349 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2350 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2351 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2352 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2353 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2354 [PLL2] = &pll2.clkr,
2355 };
2356
2357 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2358 [VPE_AXI_RESET] = { 0x0208, 15 },
2359 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2360 [MPD_AXI_RESET] = { 0x0208, 13 },
2361 [VFE_AXI_RESET] = { 0x0208, 9 },
2362 [SP_AXI_RESET] = { 0x0208, 8 },
2363 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2364 [ROT_AXI_RESET] = { 0x0208, 6 },
2365 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2366 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2367 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2368 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2369 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2370 [FAB_S0_AXI_RESET] = { 0x0208 },
2371 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2372 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2373 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2374 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2375 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2376 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2377 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2378 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2379 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2380 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2381 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2382 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2383 [APU_AHB_RESET] = { 0x020c, 18 },
2384 [CSI_AHB_RESET] = { 0x020c, 17 },
2385 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2386 [VPE_AHB_RESET] = { 0x020c, 14 },
2387 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2388 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2389 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2390 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2391 [HDMI_AHB_RESET] = { 0x020c, 9 },
2392 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2393 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2394 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2395 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2396 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2397 [MDP_AHB_RESET] = { 0x020c, 3 },
2398 [ROT_AHB_RESET] = { 0x020c, 2 },
2399 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2400 [VFE_AHB_RESET] = { 0x020c, 0 },
2401 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2402 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2403 [CSIPHY2_RESET] = { 0x0210, 29 },
2404 [CSI_PIX1_RESET] = { 0x0210, 28 },
2405 [CSIPHY0_RESET] = { 0x0210, 27 },
2406 [CSIPHY1_RESET] = { 0x0210, 26 },
2407 [DSI2_RESET] = { 0x0210, 25 },
2408 [VFE_CSI_RESET] = { 0x0210, 24 },
2409 [MDP_RESET] = { 0x0210, 21 },
2410 [AMP_RESET] = { 0x0210, 20 },
2411 [JPEGD_RESET] = { 0x0210, 19 },
2412 [CSI1_RESET] = { 0x0210, 18 },
2413 [VPE_RESET] = { 0x0210, 17 },
2414 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2415 [VFE_RESET] = { 0x0210, 15 },
2416 [GFX2D0_RESET] = { 0x0210, 14 },
2417 [GFX2D1_RESET] = { 0x0210, 13 },
2418 [GFX3D_RESET] = { 0x0210, 12 },
2419 [HDMI_RESET] = { 0x0210, 11 },
2420 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2421 [IJPEG_RESET] = { 0x0210, 9 },
2422 [CSI0_RESET] = { 0x0210, 8 },
2423 [DSI_RESET] = { 0x0210, 7 },
2424 [VCODEC_RESET] = { 0x0210, 6 },
2425 [MDP_TV_RESET] = { 0x0210, 4 },
2426 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2427 [ROT_RESET] = { 0x0210, 2 },
2428 [TV_HDMI_RESET] = { 0x0210, 1 },
2429 [TV_ENC_RESET] = { 0x0210 },
2430 [CSI2_RESET] = { 0x0214, 2 },
2431 [CSI_RDI1_RESET] = { 0x0214, 1 },
2432 [CSI_RDI2_RESET] = { 0x0214 },
2433 };
2434
2435 static struct clk_regmap *mmcc_apq8064_clks[] = {
2436 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2437 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2438 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2439 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2440 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2441 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2442 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2443 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2444 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2445 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2446 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2447 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2448 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2449 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2450 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2451 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2452 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2453 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2454 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2455 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2456 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2457 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2458 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2459 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2460 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2461 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2462 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2463 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2464 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2465 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2466 [CSI0_SRC] = &csi0_src.clkr,
2467 [CSI0_CLK] = &csi0_clk.clkr,
2468 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2469 [CSI1_SRC] = &csi1_src.clkr,
2470 [CSI1_CLK] = &csi1_clk.clkr,
2471 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2472 [CSI2_SRC] = &csi2_src.clkr,
2473 [CSI2_CLK] = &csi2_clk.clkr,
2474 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2475 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2476 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2477 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2478 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2479 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2480 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2481 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2482 [GFX3D_SRC] = &gfx3d_src.clkr,
2483 [GFX3D_CLK] = &gfx3d_clk.clkr,
2484 [IJPEG_SRC] = &ijpeg_src.clkr,
2485 [IJPEG_CLK] = &ijpeg_clk.clkr,
2486 [JPEGD_SRC] = &jpegd_src.clkr,
2487 [JPEGD_CLK] = &jpegd_clk.clkr,
2488 [MDP_SRC] = &mdp_src.clkr,
2489 [MDP_CLK] = &mdp_clk.clkr,
2490 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2491 [ROT_SRC] = &rot_src.clkr,
2492 [ROT_CLK] = &rot_clk.clkr,
2493 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2494 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2495 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2496 [TV_SRC] = &tv_src.clkr,
2497 [VCODEC_SRC] = &vcodec_src.clkr,
2498 [VCODEC_CLK] = &vcodec_clk.clkr,
2499 [VFE_SRC] = &vfe_src.clkr,
2500 [VFE_CLK] = &vfe_clk.clkr,
2501 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2502 [VPE_SRC] = &vpe_src.clkr,
2503 [VPE_CLK] = &vpe_clk.clkr,
2504 [CAMCLK0_SRC] = &camclk0_src.clkr,
2505 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2506 [CAMCLK1_SRC] = &camclk1_src.clkr,
2507 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2508 [CAMCLK2_SRC] = &camclk2_src.clkr,
2509 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2510 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2511 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2512 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2513 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2514 [PLL2] = &pll2.clkr,
2515 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2516 [NPL_TV_CLK] = &npl_tv_clk.clkr,
2517 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2518 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2519 [VCAP_SRC] = &vcap_src.clkr,
2520 [VCAP_CLK] = &vcap_clk.clkr,
2521 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2522 [PLL15] = &pll15.clkr,
2523 };
2524
2525 static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2526 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2527 [VCAP_AXI_RESET] = { 0x0208, 16 },
2528 [VPE_AXI_RESET] = { 0x0208, 15 },
2529 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2530 [MPD_AXI_RESET] = { 0x0208, 13 },
2531 [VFE_AXI_RESET] = { 0x0208, 9 },
2532 [SP_AXI_RESET] = { 0x0208, 8 },
2533 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2534 [ROT_AXI_RESET] = { 0x0208, 6 },
2535 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2536 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2537 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2538 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2539 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2540 [FAB_S0_AXI_RESET] = { 0x0208 },
2541 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2542 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2543 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2544 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2545 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2546 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2547 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2548 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2549 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2550 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2551 [APU_AHB_RESET] = { 0x020c, 18 },
2552 [CSI_AHB_RESET] = { 0x020c, 17 },
2553 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2554 [VPE_AHB_RESET] = { 0x020c, 14 },
2555 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2556 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2557 [HDMI_AHB_RESET] = { 0x020c, 9 },
2558 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2559 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2560 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2561 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2562 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2563 [MDP_AHB_RESET] = { 0x020c, 3 },
2564 [ROT_AHB_RESET] = { 0x020c, 2 },
2565 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2566 [VFE_AHB_RESET] = { 0x020c, 0 },
2567 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2568 [VCAP_AHB_RESET] = { 0x0200, 2 },
2569 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2570 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2571 [CSIPHY2_RESET] = { 0x0210, 31 },
2572 [CSI_PIX1_RESET] = { 0x0210, 30 },
2573 [CSIPHY0_RESET] = { 0x0210, 29 },
2574 [CSIPHY1_RESET] = { 0x0210, 28 },
2575 [CSI_RDI_RESET] = { 0x0210, 27 },
2576 [CSI_PIX_RESET] = { 0x0210, 26 },
2577 [DSI2_RESET] = { 0x0210, 25 },
2578 [VFE_CSI_RESET] = { 0x0210, 24 },
2579 [MDP_RESET] = { 0x0210, 21 },
2580 [AMP_RESET] = { 0x0210, 20 },
2581 [JPEGD_RESET] = { 0x0210, 19 },
2582 [CSI1_RESET] = { 0x0210, 18 },
2583 [VPE_RESET] = { 0x0210, 17 },
2584 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2585 [VFE_RESET] = { 0x0210, 15 },
2586 [GFX3D_RESET] = { 0x0210, 12 },
2587 [HDMI_RESET] = { 0x0210, 11 },
2588 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2589 [IJPEG_RESET] = { 0x0210, 9 },
2590 [CSI0_RESET] = { 0x0210, 8 },
2591 [DSI_RESET] = { 0x0210, 7 },
2592 [VCODEC_RESET] = { 0x0210, 6 },
2593 [MDP_TV_RESET] = { 0x0210, 4 },
2594 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2595 [ROT_RESET] = { 0x0210, 2 },
2596 [TV_HDMI_RESET] = { 0x0210, 1 },
2597 [VCAP_NPL_RESET] = { 0x0214, 4 },
2598 [VCAP_RESET] = { 0x0214, 3 },
2599 [CSI2_RESET] = { 0x0214, 2 },
2600 [CSI_RDI1_RESET] = { 0x0214, 1 },
2601 [CSI_RDI2_RESET] = { 0x0214 },
2602 };
2603
2604 static const struct regmap_config mmcc_msm8960_regmap_config = {
2605 .reg_bits = 32,
2606 .reg_stride = 4,
2607 .val_bits = 32,
2608 .max_register = 0x334,
2609 .fast_io = true,
2610 };
2611
2612 static const struct regmap_config mmcc_apq8064_regmap_config = {
2613 .reg_bits = 32,
2614 .reg_stride = 4,
2615 .val_bits = 32,
2616 .max_register = 0x350,
2617 .fast_io = true,
2618 };
2619
2620 static const struct qcom_cc_desc mmcc_msm8960_desc = {
2621 .config = &mmcc_msm8960_regmap_config,
2622 .clks = mmcc_msm8960_clks,
2623 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2624 .resets = mmcc_msm8960_resets,
2625 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2626 };
2627
2628 static const struct qcom_cc_desc mmcc_apq8064_desc = {
2629 .config = &mmcc_apq8064_regmap_config,
2630 .clks = mmcc_apq8064_clks,
2631 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
2632 .resets = mmcc_apq8064_resets,
2633 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
2634 };
2635
2636 static const struct of_device_id mmcc_msm8960_match_table[] = {
2637 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
2638 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
2639 { }
2640 };
2641 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2642
2643 static int mmcc_msm8960_probe(struct platform_device *pdev)
2644 {
2645 const struct of_device_id *match;
2646 struct regmap *regmap;
2647 bool is_8064;
2648 struct device *dev = &pdev->dev;
2649
2650 match = of_match_device(mmcc_msm8960_match_table, dev);
2651 if (!match)
2652 return -EINVAL;
2653
2654 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
2655 if (is_8064) {
2656 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
2657 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
2658 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2659 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2660 }
2661
2662 regmap = qcom_cc_map(pdev, match->data);
2663 if (IS_ERR(regmap))
2664 return PTR_ERR(regmap);
2665
2666 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
2667
2668 return qcom_cc_really_probe(pdev, match->data, regmap);
2669 }
2670
2671 static int mmcc_msm8960_remove(struct platform_device *pdev)
2672 {
2673 qcom_cc_remove(pdev);
2674 return 0;
2675 }
2676
2677 static struct platform_driver mmcc_msm8960_driver = {
2678 .probe = mmcc_msm8960_probe,
2679 .remove = mmcc_msm8960_remove,
2680 .driver = {
2681 .name = "mmcc-msm8960",
2682 .owner = THIS_MODULE,
2683 .of_match_table = mmcc_msm8960_match_table,
2684 },
2685 };
2686
2687 module_platform_driver(mmcc_msm8960_driver);
2688
2689 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2690 MODULE_LICENSE("GPL v2");
2691 MODULE_ALIAS("platform:mmcc-msm8960");
Linux kernel - Deliverables
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