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clk: samsung: exynos5433: Constify all clock initializers
[deliverable/linux.git] / drivers / clk / samsung / clk-exynos5433.c
1 /*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5443 SoC.
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/of.h>
14
15 #include <dt-bindings/clock/exynos5433.h>
16
17 #include "clk.h"
18 #include "clk-pll.h"
19
20 /*
21 * Register offset definitions for CMU_TOP
22 */
23 #define ISP_PLL_LOCK 0x0000
24 #define AUD_PLL_LOCK 0x0004
25 #define ISP_PLL_CON0 0x0100
26 #define ISP_PLL_CON1 0x0104
27 #define ISP_PLL_FREQ_DET 0x0108
28 #define AUD_PLL_CON0 0x0110
29 #define AUD_PLL_CON1 0x0114
30 #define AUD_PLL_CON2 0x0118
31 #define AUD_PLL_FREQ_DET 0x011c
32 #define MUX_SEL_TOP0 0x0200
33 #define MUX_SEL_TOP1 0x0204
34 #define MUX_SEL_TOP2 0x0208
35 #define MUX_SEL_TOP3 0x020c
36 #define MUX_SEL_TOP4 0x0210
37 #define MUX_SEL_TOP_MSCL 0x0220
38 #define MUX_SEL_TOP_CAM1 0x0224
39 #define MUX_SEL_TOP_DISP 0x0228
40 #define MUX_SEL_TOP_FSYS0 0x0230
41 #define MUX_SEL_TOP_FSYS1 0x0234
42 #define MUX_SEL_TOP_PERIC0 0x0238
43 #define MUX_SEL_TOP_PERIC1 0x023c
44 #define MUX_ENABLE_TOP0 0x0300
45 #define MUX_ENABLE_TOP1 0x0304
46 #define MUX_ENABLE_TOP2 0x0308
47 #define MUX_ENABLE_TOP3 0x030c
48 #define MUX_ENABLE_TOP4 0x0310
49 #define MUX_ENABLE_TOP_MSCL 0x0320
50 #define MUX_ENABLE_TOP_CAM1 0x0324
51 #define MUX_ENABLE_TOP_DISP 0x0328
52 #define MUX_ENABLE_TOP_FSYS0 0x0330
53 #define MUX_ENABLE_TOP_FSYS1 0x0334
54 #define MUX_ENABLE_TOP_PERIC0 0x0338
55 #define MUX_ENABLE_TOP_PERIC1 0x033c
56 #define MUX_STAT_TOP0 0x0400
57 #define MUX_STAT_TOP1 0x0404
58 #define MUX_STAT_TOP2 0x0408
59 #define MUX_STAT_TOP3 0x040c
60 #define MUX_STAT_TOP4 0x0410
61 #define MUX_STAT_TOP_MSCL 0x0420
62 #define MUX_STAT_TOP_CAM1 0x0424
63 #define MUX_STAT_TOP_FSYS0 0x0430
64 #define MUX_STAT_TOP_FSYS1 0x0434
65 #define MUX_STAT_TOP_PERIC0 0x0438
66 #define MUX_STAT_TOP_PERIC1 0x043c
67 #define DIV_TOP0 0x0600
68 #define DIV_TOP1 0x0604
69 #define DIV_TOP2 0x0608
70 #define DIV_TOP3 0x060c
71 #define DIV_TOP4 0x0610
72 #define DIV_TOP_MSCL 0x0618
73 #define DIV_TOP_CAM10 0x061c
74 #define DIV_TOP_CAM11 0x0620
75 #define DIV_TOP_FSYS0 0x062c
76 #define DIV_TOP_FSYS1 0x0630
77 #define DIV_TOP_FSYS2 0x0634
78 #define DIV_TOP_PERIC0 0x0638
79 #define DIV_TOP_PERIC1 0x063c
80 #define DIV_TOP_PERIC2 0x0640
81 #define DIV_TOP_PERIC3 0x0644
82 #define DIV_TOP_PERIC4 0x0648
83 #define DIV_TOP_PLL_FREQ_DET 0x064c
84 #define DIV_STAT_TOP0 0x0700
85 #define DIV_STAT_TOP1 0x0704
86 #define DIV_STAT_TOP2 0x0708
87 #define DIV_STAT_TOP3 0x070c
88 #define DIV_STAT_TOP4 0x0710
89 #define DIV_STAT_TOP_MSCL 0x0718
90 #define DIV_STAT_TOP_CAM10 0x071c
91 #define DIV_STAT_TOP_CAM11 0x0720
92 #define DIV_STAT_TOP_FSYS0 0x072c
93 #define DIV_STAT_TOP_FSYS1 0x0730
94 #define DIV_STAT_TOP_FSYS2 0x0734
95 #define DIV_STAT_TOP_PERIC0 0x0738
96 #define DIV_STAT_TOP_PERIC1 0x073c
97 #define DIV_STAT_TOP_PERIC2 0x0740
98 #define DIV_STAT_TOP_PERIC3 0x0744
99 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
100 #define ENABLE_ACLK_TOP 0x0800
101 #define ENABLE_SCLK_TOP 0x0a00
102 #define ENABLE_SCLK_TOP_MSCL 0x0a04
103 #define ENABLE_SCLK_TOP_CAM1 0x0a08
104 #define ENABLE_SCLK_TOP_DISP 0x0a0c
105 #define ENABLE_SCLK_TOP_FSYS 0x0a10
106 #define ENABLE_SCLK_TOP_PERIC 0x0a14
107 #define ENABLE_IP_TOP 0x0b00
108 #define ENABLE_CMU_TOP 0x0c00
109 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
110
111 static const unsigned long top_clk_regs[] __initconst = {
112 ISP_PLL_LOCK,
113 AUD_PLL_LOCK,
114 ISP_PLL_CON0,
115 ISP_PLL_CON1,
116 ISP_PLL_FREQ_DET,
117 AUD_PLL_CON0,
118 AUD_PLL_CON1,
119 AUD_PLL_CON2,
120 AUD_PLL_FREQ_DET,
121 MUX_SEL_TOP0,
122 MUX_SEL_TOP1,
123 MUX_SEL_TOP2,
124 MUX_SEL_TOP3,
125 MUX_SEL_TOP4,
126 MUX_SEL_TOP_MSCL,
127 MUX_SEL_TOP_CAM1,
128 MUX_SEL_TOP_DISP,
129 MUX_SEL_TOP_FSYS0,
130 MUX_SEL_TOP_FSYS1,
131 MUX_SEL_TOP_PERIC0,
132 MUX_SEL_TOP_PERIC1,
133 MUX_ENABLE_TOP0,
134 MUX_ENABLE_TOP1,
135 MUX_ENABLE_TOP2,
136 MUX_ENABLE_TOP3,
137 MUX_ENABLE_TOP4,
138 MUX_ENABLE_TOP_MSCL,
139 MUX_ENABLE_TOP_CAM1,
140 MUX_ENABLE_TOP_DISP,
141 MUX_ENABLE_TOP_FSYS0,
142 MUX_ENABLE_TOP_FSYS1,
143 MUX_ENABLE_TOP_PERIC0,
144 MUX_ENABLE_TOP_PERIC1,
145 DIV_TOP0,
146 DIV_TOP1,
147 DIV_TOP2,
148 DIV_TOP3,
149 DIV_TOP4,
150 DIV_TOP_MSCL,
151 DIV_TOP_CAM10,
152 DIV_TOP_CAM11,
153 DIV_TOP_FSYS0,
154 DIV_TOP_FSYS1,
155 DIV_TOP_FSYS2,
156 DIV_TOP_PERIC0,
157 DIV_TOP_PERIC1,
158 DIV_TOP_PERIC2,
159 DIV_TOP_PERIC3,
160 DIV_TOP_PERIC4,
161 DIV_TOP_PLL_FREQ_DET,
162 ENABLE_ACLK_TOP,
163 ENABLE_SCLK_TOP,
164 ENABLE_SCLK_TOP_MSCL,
165 ENABLE_SCLK_TOP_CAM1,
166 ENABLE_SCLK_TOP_DISP,
167 ENABLE_SCLK_TOP_FSYS,
168 ENABLE_SCLK_TOP_PERIC,
169 ENABLE_IP_TOP,
170 ENABLE_CMU_TOP,
171 ENABLE_CMU_TOP_DIV_STAT,
172 };
173
174 /* list of all parent clock list */
175 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
176 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
177 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
178 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
179 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
180 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
181 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
182 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
183
184 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
185 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
186 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
187 "mout_mfc_pll_user", };
188 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
189
190 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
191 "mout_mphy_pll_user", };
192 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
193 "mout_bus_pll_user", };
194 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
195
196 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
197 "mout_mphy_pll_user", };
198 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
199 "mout_mphy_pll_user", };
200 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
201 "mout_mphy_pll_user", };
202
203 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
204 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
205
206 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
207 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
208 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
209 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
210 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
211
212 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
213 "oscclk", "ioclk_spdif_extclk", };
214 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
215 "mout_aud_pll_user_t",};
216 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
217 "mout_aud_pll_user_t",};
218
219 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
220
221 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
222 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
223 };
224
225 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
226 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
227 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
228 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
229 /* Xi2s1SDI input clock for SPDIF */
230 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
231 /* XspiCLK[4:0] input clock for SPI */
232 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
233 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
234 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
235 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
236 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
237 /* Xi2s1SCLK input clock for I2S1_BCLK */
238 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
239 };
240
241 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
242 /* MUX_SEL_TOP0 */
243 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
244 4, 1),
245 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
246 0, 1),
247
248 /* MUX_SEL_TOP1 */
249 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
250 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
251 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
252 MUX_SEL_TOP1, 8, 1),
253 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
254 MUX_SEL_TOP1, 4, 1),
255 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
256 MUX_SEL_TOP1, 0, 1),
257
258 /* MUX_SEL_TOP2 */
259 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
260 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
261 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
262 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
263 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
264 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
265 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
266 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
267 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
268 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
269 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
270 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
271
272 /* MUX_SEL_TOP3 */
273 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
274 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
275 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
276 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
277 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
278 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
279 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
280 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
281 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
282 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
283 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
284 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
285
286 /* MUX_SEL_TOP4 */
287 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
288 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
289 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
290 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
291 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
292 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
293
294 /* MUX_SEL_TOP_MSCL */
295 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
296 MUX_SEL_TOP_MSCL, 8, 1),
297 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
298 MUX_SEL_TOP_MSCL, 4, 1),
299 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
300 MUX_SEL_TOP_MSCL, 0, 1),
301
302 /* MUX_SEL_TOP_CAM1 */
303 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
304 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
305 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
306 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
307 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
308 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
309 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
310 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
311 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
312 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
313 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
314 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
315
316 /* MUX_SEL_TOP_FSYS0 */
317 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
318 MUX_SEL_TOP_FSYS0, 28, 1),
319 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
320 MUX_SEL_TOP_FSYS0, 24, 1),
321 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
322 MUX_SEL_TOP_FSYS0, 20, 1),
323 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
324 MUX_SEL_TOP_FSYS0, 16, 1),
325 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
326 MUX_SEL_TOP_FSYS0, 12, 1),
327 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
328 MUX_SEL_TOP_FSYS0, 8, 1),
329 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
330 MUX_SEL_TOP_FSYS0, 4, 1),
331 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
332 MUX_SEL_TOP_FSYS0, 0, 1),
333
334 /* MUX_SEL_TOP_FSYS1 */
335 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
336 MUX_SEL_TOP_FSYS1, 12, 1),
337 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
338 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
339 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
340 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
341 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
342 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
343
344 /* MUX_SEL_TOP_PERIC0 */
345 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
346 MUX_SEL_TOP_PERIC0, 28, 1),
347 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
348 MUX_SEL_TOP_PERIC0, 24, 1),
349 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
350 MUX_SEL_TOP_PERIC0, 20, 1),
351 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
352 MUX_SEL_TOP_PERIC0, 16, 1),
353 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
354 MUX_SEL_TOP_PERIC0, 12, 1),
355 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
356 MUX_SEL_TOP_PERIC0, 8, 1),
357 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
358 MUX_SEL_TOP_PERIC0, 4, 1),
359 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
360 MUX_SEL_TOP_PERIC0, 0, 1),
361
362 /* MUX_SEL_TOP_PERIC1 */
363 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
364 MUX_SEL_TOP_PERIC1, 16, 1),
365 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
366 MUX_SEL_TOP_PERIC1, 12, 2),
367 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
368 MUX_SEL_TOP_PERIC1, 4, 2),
369 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
370 MUX_SEL_TOP_PERIC1, 0, 2),
371
372 /* MUX_SEL_TOP_DISP */
373 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
374 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
375 };
376
377 static const struct samsung_div_clock top_div_clks[] __initconst = {
378 /* DIV_TOP0 */
379 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
380 DIV_TOP0, 28, 3),
381 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
382 DIV_TOP0, 24, 3),
383 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
384 DIV_TOP0, 20, 3),
385 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
386 DIV_TOP0, 16, 3),
387 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
388 DIV_TOP0, 12, 3),
389 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
390 DIV_TOP0, 8, 3),
391 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
392 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
393 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
394 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
395
396 /* DIV_TOP1 */
397 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
398 DIV_TOP1, 28, 3),
399 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
400 DIV_TOP1, 24, 3),
401 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
402 DIV_TOP1, 20, 3),
403 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
404 DIV_TOP1, 12, 3),
405 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
406 DIV_TOP1, 8, 3),
407 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
408 DIV_TOP1, 0, 3),
409
410 /* DIV_TOP2 */
411 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
412 DIV_TOP2, 4, 3),
413 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
414 DIV_TOP2, 0, 3),
415
416 /* DIV_TOP3 */
417 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
418 "mout_bus_pll_user", DIV_TOP3, 24, 3),
419 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
420 "mout_bus_pll_user", DIV_TOP3, 20, 3),
421 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
422 "mout_bus_pll_user", DIV_TOP3, 16, 3),
423 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
424 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
425 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
426 "mout_bus_pll_user", DIV_TOP3, 8, 3),
427 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
428 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
429 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
430 "mout_bus_pll_user", DIV_TOP3, 0, 3),
431
432 /* DIV_TOP4 */
433 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
434 DIV_TOP4, 8, 3),
435 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
436 DIV_TOP4, 4, 3),
437 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
438 DIV_TOP4, 0, 3),
439
440 /* DIV_TOP_MSCL */
441 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
442 DIV_TOP_MSCL, 0, 4),
443
444 /* DIV_TOP_CAM10 */
445 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
446 DIV_TOP_CAM10, 24, 5),
447 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
448 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
449 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
450 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
451 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
452 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
453 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
454 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
455
456 /* DIV_TOP_CAM11 */
457 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
458 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
459 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
460 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
461 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
462 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
463 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
464 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
465 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
466 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
467 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
468 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
469
470 /* DIV_TOP_FSYS0 */
471 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
472 DIV_TOP_FSYS0, 16, 8),
473 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
474 DIV_TOP_FSYS0, 12, 4),
475 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
476 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
477 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
478 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
479
480 /* DIV_TOP_FSYS1 */
481 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
482 DIV_TOP_FSYS1, 4, 8),
483 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
484 DIV_TOP_FSYS1, 0, 4),
485
486 /* DIV_TOP_FSYS2 */
487 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
488 DIV_TOP_FSYS2, 12, 3),
489 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
490 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
491 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
492 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
493 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
494 DIV_TOP_FSYS2, 0, 4),
495
496 /* DIV_TOP_PERIC0 */
497 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
498 DIV_TOP_PERIC0, 16, 8),
499 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
500 DIV_TOP_PERIC0, 12, 4),
501 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
502 DIV_TOP_PERIC0, 4, 8),
503 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
504 DIV_TOP_PERIC0, 0, 4),
505
506 /* DIV_TOP_PERIC1 */
507 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
508 DIV_TOP_PERIC1, 4, 8),
509 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
510 DIV_TOP_PERIC1, 0, 4),
511
512 /* DIV_TOP_PERIC2 */
513 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
514 DIV_TOP_PERIC2, 8, 4),
515 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
516 DIV_TOP_PERIC2, 4, 4),
517 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
518 DIV_TOP_PERIC2, 0, 4),
519
520 /* DIV_TOP_PERIC3 */
521 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
522 DIV_TOP_PERIC3, 16, 6),
523 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
524 DIV_TOP_PERIC3, 8, 8),
525 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
526 DIV_TOP_PERIC3, 4, 4),
527 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
528 DIV_TOP_PERIC3, 0, 4),
529
530 /* DIV_TOP_PERIC4 */
531 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
532 DIV_TOP_PERIC4, 16, 8),
533 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
534 DIV_TOP_PERIC4, 12, 4),
535 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
536 DIV_TOP_PERIC4, 4, 8),
537 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
538 DIV_TOP_PERIC4, 0, 4),
539 };
540
541 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
542 /* ENABLE_ACLK_TOP */
543 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
544 ENABLE_ACLK_TOP, 30, 0, 0),
545 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
546 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
547 29, CLK_IGNORE_UNUSED, 0),
548 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
549 ENABLE_ACLK_TOP, 26,
550 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
551 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
552 ENABLE_ACLK_TOP, 25,
553 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
554 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
555 ENABLE_ACLK_TOP, 24,
556 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
557 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
558 ENABLE_ACLK_TOP, 23,
559 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
560 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
561 ENABLE_ACLK_TOP, 22,
562 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
563 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
564 ENABLE_ACLK_TOP, 21,
565 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
566 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
567 ENABLE_ACLK_TOP, 19,
568 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
569 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
570 ENABLE_ACLK_TOP, 18,
571 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
572 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
573 ENABLE_ACLK_TOP, 15,
574 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
575 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
576 ENABLE_ACLK_TOP, 14,
577 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
578 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
579 ENABLE_ACLK_TOP, 13,
580 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
581 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
582 ENABLE_ACLK_TOP, 12,
583 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
584 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
585 ENABLE_ACLK_TOP, 11,
586 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
587 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
588 ENABLE_ACLK_TOP, 10,
589 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
590 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
591 ENABLE_ACLK_TOP, 9,
592 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
593 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
594 ENABLE_ACLK_TOP, 8,
595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
596 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
597 ENABLE_ACLK_TOP, 7,
598 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
599 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
600 ENABLE_ACLK_TOP, 6,
601 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
602 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
603 ENABLE_ACLK_TOP, 5,
604 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
605 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
606 ENABLE_ACLK_TOP, 3,
607 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
608 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
609 ENABLE_ACLK_TOP, 2,
610 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
611 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
612 ENABLE_ACLK_TOP, 0,
613 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
614
615 /* ENABLE_SCLK_TOP_MSCL */
616 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
617 ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
618
619 /* ENABLE_SCLK_TOP_CAM1 */
620 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
621 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
622 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
623 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
624 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
625 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
626 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
627 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
628 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
629 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
630 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
631 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
632 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
633 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
634
635 /* ENABLE_SCLK_TOP_DISP */
636 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
637 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
638 CLK_IGNORE_UNUSED, 0),
639
640 /* ENABLE_SCLK_TOP_FSYS */
641 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
642 ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
643 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
644 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
645 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
646 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
647 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
648 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
649 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
650 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
651 3, CLK_SET_RATE_PARENT, 0),
652 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
653 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
654 1, CLK_SET_RATE_PARENT, 0),
655 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
656 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
657 0, CLK_SET_RATE_PARENT, 0),
658
659 /* ENABLE_SCLK_TOP_PERIC */
660 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
661 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
662 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
663 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
664 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
665 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
666 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
667 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
668 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
669 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
670 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
671 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
672 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
673 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
674 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
675 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
676 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
677 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
678 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
679 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
680 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
681 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
682
683 /* MUX_ENABLE_TOP_PERIC1 */
684 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
685 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
686 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
687 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
688 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
689 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
690 };
691
692 /*
693 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
694 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
695 */
696 static const struct samsung_pll_rate_table exynos5443_pll_rates[] = {
697 PLL_35XX_RATE(2500000000U, 625, 6, 0),
698 PLL_35XX_RATE(2400000000U, 500, 5, 0),
699 PLL_35XX_RATE(2300000000U, 575, 6, 0),
700 PLL_35XX_RATE(2200000000U, 550, 6, 0),
701 PLL_35XX_RATE(2100000000U, 350, 4, 0),
702 PLL_35XX_RATE(2000000000U, 500, 6, 0),
703 PLL_35XX_RATE(1900000000U, 475, 6, 0),
704 PLL_35XX_RATE(1800000000U, 375, 5, 0),
705 PLL_35XX_RATE(1700000000U, 425, 6, 0),
706 PLL_35XX_RATE(1600000000U, 400, 6, 0),
707 PLL_35XX_RATE(1500000000U, 250, 4, 0),
708 PLL_35XX_RATE(1400000000U, 350, 6, 0),
709 PLL_35XX_RATE(1332000000U, 222, 4, 0),
710 PLL_35XX_RATE(1300000000U, 325, 6, 0),
711 PLL_35XX_RATE(1200000000U, 500, 5, 1),
712 PLL_35XX_RATE(1100000000U, 550, 6, 1),
713 PLL_35XX_RATE(1086000000U, 362, 4, 1),
714 PLL_35XX_RATE(1066000000U, 533, 6, 1),
715 PLL_35XX_RATE(1000000000U, 500, 6, 1),
716 PLL_35XX_RATE(933000000U, 311, 4, 1),
717 PLL_35XX_RATE(921000000U, 307, 4, 1),
718 PLL_35XX_RATE(900000000U, 375, 5, 1),
719 PLL_35XX_RATE(825000000U, 275, 4, 1),
720 PLL_35XX_RATE(800000000U, 400, 6, 1),
721 PLL_35XX_RATE(733000000U, 733, 12, 1),
722 PLL_35XX_RATE(700000000U, 175, 3, 1),
723 PLL_35XX_RATE(667000000U, 222, 4, 1),
724 PLL_35XX_RATE(633000000U, 211, 4, 1),
725 PLL_35XX_RATE(600000000U, 500, 5, 2),
726 PLL_35XX_RATE(552000000U, 460, 5, 2),
727 PLL_35XX_RATE(550000000U, 550, 6, 2),
728 PLL_35XX_RATE(543000000U, 362, 4, 2),
729 PLL_35XX_RATE(533000000U, 533, 6, 2),
730 PLL_35XX_RATE(500000000U, 500, 6, 2),
731 PLL_35XX_RATE(444000000U, 370, 5, 2),
732 PLL_35XX_RATE(420000000U, 350, 5, 2),
733 PLL_35XX_RATE(400000000U, 400, 6, 2),
734 PLL_35XX_RATE(350000000U, 350, 6, 2),
735 PLL_35XX_RATE(333000000U, 222, 4, 2),
736 PLL_35XX_RATE(300000000U, 500, 5, 3),
737 PLL_35XX_RATE(266000000U, 532, 6, 3),
738 PLL_35XX_RATE(200000000U, 400, 6, 3),
739 PLL_35XX_RATE(166000000U, 332, 6, 3),
740 PLL_35XX_RATE(160000000U, 320, 6, 3),
741 PLL_35XX_RATE(133000000U, 532, 6, 4),
742 PLL_35XX_RATE(100000000U, 400, 6, 4),
743 { /* sentinel */ }
744 };
745
746 /* AUD_PLL */
747 static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
748 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
749 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
750 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
751 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
752 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
753 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
754 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
755 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
756 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
757 { /* sentinel */ }
758 };
759
760 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
761 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
762 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
763 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
764 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
765 };
766
767 static const struct samsung_cmu_info top_cmu_info __initconst = {
768 .pll_clks = top_pll_clks,
769 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
770 .mux_clks = top_mux_clks,
771 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
772 .div_clks = top_div_clks,
773 .nr_div_clks = ARRAY_SIZE(top_div_clks),
774 .gate_clks = top_gate_clks,
775 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
776 .fixed_clks = top_fixed_clks,
777 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
778 .fixed_factor_clks = top_fixed_factor_clks,
779 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
780 .nr_clk_ids = TOP_NR_CLK,
781 .clk_regs = top_clk_regs,
782 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
783 };
784
785 static void __init exynos5433_cmu_top_init(struct device_node *np)
786 {
787 samsung_cmu_register_one(np, &top_cmu_info);
788 }
789 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
790 exynos5433_cmu_top_init);
791
792 /*
793 * Register offset definitions for CMU_CPIF
794 */
795 #define MPHY_PLL_LOCK 0x0000
796 #define MPHY_PLL_CON0 0x0100
797 #define MPHY_PLL_CON1 0x0104
798 #define MPHY_PLL_FREQ_DET 0x010c
799 #define MUX_SEL_CPIF0 0x0200
800 #define DIV_CPIF 0x0600
801 #define ENABLE_SCLK_CPIF 0x0a00
802
803 static const unsigned long cpif_clk_regs[] __initconst = {
804 MPHY_PLL_LOCK,
805 MPHY_PLL_CON0,
806 MPHY_PLL_CON1,
807 MPHY_PLL_FREQ_DET,
808 MUX_SEL_CPIF0,
809 DIV_CPIF,
810 ENABLE_SCLK_CPIF,
811 };
812
813 /* list of all parent clock list */
814 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
815
816 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
817 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
818 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
819 };
820
821 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
822 /* MUX_SEL_CPIF0 */
823 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
824 0, 1),
825 };
826
827 static const struct samsung_div_clock cpif_div_clks[] __initconst = {
828 /* DIV_CPIF */
829 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
830 0, 6),
831 };
832
833 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
834 /* ENABLE_SCLK_CPIF */
835 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
836 ENABLE_SCLK_CPIF, 9, 0, 0),
837 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
838 ENABLE_SCLK_CPIF, 4, 0, 0),
839 };
840
841 static const struct samsung_cmu_info cpif_cmu_info __initconst = {
842 .pll_clks = cpif_pll_clks,
843 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
844 .mux_clks = cpif_mux_clks,
845 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
846 .div_clks = cpif_div_clks,
847 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
848 .gate_clks = cpif_gate_clks,
849 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
850 .nr_clk_ids = CPIF_NR_CLK,
851 .clk_regs = cpif_clk_regs,
852 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
853 };
854
855 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
856 {
857 samsung_cmu_register_one(np, &cpif_cmu_info);
858 }
859 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
860 exynos5433_cmu_cpif_init);
861
862 /*
863 * Register offset definitions for CMU_MIF
864 */
865 #define MEM0_PLL_LOCK 0x0000
866 #define MEM1_PLL_LOCK 0x0004
867 #define BUS_PLL_LOCK 0x0008
868 #define MFC_PLL_LOCK 0x000c
869 #define MEM0_PLL_CON0 0x0100
870 #define MEM0_PLL_CON1 0x0104
871 #define MEM0_PLL_FREQ_DET 0x010c
872 #define MEM1_PLL_CON0 0x0110
873 #define MEM1_PLL_CON1 0x0114
874 #define MEM1_PLL_FREQ_DET 0x011c
875 #define BUS_PLL_CON0 0x0120
876 #define BUS_PLL_CON1 0x0124
877 #define BUS_PLL_FREQ_DET 0x012c
878 #define MFC_PLL_CON0 0x0130
879 #define MFC_PLL_CON1 0x0134
880 #define MFC_PLL_FREQ_DET 0x013c
881 #define MUX_SEL_MIF0 0x0200
882 #define MUX_SEL_MIF1 0x0204
883 #define MUX_SEL_MIF2 0x0208
884 #define MUX_SEL_MIF3 0x020c
885 #define MUX_SEL_MIF4 0x0210
886 #define MUX_SEL_MIF5 0x0214
887 #define MUX_SEL_MIF6 0x0218
888 #define MUX_SEL_MIF7 0x021c
889 #define MUX_ENABLE_MIF0 0x0300
890 #define MUX_ENABLE_MIF1 0x0304
891 #define MUX_ENABLE_MIF2 0x0308
892 #define MUX_ENABLE_MIF3 0x030c
893 #define MUX_ENABLE_MIF4 0x0310
894 #define MUX_ENABLE_MIF5 0x0314
895 #define MUX_ENABLE_MIF6 0x0318
896 #define MUX_ENABLE_MIF7 0x031c
897 #define MUX_STAT_MIF0 0x0400
898 #define MUX_STAT_MIF1 0x0404
899 #define MUX_STAT_MIF2 0x0408
900 #define MUX_STAT_MIF3 0x040c
901 #define MUX_STAT_MIF4 0x0410
902 #define MUX_STAT_MIF5 0x0414
903 #define MUX_STAT_MIF6 0x0418
904 #define MUX_STAT_MIF7 0x041c
905 #define DIV_MIF1 0x0604
906 #define DIV_MIF2 0x0608
907 #define DIV_MIF3 0x060c
908 #define DIV_MIF4 0x0610
909 #define DIV_MIF5 0x0614
910 #define DIV_MIF_PLL_FREQ_DET 0x0618
911 #define DIV_STAT_MIF1 0x0704
912 #define DIV_STAT_MIF2 0x0708
913 #define DIV_STAT_MIF3 0x070c
914 #define DIV_STAT_MIF4 0x0710
915 #define DIV_STAT_MIF5 0x0714
916 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
917 #define ENABLE_ACLK_MIF0 0x0800
918 #define ENABLE_ACLK_MIF1 0x0804
919 #define ENABLE_ACLK_MIF2 0x0808
920 #define ENABLE_ACLK_MIF3 0x080c
921 #define ENABLE_PCLK_MIF 0x0900
922 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
923 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
924 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
925 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
926 #define ENABLE_SCLK_MIF 0x0a00
927 #define ENABLE_IP_MIF0 0x0b00
928 #define ENABLE_IP_MIF1 0x0b04
929 #define ENABLE_IP_MIF2 0x0b08
930 #define ENABLE_IP_MIF3 0x0b0c
931 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
932 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
933 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
934 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
935 #define CLKOUT_CMU_MIF 0x0c00
936 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
937 #define DREX_FREQ_CTRL0 0x1000
938 #define DREX_FREQ_CTRL1 0x1004
939 #define PAUSE 0x1008
940 #define DDRPHY_LOCK_CTRL 0x100c
941
942 static const unsigned long mif_clk_regs[] __initconst = {
943 MEM0_PLL_LOCK,
944 MEM1_PLL_LOCK,
945 BUS_PLL_LOCK,
946 MFC_PLL_LOCK,
947 MEM0_PLL_CON0,
948 MEM0_PLL_CON1,
949 MEM0_PLL_FREQ_DET,
950 MEM1_PLL_CON0,
951 MEM1_PLL_CON1,
952 MEM1_PLL_FREQ_DET,
953 BUS_PLL_CON0,
954 BUS_PLL_CON1,
955 BUS_PLL_FREQ_DET,
956 MFC_PLL_CON0,
957 MFC_PLL_CON1,
958 MFC_PLL_FREQ_DET,
959 MUX_SEL_MIF0,
960 MUX_SEL_MIF1,
961 MUX_SEL_MIF2,
962 MUX_SEL_MIF3,
963 MUX_SEL_MIF4,
964 MUX_SEL_MIF5,
965 MUX_SEL_MIF6,
966 MUX_SEL_MIF7,
967 MUX_ENABLE_MIF0,
968 MUX_ENABLE_MIF1,
969 MUX_ENABLE_MIF2,
970 MUX_ENABLE_MIF3,
971 MUX_ENABLE_MIF4,
972 MUX_ENABLE_MIF5,
973 MUX_ENABLE_MIF6,
974 MUX_ENABLE_MIF7,
975 DIV_MIF1,
976 DIV_MIF2,
977 DIV_MIF3,
978 DIV_MIF4,
979 DIV_MIF5,
980 DIV_MIF_PLL_FREQ_DET,
981 ENABLE_ACLK_MIF0,
982 ENABLE_ACLK_MIF1,
983 ENABLE_ACLK_MIF2,
984 ENABLE_ACLK_MIF3,
985 ENABLE_PCLK_MIF,
986 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
987 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
988 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
989 ENABLE_PCLK_MIF_SECURE_RTC,
990 ENABLE_SCLK_MIF,
991 ENABLE_IP_MIF0,
992 ENABLE_IP_MIF1,
993 ENABLE_IP_MIF2,
994 ENABLE_IP_MIF3,
995 ENABLE_IP_MIF_SECURE_DREX0_TZ,
996 ENABLE_IP_MIF_SECURE_DREX1_TZ,
997 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
998 ENABLE_IP_MIF_SECURE_RTC,
999 CLKOUT_CMU_MIF,
1000 CLKOUT_CMU_MIF_DIV_STAT,
1001 DREX_FREQ_CTRL0,
1002 DREX_FREQ_CTRL1,
1003 PAUSE,
1004 DDRPHY_LOCK_CTRL,
1005 };
1006
1007 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1008 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1009 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1010 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1011 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
1012 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1013 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
1014 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1015 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
1016 };
1017
1018 /* list of all parent clock list */
1019 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1020 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1021 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1022 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1023 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1024 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1025 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1026 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1027
1028 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1029 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1030 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1031 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1032
1033 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1034 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1035
1036 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1037 "mout_bus_pll_div2", };
1038 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1039
1040 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1041 "sclk_mphy_pll", };
1042 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1043 "mout_mfc_pll_div2", };
1044 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1045 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1046 "sclk_mphy_pll", };
1047 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1048 "mout_mfc_pll_div2", };
1049
1050 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1051 "sclk_mphy_pll", };
1052 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1053 "mout_mfc_pll_div2", };
1054 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1055 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1056 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1057
1058 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1059 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1060
1061 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1062 "sclk_mphy_pll", };
1063 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1064 "mout_mfc_pll_div2", };
1065 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1066 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1067
1068 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1069 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1070 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1071 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1072 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1073 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1074 };
1075
1076 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1077 /* MUX_SEL_MIF0 */
1078 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1079 MUX_SEL_MIF0, 28, 1),
1080 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1081 MUX_SEL_MIF0, 24, 1),
1082 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1083 MUX_SEL_MIF0, 20, 1),
1084 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1085 MUX_SEL_MIF0, 16, 1),
1086 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1087 12, 1),
1088 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1089 8, 1),
1090 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1091 4, 1),
1092 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1093 0, 1),
1094
1095 /* MUX_SEL_MIF1 */
1096 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1097 MUX_SEL_MIF1, 24, 1),
1098 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1099 MUX_SEL_MIF1, 20, 1),
1100 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1101 MUX_SEL_MIF1, 16, 1),
1102 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1103 MUX_SEL_MIF1, 12, 1),
1104 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1105 MUX_SEL_MIF1, 8, 1),
1106 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1107 MUX_SEL_MIF1, 4, 1),
1108
1109 /* MUX_SEL_MIF2 */
1110 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1111 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1112 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1113 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1114
1115 /* MUX_SEL_MIF3 */
1116 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1117 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1118 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1119 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1120
1121 /* MUX_SEL_MIF4 */
1122 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1123 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1124 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1125 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1126 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1127 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1128 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1129 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1130 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1131 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1132 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1133 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1134
1135 /* MUX_SEL_MIF5 */
1136 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1137 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1138 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1139 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1140 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1141 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1142 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1143 MUX_SEL_MIF5, 8, 1),
1144 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1145 MUX_SEL_MIF5, 4, 1),
1146 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1147 MUX_SEL_MIF5, 0, 1),
1148
1149 /* MUX_SEL_MIF6 */
1150 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1151 MUX_SEL_MIF6, 8, 1),
1152 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1153 MUX_SEL_MIF6, 4, 1),
1154 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1155 MUX_SEL_MIF6, 0, 1),
1156
1157 /* MUX_SEL_MIF7 */
1158 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1159 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1160 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1161 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1162 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1163 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1164 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1165 MUX_SEL_MIF7, 8, 1),
1166 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1167 MUX_SEL_MIF7, 4, 1),
1168 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1169 MUX_SEL_MIF7, 0, 1),
1170 };
1171
1172 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1173 /* DIV_MIF1 */
1174 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1175 DIV_MIF1, 16, 2),
1176 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1177 12, 2),
1178 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1179 8, 2),
1180 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1181 4, 4),
1182
1183 /* DIV_MIF2 */
1184 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1185 DIV_MIF2, 20, 3),
1186 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1187 DIV_MIF2, 16, 4),
1188 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1189 DIV_MIF2, 12, 4),
1190 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1191 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1192 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1193 DIV_MIF2, 4, 2),
1194 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1195 DIV_MIF2, 0, 3),
1196
1197 /* DIV_MIF3 */
1198 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1199 DIV_MIF3, 16, 4),
1200 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1201 DIV_MIF3, 4, 3),
1202 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1203 DIV_MIF3, 0, 3),
1204
1205 /* DIV_MIF4 */
1206 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1207 DIV_MIF4, 24, 4),
1208 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1209 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1210 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1211 DIV_MIF4, 16, 4),
1212 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1213 DIV_MIF4, 12, 4),
1214 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1215 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1216 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1217 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1218 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1219 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1220
1221 /* DIV_MIF5 */
1222 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1223 0, 3),
1224 };
1225
1226 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1227 /* ENABLE_ACLK_MIF0 */
1228 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1229 19, CLK_IGNORE_UNUSED, 0),
1230 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1231 18, CLK_IGNORE_UNUSED, 0),
1232 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1233 17, CLK_IGNORE_UNUSED, 0),
1234 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1235 16, CLK_IGNORE_UNUSED, 0),
1236 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1237 15, CLK_IGNORE_UNUSED, 0),
1238 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1239 14, CLK_IGNORE_UNUSED, 0),
1240 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1241 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1242 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1243 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1244 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1245 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1246 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1247 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1248 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1249 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1250 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1251 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1252 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1253 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1254 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1255 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1256 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1257 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1258 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1259 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1260 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1261 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1262 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1263 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1264 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1265 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1266 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1267 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1268
1269 /* ENABLE_ACLK_MIF1 */
1270 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1271 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1272 CLK_IGNORE_UNUSED, 0),
1273 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1274 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1275 27, CLK_IGNORE_UNUSED, 0),
1276 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1277 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1278 26, CLK_IGNORE_UNUSED, 0),
1279 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1280 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1281 25, CLK_IGNORE_UNUSED, 0),
1282 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1283 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1284 24, CLK_IGNORE_UNUSED, 0),
1285 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1286 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1287 23, CLK_IGNORE_UNUSED, 0),
1288 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1289 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1290 22, CLK_IGNORE_UNUSED, 0),
1291 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1292 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1293 21, CLK_IGNORE_UNUSED, 0),
1294 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1295 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1296 20, CLK_IGNORE_UNUSED, 0),
1297 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1298 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1299 19, CLK_IGNORE_UNUSED, 0),
1300 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1301 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1302 18, CLK_IGNORE_UNUSED, 0),
1303 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1304 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1305 17, CLK_IGNORE_UNUSED, 0),
1306 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1307 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1308 16, CLK_IGNORE_UNUSED, 0),
1309 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1310 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1311 15, CLK_IGNORE_UNUSED, 0),
1312 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1313 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1314 14, CLK_IGNORE_UNUSED, 0),
1315 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1316 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1317 13, CLK_IGNORE_UNUSED, 0),
1318 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1319 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1320 12, CLK_IGNORE_UNUSED, 0),
1321 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1322 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1323 11, CLK_IGNORE_UNUSED, 0),
1324 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1325 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1326 10, CLK_IGNORE_UNUSED, 0),
1327 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1328 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1329 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1330 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1331 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1332 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1333 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1334 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1335 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1336 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1337 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1338 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1339 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1340 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1341 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1342 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1343 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1344 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1345 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1346 0, CLK_IGNORE_UNUSED, 0),
1347
1348 /* ENABLE_ACLK_MIF2 */
1349 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1350 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1351 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1352 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1353 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1354 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1355 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1356 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1357 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1358 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1359 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1360 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1361 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1362 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1363 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1364 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1365 CLK_IGNORE_UNUSED, 0),
1366 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1367 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1368 5, CLK_IGNORE_UNUSED, 0),
1369 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1370 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1371 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1372 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1373 3, CLK_IGNORE_UNUSED, 0),
1374 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1375 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1376
1377 /* ENABLE_ACLK_MIF3 */
1378 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1379 ENABLE_ACLK_MIF3, 4,
1380 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1381 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1382 ENABLE_ACLK_MIF3, 1,
1383 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1384 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1385 ENABLE_ACLK_MIF3, 0,
1386 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1387
1388 /* ENABLE_PCLK_MIF */
1389 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1390 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1391 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1392 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1393 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1394 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1395 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1396 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1397 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1398 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1399 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1400 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1401 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1402 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1403 CLK_IGNORE_UNUSED, 0),
1404 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1405 ENABLE_PCLK_MIF, 19, 0, 0),
1406 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1407 ENABLE_PCLK_MIF, 18, 0, 0),
1408 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1409 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1410 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1411 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1412 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1413 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1414 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1415 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1416 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1417 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1418 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1419 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1420 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1421 ENABLE_PCLK_MIF, 11, 0, 0),
1422 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1423 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1424 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1425 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1426 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1427 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1428 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1429 ENABLE_PCLK_MIF, 7, 0, 0),
1430 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1431 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1432 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1433 ENABLE_PCLK_MIF, 5, 0, 0),
1434 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1435 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1436 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1437 ENABLE_PCLK_MIF, 2, 0, 0),
1438 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1439 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1440
1441 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1442 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1443 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1444
1445 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1446 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1447 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1448
1449 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1450 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1451 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1452
1453 /* ENABLE_PCLK_MIF_SECURE_RTC */
1454 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1455 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1456
1457 /* ENABLE_SCLK_MIF */
1458 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1459 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1460 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1461 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1462 14, CLK_IGNORE_UNUSED, 0),
1463 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1464 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1465 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1466 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1467 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1468 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1469 7, CLK_IGNORE_UNUSED, 0),
1470 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1471 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1472 6, CLK_IGNORE_UNUSED, 0),
1473 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1474 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1475 5, CLK_IGNORE_UNUSED, 0),
1476 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1477 ENABLE_SCLK_MIF, 4,
1478 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1479 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1480 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1481 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1482 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1483 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1484 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1485 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1486 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1487 };
1488
1489 static const struct samsung_cmu_info mif_cmu_info __initconst = {
1490 .pll_clks = mif_pll_clks,
1491 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1492 .mux_clks = mif_mux_clks,
1493 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1494 .div_clks = mif_div_clks,
1495 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1496 .gate_clks = mif_gate_clks,
1497 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1498 .fixed_factor_clks = mif_fixed_factor_clks,
1499 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1500 .nr_clk_ids = MIF_NR_CLK,
1501 .clk_regs = mif_clk_regs,
1502 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1503 };
1504
1505 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1506 {
1507 samsung_cmu_register_one(np, &mif_cmu_info);
1508 }
1509 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1510 exynos5433_cmu_mif_init);
1511
1512 /*
1513 * Register offset definitions for CMU_PERIC
1514 */
1515 #define DIV_PERIC 0x0600
1516 #define DIV_STAT_PERIC 0x0700
1517 #define ENABLE_ACLK_PERIC 0x0800
1518 #define ENABLE_PCLK_PERIC0 0x0900
1519 #define ENABLE_PCLK_PERIC1 0x0904
1520 #define ENABLE_SCLK_PERIC 0x0A00
1521 #define ENABLE_IP_PERIC0 0x0B00
1522 #define ENABLE_IP_PERIC1 0x0B04
1523 #define ENABLE_IP_PERIC2 0x0B08
1524
1525 static const unsigned long peric_clk_regs[] __initconst = {
1526 DIV_PERIC,
1527 ENABLE_ACLK_PERIC,
1528 ENABLE_PCLK_PERIC0,
1529 ENABLE_PCLK_PERIC1,
1530 ENABLE_SCLK_PERIC,
1531 ENABLE_IP_PERIC0,
1532 ENABLE_IP_PERIC1,
1533 ENABLE_IP_PERIC2,
1534 };
1535
1536 static const struct samsung_div_clock peric_div_clks[] __initconst = {
1537 /* DIV_PERIC */
1538 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1539 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1540 };
1541
1542 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1543 /* ENABLE_ACLK_PERIC */
1544 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1545 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1546 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1547 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1548 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1549 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1550 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1551 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1552
1553 /* ENABLE_PCLK_PERIC0 */
1554 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1555 31, CLK_SET_RATE_PARENT, 0),
1556 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1557 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1558 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1559 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1560 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1561 28, CLK_SET_RATE_PARENT, 0),
1562 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1563 26, CLK_SET_RATE_PARENT, 0),
1564 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1565 25, CLK_SET_RATE_PARENT, 0),
1566 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1567 24, CLK_SET_RATE_PARENT, 0),
1568 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1569 23, CLK_SET_RATE_PARENT, 0),
1570 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1571 22, CLK_SET_RATE_PARENT, 0),
1572 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1573 21, CLK_SET_RATE_PARENT, 0),
1574 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1575 20, CLK_SET_RATE_PARENT, 0),
1576 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1577 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1578 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1579 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1580 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1581 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1582 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1583 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1584 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1585 ENABLE_PCLK_PERIC0, 15,
1586 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1587 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1588 14, CLK_SET_RATE_PARENT, 0),
1589 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1590 13, CLK_SET_RATE_PARENT, 0),
1591 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1592 12, CLK_SET_RATE_PARENT, 0),
1593 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1594 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1595 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1596 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1597 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1598 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1599 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1600 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1601 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1602 7, CLK_SET_RATE_PARENT, 0),
1603 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1604 6, CLK_SET_RATE_PARENT, 0),
1605 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1606 5, CLK_SET_RATE_PARENT, 0),
1607 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1608 4, CLK_SET_RATE_PARENT, 0),
1609 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1610 3, CLK_SET_RATE_PARENT, 0),
1611 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1612 2, CLK_SET_RATE_PARENT, 0),
1613 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1614 1, CLK_SET_RATE_PARENT, 0),
1615 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1616 0, CLK_SET_RATE_PARENT, 0),
1617
1618 /* ENABLE_PCLK_PERIC1 */
1619 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1620 9, CLK_SET_RATE_PARENT, 0),
1621 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1622 8, CLK_SET_RATE_PARENT, 0),
1623 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1624 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1625 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1626 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1627 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1628 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1629 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1630 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1631 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1632 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1633 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1634 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1635 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1636 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1637 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1638 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1639
1640 /* ENABLE_SCLK_PERIC */
1641 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1642 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1643 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1644 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1645 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1646 19, CLK_SET_RATE_PARENT, 0),
1647 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1648 18, CLK_SET_RATE_PARENT, 0),
1649 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1650 17, 0, 0),
1651 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1652 16, 0, 0),
1653 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1654 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1655 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1656 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1657 ENABLE_SCLK_PERIC, 12,
1658 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1659 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1660 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1661 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1662 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1663 CLK_SET_RATE_PARENT, 0),
1664 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1665 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1666 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1667 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1668 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1669 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1670 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1671 5, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1673 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1675 3, CLK_SET_RATE_PARENT, 0),
1676 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1677 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1678 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1679 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1680 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1681 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1682 };
1683
1684 static const struct samsung_cmu_info peric_cmu_info __initconst = {
1685 .div_clks = peric_div_clks,
1686 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1687 .gate_clks = peric_gate_clks,
1688 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1689 .nr_clk_ids = PERIC_NR_CLK,
1690 .clk_regs = peric_clk_regs,
1691 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1692 };
1693
1694 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1695 {
1696 samsung_cmu_register_one(np, &peric_cmu_info);
1697 }
1698
1699 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1700 exynos5433_cmu_peric_init);
1701
1702 /*
1703 * Register offset definitions for CMU_PERIS
1704 */
1705 #define ENABLE_ACLK_PERIS 0x0800
1706 #define ENABLE_PCLK_PERIS 0x0900
1707 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1708 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1709 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1710 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1711 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1712 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1713 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1714 #define ENABLE_SCLK_PERIS 0x0a00
1715 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1716 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1717 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1718 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1719 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1720 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1721 #define ENABLE_IP_PERIS0 0x0b00
1722 #define ENABLE_IP_PERIS1 0x0b04
1723 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1724 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1725 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1726 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1727 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1728 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1729 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1730
1731 static const unsigned long peris_clk_regs[] __initconst = {
1732 ENABLE_ACLK_PERIS,
1733 ENABLE_PCLK_PERIS,
1734 ENABLE_PCLK_PERIS_SECURE_TZPC,
1735 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1736 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1737 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1738 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1739 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1740 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1741 ENABLE_SCLK_PERIS,
1742 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1743 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1744 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1745 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1746 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1747 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1748 ENABLE_IP_PERIS0,
1749 ENABLE_IP_PERIS1,
1750 ENABLE_IP_PERIS_SECURE_TZPC,
1751 ENABLE_IP_PERIS_SECURE_SECKEY,
1752 ENABLE_IP_PERIS_SECURE_CHIPID,
1753 ENABLE_IP_PERIS_SECURE_TOPRTC,
1754 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1755 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1756 ENABLE_IP_PERIS_SECURE_OTP_CON,
1757 };
1758
1759 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1760 /* ENABLE_ACLK_PERIS */
1761 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1762 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1763 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1764 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1765 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1766 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1767
1768 /* ENABLE_PCLK_PERIS */
1769 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1770 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1771 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1772 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1773 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1774 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1775 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1776 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1777 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1778 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1779 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1780 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1781 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1782 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1783 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1784 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1785 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1786 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1787 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1788 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1789
1790 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1791 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1792 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1793 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1794 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1795 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1796 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1797 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1798 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1799 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1800 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1801 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1802 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1803 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1804 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1805 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1806 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1807 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1808 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1809 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1810 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1811 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1812 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1813 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1814 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1815 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1816 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1817
1818 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1819 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1820 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1821
1822 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1823 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1824 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1825
1826 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1827 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1828 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1829
1830 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1831 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1832 "aclk_peris_66",
1833 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1834
1835 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1836 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1837 "aclk_peris_66",
1838 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1839
1840 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1841 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1842 "aclk_peris_66",
1843 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1844
1845 /* ENABLE_SCLK_PERIS */
1846 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1847 ENABLE_SCLK_PERIS, 10, 0, 0),
1848 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1849 ENABLE_SCLK_PERIS, 4, 0, 0),
1850 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1851 ENABLE_SCLK_PERIS, 3, 0, 0),
1852
1853 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1854 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1855 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1856
1857 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1858 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1859 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1860
1861 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1862 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1863 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1864
1865 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1866 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1867 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1868
1869 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1870 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1871 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1872
1873 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1874 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1875 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1876 };
1877
1878 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1879 .gate_clks = peris_gate_clks,
1880 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1881 .nr_clk_ids = PERIS_NR_CLK,
1882 .clk_regs = peris_clk_regs,
1883 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1884 };
1885
1886 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1887 {
1888 samsung_cmu_register_one(np, &peris_cmu_info);
1889 }
1890
1891 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1892 exynos5433_cmu_peris_init);
1893
1894 /*
1895 * Register offset definitions for CMU_FSYS
1896 */
1897 #define MUX_SEL_FSYS0 0x0200
1898 #define MUX_SEL_FSYS1 0x0204
1899 #define MUX_SEL_FSYS2 0x0208
1900 #define MUX_SEL_FSYS3 0x020c
1901 #define MUX_SEL_FSYS4 0x0210
1902 #define MUX_ENABLE_FSYS0 0x0300
1903 #define MUX_ENABLE_FSYS1 0x0304
1904 #define MUX_ENABLE_FSYS2 0x0308
1905 #define MUX_ENABLE_FSYS3 0x030c
1906 #define MUX_ENABLE_FSYS4 0x0310
1907 #define MUX_STAT_FSYS0 0x0400
1908 #define MUX_STAT_FSYS1 0x0404
1909 #define MUX_STAT_FSYS2 0x0408
1910 #define MUX_STAT_FSYS3 0x040c
1911 #define MUX_STAT_FSYS4 0x0410
1912 #define MUX_IGNORE_FSYS2 0x0508
1913 #define MUX_IGNORE_FSYS3 0x050c
1914 #define ENABLE_ACLK_FSYS0 0x0800
1915 #define ENABLE_ACLK_FSYS1 0x0804
1916 #define ENABLE_PCLK_FSYS 0x0900
1917 #define ENABLE_SCLK_FSYS 0x0a00
1918 #define ENABLE_IP_FSYS0 0x0b00
1919 #define ENABLE_IP_FSYS1 0x0b04
1920
1921 /* list of all parent clock list */
1922 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1923 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
1924 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1925 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1926 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1927 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1928 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1929 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1930 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1931
1932 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1933 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1934 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1935 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1936 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1937 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1938 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1939 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1940 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1941 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1942 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1943 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1944 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1945 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1946 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1947 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1948 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1949 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1950 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1951 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1952 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1953 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1954 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1955 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1956 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1957 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1958 PNAME(mout_sclk_mphy_p)
1959 = { "mout_sclk_ufs_mphy_user",
1960 "mout_phyclk_lli_mphy_to_ufs_user", };
1961
1962 static const unsigned long fsys_clk_regs[] __initconst = {
1963 MUX_SEL_FSYS0,
1964 MUX_SEL_FSYS1,
1965 MUX_SEL_FSYS2,
1966 MUX_SEL_FSYS3,
1967 MUX_SEL_FSYS4,
1968 MUX_ENABLE_FSYS0,
1969 MUX_ENABLE_FSYS1,
1970 MUX_ENABLE_FSYS2,
1971 MUX_ENABLE_FSYS3,
1972 MUX_ENABLE_FSYS4,
1973 MUX_IGNORE_FSYS2,
1974 MUX_IGNORE_FSYS3,
1975 ENABLE_ACLK_FSYS0,
1976 ENABLE_ACLK_FSYS1,
1977 ENABLE_PCLK_FSYS,
1978 ENABLE_SCLK_FSYS,
1979 ENABLE_IP_FSYS0,
1980 ENABLE_IP_FSYS1,
1981 };
1982
1983 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
1984 /* PHY clocks from USBDRD30_PHY */
1985 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1986 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
1987 0, 60000000),
1988 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
1989 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
1990 0, 125000000),
1991 /* PHY clocks from USBHOST30_PHY */
1992 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
1993 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
1994 0, 60000000),
1995 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
1996 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
1997 0, 125000000),
1998 /* PHY clocks from USBHOST20_PHY */
1999 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2000 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2001 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2002 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2003 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2004 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2005 0, 48000000),
2006 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2007 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2008 60000000),
2009 /* PHY clocks from UFS_PHY */
2010 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2011 NULL, 0, 300000000),
2012 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2013 NULL, 0, 300000000),
2014 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2015 NULL, 0, 300000000),
2016 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2017 NULL, 0, 300000000),
2018 /* PHY clocks from LLI_PHY */
2019 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2020 NULL, 0, 26000000),
2021 };
2022
2023 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2024 /* MUX_SEL_FSYS0 */
2025 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2026 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2027 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2028 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2029
2030 /* MUX_SEL_FSYS1 */
2031 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2032 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2033 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2034 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2035 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2036 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2037 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2038 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2039 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2040 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2041 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2042 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2043 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2044 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2045
2046 /* MUX_SEL_FSYS2 */
2047 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2048 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2049 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2050 MUX_SEL_FSYS2, 28, 1),
2051 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2052 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2053 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2054 MUX_SEL_FSYS2, 24, 1),
2055 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2056 "mout_phyclk_usbhost20_phy_hsic1",
2057 mout_phyclk_usbhost20_phy_hsic1_p,
2058 MUX_SEL_FSYS2, 20, 1),
2059 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2060 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2061 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2062 MUX_SEL_FSYS2, 16, 1),
2063 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2064 "mout_phyclk_usbhost20_phy_phyclock_user",
2065 mout_phyclk_usbhost20_phy_phyclock_user_p,
2066 MUX_SEL_FSYS2, 12, 1),
2067 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2068 "mout_phyclk_usbhost20_phy_freeclk_user",
2069 mout_phyclk_usbhost20_phy_freeclk_user_p,
2070 MUX_SEL_FSYS2, 8, 1),
2071 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2072 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2073 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2074 MUX_SEL_FSYS2, 4, 1),
2075 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2076 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2077 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2078 MUX_SEL_FSYS2, 0, 1),
2079
2080 /* MUX_SEL_FSYS3 */
2081 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2082 "mout_phyclk_ufs_rx1_symbol_user",
2083 mout_phyclk_ufs_rx1_symbol_user_p,
2084 MUX_SEL_FSYS3, 16, 1),
2085 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2086 "mout_phyclk_ufs_rx0_symbol_user",
2087 mout_phyclk_ufs_rx0_symbol_user_p,
2088 MUX_SEL_FSYS3, 12, 1),
2089 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2090 "mout_phyclk_ufs_tx1_symbol_user",
2091 mout_phyclk_ufs_tx1_symbol_user_p,
2092 MUX_SEL_FSYS3, 8, 1),
2093 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2094 "mout_phyclk_ufs_tx0_symbol_user",
2095 mout_phyclk_ufs_tx0_symbol_user_p,
2096 MUX_SEL_FSYS3, 4, 1),
2097 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2098 "mout_phyclk_lli_mphy_to_ufs_user",
2099 mout_phyclk_lli_mphy_to_ufs_user_p,
2100 MUX_SEL_FSYS3, 0, 1),
2101
2102 /* MUX_SEL_FSYS4 */
2103 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2104 MUX_SEL_FSYS4, 0, 1),
2105 };
2106
2107 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2108 /* ENABLE_ACLK_FSYS0 */
2109 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2110 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2111 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2112 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2113 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2114 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2115 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2116 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2117 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2118 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2119 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2120 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2121 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2122 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2123 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2124 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2125 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2126 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2127 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2128 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2129 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2130 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2131
2132 /* ENABLE_ACLK_FSYS1 */
2133 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2134 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2135 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2136 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2137 26, CLK_IGNORE_UNUSED, 0),
2138 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2139 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2140 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2141 ENABLE_ACLK_FSYS1, 24, 0, 0),
2142 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2143 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2144 22, CLK_IGNORE_UNUSED, 0),
2145 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2146 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2147 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2148 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2149 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2150 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2151 13, 0, 0),
2152 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2153 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2154 12, 0, 0),
2155 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2156 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2157 11, CLK_IGNORE_UNUSED, 0),
2158 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2159 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2160 10, CLK_IGNORE_UNUSED, 0),
2161 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2162 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2163 9, CLK_IGNORE_UNUSED, 0),
2164 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2165 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2166 8, CLK_IGNORE_UNUSED, 0),
2167 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2168 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2169 7, CLK_IGNORE_UNUSED, 0),
2170 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2171 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2172 6, CLK_IGNORE_UNUSED, 0),
2173 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2174 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2175 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2176 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2177 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2178 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2179 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2180 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2181 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2182 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2183 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2184 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2185
2186 /* ENABLE_PCLK_FSYS */
2187 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2188 ENABLE_PCLK_FSYS, 17, 0, 0),
2189 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2190 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2191 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2192 ENABLE_PCLK_FSYS, 14, 0, 0),
2193 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2194 ENABLE_PCLK_FSYS, 13, 0, 0),
2195 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2196 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2197 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2198 ENABLE_PCLK_FSYS, 5, 0, 0),
2199 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2200 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2201 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2202 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2203 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2204 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2205 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2206 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2207 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2208 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2209 0, CLK_IGNORE_UNUSED, 0),
2210
2211 /* ENABLE_SCLK_FSYS */
2212 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2213 ENABLE_SCLK_FSYS, 21, 0, 0),
2214 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2215 "phyclk_usbhost30_uhost30_pipe_pclk",
2216 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2217 ENABLE_SCLK_FSYS, 18, 0, 0),
2218 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2219 "phyclk_usbhost30_uhost30_phyclock",
2220 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2221 ENABLE_SCLK_FSYS, 17, 0, 0),
2222 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2223 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2224 16, 0, 0),
2225 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2226 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2227 15, 0, 0),
2228 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2229 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2230 14, 0, 0),
2231 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2232 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2233 13, 0, 0),
2234 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2235 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2236 12, 0, 0),
2237 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2238 "phyclk_usbhost20_phy_clk48mohci",
2239 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2240 ENABLE_SCLK_FSYS, 11, 0, 0),
2241 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2242 "phyclk_usbhost20_phy_phyclock",
2243 "mout_phyclk_usbhost20_phy_phyclock_user",
2244 ENABLE_SCLK_FSYS, 10, 0, 0),
2245 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2246 "phyclk_usbhost20_phy_freeclk",
2247 "mout_phyclk_usbhost20_phy_freeclk_user",
2248 ENABLE_SCLK_FSYS, 9, 0, 0),
2249 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2250 "phyclk_usbdrd30_udrd30_pipe_pclk",
2251 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2252 ENABLE_SCLK_FSYS, 8, 0, 0),
2253 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2254 "phyclk_usbdrd30_udrd30_phyclock",
2255 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2256 ENABLE_SCLK_FSYS, 7, 0, 0),
2257 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2258 ENABLE_SCLK_FSYS, 6, 0, 0),
2259 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2260 ENABLE_SCLK_FSYS, 5, 0, 0),
2261 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2262 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2263 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2264 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2265 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2266 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2267 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2268 ENABLE_SCLK_FSYS, 1, 0, 0),
2269 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2270 ENABLE_SCLK_FSYS, 0, 0, 0),
2271
2272 /* ENABLE_IP_FSYS0 */
2273 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2274 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2275 };
2276
2277 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2278 .mux_clks = fsys_mux_clks,
2279 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2280 .gate_clks = fsys_gate_clks,
2281 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2282 .fixed_clks = fsys_fixed_clks,
2283 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2284 .nr_clk_ids = FSYS_NR_CLK,
2285 .clk_regs = fsys_clk_regs,
2286 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2287 };
2288
2289 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2290 {
2291 samsung_cmu_register_one(np, &fsys_cmu_info);
2292 }
2293
2294 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2295 exynos5433_cmu_fsys_init);
2296
2297 /*
2298 * Register offset definitions for CMU_G2D
2299 */
2300 #define MUX_SEL_G2D0 0x0200
2301 #define MUX_SEL_ENABLE_G2D0 0x0300
2302 #define MUX_SEL_STAT_G2D0 0x0400
2303 #define DIV_G2D 0x0600
2304 #define DIV_STAT_G2D 0x0700
2305 #define DIV_ENABLE_ACLK_G2D 0x0800
2306 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2307 #define DIV_ENABLE_PCLK_G2D 0x0900
2308 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2309 #define DIV_ENABLE_IP_G2D0 0x0b00
2310 #define DIV_ENABLE_IP_G2D1 0x0b04
2311 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2312
2313 static const unsigned long g2d_clk_regs[] __initconst = {
2314 MUX_SEL_G2D0,
2315 MUX_SEL_ENABLE_G2D0,
2316 DIV_G2D,
2317 DIV_ENABLE_ACLK_G2D,
2318 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2319 DIV_ENABLE_PCLK_G2D,
2320 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2321 DIV_ENABLE_IP_G2D0,
2322 DIV_ENABLE_IP_G2D1,
2323 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2324 };
2325
2326 /* list of all parent clock list */
2327 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2328 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2329
2330 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2331 /* MUX_SEL_G2D0 */
2332 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2333 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2334 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2335 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2336 };
2337
2338 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2339 /* DIV_G2D */
2340 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2341 DIV_G2D, 0, 2),
2342 };
2343
2344 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2345 /* DIV_ENABLE_ACLK_G2D */
2346 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2347 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2348 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2349 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2350 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2351 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2352 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2353 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2354 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2355 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2356 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2357 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2358 7, 0, 0),
2359 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2360 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2361 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2362 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2363 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2364 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2365 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2366 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2367 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2368 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2369 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2370 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2371 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2372 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2373
2374 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2375 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2376 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2377
2378 /* DIV_ENABLE_PCLK_G2D */
2379 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2380 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2381 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2382 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2383 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2384 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2385 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2386 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2387 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2388 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2389 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2390 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2391 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2392 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2393 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2394 0, 0, 0),
2395
2396 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2397 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2398 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2399 };
2400
2401 static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2402 .mux_clks = g2d_mux_clks,
2403 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2404 .div_clks = g2d_div_clks,
2405 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2406 .gate_clks = g2d_gate_clks,
2407 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2408 .nr_clk_ids = G2D_NR_CLK,
2409 .clk_regs = g2d_clk_regs,
2410 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2411 };
2412
2413 static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2414 {
2415 samsung_cmu_register_one(np, &g2d_cmu_info);
2416 }
2417
2418 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2419 exynos5433_cmu_g2d_init);
2420
2421 /*
2422 * Register offset definitions for CMU_DISP
2423 */
2424 #define DISP_PLL_LOCK 0x0000
2425 #define DISP_PLL_CON0 0x0100
2426 #define DISP_PLL_CON1 0x0104
2427 #define DISP_PLL_FREQ_DET 0x0108
2428 #define MUX_SEL_DISP0 0x0200
2429 #define MUX_SEL_DISP1 0x0204
2430 #define MUX_SEL_DISP2 0x0208
2431 #define MUX_SEL_DISP3 0x020c
2432 #define MUX_SEL_DISP4 0x0210
2433 #define MUX_ENABLE_DISP0 0x0300
2434 #define MUX_ENABLE_DISP1 0x0304
2435 #define MUX_ENABLE_DISP2 0x0308
2436 #define MUX_ENABLE_DISP3 0x030c
2437 #define MUX_ENABLE_DISP4 0x0310
2438 #define MUX_STAT_DISP0 0x0400
2439 #define MUX_STAT_DISP1 0x0404
2440 #define MUX_STAT_DISP2 0x0408
2441 #define MUX_STAT_DISP3 0x040c
2442 #define MUX_STAT_DISP4 0x0410
2443 #define MUX_IGNORE_DISP2 0x0508
2444 #define DIV_DISP 0x0600
2445 #define DIV_DISP_PLL_FREQ_DET 0x0604
2446 #define DIV_STAT_DISP 0x0700
2447 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2448 #define ENABLE_ACLK_DISP0 0x0800
2449 #define ENABLE_ACLK_DISP1 0x0804
2450 #define ENABLE_PCLK_DISP 0x0900
2451 #define ENABLE_SCLK_DISP 0x0a00
2452 #define ENABLE_IP_DISP0 0x0b00
2453 #define ENABLE_IP_DISP1 0x0b04
2454 #define CLKOUT_CMU_DISP 0x0c00
2455 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2456
2457 static const unsigned long disp_clk_regs[] __initconst = {
2458 DISP_PLL_LOCK,
2459 DISP_PLL_CON0,
2460 DISP_PLL_CON1,
2461 DISP_PLL_FREQ_DET,
2462 MUX_SEL_DISP0,
2463 MUX_SEL_DISP1,
2464 MUX_SEL_DISP2,
2465 MUX_SEL_DISP3,
2466 MUX_SEL_DISP4,
2467 MUX_ENABLE_DISP0,
2468 MUX_ENABLE_DISP1,
2469 MUX_ENABLE_DISP2,
2470 MUX_ENABLE_DISP3,
2471 MUX_ENABLE_DISP4,
2472 MUX_IGNORE_DISP2,
2473 DIV_DISP,
2474 DIV_DISP_PLL_FREQ_DET,
2475 ENABLE_ACLK_DISP0,
2476 ENABLE_ACLK_DISP1,
2477 ENABLE_PCLK_DISP,
2478 ENABLE_SCLK_DISP,
2479 ENABLE_IP_DISP0,
2480 ENABLE_IP_DISP1,
2481 CLKOUT_CMU_DISP,
2482 CLKOUT_CMU_DISP_DIV_STAT,
2483 };
2484
2485 /* list of all parent clock list */
2486 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2487 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2488 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2489 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2490 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2491 "sclk_decon_tv_eclk_disp", };
2492 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2493 "sclk_decon_vclk_disp", };
2494 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2495 "sclk_decon_eclk_disp", };
2496 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2497 "sclk_decon_tv_vclk_disp", };
2498 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2499
2500 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2501 "phyclk_mipidphy1_bitclkdiv8_phy", };
2502 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2503 "phyclk_mipidphy1_rxclkesc0_phy", };
2504 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2505 "phyclk_mipidphy0_bitclkdiv8_phy", };
2506 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2507 "phyclk_mipidphy0_rxclkesc0_phy", };
2508 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2509 "phyclk_hdmiphy_tmds_clko_phy", };
2510 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2511 "phyclk_hdmiphy_pixel_clko_phy", };
2512
2513 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2514 "mout_sclk_dsim0_user", };
2515 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2516 "mout_sclk_decon_tv_eclk_user", };
2517 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2518 "mout_sclk_decon_vclk_user", };
2519 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2520 "mout_sclk_decon_eclk_user", };
2521
2522 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2523 "mout_sclk_dsim1_user", };
2524 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2525 "mout_phyclk_hdmiphy_pixel_clko_user",
2526 "mout_sclk_decon_tv_vclk_b_disp", };
2527 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2528 "mout_sclk_decon_tv_vclk_user", };
2529
2530 static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2531 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2532 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2533 };
2534
2535 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2536 /*
2537 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2538 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2539 * and sclk_decon_{vclk|tv_vclk}.
2540 */
2541 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2542 1, 2, 0),
2543 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2544 1, 2, 0),
2545 };
2546
2547 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2548 /* PHY clocks from MIPI_DPHY1 */
2549 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2550 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2551 /* PHY clocks from MIPI_DPHY0 */
2552 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
2553 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
2554 /* PHY clocks from HDMI_PHY */
2555 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2556 NULL, 0, 300000000),
2557 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2558 NULL, 0, 166000000),
2559 };
2560
2561 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2562 /* MUX_SEL_DISP0 */
2563 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2564 0, 1),
2565
2566 /* MUX_SEL_DISP1 */
2567 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2568 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2569 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2570 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2571 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2572 MUX_SEL_DISP1, 20, 1),
2573 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2574 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2575 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2576 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2577 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2578 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2579 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2580 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2581 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2582 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2583
2584 /* MUX_SEL_DISP2 */
2585 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2586 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2587 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2588 20, 1),
2589 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2590 "mout_phyclk_mipidphy1_rxclkesc0_user",
2591 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2592 16, 1),
2593 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2594 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2595 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2596 12, 1),
2597 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2598 "mout_phyclk_mipidphy0_rxclkesc0_user",
2599 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2600 8, 1),
2601 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2602 "mout_phyclk_hdmiphy_tmds_clko_user",
2603 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2604 4, 1),
2605 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2606 "mout_phyclk_hdmiphy_pixel_clko_user",
2607 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2608 0, 1),
2609
2610 /* MUX_SEL_DISP3 */
2611 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2612 MUX_SEL_DISP3, 12, 1),
2613 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2614 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2615 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2616 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2617 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2618 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2619
2620 /* MUX_SEL_DISP4 */
2621 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2622 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2623 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2624 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2625 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2626 "mout_sclk_decon_tv_vclk_c_disp",
2627 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2628 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2629 "mout_sclk_decon_tv_vclk_b_disp",
2630 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2631 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2632 "mout_sclk_decon_tv_vclk_a_disp",
2633 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2634 };
2635
2636 static const struct samsung_div_clock disp_div_clks[] __initconst = {
2637 /* DIV_DISP */
2638 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2639 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2640 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2641 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2642 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2643 DIV_DISP, 16, 3),
2644 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2645 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2646 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2647 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2648 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2649 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2650 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2651 DIV_DISP, 0, 2),
2652 };
2653
2654 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2655 /* ENABLE_ACLK_DISP0 */
2656 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2657 ENABLE_ACLK_DISP0, 2, 0, 0),
2658 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2659 ENABLE_ACLK_DISP0, 0, 0, 0),
2660
2661 /* ENABLE_ACLK_DISP1 */
2662 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2663 ENABLE_ACLK_DISP1, 25, 0, 0),
2664 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2665 ENABLE_ACLK_DISP1, 24, 0, 0),
2666 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2667 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2668 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2669 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2670 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2671 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2672 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2673 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2674 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2675 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2676 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2677 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2678 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2679 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2680 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2681 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2682 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2683 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2684 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2685 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2686 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2687 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2688 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2689 "div_pclk_disp", ENABLE_ACLK_DISP1,
2690 12, CLK_IGNORE_UNUSED, 0),
2691 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2692 "div_pclk_disp", ENABLE_ACLK_DISP1,
2693 11, CLK_IGNORE_UNUSED, 0),
2694 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2695 "div_pclk_disp", ENABLE_ACLK_DISP1,
2696 10, CLK_IGNORE_UNUSED, 0),
2697 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2698 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2699 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2700 ENABLE_ACLK_DISP1, 7, 0, 0),
2701 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2702 ENABLE_ACLK_DISP1, 6, 0, 0),
2703 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2704 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2705 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2706 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2707 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2708 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2709 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2710 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2711 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2712 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2713 CLK_IGNORE_UNUSED, 0),
2714 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2715 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2716 0, CLK_IGNORE_UNUSED, 0),
2717
2718 /* ENABLE_PCLK_DISP */
2719 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2720 ENABLE_PCLK_DISP, 23, 0, 0),
2721 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2722 ENABLE_PCLK_DISP, 22, 0, 0),
2723 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2724 ENABLE_PCLK_DISP, 21, 0, 0),
2725 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2726 ENABLE_PCLK_DISP, 20, 0, 0),
2727 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2728 ENABLE_PCLK_DISP, 19, 0, 0),
2729 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2730 ENABLE_PCLK_DISP, 18, 0, 0),
2731 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2732 ENABLE_PCLK_DISP, 17, 0, 0),
2733 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2734 ENABLE_PCLK_DISP, 16, 0, 0),
2735 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2736 ENABLE_PCLK_DISP, 15, 0, 0),
2737 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2738 ENABLE_PCLK_DISP, 14, 0, 0),
2739 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2740 ENABLE_PCLK_DISP, 13, 0, 0),
2741 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2742 ENABLE_PCLK_DISP, 12, 0, 0),
2743 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2744 ENABLE_PCLK_DISP, 11, 0, 0),
2745 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2746 ENABLE_PCLK_DISP, 10, 0, 0),
2747 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2748 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2749 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2750 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2751 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2752 ENABLE_PCLK_DISP, 7, 0, 0),
2753 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2754 ENABLE_PCLK_DISP, 6, 0, 0),
2755 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2756 ENABLE_PCLK_DISP, 5, 0, 0),
2757 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2758 ENABLE_PCLK_DISP, 3, 0, 0),
2759 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2760 ENABLE_PCLK_DISP, 2, 0, 0),
2761 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2762 ENABLE_PCLK_DISP, 1, 0, 0),
2763 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2764 ENABLE_PCLK_DISP, 0, 0, 0),
2765
2766 /* ENABLE_SCLK_DISP */
2767 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2768 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2769 ENABLE_SCLK_DISP, 26, 0, 0),
2770 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2771 "mout_phyclk_mipidphy1_rxclkesc0_user",
2772 ENABLE_SCLK_DISP, 25, 0, 0),
2773 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2774 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2775 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2776 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2777 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2778 ENABLE_SCLK_DISP, 22, 0, 0),
2779 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2780 "div_sclk_decon_tv_vclk_disp",
2781 ENABLE_SCLK_DISP, 21, 0, 0),
2782 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2783 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2784 ENABLE_SCLK_DISP, 15, 0, 0),
2785 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2786 "mout_phyclk_mipidphy0_rxclkesc0_user",
2787 ENABLE_SCLK_DISP, 14, 0, 0),
2788 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2789 "mout_phyclk_hdmiphy_tmds_clko_user",
2790 ENABLE_SCLK_DISP, 13, 0, 0),
2791 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2792 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2793 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2794 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2795 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2796 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2797 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2798 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2799 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2800 ENABLE_SCLK_DISP, 7, 0, 0),
2801 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2802 ENABLE_SCLK_DISP, 6, 0, 0),
2803 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2804 ENABLE_SCLK_DISP, 5, 0, 0),
2805 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2806 "div_sclk_decon_tv_eclk_disp",
2807 ENABLE_SCLK_DISP, 4, 0, 0),
2808 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2809 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2810 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2811 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2812 };
2813
2814 static const struct samsung_cmu_info disp_cmu_info __initconst = {
2815 .pll_clks = disp_pll_clks,
2816 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2817 .mux_clks = disp_mux_clks,
2818 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2819 .div_clks = disp_div_clks,
2820 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2821 .gate_clks = disp_gate_clks,
2822 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2823 .fixed_clks = disp_fixed_clks,
2824 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2825 .fixed_factor_clks = disp_fixed_factor_clks,
2826 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2827 .nr_clk_ids = DISP_NR_CLK,
2828 .clk_regs = disp_clk_regs,
2829 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2830 };
2831
2832 static void __init exynos5433_cmu_disp_init(struct device_node *np)
2833 {
2834 samsung_cmu_register_one(np, &disp_cmu_info);
2835 }
2836
2837 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2838 exynos5433_cmu_disp_init);
2839
2840 /*
2841 * Register offset definitions for CMU_AUD
2842 */
2843 #define MUX_SEL_AUD0 0x0200
2844 #define MUX_SEL_AUD1 0x0204
2845 #define MUX_ENABLE_AUD0 0x0300
2846 #define MUX_ENABLE_AUD1 0x0304
2847 #define MUX_STAT_AUD0 0x0400
2848 #define DIV_AUD0 0x0600
2849 #define DIV_AUD1 0x0604
2850 #define DIV_STAT_AUD0 0x0700
2851 #define DIV_STAT_AUD1 0x0704
2852 #define ENABLE_ACLK_AUD 0x0800
2853 #define ENABLE_PCLK_AUD 0x0900
2854 #define ENABLE_SCLK_AUD0 0x0a00
2855 #define ENABLE_SCLK_AUD1 0x0a04
2856 #define ENABLE_IP_AUD0 0x0b00
2857 #define ENABLE_IP_AUD1 0x0b04
2858
2859 static const unsigned long aud_clk_regs[] __initconst = {
2860 MUX_SEL_AUD0,
2861 MUX_SEL_AUD1,
2862 MUX_ENABLE_AUD0,
2863 MUX_ENABLE_AUD1,
2864 DIV_AUD0,
2865 DIV_AUD1,
2866 ENABLE_ACLK_AUD,
2867 ENABLE_PCLK_AUD,
2868 ENABLE_SCLK_AUD0,
2869 ENABLE_SCLK_AUD1,
2870 ENABLE_IP_AUD0,
2871 ENABLE_IP_AUD1,
2872 };
2873
2874 /* list of all parent clock list */
2875 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2876 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2877
2878 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2879 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2880 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2881 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2882 };
2883
2884 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2885 /* MUX_SEL_AUD0 */
2886 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2887 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2888
2889 /* MUX_SEL_AUD1 */
2890 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2891 MUX_SEL_AUD1, 8, 1),
2892 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2893 MUX_SEL_AUD1, 0, 1),
2894 };
2895
2896 static const struct samsung_div_clock aud_div_clks[] __initconst = {
2897 /* DIV_AUD0 */
2898 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2899 12, 4),
2900 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2901 8, 4),
2902 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2903 4, 4),
2904 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2905 0, 4),
2906
2907 /* DIV_AUD1 */
2908 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2909 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2910 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2911 DIV_AUD1, 12, 4),
2912 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2913 DIV_AUD1, 4, 8),
2914 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2915 DIV_AUD1, 0, 4),
2916 };
2917
2918 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2919 /* ENABLE_ACLK_AUD */
2920 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2921 ENABLE_ACLK_AUD, 12, 0, 0),
2922 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2923 ENABLE_ACLK_AUD, 7, 0, 0),
2924 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2925 ENABLE_ACLK_AUD, 0, 4, 0),
2926 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2927 ENABLE_ACLK_AUD, 0, 3, 0),
2928 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2929 ENABLE_ACLK_AUD, 0, 2, 0),
2930 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2931 0, 1, 0),
2932 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2933 0, CLK_IGNORE_UNUSED, 0),
2934
2935 /* ENABLE_PCLK_AUD */
2936 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2937 13, 0, 0),
2938 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2939 12, 0, 0),
2940 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2941 11, 0, 0),
2942 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2943 ENABLE_PCLK_AUD, 10, 0, 0),
2944 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2945 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2946 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2947 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2948 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2949 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2950 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2951 ENABLE_PCLK_AUD, 6, 0, 0),
2952 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2953 ENABLE_PCLK_AUD, 5, 0, 0),
2954 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2955 ENABLE_PCLK_AUD, 4, 0, 0),
2956 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2957 ENABLE_PCLK_AUD, 3, 0, 0),
2958 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2959 2, 0, 0),
2960 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2961 ENABLE_PCLK_AUD, 0, 0, 0),
2962
2963 /* ENABLE_SCLK_AUD0 */
2964 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2965 2, 0, 0),
2966 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2967 ENABLE_SCLK_AUD0, 1, 0, 0),
2968 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
2969 0, 0, 0),
2970
2971 /* ENABLE_SCLK_AUD1 */
2972 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
2973 ENABLE_SCLK_AUD1, 6, 0, 0),
2974 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
2975 ENABLE_SCLK_AUD1, 5, 0, 0),
2976 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2977 ENABLE_SCLK_AUD1, 4, 0, 0),
2978 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2979 ENABLE_SCLK_AUD1, 3, 0, 0),
2980 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2981 ENABLE_SCLK_AUD1, 2, 0, 0),
2982 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
2983 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
2984 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
2985 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
2986 };
2987
2988 static const struct samsung_cmu_info aud_cmu_info __initconst = {
2989 .mux_clks = aud_mux_clks,
2990 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
2991 .div_clks = aud_div_clks,
2992 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
2993 .gate_clks = aud_gate_clks,
2994 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
2995 .fixed_clks = aud_fixed_clks,
2996 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
2997 .nr_clk_ids = AUD_NR_CLK,
2998 .clk_regs = aud_clk_regs,
2999 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3000 };
3001
3002 static void __init exynos5433_cmu_aud_init(struct device_node *np)
3003 {
3004 samsung_cmu_register_one(np, &aud_cmu_info);
3005 }
3006 CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
3007 exynos5433_cmu_aud_init);
3008
3009
3010 /*
3011 * Register offset definitions for CMU_BUS{0|1|2}
3012 */
3013 #define DIV_BUS 0x0600
3014 #define DIV_STAT_BUS 0x0700
3015 #define ENABLE_ACLK_BUS 0x0800
3016 #define ENABLE_PCLK_BUS 0x0900
3017 #define ENABLE_IP_BUS0 0x0b00
3018 #define ENABLE_IP_BUS1 0x0b04
3019
3020 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3021 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3022 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3023
3024 /* list of all parent clock list */
3025 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3026
3027 #define CMU_BUS_COMMON_CLK_REGS \
3028 DIV_BUS, \
3029 ENABLE_ACLK_BUS, \
3030 ENABLE_PCLK_BUS, \
3031 ENABLE_IP_BUS0, \
3032 ENABLE_IP_BUS1
3033
3034 static const unsigned long bus01_clk_regs[] __initconst = {
3035 CMU_BUS_COMMON_CLK_REGS,
3036 };
3037
3038 static const unsigned long bus2_clk_regs[] __initconst = {
3039 MUX_SEL_BUS2,
3040 MUX_ENABLE_BUS2,
3041 CMU_BUS_COMMON_CLK_REGS,
3042 };
3043
3044 static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3045 /* DIV_BUS0 */
3046 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3047 DIV_BUS, 0, 3),
3048 };
3049
3050 /* CMU_BUS0 clocks */
3051 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3052 /* ENABLE_ACLK_BUS0 */
3053 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3054 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3055 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3056 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3057 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3058 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3059
3060 /* ENABLE_PCLK_BUS0 */
3061 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3062 ENABLE_PCLK_BUS, 2, 0, 0),
3063 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3064 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3065 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3066 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3067 };
3068
3069 /* CMU_BUS1 clocks */
3070 static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3071 /* DIV_BUS1 */
3072 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3073 DIV_BUS, 0, 3),
3074 };
3075
3076 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3077 /* ENABLE_ACLK_BUS1 */
3078 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3079 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3080 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3081 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3082 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3083 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3084
3085 /* ENABLE_PCLK_BUS1 */
3086 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3087 ENABLE_PCLK_BUS, 2, 0, 0),
3088 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3089 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3090 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3091 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3092 };
3093
3094 /* CMU_BUS2 clocks */
3095 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3096 /* MUX_SEL_BUS2 */
3097 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3098 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3099 };
3100
3101 static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3102 /* DIV_BUS2 */
3103 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3104 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3105 };
3106
3107 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3108 /* ENABLE_ACLK_BUS2 */
3109 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3110 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3111 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3112 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3113 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3114 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3115 1, CLK_IGNORE_UNUSED, 0),
3116 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3117 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3118 0, CLK_IGNORE_UNUSED, 0),
3119
3120 /* ENABLE_PCLK_BUS2 */
3121 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3122 ENABLE_PCLK_BUS, 2, 0, 0),
3123 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3124 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3125 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3126 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3127 };
3128
3129 #define CMU_BUS_INFO_CLKS(id) \
3130 .div_clks = bus##id##_div_clks, \
3131 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3132 .gate_clks = bus##id##_gate_clks, \
3133 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3134 .nr_clk_ids = BUSx_NR_CLK
3135
3136 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3137 CMU_BUS_INFO_CLKS(0),
3138 .clk_regs = bus01_clk_regs,
3139 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3140 };
3141
3142 static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3143 CMU_BUS_INFO_CLKS(1),
3144 .clk_regs = bus01_clk_regs,
3145 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3146 };
3147
3148 static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3149 CMU_BUS_INFO_CLKS(2),
3150 .mux_clks = bus2_mux_clks,
3151 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3152 .clk_regs = bus2_clk_regs,
3153 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3154 };
3155
3156 #define exynos5433_cmu_bus_init(id) \
3157 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3158 { \
3159 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3160 } \
3161 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3162 "samsung,exynos5433-cmu-bus"#id, \
3163 exynos5433_cmu_bus##id##_init)
3164
3165 exynos5433_cmu_bus_init(0);
3166 exynos5433_cmu_bus_init(1);
3167 exynos5433_cmu_bus_init(2);
3168
3169 /*
3170 * Register offset definitions for CMU_G3D
3171 */
3172 #define G3D_PLL_LOCK 0x0000
3173 #define G3D_PLL_CON0 0x0100
3174 #define G3D_PLL_CON1 0x0104
3175 #define G3D_PLL_FREQ_DET 0x010c
3176 #define MUX_SEL_G3D 0x0200
3177 #define MUX_ENABLE_G3D 0x0300
3178 #define MUX_STAT_G3D 0x0400
3179 #define DIV_G3D 0x0600
3180 #define DIV_G3D_PLL_FREQ_DET 0x0604
3181 #define DIV_STAT_G3D 0x0700
3182 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3183 #define ENABLE_ACLK_G3D 0x0800
3184 #define ENABLE_PCLK_G3D 0x0900
3185 #define ENABLE_SCLK_G3D 0x0a00
3186 #define ENABLE_IP_G3D0 0x0b00
3187 #define ENABLE_IP_G3D1 0x0b04
3188 #define CLKOUT_CMU_G3D 0x0c00
3189 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3190 #define CLK_STOPCTRL 0x1000
3191
3192 static const unsigned long g3d_clk_regs[] __initconst = {
3193 G3D_PLL_LOCK,
3194 G3D_PLL_CON0,
3195 G3D_PLL_CON1,
3196 G3D_PLL_FREQ_DET,
3197 MUX_SEL_G3D,
3198 MUX_ENABLE_G3D,
3199 DIV_G3D,
3200 DIV_G3D_PLL_FREQ_DET,
3201 ENABLE_ACLK_G3D,
3202 ENABLE_PCLK_G3D,
3203 ENABLE_SCLK_G3D,
3204 ENABLE_IP_G3D0,
3205 ENABLE_IP_G3D1,
3206 CLKOUT_CMU_G3D,
3207 CLKOUT_CMU_G3D_DIV_STAT,
3208 CLK_STOPCTRL,
3209 };
3210
3211 /* list of all parent clock list */
3212 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3213 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3214
3215 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3216 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3217 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3218 };
3219
3220 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3221 /* MUX_SEL_G3D */
3222 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3223 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3224 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3225 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3226 };
3227
3228 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3229 /* DIV_G3D */
3230 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3231 8, 2),
3232 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3233 4, 3),
3234 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3235 0, 3, CLK_SET_RATE_PARENT, 0),
3236 };
3237
3238 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3239 /* ENABLE_ACLK_G3D */
3240 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3241 ENABLE_ACLK_G3D, 7, 0, 0),
3242 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3243 ENABLE_ACLK_G3D, 6, 0, 0),
3244 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3245 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3246 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3247 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3248 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3249 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3250 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3251 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3252 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3253 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3254 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3255 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3256
3257 /* ENABLE_PCLK_G3D */
3258 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3259 ENABLE_PCLK_G3D, 3, 0, 0),
3260 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3261 ENABLE_PCLK_G3D, 2, 0, 0),
3262 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3263 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3264 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3265 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3266
3267 /* ENABLE_SCLK_G3D */
3268 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3269 ENABLE_SCLK_G3D, 0, 0, 0),
3270 };
3271
3272 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3273 .pll_clks = g3d_pll_clks,
3274 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3275 .mux_clks = g3d_mux_clks,
3276 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3277 .div_clks = g3d_div_clks,
3278 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3279 .gate_clks = g3d_gate_clks,
3280 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3281 .nr_clk_ids = G3D_NR_CLK,
3282 .clk_regs = g3d_clk_regs,
3283 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3284 };
3285
3286 static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3287 {
3288 samsung_cmu_register_one(np, &g3d_cmu_info);
3289 }
3290 CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3291 exynos5433_cmu_g3d_init);
3292
3293 /*
3294 * Register offset definitions for CMU_GSCL
3295 */
3296 #define MUX_SEL_GSCL 0x0200
3297 #define MUX_ENABLE_GSCL 0x0300
3298 #define MUX_STAT_GSCL 0x0400
3299 #define ENABLE_ACLK_GSCL 0x0800
3300 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3301 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3302 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3303 #define ENABLE_PCLK_GSCL 0x0900
3304 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3305 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3306 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3307 #define ENABLE_IP_GSCL0 0x0b00
3308 #define ENABLE_IP_GSCL1 0x0b04
3309 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3310 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3311 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3312
3313 static const unsigned long gscl_clk_regs[] __initconst = {
3314 MUX_SEL_GSCL,
3315 MUX_ENABLE_GSCL,
3316 ENABLE_ACLK_GSCL,
3317 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3318 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3319 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3320 ENABLE_PCLK_GSCL,
3321 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3322 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3323 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3324 ENABLE_IP_GSCL0,
3325 ENABLE_IP_GSCL1,
3326 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3327 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3328 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3329 };
3330
3331 /* list of all parent clock list */
3332 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3333 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3334
3335 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3336 /* MUX_SEL_GSCL */
3337 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3338 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3339 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3340 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3341 };
3342
3343 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3344 /* ENABLE_ACLK_GSCL */
3345 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3346 ENABLE_ACLK_GSCL, 11, 0, 0),
3347 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3348 ENABLE_ACLK_GSCL, 10, 0, 0),
3349 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3350 ENABLE_ACLK_GSCL, 9, 0, 0),
3351 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3352 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3353 8, CLK_IGNORE_UNUSED, 0),
3354 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3355 ENABLE_ACLK_GSCL, 7, 0, 0),
3356 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3357 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3358 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3359 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
3360 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3361 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
3362 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3363 ENABLE_ACLK_GSCL, 3, 0, 0),
3364 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3365 ENABLE_ACLK_GSCL, 2, 0, 0),
3366 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3367 ENABLE_ACLK_GSCL, 1, 0, 0),
3368 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3369 ENABLE_ACLK_GSCL, 0, 0, 0),
3370
3371 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3372 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3373 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3374
3375 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3376 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3377 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3378
3379 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3380 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3381 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3382
3383 /* ENABLE_PCLK_GSCL */
3384 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3385 ENABLE_PCLK_GSCL, 7, 0, 0),
3386 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3387 ENABLE_PCLK_GSCL, 6, 0, 0),
3388 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3389 ENABLE_PCLK_GSCL, 5, 0, 0),
3390 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3391 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3392 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3393 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3394 3, CLK_IGNORE_UNUSED, 0),
3395 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3396 ENABLE_PCLK_GSCL, 2, 0, 0),
3397 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3398 ENABLE_PCLK_GSCL, 1, 0, 0),
3399 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3400 ENABLE_PCLK_GSCL, 0, 0, 0),
3401
3402 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3403 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3404 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3405
3406 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3407 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3408 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3409
3410 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3411 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3412 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3413 };
3414
3415 static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3416 .mux_clks = gscl_mux_clks,
3417 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3418 .gate_clks = gscl_gate_clks,
3419 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3420 .nr_clk_ids = GSCL_NR_CLK,
3421 .clk_regs = gscl_clk_regs,
3422 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3423 };
3424
3425 static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3426 {
3427 samsung_cmu_register_one(np, &gscl_cmu_info);
3428 }
3429 CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3430 exynos5433_cmu_gscl_init);
3431
3432 /*
3433 * Register offset definitions for CMU_APOLLO
3434 */
3435 #define APOLLO_PLL_LOCK 0x0000
3436 #define APOLLO_PLL_CON0 0x0100
3437 #define APOLLO_PLL_CON1 0x0104
3438 #define APOLLO_PLL_FREQ_DET 0x010c
3439 #define MUX_SEL_APOLLO0 0x0200
3440 #define MUX_SEL_APOLLO1 0x0204
3441 #define MUX_SEL_APOLLO2 0x0208
3442 #define MUX_ENABLE_APOLLO0 0x0300
3443 #define MUX_ENABLE_APOLLO1 0x0304
3444 #define MUX_ENABLE_APOLLO2 0x0308
3445 #define MUX_STAT_APOLLO0 0x0400
3446 #define MUX_STAT_APOLLO1 0x0404
3447 #define MUX_STAT_APOLLO2 0x0408
3448 #define DIV_APOLLO0 0x0600
3449 #define DIV_APOLLO1 0x0604
3450 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3451 #define DIV_STAT_APOLLO0 0x0700
3452 #define DIV_STAT_APOLLO1 0x0704
3453 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3454 #define ENABLE_ACLK_APOLLO 0x0800
3455 #define ENABLE_PCLK_APOLLO 0x0900
3456 #define ENABLE_SCLK_APOLLO 0x0a00
3457 #define ENABLE_IP_APOLLO0 0x0b00
3458 #define ENABLE_IP_APOLLO1 0x0b04
3459 #define CLKOUT_CMU_APOLLO 0x0c00
3460 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3461 #define ARMCLK_STOPCTRL 0x1000
3462 #define APOLLO_PWR_CTRL 0x1020
3463 #define APOLLO_PWR_CTRL2 0x1024
3464 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3465 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3466 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3467
3468 static const unsigned long apollo_clk_regs[] __initconst = {
3469 APOLLO_PLL_LOCK,
3470 APOLLO_PLL_CON0,
3471 APOLLO_PLL_CON1,
3472 APOLLO_PLL_FREQ_DET,
3473 MUX_SEL_APOLLO0,
3474 MUX_SEL_APOLLO1,
3475 MUX_SEL_APOLLO2,
3476 MUX_ENABLE_APOLLO0,
3477 MUX_ENABLE_APOLLO1,
3478 MUX_ENABLE_APOLLO2,
3479 DIV_APOLLO0,
3480 DIV_APOLLO1,
3481 DIV_APOLLO_PLL_FREQ_DET,
3482 ENABLE_ACLK_APOLLO,
3483 ENABLE_PCLK_APOLLO,
3484 ENABLE_SCLK_APOLLO,
3485 ENABLE_IP_APOLLO0,
3486 ENABLE_IP_APOLLO1,
3487 CLKOUT_CMU_APOLLO,
3488 CLKOUT_CMU_APOLLO_DIV_STAT,
3489 ARMCLK_STOPCTRL,
3490 APOLLO_PWR_CTRL,
3491 APOLLO_PWR_CTRL2,
3492 APOLLO_INTR_SPREAD_ENABLE,
3493 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3494 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3495 };
3496
3497 /* list of all parent clock list */
3498 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3499 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3500 PNAME(mout_apollo_p) = { "mout_apollo_pll",
3501 "mout_bus_pll_apollo_user", };
3502
3503 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3504 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3505 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3506 };
3507
3508 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3509 /* MUX_SEL_APOLLO0 */
3510 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3511 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0),
3512
3513 /* MUX_SEL_APOLLO1 */
3514 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3515 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3516
3517 /* MUX_SEL_APOLLO2 */
3518 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3519 0, 1, CLK_SET_RATE_PARENT, 0),
3520 };
3521
3522 static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3523 /* DIV_APOLLO0 */
3524 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3525 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3526 CLK_DIVIDER_READ_ONLY),
3527 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3528 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3529 CLK_DIVIDER_READ_ONLY),
3530 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3531 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3532 CLK_DIVIDER_READ_ONLY),
3533 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3534 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3535 CLK_DIVIDER_READ_ONLY),
3536 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3537 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3538 CLK_DIVIDER_READ_ONLY),
3539 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3540 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3541 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3542 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3543
3544 /* DIV_APOLLO1 */
3545 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3546 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3547 CLK_DIVIDER_READ_ONLY),
3548 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3549 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3550 CLK_DIVIDER_READ_ONLY),
3551 };
3552
3553 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3554 /* ENABLE_ACLK_APOLLO */
3555 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3556 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3557 6, CLK_IGNORE_UNUSED, 0),
3558 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3559 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3560 5, CLK_IGNORE_UNUSED, 0),
3561 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3562 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3563 4, CLK_IGNORE_UNUSED, 0),
3564 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3565 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3566 3, CLK_IGNORE_UNUSED, 0),
3567 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3568 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3569 2, CLK_IGNORE_UNUSED, 0),
3570 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3571 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3572 1, CLK_IGNORE_UNUSED, 0),
3573 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3574 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3575 0, CLK_IGNORE_UNUSED, 0),
3576
3577 /* ENABLE_PCLK_APOLLO */
3578 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3579 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3580 2, CLK_IGNORE_UNUSED, 0),
3581 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3582 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3583 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3584 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3585 0, CLK_IGNORE_UNUSED, 0),
3586
3587 /* ENABLE_SCLK_APOLLO */
3588 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3589 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3590 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3591 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3592 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2",
3593 ENABLE_SCLK_APOLLO, 0,
3594 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3595 };
3596
3597 static const struct samsung_cmu_info apollo_cmu_info __initconst = {
3598 .pll_clks = apollo_pll_clks,
3599 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
3600 .mux_clks = apollo_mux_clks,
3601 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
3602 .div_clks = apollo_div_clks,
3603 .nr_div_clks = ARRAY_SIZE(apollo_div_clks),
3604 .gate_clks = apollo_gate_clks,
3605 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
3606 .nr_clk_ids = APOLLO_NR_CLK,
3607 .clk_regs = apollo_clk_regs,
3608 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
3609 };
3610
3611 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3612 {
3613 samsung_cmu_register_one(np, &apollo_cmu_info);
3614 }
3615 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3616 exynos5433_cmu_apollo_init);
3617
3618 /*
3619 * Register offset definitions for CMU_ATLAS
3620 */
3621 #define ATLAS_PLL_LOCK 0x0000
3622 #define ATLAS_PLL_CON0 0x0100
3623 #define ATLAS_PLL_CON1 0x0104
3624 #define ATLAS_PLL_FREQ_DET 0x010c
3625 #define MUX_SEL_ATLAS0 0x0200
3626 #define MUX_SEL_ATLAS1 0x0204
3627 #define MUX_SEL_ATLAS2 0x0208
3628 #define MUX_ENABLE_ATLAS0 0x0300
3629 #define MUX_ENABLE_ATLAS1 0x0304
3630 #define MUX_ENABLE_ATLAS2 0x0308
3631 #define MUX_STAT_ATLAS0 0x0400
3632 #define MUX_STAT_ATLAS1 0x0404
3633 #define MUX_STAT_ATLAS2 0x0408
3634 #define DIV_ATLAS0 0x0600
3635 #define DIV_ATLAS1 0x0604
3636 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3637 #define DIV_STAT_ATLAS0 0x0700
3638 #define DIV_STAT_ATLAS1 0x0704
3639 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3640 #define ENABLE_ACLK_ATLAS 0x0800
3641 #define ENABLE_PCLK_ATLAS 0x0900
3642 #define ENABLE_SCLK_ATLAS 0x0a00
3643 #define ENABLE_IP_ATLAS0 0x0b00
3644 #define ENABLE_IP_ATLAS1 0x0b04
3645 #define CLKOUT_CMU_ATLAS 0x0c00
3646 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3647 #define ARMCLK_STOPCTRL 0x1000
3648 #define ATLAS_PWR_CTRL 0x1020
3649 #define ATLAS_PWR_CTRL2 0x1024
3650 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3651 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3652 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3653
3654 static const unsigned long atlas_clk_regs[] __initconst = {
3655 ATLAS_PLL_LOCK,
3656 ATLAS_PLL_CON0,
3657 ATLAS_PLL_CON1,
3658 ATLAS_PLL_FREQ_DET,
3659 MUX_SEL_ATLAS0,
3660 MUX_SEL_ATLAS1,
3661 MUX_SEL_ATLAS2,
3662 MUX_ENABLE_ATLAS0,
3663 MUX_ENABLE_ATLAS1,
3664 MUX_ENABLE_ATLAS2,
3665 DIV_ATLAS0,
3666 DIV_ATLAS1,
3667 DIV_ATLAS_PLL_FREQ_DET,
3668 ENABLE_ACLK_ATLAS,
3669 ENABLE_PCLK_ATLAS,
3670 ENABLE_SCLK_ATLAS,
3671 ENABLE_IP_ATLAS0,
3672 ENABLE_IP_ATLAS1,
3673 CLKOUT_CMU_ATLAS,
3674 CLKOUT_CMU_ATLAS_DIV_STAT,
3675 ARMCLK_STOPCTRL,
3676 ATLAS_PWR_CTRL,
3677 ATLAS_PWR_CTRL2,
3678 ATLAS_INTR_SPREAD_ENABLE,
3679 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3680 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3681 };
3682
3683 /* list of all parent clock list */
3684 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3685 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3686 PNAME(mout_atlas_p) = { "mout_atlas_pll",
3687 "mout_bus_pll_atlas_user", };
3688
3689 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3690 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3691 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3692 };
3693
3694 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3695 /* MUX_SEL_ATLAS0 */
3696 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3697 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0),
3698
3699 /* MUX_SEL_ATLAS1 */
3700 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3701 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3702
3703 /* MUX_SEL_ATLAS2 */
3704 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3705 0, 1, CLK_SET_RATE_PARENT, 0),
3706 };
3707
3708 static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3709 /* DIV_ATLAS0 */
3710 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3711 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3712 CLK_DIVIDER_READ_ONLY),
3713 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3714 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3715 CLK_DIVIDER_READ_ONLY),
3716 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3717 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3718 CLK_DIVIDER_READ_ONLY),
3719 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3720 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3721 CLK_DIVIDER_READ_ONLY),
3722 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3723 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3724 CLK_DIVIDER_READ_ONLY),
3725 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3726 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3727 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3728 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3729
3730 /* DIV_ATLAS1 */
3731 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3732 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3733 CLK_DIVIDER_READ_ONLY),
3734 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3735 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3736 CLK_DIVIDER_READ_ONLY),
3737 };
3738
3739 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3740 /* ENABLE_ACLK_ATLAS */
3741 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3742 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3743 9, CLK_IGNORE_UNUSED, 0),
3744 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3745 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3746 8, CLK_IGNORE_UNUSED, 0),
3747 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3748 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3749 7, CLK_IGNORE_UNUSED, 0),
3750 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3751 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3752 6, CLK_IGNORE_UNUSED, 0),
3753 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3754 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3755 5, CLK_IGNORE_UNUSED, 0),
3756 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3757 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3758 4, CLK_IGNORE_UNUSED, 0),
3759 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3760 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3761 3, CLK_IGNORE_UNUSED, 0),
3762 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3763 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3764 2, CLK_IGNORE_UNUSED, 0),
3765 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3766 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3767 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3768 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3769
3770 /* ENABLE_PCLK_ATLAS */
3771 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3772 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3773 5, CLK_IGNORE_UNUSED, 0),
3774 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3775 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3776 4, CLK_IGNORE_UNUSED, 0),
3777 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3778 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3779 3, CLK_IGNORE_UNUSED, 0),
3780 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3781 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3782 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3783 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3784 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3785 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3786
3787 /* ENABLE_SCLK_ATLAS */
3788 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3789 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3790 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3791 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3792 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3793 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3794 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3795 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3796 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3797 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3798 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3799 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3800 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3801 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3802 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3803 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3804 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3805 ENABLE_SCLK_ATLAS, 0,
3806 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3807 };
3808
3809 static const struct samsung_cmu_info atlas_cmu_info __initconst = {
3810 .pll_clks = atlas_pll_clks,
3811 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
3812 .mux_clks = atlas_mux_clks,
3813 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
3814 .div_clks = atlas_div_clks,
3815 .nr_div_clks = ARRAY_SIZE(atlas_div_clks),
3816 .gate_clks = atlas_gate_clks,
3817 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
3818 .nr_clk_ids = ATLAS_NR_CLK,
3819 .clk_regs = atlas_clk_regs,
3820 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
3821 };
3822
3823 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3824 {
3825 samsung_cmu_register_one(np, &atlas_cmu_info);
3826 }
3827 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3828 exynos5433_cmu_atlas_init);
3829
3830 /*
3831 * Register offset definitions for CMU_MSCL
3832 */
3833 #define MUX_SEL_MSCL0 0x0200
3834 #define MUX_SEL_MSCL1 0x0204
3835 #define MUX_ENABLE_MSCL0 0x0300
3836 #define MUX_ENABLE_MSCL1 0x0304
3837 #define MUX_STAT_MSCL0 0x0400
3838 #define MUX_STAT_MSCL1 0x0404
3839 #define DIV_MSCL 0x0600
3840 #define DIV_STAT_MSCL 0x0700
3841 #define ENABLE_ACLK_MSCL 0x0800
3842 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3843 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3844 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3845 #define ENABLE_PCLK_MSCL 0x0900
3846 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3847 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3848 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3849 #define ENABLE_SCLK_MSCL 0x0a00
3850 #define ENABLE_IP_MSCL0 0x0b00
3851 #define ENABLE_IP_MSCL1 0x0b04
3852 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3853 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3854 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3855
3856 static const unsigned long mscl_clk_regs[] __initconst = {
3857 MUX_SEL_MSCL0,
3858 MUX_SEL_MSCL1,
3859 MUX_ENABLE_MSCL0,
3860 MUX_ENABLE_MSCL1,
3861 DIV_MSCL,
3862 ENABLE_ACLK_MSCL,
3863 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3864 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3865 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3866 ENABLE_PCLK_MSCL,
3867 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3868 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3869 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3870 ENABLE_SCLK_MSCL,
3871 ENABLE_IP_MSCL0,
3872 ENABLE_IP_MSCL1,
3873 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3874 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3875 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3876 };
3877
3878 /* list of all parent clock list */
3879 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3880 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3881 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3882 "mout_aclk_mscl_400_user", };
3883
3884 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
3885 /* MUX_SEL_MSCL0 */
3886 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3887 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3888 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3889 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3890
3891 /* MUX_SEL_MSCL1 */
3892 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3893 MUX_SEL_MSCL1, 0, 1),
3894 };
3895
3896 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
3897 /* DIV_MSCL */
3898 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3899 DIV_MSCL, 0, 3),
3900 };
3901
3902 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
3903 /* ENABLE_ACLK_MSCL */
3904 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3905 ENABLE_ACLK_MSCL, 9, 0, 0),
3906 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
3907 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
3908 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
3909 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
3910 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3911 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
3912 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3913 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
3914 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
3915 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3916 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
3917 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3918 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
3919 ENABLE_ACLK_MSCL, 2, 0, 0),
3920 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
3921 ENABLE_ACLK_MSCL, 1, 0, 0),
3922 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
3923 ENABLE_ACLK_MSCL, 0, 0, 0),
3924
3925 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3926 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
3927 "mout_aclk_mscl_400_user",
3928 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3929 0, CLK_IGNORE_UNUSED, 0),
3930
3931 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3932 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
3933 "mout_aclk_mscl_400_user",
3934 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3935 0, CLK_IGNORE_UNUSED, 0),
3936
3937 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
3938 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
3939 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3940 0, CLK_IGNORE_UNUSED, 0),
3941
3942 /* ENABLE_PCLK_MSCL */
3943 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
3944 ENABLE_PCLK_MSCL, 7, 0, 0),
3945 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
3946 ENABLE_PCLK_MSCL, 6, 0, 0),
3947 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
3948 ENABLE_PCLK_MSCL, 5, 0, 0),
3949 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
3950 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3951 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
3952 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3953 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
3954 ENABLE_PCLK_MSCL, 2, 0, 0),
3955 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
3956 ENABLE_PCLK_MSCL, 1, 0, 0),
3957 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
3958 ENABLE_PCLK_MSCL, 0, 0, 0),
3959
3960 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3961 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
3962 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3963 0, CLK_IGNORE_UNUSED, 0),
3964
3965 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3966 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
3967 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3968 0, CLK_IGNORE_UNUSED, 0),
3969
3970 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
3971 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
3972 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3973 0, CLK_IGNORE_UNUSED, 0),
3974
3975 /* ENABLE_SCLK_MSCL */
3976 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
3977 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3978 };
3979
3980 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
3981 .mux_clks = mscl_mux_clks,
3982 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
3983 .div_clks = mscl_div_clks,
3984 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
3985 .gate_clks = mscl_gate_clks,
3986 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
3987 .nr_clk_ids = MSCL_NR_CLK,
3988 .clk_regs = mscl_clk_regs,
3989 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
3990 };
3991
3992 static void __init exynos5433_cmu_mscl_init(struct device_node *np)
3993 {
3994 samsung_cmu_register_one(np, &mscl_cmu_info);
3995 }
3996 CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
3997 exynos5433_cmu_mscl_init);
3998
3999 /*
4000 * Register offset definitions for CMU_MFC
4001 */
4002 #define MUX_SEL_MFC 0x0200
4003 #define MUX_ENABLE_MFC 0x0300
4004 #define MUX_STAT_MFC 0x0400
4005 #define DIV_MFC 0x0600
4006 #define DIV_STAT_MFC 0x0700
4007 #define ENABLE_ACLK_MFC 0x0800
4008 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4009 #define ENABLE_PCLK_MFC 0x0900
4010 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4011 #define ENABLE_IP_MFC0 0x0b00
4012 #define ENABLE_IP_MFC1 0x0b04
4013 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4014
4015 static const unsigned long mfc_clk_regs[] __initconst = {
4016 MUX_SEL_MFC,
4017 MUX_ENABLE_MFC,
4018 DIV_MFC,
4019 ENABLE_ACLK_MFC,
4020 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4021 ENABLE_PCLK_MFC,
4022 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4023 ENABLE_IP_MFC0,
4024 ENABLE_IP_MFC1,
4025 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4026 };
4027
4028 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4029
4030 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4031 /* MUX_SEL_MFC */
4032 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4033 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4034 };
4035
4036 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4037 /* DIV_MFC */
4038 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4039 DIV_MFC, 0, 2),
4040 };
4041
4042 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4043 /* ENABLE_ACLK_MFC */
4044 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4045 ENABLE_ACLK_MFC, 6, 0, 0),
4046 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4047 ENABLE_ACLK_MFC, 5, 0, 0),
4048 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4049 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4050 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4051 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4052 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4053 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4054 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4055 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4056 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4057 ENABLE_ACLK_MFC, 0, 0, 0),
4058
4059 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4060 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4061 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4062 1, CLK_IGNORE_UNUSED, 0),
4063 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4064 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4065 0, CLK_IGNORE_UNUSED, 0),
4066
4067 /* ENABLE_PCLK_MFC */
4068 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4069 ENABLE_PCLK_MFC, 4, 0, 0),
4070 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4071 ENABLE_PCLK_MFC, 3, 0, 0),
4072 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4073 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4074 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4075 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4076 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4077 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4078
4079 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4080 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4081 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4082 1, CLK_IGNORE_UNUSED, 0),
4083 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4084 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4085 0, CLK_IGNORE_UNUSED, 0),
4086 };
4087
4088 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4089 .mux_clks = mfc_mux_clks,
4090 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4091 .div_clks = mfc_div_clks,
4092 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4093 .gate_clks = mfc_gate_clks,
4094 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4095 .nr_clk_ids = MFC_NR_CLK,
4096 .clk_regs = mfc_clk_regs,
4097 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4098 };
4099
4100 static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4101 {
4102 samsung_cmu_register_one(np, &mfc_cmu_info);
4103 }
4104 CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4105 exynos5433_cmu_mfc_init);
4106
4107 /*
4108 * Register offset definitions for CMU_HEVC
4109 */
4110 #define MUX_SEL_HEVC 0x0200
4111 #define MUX_ENABLE_HEVC 0x0300
4112 #define MUX_STAT_HEVC 0x0400
4113 #define DIV_HEVC 0x0600
4114 #define DIV_STAT_HEVC 0x0700
4115 #define ENABLE_ACLK_HEVC 0x0800
4116 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4117 #define ENABLE_PCLK_HEVC 0x0900
4118 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4119 #define ENABLE_IP_HEVC0 0x0b00
4120 #define ENABLE_IP_HEVC1 0x0b04
4121 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4122
4123 static const unsigned long hevc_clk_regs[] __initconst = {
4124 MUX_SEL_HEVC,
4125 MUX_ENABLE_HEVC,
4126 DIV_HEVC,
4127 ENABLE_ACLK_HEVC,
4128 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4129 ENABLE_PCLK_HEVC,
4130 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4131 ENABLE_IP_HEVC0,
4132 ENABLE_IP_HEVC1,
4133 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4134 };
4135
4136 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4137
4138 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4139 /* MUX_SEL_HEVC */
4140 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4141 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4142 };
4143
4144 static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4145 /* DIV_HEVC */
4146 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4147 DIV_HEVC, 0, 2),
4148 };
4149
4150 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4151 /* ENABLE_ACLK_HEVC */
4152 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4153 ENABLE_ACLK_HEVC, 6, 0, 0),
4154 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4155 ENABLE_ACLK_HEVC, 5, 0, 0),
4156 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4157 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4158 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4159 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4160 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4161 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4162 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4163 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4164 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4165 ENABLE_ACLK_HEVC, 0, 0, 0),
4166
4167 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4168 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4169 "mout_aclk_hevc_400_user",
4170 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4171 1, CLK_IGNORE_UNUSED, 0),
4172 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4173 "mout_aclk_hevc_400_user",
4174 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4175 0, CLK_IGNORE_UNUSED, 0),
4176
4177 /* ENABLE_PCLK_HEVC */
4178 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4179 ENABLE_PCLK_HEVC, 4, 0, 0),
4180 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4181 ENABLE_PCLK_HEVC, 3, 0, 0),
4182 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4183 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4184 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4185 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4186 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4187 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4188
4189 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4190 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4191 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4192 1, CLK_IGNORE_UNUSED, 0),
4193 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4194 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4195 0, CLK_IGNORE_UNUSED, 0),
4196 };
4197
4198 static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4199 .mux_clks = hevc_mux_clks,
4200 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4201 .div_clks = hevc_div_clks,
4202 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4203 .gate_clks = hevc_gate_clks,
4204 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4205 .nr_clk_ids = HEVC_NR_CLK,
4206 .clk_regs = hevc_clk_regs,
4207 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4208 };
4209
4210 static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4211 {
4212 samsung_cmu_register_one(np, &hevc_cmu_info);
4213 }
4214 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4215 exynos5433_cmu_hevc_init);
4216
4217 /*
4218 * Register offset definitions for CMU_ISP
4219 */
4220 #define MUX_SEL_ISP 0x0200
4221 #define MUX_ENABLE_ISP 0x0300
4222 #define MUX_STAT_ISP 0x0400
4223 #define DIV_ISP 0x0600
4224 #define DIV_STAT_ISP 0x0700
4225 #define ENABLE_ACLK_ISP0 0x0800
4226 #define ENABLE_ACLK_ISP1 0x0804
4227 #define ENABLE_ACLK_ISP2 0x0808
4228 #define ENABLE_PCLK_ISP 0x0900
4229 #define ENABLE_SCLK_ISP 0x0a00
4230 #define ENABLE_IP_ISP0 0x0b00
4231 #define ENABLE_IP_ISP1 0x0b04
4232 #define ENABLE_IP_ISP2 0x0b08
4233 #define ENABLE_IP_ISP3 0x0b0c
4234
4235 static const unsigned long isp_clk_regs[] __initconst = {
4236 MUX_SEL_ISP,
4237 MUX_ENABLE_ISP,
4238 DIV_ISP,
4239 ENABLE_ACLK_ISP0,
4240 ENABLE_ACLK_ISP1,
4241 ENABLE_ACLK_ISP2,
4242 ENABLE_PCLK_ISP,
4243 ENABLE_SCLK_ISP,
4244 ENABLE_IP_ISP0,
4245 ENABLE_IP_ISP1,
4246 ENABLE_IP_ISP2,
4247 ENABLE_IP_ISP3,
4248 };
4249
4250 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4251 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4252
4253 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4254 /* MUX_SEL_ISP */
4255 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4256 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4257 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4258 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4259 };
4260
4261 static const struct samsung_div_clock isp_div_clks[] __initconst = {
4262 /* DIV_ISP */
4263 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4264 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4265 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4266 DIV_ISP, 8, 3),
4267 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4268 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4269 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4270 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4271 };
4272
4273 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4274 /* ENABLE_ACLK_ISP0 */
4275 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4276 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4277 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4278 ENABLE_ACLK_ISP0, 5, 0, 0),
4279 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4280 ENABLE_ACLK_ISP0, 4, 0, 0),
4281 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4282 ENABLE_ACLK_ISP0, 3, 0, 0),
4283 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4284 ENABLE_ACLK_ISP0, 2, 0, 0),
4285 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4286 ENABLE_ACLK_ISP0, 1, 0, 0),
4287 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4288 ENABLE_ACLK_ISP0, 0, 0, 0),
4289
4290 /* ENABLE_ACLK_ISP1 */
4291 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4292 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4293 17, CLK_IGNORE_UNUSED, 0),
4294 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4295 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4296 16, CLK_IGNORE_UNUSED, 0),
4297 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4298 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4299 15, CLK_IGNORE_UNUSED, 0),
4300 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4301 "div_pclk_isp", ENABLE_ACLK_ISP1,
4302 14, CLK_IGNORE_UNUSED, 0),
4303 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4304 "div_pclk_isp", ENABLE_ACLK_ISP1,
4305 13, CLK_IGNORE_UNUSED, 0),
4306 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4307 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4308 12, CLK_IGNORE_UNUSED, 0),
4309 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4310 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4311 11, CLK_IGNORE_UNUSED, 0),
4312 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4313 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4314 10, CLK_IGNORE_UNUSED, 0),
4315 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4316 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4317 9, CLK_IGNORE_UNUSED, 0),
4318 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4319 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4320 8, CLK_IGNORE_UNUSED, 0),
4321 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4322 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4323 7, CLK_IGNORE_UNUSED, 0),
4324 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4325 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4326 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4327 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4328 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4329 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4330 4, CLK_IGNORE_UNUSED, 0),
4331 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4332 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4333 3, CLK_IGNORE_UNUSED, 0),
4334 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4335 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4336 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4337 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4338 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4339 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4340
4341 /* ENABLE_ACLK_ISP2 */
4342 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4343 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4344 13, CLK_IGNORE_UNUSED, 0),
4345 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4346 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4347 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4348 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4349 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4350 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4351 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4352 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4353 9, CLK_IGNORE_UNUSED, 0),
4354 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4355 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4356 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4357 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4358 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4359 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4360 6, CLK_IGNORE_UNUSED, 0),
4361 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4362 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4363 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4364 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4365 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4366 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4367 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4368 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4369 2, CLK_IGNORE_UNUSED, 0),
4370 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4371 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4372 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4373 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4374
4375 /* ENABLE_PCLK_ISP */
4376 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4377 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4378 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4379 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4380 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4381 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4382 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4383 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4384 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4385 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4386 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4387 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4388 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4389 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4390 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4391 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4392 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4393 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4394 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4395 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4396 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4397 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4398 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4399 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4400 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4401 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4402 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4403 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4404 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4405 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4406 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4407 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4408 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4409 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4410 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4411 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4412 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4413 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4414 7, CLK_IGNORE_UNUSED, 0),
4415 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4416 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4417 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4418 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4419 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4420 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4421 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4422 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4423 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4424 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4425 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4426 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4427 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4428 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4429
4430 /* ENABLE_SCLK_ISP */
4431 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4432 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4433 5, CLK_IGNORE_UNUSED, 0),
4434 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4435 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4436 4, CLK_IGNORE_UNUSED, 0),
4437 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4438 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4439 3, CLK_IGNORE_UNUSED, 0),
4440 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4441 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4442 2, CLK_IGNORE_UNUSED, 0),
4443 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4444 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4445 1, CLK_IGNORE_UNUSED, 0),
4446 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4447 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4448 0, CLK_IGNORE_UNUSED, 0),
4449 };
4450
4451 static const struct samsung_cmu_info isp_cmu_info __initconst = {
4452 .mux_clks = isp_mux_clks,
4453 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4454 .div_clks = isp_div_clks,
4455 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4456 .gate_clks = isp_gate_clks,
4457 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4458 .nr_clk_ids = ISP_NR_CLK,
4459 .clk_regs = isp_clk_regs,
4460 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4461 };
4462
4463 static void __init exynos5433_cmu_isp_init(struct device_node *np)
4464 {
4465 samsung_cmu_register_one(np, &isp_cmu_info);
4466 }
4467 CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4468 exynos5433_cmu_isp_init);
4469
4470 /*
4471 * Register offset definitions for CMU_CAM0
4472 */
4473 #define MUX_SEL_CAM00 0x0200
4474 #define MUX_SEL_CAM01 0x0204
4475 #define MUX_SEL_CAM02 0x0208
4476 #define MUX_SEL_CAM03 0x020c
4477 #define MUX_SEL_CAM04 0x0210
4478 #define MUX_ENABLE_CAM00 0x0300
4479 #define MUX_ENABLE_CAM01 0x0304
4480 #define MUX_ENABLE_CAM02 0x0308
4481 #define MUX_ENABLE_CAM03 0x030c
4482 #define MUX_ENABLE_CAM04 0x0310
4483 #define MUX_STAT_CAM00 0x0400
4484 #define MUX_STAT_CAM01 0x0404
4485 #define MUX_STAT_CAM02 0x0408
4486 #define MUX_STAT_CAM03 0x040c
4487 #define MUX_STAT_CAM04 0x0410
4488 #define MUX_IGNORE_CAM01 0x0504
4489 #define DIV_CAM00 0x0600
4490 #define DIV_CAM01 0x0604
4491 #define DIV_CAM02 0x0608
4492 #define DIV_CAM03 0x060c
4493 #define DIV_STAT_CAM00 0x0700
4494 #define DIV_STAT_CAM01 0x0704
4495 #define DIV_STAT_CAM02 0x0708
4496 #define DIV_STAT_CAM03 0x070c
4497 #define ENABLE_ACLK_CAM00 0X0800
4498 #define ENABLE_ACLK_CAM01 0X0804
4499 #define ENABLE_ACLK_CAM02 0X0808
4500 #define ENABLE_PCLK_CAM0 0X0900
4501 #define ENABLE_SCLK_CAM0 0X0a00
4502 #define ENABLE_IP_CAM00 0X0b00
4503 #define ENABLE_IP_CAM01 0X0b04
4504 #define ENABLE_IP_CAM02 0X0b08
4505 #define ENABLE_IP_CAM03 0X0b0C
4506
4507 static const unsigned long cam0_clk_regs[] __initconst = {
4508 MUX_SEL_CAM00,
4509 MUX_SEL_CAM01,
4510 MUX_SEL_CAM02,
4511 MUX_SEL_CAM03,
4512 MUX_SEL_CAM04,
4513 MUX_ENABLE_CAM00,
4514 MUX_ENABLE_CAM01,
4515 MUX_ENABLE_CAM02,
4516 MUX_ENABLE_CAM03,
4517 MUX_ENABLE_CAM04,
4518 MUX_IGNORE_CAM01,
4519 DIV_CAM00,
4520 DIV_CAM01,
4521 DIV_CAM02,
4522 DIV_CAM03,
4523 ENABLE_ACLK_CAM00,
4524 ENABLE_ACLK_CAM01,
4525 ENABLE_ACLK_CAM02,
4526 ENABLE_PCLK_CAM0,
4527 ENABLE_SCLK_CAM0,
4528 ENABLE_IP_CAM00,
4529 ENABLE_IP_CAM01,
4530 ENABLE_IP_CAM02,
4531 ENABLE_IP_CAM03,
4532 };
4533 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4534 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4535 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4536
4537 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4538 "phyclk_rxbyteclkhs0_s4_phy", };
4539 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4540 "phyclk_rxbyteclkhs0_s2a_phy", };
4541
4542 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4543 "mout_aclk_cam0_333_user", };
4544 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4545 "mout_aclk_cam0_400_user", };
4546 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4547 "mout_aclk_cam0_333_user", };
4548 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4549 "mout_aclk_cam0_400_user", };
4550 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4551 "mout_aclk_cam0_333_user", };
4552 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4553 "mout_aclk_cam0_400_user", };
4554 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4555 "mout_aclk_cam0_333_user", };
4556
4557 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4558 "mout_aclk_cam0_333_user" };
4559 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4560 "mout_aclk_cam0_400_user", };
4561 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4562 "mout_aclk_cam0_333_user", };
4563 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4564 "mout_aclk-cam0_400_user", };
4565 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4566 "mout_aclk_cam0_333_user", };
4567 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4568 "mout_aclk_cam0_400_user", };
4569 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4570 "mout_aclk_cam0_333_user", };
4571 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4572 "mout_aclk_cam0_400_user", };
4573
4574 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4575 "div_pclk_lite_d", };
4576 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4577 "div_pclk_pixelasync_lite_c", };
4578 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4579 "div_pclk_lite_b", };
4580 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4581 "mout_aclk_cam0_333_user", };
4582 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4583 "mout_aclk_cam0_400_user", };
4584 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4585 "mout_sclk_pixelasync_lite_c_init_a",
4586 "mout_aclk_cam0_400_user", };
4587 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4588 "mout_aclk_cam0_552_user",
4589 "mout_aclk_cam0_400_user", };
4590
4591 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4592 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4593 NULL, 0, 100000000),
4594 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4595 NULL, 0, 100000000),
4596 };
4597
4598 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4599 /* MUX_SEL_CAM00 */
4600 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4601 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4602 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4603 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4604 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4605 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4606
4607 /* MUX_SEL_CAM01 */
4608 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4609 "mout_phyclk_rxbyteclkhs0_s4_user",
4610 mout_phyclk_rxbyteclkhs0_s4_user_p,
4611 MUX_SEL_CAM01, 4, 1),
4612 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4613 "mout_phyclk_rxbyteclkhs0_s2a_user",
4614 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4615 MUX_SEL_CAM01, 0, 1),
4616
4617 /* MUX_SEL_CAM02 */
4618 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4619 MUX_SEL_CAM02, 24, 1),
4620 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4621 MUX_SEL_CAM02, 20, 1),
4622 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4623 MUX_SEL_CAM02, 16, 1),
4624 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4625 MUX_SEL_CAM02, 12, 1),
4626 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4627 MUX_SEL_CAM02, 8, 1),
4628 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4629 MUX_SEL_CAM02, 4, 1),
4630 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4631 MUX_SEL_CAM02, 0, 1),
4632
4633 /* MUX_SEL_CAM03 */
4634 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4635 MUX_SEL_CAM03, 28, 1),
4636 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4637 MUX_SEL_CAM03, 24, 1),
4638 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4639 MUX_SEL_CAM03, 20, 1),
4640 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4641 MUX_SEL_CAM03, 16, 1),
4642 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4643 MUX_SEL_CAM03, 12, 1),
4644 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4645 MUX_SEL_CAM03, 8, 1),
4646 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4647 MUX_SEL_CAM03, 4, 1),
4648 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4649 MUX_SEL_CAM03, 0, 1),
4650
4651 /* MUX_SEL_CAM04 */
4652 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4653 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4654 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4655 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4656 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4657 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4658 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4659 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4660 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4661 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4662 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4663 "mout_sclk_pixelasync_lite_c_init_b",
4664 mout_sclk_pixelasync_lite_c_init_b_p,
4665 MUX_SEL_CAM04, 4, 1),
4666 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4667 "mout_sclk_pixelasync_lite_c_init_a",
4668 mout_sclk_pixelasync_lite_c_init_a_p,
4669 MUX_SEL_CAM04, 0, 1),
4670 };
4671
4672 static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4673 /* DIV_CAM00 */
4674 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4675 DIV_CAM00, 8, 2),
4676 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4677 DIV_CAM00, 4, 3),
4678 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4679 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4680
4681 /* DIV_CAM01 */
4682 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4683 DIV_CAM01, 20, 2),
4684 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4685 DIV_CAM01, 16, 3),
4686 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4687 DIV_CAM01, 12, 2),
4688 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4689 DIV_CAM01, 8, 3),
4690 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4691 DIV_CAM01, 4, 2),
4692 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4693 DIV_CAM01, 0, 3),
4694
4695 /* DIV_CAM02 */
4696 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4697 DIV_CAM02, 20, 3),
4698 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4699 DIV_CAM02, 16, 3),
4700 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4701 DIV_CAM02, 12, 2),
4702 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4703 DIV_CAM02, 8, 3),
4704 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4705 DIV_CAM02, 4, 2),
4706 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4707 DIV_CAM02, 0, 3),
4708
4709 /* DIV_CAM03 */
4710 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4711 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4712 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4713 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4714 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4715 "div_sclk_pixelasync_lite_c_init",
4716 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4717 };
4718
4719 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4720 /* ENABLE_ACLK_CAM00 */
4721 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4722 6, 0, 0),
4723 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4724 5, 0, 0),
4725 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4726 4, 0, 0),
4727 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4728 3, 0, 0),
4729 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4730 ENABLE_ACLK_CAM00, 2, 0, 0),
4731 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4732 ENABLE_ACLK_CAM00, 1, 0, 0),
4733 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4734 ENABLE_ACLK_CAM00, 0, 0, 0),
4735
4736 /* ENABLE_ACLK_CAM01 */
4737 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4738 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4739 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4740 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4741 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4742 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4743 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4744 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4745 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4746 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4747 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4748 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4749 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4750 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4751 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4752 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4753 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4754 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4755 23, CLK_IGNORE_UNUSED, 0),
4756 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4757 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4758 22, CLK_IGNORE_UNUSED, 0),
4759 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4760 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4761 21, CLK_IGNORE_UNUSED, 0),
4762 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4763 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4764 20, CLK_IGNORE_UNUSED, 0),
4765 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4766 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4767 19, CLK_IGNORE_UNUSED, 0),
4768 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4769 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4770 18, CLK_IGNORE_UNUSED, 0),
4771 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4772 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4773 17, CLK_IGNORE_UNUSED, 0),
4774 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4775 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4776 16, CLK_IGNORE_UNUSED, 0),
4777 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4778 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4779 15, CLK_IGNORE_UNUSED, 0),
4780 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4781 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4782 14, CLK_IGNORE_UNUSED, 0),
4783 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4784 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4785 13, CLK_IGNORE_UNUSED, 0),
4786 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4787 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4788 12, CLK_IGNORE_UNUSED, 0),
4789 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4790 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4791 11, CLK_IGNORE_UNUSED, 0),
4792 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4793 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4794 10, CLK_IGNORE_UNUSED, 0),
4795 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4796 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4797 9, CLK_IGNORE_UNUSED, 0),
4798 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4799 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4800 8, CLK_IGNORE_UNUSED, 0),
4801 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4802 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4803 7, CLK_IGNORE_UNUSED, 0),
4804 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4805 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4806 6, CLK_IGNORE_UNUSED, 0),
4807 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4808 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4809 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4810 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4811 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4812 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4813 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4814 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4815 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4816 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4817 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4818 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4819
4820 /* ENABLE_ACLK_CAM02 */
4821 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4822 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4823 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4824 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4825 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4826 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4827 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4828 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4829 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4830 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4831 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4832 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4833 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4834 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4835 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4836 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4837 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4838 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4839 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4840 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4841
4842 /* ENABLE_PCLK_CAM0 */
4843 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4844 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4845 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4846 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4847 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4848 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4849 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4850 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4851 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4852 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4853 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4854 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4855 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4856 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4857 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4858 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4859 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4860 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4861 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4862 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4863 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4864 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4865 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4866 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
4867 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4868 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
4869 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
4870 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4871 12, CLK_IGNORE_UNUSED, 0),
4872 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
4873 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4874 11, CLK_IGNORE_UNUSED, 0),
4875 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
4876 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4877 10, CLK_IGNORE_UNUSED, 0),
4878 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
4879 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
4880 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
4881 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
4882 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
4883 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
4884 7, CLK_IGNORE_UNUSED, 0),
4885 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
4886 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
4887 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
4888 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
4889 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
4890 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
4891 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
4892 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
4893 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
4894 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
4895 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
4896 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
4897 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
4898 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
4899
4900 /* ENABLE_SCLK_CAM0 */
4901 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
4902 "mout_phyclk_rxbyteclkhs0_s4_user",
4903 ENABLE_SCLK_CAM0, 8, 0, 0),
4904 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
4905 "mout_phyclk_rxbyteclkhs0_s2a_user",
4906 ENABLE_SCLK_CAM0, 7, 0, 0),
4907 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
4908 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
4909 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
4910 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
4911 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
4912 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
4913 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
4914 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
4915 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
4916 "div_sclk_pixelasync_lite_c",
4917 ENABLE_SCLK_CAM0, 2, 0, 0),
4918 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
4919 "div_sclk_pixelasync_lite_c_init",
4920 ENABLE_SCLK_CAM0, 1, 0, 0),
4921 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
4922 "div_sclk_pixelasync_lite_c",
4923 ENABLE_SCLK_CAM0, 0, 0, 0),
4924 };
4925
4926 static const struct samsung_cmu_info cam0_cmu_info __initconst = {
4927 .mux_clks = cam0_mux_clks,
4928 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
4929 .div_clks = cam0_div_clks,
4930 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
4931 .gate_clks = cam0_gate_clks,
4932 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
4933 .fixed_clks = cam0_fixed_clks,
4934 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
4935 .nr_clk_ids = CAM0_NR_CLK,
4936 .clk_regs = cam0_clk_regs,
4937 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
4938 };
4939
4940 static void __init exynos5433_cmu_cam0_init(struct device_node *np)
4941 {
4942 samsung_cmu_register_one(np, &cam0_cmu_info);
4943 }
4944 CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
4945 exynos5433_cmu_cam0_init);
4946
4947 /*
4948 * Register offset definitions for CMU_CAM1
4949 */
4950 #define MUX_SEL_CAM10 0x0200
4951 #define MUX_SEL_CAM11 0x0204
4952 #define MUX_SEL_CAM12 0x0208
4953 #define MUX_ENABLE_CAM10 0x0300
4954 #define MUX_ENABLE_CAM11 0x0304
4955 #define MUX_ENABLE_CAM12 0x0308
4956 #define MUX_STAT_CAM10 0x0400
4957 #define MUX_STAT_CAM11 0x0404
4958 #define MUX_STAT_CAM12 0x0408
4959 #define MUX_IGNORE_CAM11 0x0504
4960 #define DIV_CAM10 0x0600
4961 #define DIV_CAM11 0x0604
4962 #define DIV_STAT_CAM10 0x0700
4963 #define DIV_STAT_CAM11 0x0704
4964 #define ENABLE_ACLK_CAM10 0X0800
4965 #define ENABLE_ACLK_CAM11 0X0804
4966 #define ENABLE_ACLK_CAM12 0X0808
4967 #define ENABLE_PCLK_CAM1 0X0900
4968 #define ENABLE_SCLK_CAM1 0X0a00
4969 #define ENABLE_IP_CAM10 0X0b00
4970 #define ENABLE_IP_CAM11 0X0b04
4971 #define ENABLE_IP_CAM12 0X0b08
4972
4973 static const unsigned long cam1_clk_regs[] __initconst = {
4974 MUX_SEL_CAM10,
4975 MUX_SEL_CAM11,
4976 MUX_SEL_CAM12,
4977 MUX_ENABLE_CAM10,
4978 MUX_ENABLE_CAM11,
4979 MUX_ENABLE_CAM12,
4980 MUX_IGNORE_CAM11,
4981 DIV_CAM10,
4982 DIV_CAM11,
4983 ENABLE_ACLK_CAM10,
4984 ENABLE_ACLK_CAM11,
4985 ENABLE_ACLK_CAM12,
4986 ENABLE_PCLK_CAM1,
4987 ENABLE_SCLK_CAM1,
4988 ENABLE_IP_CAM10,
4989 ENABLE_IP_CAM11,
4990 ENABLE_IP_CAM12,
4991 };
4992
4993 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
4994 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
4995 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
4996
4997 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
4998 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
4999 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5000
5001 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5002 "phyclk_rxbyteclkhs0_s2b_phy", };
5003
5004 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5005 "mout_aclk_cam1_333_user", };
5006 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5007 "mout_aclk_cam1_400_user", };
5008
5009 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5010 "mout_aclk_cam1_333_user", };
5011 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5012 "mout_aclk_cam1_400_user", };
5013
5014 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5015 "mout_aclk_cam1_333_user", };
5016 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5017 "mout_aclk_cam1_400_user", };
5018
5019 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5020 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5021 0, 100000000),
5022 };
5023
5024 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5025 /* MUX_SEL_CAM10 */
5026 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5027 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5028 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5029 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5030 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5031 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5032 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5033 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5034 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5035 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5036 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5037 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5038
5039 /* MUX_SEL_CAM11 */
5040 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5041 "mout_phyclk_rxbyteclkhs0_s2b_user",
5042 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5043 MUX_SEL_CAM11, 0, 1),
5044
5045 /* MUX_SEL_CAM12 */
5046 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5047 MUX_SEL_CAM12, 20, 1),
5048 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5049 MUX_SEL_CAM12, 16, 1),
5050 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5051 MUX_SEL_CAM12, 12, 1),
5052 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5053 MUX_SEL_CAM12, 8, 1),
5054 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5055 MUX_SEL_CAM12, 4, 1),
5056 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5057 MUX_SEL_CAM12, 0, 1),
5058 };
5059
5060 static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5061 /* DIV_CAM10 */
5062 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5063 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5064 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5065 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5066 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5067 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5068 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5069 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5070 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5071 DIV_CAM10, 0, 3),
5072
5073 /* DIV_CAM11 */
5074 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5075 DIV_CAM11, 16, 3),
5076 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5077 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5078 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5079 DIV_CAM11, 4, 2),
5080 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5081 DIV_CAM11, 0, 3),
5082 };
5083
5084 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5085 /* ENABLE_ACLK_CAM10 */
5086 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5087 ENABLE_ACLK_CAM10, 4, 0, 0),
5088 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5089 ENABLE_ACLK_CAM10, 3, 0, 0),
5090 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5091 ENABLE_ACLK_CAM10, 1, 0, 0),
5092 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5093 ENABLE_ACLK_CAM10, 0, 0, 0),
5094
5095 /* ENABLE_ACLK_CAM11 */
5096 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5097 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5098 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5099 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5100 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5101 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5102 27, CLK_IGNORE_UNUSED, 0),
5103 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5104 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5105 26, CLK_IGNORE_UNUSED, 0),
5106 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5107 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5108 25, CLK_IGNORE_UNUSED, 0),
5109 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5110 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5111 24, CLK_IGNORE_UNUSED, 0),
5112 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5113 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5114 23, CLK_IGNORE_UNUSED, 0),
5115 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5116 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5117 22, CLK_IGNORE_UNUSED, 0),
5118 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5119 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5120 21, CLK_IGNORE_UNUSED, 0),
5121 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5122 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5123 20, CLK_IGNORE_UNUSED, 0),
5124 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5125 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5126 19, CLK_IGNORE_UNUSED, 0),
5127 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5128 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5129 18, CLK_IGNORE_UNUSED, 0),
5130 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5131 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5132 17, CLK_IGNORE_UNUSED, 0),
5133 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5134 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5135 16, CLK_IGNORE_UNUSED, 0),
5136 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5137 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5138 15, CLK_IGNORE_UNUSED, 0),
5139 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5140 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5141 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5142 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5143 13, CLK_IGNORE_UNUSED, 0),
5144 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5145 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5146 12, CLK_IGNORE_UNUSED, 0),
5147 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5148 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5149 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5150 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5151 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5152 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5153 9, CLK_IGNORE_UNUSED, 0),
5154 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5155 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5156 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5157 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5158 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5159 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5160 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5161 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5162 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5163 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5164 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5165 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5166 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5167 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5168 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5169 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5170 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5171 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5172
5173 /* ENABLE_ACLK_CAM12 */
5174 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5175 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5176 10, CLK_IGNORE_UNUSED, 0),
5177 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5178 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5179 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5180 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5181 8, CLK_IGNORE_UNUSED, 0),
5182 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5183 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5184 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5185 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5186 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5187 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5188 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5189 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5190 4, CLK_IGNORE_UNUSED, 0),
5191 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5192 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5193 3, CLK_IGNORE_UNUSED, 0),
5194 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5195 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5196 2, CLK_IGNORE_UNUSED, 0),
5197 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5198 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5199 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5200 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5201 0, CLK_IGNORE_UNUSED, 0),
5202
5203 /* ENABLE_PCLK_CAM1 */
5204 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5205 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5206 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5207 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5208 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5209 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5210 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5211 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5212 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5213 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5214 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5215 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5216 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5217 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5218 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5219 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5220 20, CLK_IGNORE_UNUSED, 0),
5221 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5222 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5223 19, CLK_IGNORE_UNUSED, 0),
5224 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5225 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5226 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5227 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5228 17, CLK_IGNORE_UNUSED, 0),
5229 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5230 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5231 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5232 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5233 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5234 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5235 14, CLK_IGNORE_UNUSED, 0),
5236 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5237 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5238 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5239 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5240 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5241 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5242 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5243 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5244 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5245 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5246 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5247 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5248 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5249 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5250 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5251 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5252 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5253 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5254 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5255 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5256 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5257 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5258 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5259 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5260 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5261 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5262 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5263 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5264
5265 /* ENABLE_SCLK_CAM1 */
5266 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5267 15, 0, 0),
5268 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5269 14, 0, 0),
5270 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5271 13, 0, 0),
5272 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5273 12, 0, 0),
5274 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5275 "mout_phyclk_rxbyteclkhs0_s2b_user",
5276 ENABLE_SCLK_CAM1, 11, 0, 0),
5277 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5278 ENABLE_SCLK_CAM1, 10, 0, 0),
5279 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5280 ENABLE_SCLK_CAM1, 9, 0, 0),
5281 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5282 ENABLE_SCLK_CAM1, 7, 0, 0),
5283 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5284 ENABLE_SCLK_CAM1, 6, 0, 0),
5285 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5286 ENABLE_SCLK_CAM1, 5, 0, 0),
5287 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5288 ENABLE_SCLK_CAM1, 4, 0, 0),
5289 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5290 ENABLE_SCLK_CAM1, 3, 0, 0),
5291 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5292 ENABLE_SCLK_CAM1, 2, 0, 0),
5293 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5294 ENABLE_SCLK_CAM1, 1, 0, 0),
5295 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5296 ENABLE_SCLK_CAM1, 0, 0, 0),
5297 };
5298
5299 static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5300 .mux_clks = cam1_mux_clks,
5301 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5302 .div_clks = cam1_div_clks,
5303 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5304 .gate_clks = cam1_gate_clks,
5305 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5306 .fixed_clks = cam1_fixed_clks,
5307 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5308 .nr_clk_ids = CAM1_NR_CLK,
5309 .clk_regs = cam1_clk_regs,
5310 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5311 };
5312
5313 static void __init exynos5433_cmu_cam1_init(struct device_node *np)
5314 {
5315 samsung_cmu_register_one(np, &cam1_cmu_info);
5316 }
5317 CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
5318 exynos5433_cmu_cam1_init);
Linux kernel - Deliverables
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