drivers/clk/samsung/clk.h

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Copyright (c) 2013 Linaro Ltd.
   4  * Author: Thomas Abraham <thomas.ab@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Common Clock Framework support for all Samsung platforms
  11 */
  12
  13 #ifndef __SAMSUNG_CLK_H
  14 #define __SAMSUNG_CLK_H
  15
  16 #include <linux/clk.h>
  17 #include <linux/clkdev.h>
  18 #include <linux/io.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include "clk-pll.h"
  23
  24 /**
  25  * struct samsung_clock_alias: information about mux clock
  26  * @id: platform specific id of the clock.
  27  * @dev_name: name of the device to which this clock belongs.
  28  * @alias: optional clock alias name to be assigned to this clock.
  29  */
  30 struct samsung_clock_alias {
  31         unsigned int            id;
  32         const char              *dev_name;
  33         const char              *alias;
  34 };
  35
  36 #define ALIAS(_id, dname, a)    \
  37         {                                                       \
  38                 .id             = _id,                          \
  39                 .dev_name       = dname,                        \
  40                 .alias          = a,                            \
  41         }
  42
  43 #define MHZ (1000 * 1000)
  44
  45 /**
  46  * struct samsung_fixed_rate_clock: information about fixed-rate clock
  47  * @id: platform specific id of the clock.
  48  * @name: name of this fixed-rate clock.
  49  * @parent_name: optional parent clock name.
  50  * @flags: optional fixed-rate clock flags.
  51  * @fixed-rate: fixed clock rate of this clock.
  52  */
  53 struct samsung_fixed_rate_clock {
  54         unsigned int            id;
  55         char                    *name;
  56         const char              *parent_name;
  57         unsigned long           flags;
  58         unsigned long           fixed_rate;
  59 };
  60
  61 #define FRATE(_id, cname, pname, f, frate)              \
  62         {                                               \
  63                 .id             = _id,                  \
  64                 .name           = cname,                \
  65                 .parent_name    = pname,                \
  66                 .flags          = f,                    \
  67                 .fixed_rate     = frate,                \
  68         }
  69
  70 /*
  71  * struct samsung_fixed_factor_clock: information about fixed-factor clock
  72  * @id: platform specific id of the clock.
  73  * @name: name of this fixed-factor clock.
  74  * @parent_name: parent clock name.
  75  * @mult: fixed multiplication factor.
  76  * @div: fixed division factor.
  77  * @flags: optional fixed-factor clock flags.
  78  */
  79 struct samsung_fixed_factor_clock {
  80         unsigned int            id;
  81         char                    *name;
  82         const char              *parent_name;
  83         unsigned long           mult;
  84         unsigned long           div;
  85         unsigned long           flags;
  86 };
  87
  88 #define FFACTOR(_id, cname, pname, m, d, f)             \
  89         {                                               \
  90                 .id             = _id,                  \
  91                 .name           = cname,                \
  92                 .parent_name    = pname,                \
  93                 .mult           = m,                    \
  94                 .div            = d,                    \
  95                 .flags          = f,                    \
  96         }
  97
  98 /**
  99  * struct samsung_mux_clock: information about mux clock
 100  * @id: platform specific id of the clock.
 101  * @dev_name: name of the device to which this clock belongs.
 102  * @name: name of this mux clock.
 103  * @parent_names: array of pointer to parent clock names.
 104  * @num_parents: number of parents listed in @parent_names.
 105  * @flags: optional flags for basic clock.
 106  * @offset: offset of the register for configuring the mux.
 107  * @shift: starting bit location of the mux control bit-field in @reg.
 108  * @width: width of the mux control bit-field in @reg.
 109  * @mux_flags: flags for mux-type clock.
 110  * @alias: optional clock alias name to be assigned to this clock.
 111  */
 112 struct samsung_mux_clock {
 113         unsigned int            id;
 114         const char              *dev_name;
 115         const char              *name;
 116         const char              **parent_names;
 117         u8                      num_parents;
 118         unsigned long           flags;
 119         unsigned long           offset;
 120         u8                      shift;
 121         u8                      width;
 122         u8                      mux_flags;
 123         const char              *alias;
 124 };
 125
 126 #define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a)     \
 127         {                                                       \
 128                 .id             = _id,                          \
 129                 .dev_name       = dname,                        \
 130                 .name           = cname,                        \
 131                 .parent_names   = pnames,                       \
 132                 .num_parents    = ARRAY_SIZE(pnames),           \
 133                 .flags          = (f) | CLK_SET_RATE_NO_REPARENT, \
 134                 .offset         = o,                            \
 135                 .shift          = s,                            \
 136                 .width          = w,                            \
 137                 .mux_flags      = mf,                           \
 138                 .alias          = a,                            \
 139         }
 140
 141 #define MUX(_id, cname, pnames, o, s, w)                        \
 142         __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
 143
 144 #define MUX_A(_id, cname, pnames, o, s, w, a)                   \
 145         __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
 146
 147 #define MUX_F(_id, cname, pnames, o, s, w, f, mf)               \
 148         __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
 149
 150 #define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a)           \
 151         __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
 152
 153 /**
 154  * @id: platform specific id of the clock.
 155  * struct samsung_div_clock: information about div clock
 156  * @dev_name: name of the device to which this clock belongs.
 157  * @name: name of this div clock.
 158  * @parent_name: name of the parent clock.
 159  * @flags: optional flags for basic clock.
 160  * @offset: offset of the register for configuring the div.
 161  * @shift: starting bit location of the div control bit-field in @reg.
 162  * @div_flags: flags for div-type clock.
 163  * @alias: optional clock alias name to be assigned to this clock.
 164  */
 165 struct samsung_div_clock {
 166         unsigned int            id;
 167         const char              *dev_name;
 168         const char              *name;
 169         const char              *parent_name;
 170         unsigned long           flags;
 171         unsigned long           offset;
 172         u8                      shift;
 173         u8                      width;
 174         u8                      div_flags;
 175         const char              *alias;
 176         struct clk_div_table    *table;
 177 };
 178
 179 #define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t)   \
 180         {                                                       \
 181                 .id             = _id,                          \
 182                 .dev_name       = dname,                        \
 183                 .name           = cname,                        \
 184                 .parent_name    = pname,                        \
 185                 .flags          = f,                            \
 186                 .offset         = o,                            \
 187                 .shift          = s,                            \
 188                 .width          = w,                            \
 189                 .div_flags      = df,                           \
 190                 .alias          = a,                            \
 191                 .table          = t,                            \
 192         }
 193
 194 #define DIV(_id, cname, pname, o, s, w)                         \
 195         __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
 196
 197 #define DIV_A(_id, cname, pname, o, s, w, a)                    \
 198         __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
 199
 200 #define DIV_F(_id, cname, pname, o, s, w, f, df)                \
 201         __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
 202
 203 #define DIV_T(_id, cname, pname, o, s, w, t)                    \
 204         __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
 205
 206 /**
 207  * struct samsung_gate_clock: information about gate clock
 208  * @id: platform specific id of the clock.
 209  * @dev_name: name of the device to which this clock belongs.
 210  * @name: name of this gate clock.
 211  * @parent_name: name of the parent clock.
 212  * @flags: optional flags for basic clock.
 213  * @offset: offset of the register for configuring the gate.
 214  * @bit_idx: bit index of the gate control bit-field in @reg.
 215  * @gate_flags: flags for gate-type clock.
 216  * @alias: optional clock alias name to be assigned to this clock.
 217  */
 218 struct samsung_gate_clock {
 219         unsigned int            id;
 220         const char              *dev_name;
 221         const char              *name;
 222         const char              *parent_name;
 223         unsigned long           flags;
 224         unsigned long           offset;
 225         u8                      bit_idx;
 226         u8                      gate_flags;
 227         const char              *alias;
 228 };
 229
 230 #define __GATE(_id, dname, cname, pname, o, b, f, gf, a)        \
 231         {                                                       \
 232                 .id             = _id,                          \
 233                 .dev_name       = dname,                        \
 234                 .name           = cname,                        \
 235                 .parent_name    = pname,                        \
 236                 .flags          = f,                            \
 237                 .offset         = o,                            \
 238                 .bit_idx        = b,                            \
 239                 .gate_flags     = gf,                           \
 240                 .alias          = a,                            \
 241         }
 242
 243 #define GATE(_id, cname, pname, o, b, f, gf)                    \
 244         __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
 245
 246 #define GATE_A(_id, cname, pname, o, b, f, gf, a)               \
 247         __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
 248
 249 #define GATE_D(_id, dname, cname, pname, o, b, f, gf)           \
 250         __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
 251
 252 #define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a)       \
 253         __GATE(_id, dname, cname, pname, o, b, f, gf, a)
 254
 255 #define PNAME(x) static const char *x[] __initdata
 256
 257 /**
 258  * struct samsung_clk_reg_dump: register dump of clock controller registers.
 259  * @offset: clock register offset from the controller base address.
 260  * @value: the value to be register at offset.
 261  */
 262 struct samsung_clk_reg_dump {
 263         u32     offset;
 264         u32     value;
 265 };
 266
 267 /**
 268  * struct samsung_pll_clock: information about pll clock
 269  * @id: platform specific id of the clock.
 270  * @dev_name: name of the device to which this clock belongs.
 271  * @name: name of this pll clock.
 272  * @parent_name: name of the parent clock.
 273  * @flags: optional flags for basic clock.
 274  * @con_offset: offset of the register for configuring the PLL.
 275  * @lock_offset: offset of the register for locking the PLL.
 276  * @type: Type of PLL to be registered.
 277  * @alias: optional clock alias name to be assigned to this clock.
 278  */
 279 struct samsung_pll_clock {
 280         unsigned int            id;
 281         const char              *dev_name;
 282         const char              *name;
 283         const char              *parent_name;
 284         unsigned long           flags;
 285         int                     con_offset;
 286         int                     lock_offset;
 287         enum samsung_pll_type   type;
 288         const struct samsung_pll_rate_table *rate_table;
 289         const char              *alias;
 290 };
 291
 292 #define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con,    \
 293                 _rtable, _alias)                                        \
 294         {                                                               \
 295                 .id             = _id,                                  \
 296                 .type           = _typ,                                 \
 297                 .dev_name       = _dname,                               \
 298                 .name           = _name,                                \
 299                 .parent_name    = _pname,                               \
 300                 .flags          = CLK_GET_RATE_NOCACHE,                 \
 301                 .con_offset     = _con,                                 \
 302                 .lock_offset    = _lock,                                \
 303                 .rate_table     = _rtable,                              \
 304                 .alias          = _alias,                               \
 305         }
 306
 307 #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable)     \
 308         __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,     \
 309                 _lock, _con, _rtable, _name)
 310
 311 #define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
 312         __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,     \
 313                 _lock, _con, _rtable, _alias)
 314
 315 extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
 316                 unsigned long nr_clks, unsigned long *rdump,
 317                 unsigned long nr_rdump, unsigned long *soc_rdump,
 318                 unsigned long nr_soc_rdump);
 319 extern void __init samsung_clk_of_register_fixed_ext(
 320                 struct samsung_fixed_rate_clock *fixed_rate_clk,
 321                 unsigned int nr_fixed_rate_clk,
 322                 struct of_device_id *clk_matches);
 323
 324 extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
 325
 326 extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
 327                 unsigned int nr_clk);
 328 extern void __init samsung_clk_register_fixed_rate(
 329                 struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
 330 extern void __init samsung_clk_register_fixed_factor(
 331                 struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
 332 extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
 333                 unsigned int nr_clk);
 334 extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
 335                 unsigned int nr_clk);
 336 extern void __init samsung_clk_register_gate(
 337                 struct samsung_gate_clock *clk_list, unsigned int nr_clk);
 338 extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
 339                 unsigned int nr_clk, void __iomem *base);
 340
 341 extern unsigned long _get_rate(const char *clk_name);
 342
 343 #endif /* __SAMSUNG_CLK_H */