drivers/clk/sunxi/clk-sunxi.c

   1 /*
   2  * Copyright 2013 Emilio López
   3  *
   4  * Emilio López <emilio@elopez.com.ar>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clkdev.h>
  19 #include <linux/clk/sunxi.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22
  23 #include "clk-factors.h"
  24
  25 static DEFINE_SPINLOCK(clk_lock);
  26
  27 /**
  28  * sunxi_osc_clk_setup() - Setup function for gatable oscillator
  29  */
  30
  31 #define SUNXI_OSC24M_GATE       0
  32
  33 static void __init sunxi_osc_clk_setup(struct device_node *node)
  34 {
  35         struct clk *clk;
  36         const char *clk_name = node->name;
  37         const char *parent;
  38         void *reg;
  39
  40         reg = of_iomap(node, 0);
  41
  42         parent = of_clk_get_parent_name(node, 0);
  43
  44         clk = clk_register_gate(NULL, clk_name, parent, 0, reg,
  45                                 SUNXI_OSC24M_GATE, 0, &clk_lock);
  46
  47         if (clk) {
  48                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
  49                 clk_register_clkdev(clk, clk_name, NULL);
  50         }
  51 }
  52
  53
  54
  55 /**
  56  * sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1
  57  * PLL1 rate is calculated as follows
  58  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
  59  * parent_rate is always 24Mhz
  60  */
  61
  62 static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,
  63                                    u8 *n, u8 *k, u8 *m, u8 *p)
  64 {
  65         u8 div;
  66
  67         /* Normalize value to a 6M multiple */
  68         div = *freq / 6000000;
  69         *freq = 6000000 * div;
  70
  71         /* we were called to round the frequency, we can now return */
  72         if (n == NULL)
  73                 return;
  74
  75         /* m is always zero for pll1 */
  76         *m = 0;
  77
  78         /* k is 1 only on these cases */
  79         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
  80                 *k = 1;
  81         else
  82                 *k = 0;
  83
  84         /* p will be 3 for divs under 10 */
  85         if (div < 10)
  86                 *p = 3;
  87
  88         /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
  89         else if (div < 20 || (div < 32 && (div & 1)))
  90                 *p = 2;
  91
  92         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
  93          * of divs between 40-62 */
  94         else if (div < 40 || (div < 64 && (div & 2)))
  95                 *p = 1;
  96
  97         /* any other entries have p = 0 */
  98         else
  99                 *p = 0;
 100
 101         /* calculate a suitable n based on k and p */
 102         div <<= *p;
 103         div /= (*k + 1);
 104         *n = div / 4;
 105 }
 106
 107
 108
 109 /**
 110  * sunxi_get_apb1_factors() - calculates m, p factors for APB1
 111  * APB1 rate is calculated as follows
 112  * rate = (parent_rate >> p) / (m + 1);
 113  */
 114
 115 static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate,
 116                                    u8 *n, u8 *k, u8 *m, u8 *p)
 117 {
 118         u8 calcm, calcp;
 119
 120         if (parent_rate < *freq)
 121                 *freq = parent_rate;
 122
 123         parent_rate = (parent_rate + (*freq - 1)) / *freq;
 124
 125         /* Invalid rate! */
 126         if (parent_rate > 32)
 127                 return;
 128
 129         if (parent_rate <= 4)
 130                 calcp = 0;
 131         else if (parent_rate <= 8)
 132                 calcp = 1;
 133         else if (parent_rate <= 16)
 134                 calcp = 2;
 135         else
 136                 calcp = 3;
 137
 138         calcm = (parent_rate >> calcp) - 1;
 139
 140         *freq = (parent_rate >> calcp) / (calcm + 1);
 141
 142         /* we were called to round the frequency, we can now return */
 143         if (n == NULL)
 144                 return;
 145
 146         *m = calcm;
 147         *p = calcp;
 148 }
 149
 150
 151
 152 /**
 153  * sunxi_factors_clk_setup() - Setup function for factor clocks
 154  */
 155
 156 struct factors_data {
 157         struct clk_factors_config *table;
 158         void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
 159 };
 160
 161 static struct clk_factors_config pll1_config = {
 162         .nshift = 8,
 163         .nwidth = 5,
 164         .kshift = 4,
 165         .kwidth = 2,
 166         .mshift = 0,
 167         .mwidth = 2,
 168         .pshift = 16,
 169         .pwidth = 2,
 170 };
 171
 172 static struct clk_factors_config apb1_config = {
 173         .mshift = 0,
 174         .mwidth = 5,
 175         .pshift = 16,
 176         .pwidth = 2,
 177 };
 178
 179 static const __initconst struct factors_data pll1_data = {
 180         .table = &pll1_config,
 181         .getter = sunxi_get_pll1_factors,
 182 };
 183
 184 static const __initconst struct factors_data apb1_data = {
 185         .table = &apb1_config,
 186         .getter = sunxi_get_apb1_factors,
 187 };
 188
 189 static void __init sunxi_factors_clk_setup(struct device_node *node,
 190                                            struct factors_data *data)
 191 {
 192         struct clk *clk;
 193         const char *clk_name = node->name;
 194         const char *parent;
 195         void *reg;
 196
 197         reg = of_iomap(node, 0);
 198
 199         parent = of_clk_get_parent_name(node, 0);
 200
 201         clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
 202                                    data->table, data->getter, &clk_lock);
 203
 204         if (clk) {
 205                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 206                 clk_register_clkdev(clk, clk_name, NULL);
 207         }
 208 }
 209
 210
 211
 212 /**
 213  * sunxi_mux_clk_setup() - Setup function for muxes
 214  */
 215
 216 #define SUNXI_MUX_GATE_WIDTH    2
 217
 218 struct mux_data {
 219         u8 shift;
 220 };
 221
 222 static const __initconst struct mux_data cpu_data = {
 223         .shift = 16,
 224 };
 225
 226 static const __initconst struct mux_data apb1_mux_data = {
 227         .shift = 24,
 228 };
 229
 230 static void __init sunxi_mux_clk_setup(struct device_node *node,
 231                                        struct mux_data *data)
 232 {
 233         struct clk *clk;
 234         const char *clk_name = node->name;
 235         const char *parents[5];
 236         void *reg;
 237         int i = 0;
 238
 239         reg = of_iomap(node, 0);
 240
 241         while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 242                 i++;
 243
 244         clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg,
 245                                data->shift, SUNXI_MUX_GATE_WIDTH,
 246                                0, &clk_lock);
 247
 248         if (clk) {
 249                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 250                 clk_register_clkdev(clk, clk_name, NULL);
 251         }
 252 }
 253
 254
 255
 256 /**
 257  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
 258  */
 259
 260 #define SUNXI_DIVISOR_WIDTH     2
 261
 262 struct div_data {
 263         u8 shift;
 264         u8 pow;
 265 };
 266
 267 static const __initconst struct div_data axi_data = {
 268         .shift = 0,
 269         .pow = 0,
 270 };
 271
 272 static const __initconst struct div_data ahb_data = {
 273         .shift = 4,
 274         .pow = 1,
 275 };
 276
 277 static const __initconst struct div_data apb0_data = {
 278         .shift = 8,
 279         .pow = 1,
 280 };
 281
 282 static void __init sunxi_divider_clk_setup(struct device_node *node,
 283                                            struct div_data *data)
 284 {
 285         struct clk *clk;
 286         const char *clk_name = node->name;
 287         const char *clk_parent;
 288         void *reg;
 289
 290         reg = of_iomap(node, 0);
 291
 292         clk_parent = of_clk_get_parent_name(node, 0);
 293
 294         clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
 295                                    reg, data->shift, SUNXI_DIVISOR_WIDTH,
 296                                    data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
 297                                    &clk_lock);
 298         if (clk) {
 299                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 300                 clk_register_clkdev(clk, clk_name, NULL);
 301         }
 302 }
 303
 304
 305
 306 /**
 307  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
 308  */
 309
 310 #define SUNXI_GATES_MAX_SIZE    64
 311
 312 struct gates_data {
 313         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
 314 };
 315
 316 static const __initconst struct gates_data axi_gates_data = {
 317         .mask = {1},
 318 };
 319
 320 static const __initconst struct gates_data ahb_gates_data = {
 321         .mask = {0x7F77FFF, 0x14FB3F},
 322 };
 323
 324 static const __initconst struct gates_data apb0_gates_data = {
 325         .mask = {0x4EF},
 326 };
 327
 328 static const __initconst struct gates_data apb1_gates_data = {
 329         .mask = {0xFF00F7},
 330 };
 331
 332 static void __init sunxi_gates_clk_setup(struct device_node *node,
 333                                          struct gates_data *data)
 334 {
 335         struct clk_onecell_data *clk_data;
 336         const char *clk_parent;
 337         const char *clk_name;
 338         void *reg;
 339         int qty;
 340         int i = 0;
 341         int j = 0;
 342         int ignore;
 343
 344         reg = of_iomap(node, 0);
 345
 346         clk_parent = of_clk_get_parent_name(node, 0);
 347
 348         /* Worst-case size approximation and memory allocation */
 349         qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
 350         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
 351         if (!clk_data)
 352                 return;
 353         clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
 354         if (!clk_data->clks) {
 355                 kfree(clk_data);
 356                 return;
 357         }
 358
 359         for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
 360                 of_property_read_string_index(node, "clock-output-names",
 361                                               j, &clk_name);
 362
 363                 /* No driver claims this clock, but it should remain gated */
 364                 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
 365
 366                 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
 367                                                       clk_parent, ignore,
 368                                                       reg + 4 * (i/32), i % 32,
 369                                                       0, &clk_lock);
 370                 WARN_ON(IS_ERR(clk_data->clks[i]));
 371
 372                 j++;
 373         }
 374
 375         /* Adjust to the real max */
 376         clk_data->clk_num = i;
 377
 378         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 379 }
 380
 381 /* Matches for of_clk_init */
 382 static const __initconst struct of_device_id clk_match[] = {
 383         {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
 384         {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
 385         {}
 386 };
 387
 388 /* Matches for factors clocks */
 389 static const __initconst struct of_device_id clk_factors_match[] = {
 390         {.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,},
 391         {.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,},
 392         {}
 393 };
 394
 395 /* Matches for divider clocks */
 396 static const __initconst struct of_device_id clk_div_match[] = {
 397         {.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,},
 398         {.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,},
 399         {.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,},
 400         {}
 401 };
 402
 403 /* Matches for mux clocks */
 404 static const __initconst struct of_device_id clk_mux_match[] = {
 405         {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_data,},
 406         {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
 407         {}
 408 };
 409
 410 /* Matches for gate clocks */
 411 static const __initconst struct of_device_id clk_gates_match[] = {
 412         {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
 413         {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
 414         {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
 415         {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
 416         {}
 417 };
 418
 419 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
 420                                               void *function)
 421 {
 422         struct device_node *np;
 423         const struct div_data *data;
 424         const struct of_device_id *match;
 425         void (*setup_function)(struct device_node *, const void *) = function;
 426
 427         for_each_matching_node(np, clk_match) {
 428                 match = of_match_node(clk_match, np);
 429                 data = match->data;
 430                 setup_function(np, data);
 431         }
 432 }
 433
 434 void __init sunxi_init_clocks(void)
 435 {
 436         /* Register all the simple sunxi clocks on DT */
 437         of_clk_init(clk_match);
 438
 439         /* Register factor clocks */
 440         of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
 441
 442         /* Register divider clocks */
 443         of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
 444
 445         /* Register mux clocks */
 446         of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
 447
 448         /* Register gate clocks */
 449         of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
 450 }