drivers/clk/sunxi/clk-sunxi.c

   1 /*
   2  * Copyright 2013 Emilio López
   3  *
   4  * Emilio López <emilio@elopez.com.ar>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clkdev.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21
  22 #include "clk-factors.h"
  23
  24 static DEFINE_SPINLOCK(clk_lock);
  25
  26 /* Maximum number of parents our clocks have */
  27 #define SUNXI_MAX_PARENTS       5
  28
  29 /**
  30  * sun4i_osc_clk_setup() - Setup function for gatable oscillator
  31  */
  32
  33 #define SUNXI_OSC24M_GATE       0
  34
  35 static void __init sun4i_osc_clk_setup(struct device_node *node)
  36 {
  37         struct clk *clk;
  38         struct clk_fixed_rate *fixed;
  39         struct clk_gate *gate;
  40         const char *clk_name = node->name;
  41         u32 rate;
  42
  43         if (of_property_read_u32(node, "clock-frequency", &rate))
  44                 return;
  45
  46         /* allocate fixed-rate and gate clock structs */
  47         fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
  48         if (!fixed)
  49                 return;
  50         gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
  51         if (!gate)
  52                 goto err_free_fixed;
  53
  54         /* set up gate and fixed rate properties */
  55         gate->reg = of_iomap(node, 0);
  56         gate->bit_idx = SUNXI_OSC24M_GATE;
  57         gate->lock = &clk_lock;
  58         fixed->fixed_rate = rate;
  59
  60         clk = clk_register_composite(NULL, clk_name,
  61                         NULL, 0,
  62                         NULL, NULL,
  63                         &fixed->hw, &clk_fixed_rate_ops,
  64                         &gate->hw, &clk_gate_ops,
  65                         CLK_IS_ROOT);
  66
  67         if (IS_ERR(clk))
  68                 goto err_free_gate;
  69
  70         of_clk_add_provider(node, of_clk_src_simple_get, clk);
  71         clk_register_clkdev(clk, clk_name, NULL);
  72
  73         return;
  74
  75 err_free_gate:
  76         kfree(gate);
  77 err_free_fixed:
  78         kfree(fixed);
  79 }
  80 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
  81
  82
  83
  84 /**
  85  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
  86  * PLL1 rate is calculated as follows
  87  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
  88  * parent_rate is always 24Mhz
  89  */
  90
  91 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
  92                                    u8 *n, u8 *k, u8 *m, u8 *p)
  93 {
  94         u8 div;
  95
  96         /* Normalize value to a 6M multiple */
  97         div = *freq / 6000000;
  98         *freq = 6000000 * div;
  99
 100         /* we were called to round the frequency, we can now return */
 101         if (n == NULL)
 102                 return;
 103
 104         /* m is always zero for pll1 */
 105         *m = 0;
 106
 107         /* k is 1 only on these cases */
 108         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
 109                 *k = 1;
 110         else
 111                 *k = 0;
 112
 113         /* p will be 3 for divs under 10 */
 114         if (div < 10)
 115                 *p = 3;
 116
 117         /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
 118         else if (div < 20 || (div < 32 && (div & 1)))
 119                 *p = 2;
 120
 121         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
 122          * of divs between 40-62 */
 123         else if (div < 40 || (div < 64 && (div & 2)))
 124                 *p = 1;
 125
 126         /* any other entries have p = 0 */
 127         else
 128                 *p = 0;
 129
 130         /* calculate a suitable n based on k and p */
 131         div <<= *p;
 132         div /= (*k + 1);
 133         *n = div / 4;
 134 }
 135
 136 /**
 137  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
 138  * PLL1 rate is calculated as follows
 139  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
 140  * parent_rate should always be 24MHz
 141  */
 142 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
 143                                        u8 *n, u8 *k, u8 *m, u8 *p)
 144 {
 145         /*
 146          * We can operate only on MHz, this will make our life easier
 147          * later.
 148          */
 149         u32 freq_mhz = *freq / 1000000;
 150         u32 parent_freq_mhz = parent_rate / 1000000;
 151
 152         /*
 153          * Round down the frequency to the closest multiple of either
 154          * 6 or 16
 155          */
 156         u32 round_freq_6 = round_down(freq_mhz, 6);
 157         u32 round_freq_16 = round_down(freq_mhz, 16);
 158
 159         if (round_freq_6 > round_freq_16)
 160                 freq_mhz = round_freq_6;
 161         else
 162                 freq_mhz = round_freq_16;
 163
 164         *freq = freq_mhz * 1000000;
 165
 166         /*
 167          * If the factors pointer are null, we were just called to
 168          * round down the frequency.
 169          * Exit.
 170          */
 171         if (n == NULL)
 172                 return;
 173
 174         /* If the frequency is a multiple of 32 MHz, k is always 3 */
 175         if (!(freq_mhz % 32))
 176                 *k = 3;
 177         /* If the frequency is a multiple of 9 MHz, k is always 2 */
 178         else if (!(freq_mhz % 9))
 179                 *k = 2;
 180         /* If the frequency is a multiple of 8 MHz, k is always 1 */
 181         else if (!(freq_mhz % 8))
 182                 *k = 1;
 183         /* Otherwise, we don't use the k factor */
 184         else
 185                 *k = 0;
 186
 187         /*
 188          * If the frequency is a multiple of 2 but not a multiple of
 189          * 3, m is 3. This is the first time we use 6 here, yet we
 190          * will use it on several other places.
 191          * We use this number because it's the lowest frequency we can
 192          * generate (with n = 0, k = 0, m = 3), so every other frequency
 193          * somehow relates to this frequency.
 194          */
 195         if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
 196                 *m = 2;
 197         /*
 198          * If the frequency is a multiple of 6MHz, but the factor is
 199          * odd, m will be 3
 200          */
 201         else if ((freq_mhz / 6) & 1)
 202                 *m = 3;
 203         /* Otherwise, we end up with m = 1 */
 204         else
 205                 *m = 1;
 206
 207         /* Calculate n thanks to the above factors we already got */
 208         *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
 209
 210         /*
 211          * If n end up being outbound, and that we can still decrease
 212          * m, do it.
 213          */
 214         if ((*n + 1) > 31 && (*m + 1) > 1) {
 215                 *n = (*n + 1) / 2 - 1;
 216                 *m = (*m + 1) / 2 - 1;
 217         }
 218 }
 219
 220 /**
 221  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
 222  * APB1 rate is calculated as follows
 223  * rate = (parent_rate >> p) / (m + 1);
 224  */
 225
 226 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
 227                                    u8 *n, u8 *k, u8 *m, u8 *p)
 228 {
 229         u8 calcm, calcp;
 230
 231         if (parent_rate < *freq)
 232                 *freq = parent_rate;
 233
 234         parent_rate = (parent_rate + (*freq - 1)) / *freq;
 235
 236         /* Invalid rate! */
 237         if (parent_rate > 32)
 238                 return;
 239
 240         if (parent_rate <= 4)
 241                 calcp = 0;
 242         else if (parent_rate <= 8)
 243                 calcp = 1;
 244         else if (parent_rate <= 16)
 245                 calcp = 2;
 246         else
 247                 calcp = 3;
 248
 249         calcm = (parent_rate >> calcp) - 1;
 250
 251         *freq = (parent_rate >> calcp) / (calcm + 1);
 252
 253         /* we were called to round the frequency, we can now return */
 254         if (n == NULL)
 255                 return;
 256
 257         *m = calcm;
 258         *p = calcp;
 259 }
 260
 261
 262
 263 /**
 264  * sunxi_factors_clk_setup() - Setup function for factor clocks
 265  */
 266
 267 #define SUNXI_FACTORS_MUX_MASK 0x3
 268
 269 struct factors_data {
 270         int enable;
 271         int mux;
 272         struct clk_factors_config *table;
 273         void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
 274 };
 275
 276 static struct clk_factors_config sun4i_pll1_config = {
 277         .nshift = 8,
 278         .nwidth = 5,
 279         .kshift = 4,
 280         .kwidth = 2,
 281         .mshift = 0,
 282         .mwidth = 2,
 283         .pshift = 16,
 284         .pwidth = 2,
 285 };
 286
 287 static struct clk_factors_config sun6i_a31_pll1_config = {
 288         .nshift = 8,
 289         .nwidth = 5,
 290         .kshift = 4,
 291         .kwidth = 2,
 292         .mshift = 0,
 293         .mwidth = 2,
 294 };
 295
 296 static struct clk_factors_config sun4i_apb1_config = {
 297         .mshift = 0,
 298         .mwidth = 5,
 299         .pshift = 16,
 300         .pwidth = 2,
 301 };
 302
 303 static const struct factors_data sun4i_pll1_data __initconst = {
 304         .table = &sun4i_pll1_config,
 305         .getter = sun4i_get_pll1_factors,
 306 };
 307
 308 static const struct factors_data sun6i_a31_pll1_data __initconst = {
 309         .table = &sun6i_a31_pll1_config,
 310         .getter = sun6i_a31_get_pll1_factors,
 311 };
 312
 313 static const struct factors_data sun4i_apb1_data __initconst = {
 314         .table = &sun4i_apb1_config,
 315         .getter = sun4i_get_apb1_factors,
 316 };
 317
 318 static void __init sunxi_factors_clk_setup(struct device_node *node,
 319                                            struct factors_data *data)
 320 {
 321         struct clk *clk;
 322         struct clk_factors *factors;
 323         struct clk_gate *gate = NULL;
 324         struct clk_mux *mux = NULL;
 325         struct clk_hw *gate_hw = NULL;
 326         struct clk_hw *mux_hw = NULL;
 327         const char *clk_name = node->name;
 328         const char *parents[SUNXI_MAX_PARENTS];
 329         void *reg;
 330         int i = 0;
 331
 332         reg = of_iomap(node, 0);
 333
 334         /* if we have a mux, we will have >1 parents */
 335         while (i < SUNXI_MAX_PARENTS &&
 336                (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 337                 i++;
 338
 339         factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
 340         if (!factors)
 341                 return;
 342
 343         /* Add a gate if this factor clock can be gated */
 344         if (data->enable) {
 345                 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
 346                 if (!gate) {
 347                         kfree(factors);
 348                         return;
 349                 }
 350
 351                 /* set up gate properties */
 352                 gate->reg = reg;
 353                 gate->bit_idx = data->enable;
 354                 gate->lock = &clk_lock;
 355                 gate_hw = &gate->hw;
 356         }
 357
 358         /* Add a mux if this factor clock can be muxed */
 359         if (data->mux) {
 360                 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
 361                 if (!mux) {
 362                         kfree(factors);
 363                         kfree(gate);
 364                         return;
 365                 }
 366
 367                 /* set up gate properties */
 368                 mux->reg = reg;
 369                 mux->shift = data->mux;
 370                 mux->mask = SUNXI_FACTORS_MUX_MASK;
 371                 mux->lock = &clk_lock;
 372                 mux_hw = &mux->hw;
 373         }
 374
 375         /* set up factors properties */
 376         factors->reg = reg;
 377         factors->config = data->table;
 378         factors->get_factors = data->getter;
 379         factors->lock = &clk_lock;
 380
 381         clk = clk_register_composite(NULL, clk_name,
 382                         parents, i,
 383                         mux_hw, &clk_mux_ops,
 384                         &factors->hw, &clk_factors_ops,
 385                         gate_hw, &clk_gate_ops,
 386                         i ? 0 : CLK_IS_ROOT);
 387
 388         if (!IS_ERR(clk)) {
 389                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 390                 clk_register_clkdev(clk, clk_name, NULL);
 391         }
 392 }
 393
 394
 395
 396 /**
 397  * sunxi_mux_clk_setup() - Setup function for muxes
 398  */
 399
 400 #define SUNXI_MUX_GATE_WIDTH    2
 401
 402 struct mux_data {
 403         u8 shift;
 404 };
 405
 406 static const struct mux_data sun4i_cpu_mux_data __initconst = {
 407         .shift = 16,
 408 };
 409
 410 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
 411         .shift = 12,
 412 };
 413
 414 static const struct mux_data sun4i_apb1_mux_data __initconst = {
 415         .shift = 24,
 416 };
 417
 418 static void __init sunxi_mux_clk_setup(struct device_node *node,
 419                                        struct mux_data *data)
 420 {
 421         struct clk *clk;
 422         const char *clk_name = node->name;
 423         const char *parents[5];
 424         void *reg;
 425         int i = 0;
 426
 427         reg = of_iomap(node, 0);
 428
 429         while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 430                 i++;
 431
 432         clk = clk_register_mux(NULL, clk_name, parents, i,
 433                                CLK_SET_RATE_NO_REPARENT, reg,
 434                                data->shift, SUNXI_MUX_GATE_WIDTH,
 435                                0, &clk_lock);
 436
 437         if (clk) {
 438                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 439                 clk_register_clkdev(clk, clk_name, NULL);
 440         }
 441 }
 442
 443
 444
 445 /**
 446  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
 447  */
 448
 449 struct div_data {
 450         u8      shift;
 451         u8      pow;
 452         u8      width;
 453 };
 454
 455 static const struct div_data sun4i_axi_data __initconst = {
 456         .shift  = 0,
 457         .pow    = 0,
 458         .width  = 2,
 459 };
 460
 461 static const struct div_data sun4i_ahb_data __initconst = {
 462         .shift  = 4,
 463         .pow    = 1,
 464         .width  = 2,
 465 };
 466
 467 static const struct div_data sun4i_apb0_data __initconst = {
 468         .shift  = 8,
 469         .pow    = 1,
 470         .width  = 2,
 471 };
 472
 473 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
 474         .shift  = 0,
 475         .pow    = 0,
 476         .width  = 4,
 477 };
 478
 479 static void __init sunxi_divider_clk_setup(struct device_node *node,
 480                                            struct div_data *data)
 481 {
 482         struct clk *clk;
 483         const char *clk_name = node->name;
 484         const char *clk_parent;
 485         void *reg;
 486
 487         reg = of_iomap(node, 0);
 488
 489         clk_parent = of_clk_get_parent_name(node, 0);
 490
 491         clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
 492                                    reg, data->shift, data->width,
 493                                    data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
 494                                    &clk_lock);
 495         if (clk) {
 496                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 497                 clk_register_clkdev(clk, clk_name, NULL);
 498         }
 499 }
 500
 501
 502
 503 /**
 504  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
 505  */
 506
 507 #define SUNXI_GATES_MAX_SIZE    64
 508
 509 struct gates_data {
 510         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
 511 };
 512
 513 static const struct gates_data sun4i_axi_gates_data __initconst = {
 514         .mask = {1},
 515 };
 516
 517 static const struct gates_data sun4i_ahb_gates_data __initconst = {
 518         .mask = {0x7F77FFF, 0x14FB3F},
 519 };
 520
 521 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
 522         .mask = {0x147667e7, 0x185915},
 523 };
 524
 525 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
 526         .mask = {0x107067e7, 0x185111},
 527 };
 528
 529 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
 530         .mask = {0xEDFE7F62, 0x794F931},
 531 };
 532
 533 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
 534         .mask = { 0x12f77fff, 0x16ff3f },
 535 };
 536
 537 static const struct gates_data sun4i_apb0_gates_data __initconst = {
 538         .mask = {0x4EF},
 539 };
 540
 541 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
 542         .mask = {0x469},
 543 };
 544
 545 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
 546         .mask = {0x61},
 547 };
 548
 549 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
 550         .mask = { 0x4ff },
 551 };
 552
 553 static const struct gates_data sun4i_apb1_gates_data __initconst = {
 554         .mask = {0xFF00F7},
 555 };
 556
 557 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
 558         .mask = {0xf0007},
 559 };
 560
 561 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
 562         .mask = {0xa0007},
 563 };
 564
 565 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
 566         .mask = {0x3031},
 567 };
 568
 569 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
 570         .mask = {0x3F000F},
 571 };
 572
 573 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
 574         .mask = { 0xff80ff },
 575 };
 576
 577 static void __init sunxi_gates_clk_setup(struct device_node *node,
 578                                          struct gates_data *data)
 579 {
 580         struct clk_onecell_data *clk_data;
 581         const char *clk_parent;
 582         const char *clk_name;
 583         void *reg;
 584         int qty;
 585         int i = 0;
 586         int j = 0;
 587         int ignore;
 588
 589         reg = of_iomap(node, 0);
 590
 591         clk_parent = of_clk_get_parent_name(node, 0);
 592
 593         /* Worst-case size approximation and memory allocation */
 594         qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
 595         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
 596         if (!clk_data)
 597                 return;
 598         clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
 599         if (!clk_data->clks) {
 600                 kfree(clk_data);
 601                 return;
 602         }
 603
 604         for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
 605                 of_property_read_string_index(node, "clock-output-names",
 606                                               j, &clk_name);
 607
 608                 /* No driver claims this clock, but it should remain gated */
 609                 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
 610
 611                 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
 612                                                       clk_parent, ignore,
 613                                                       reg + 4 * (i/32), i % 32,
 614                                                       0, &clk_lock);
 615                 WARN_ON(IS_ERR(clk_data->clks[i]));
 616
 617                 j++;
 618         }
 619
 620         /* Adjust to the real max */
 621         clk_data->clk_num = i;
 622
 623         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 624 }
 625
 626 /* Matches for factors clocks */
 627 static const struct of_device_id clk_factors_match[] __initconst = {
 628         {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
 629         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 630         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 631         {}
 632 };
 633
 634 /* Matches for divider clocks */
 635 static const struct of_device_id clk_div_match[] __initconst = {
 636         {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
 637         {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
 638         {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
 639         {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
 640         {}
 641 };
 642
 643 /* Matches for mux clocks */
 644 static const struct of_device_id clk_mux_match[] __initconst = {
 645         {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
 646         {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
 647         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
 648         {}
 649 };
 650
 651 /* Matches for gate clocks */
 652 static const struct of_device_id clk_gates_match[] __initconst = {
 653         {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
 654         {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
 655         {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
 656         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
 657         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
 658         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
 659         {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
 660         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
 661         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
 662         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
 663         {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
 664         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
 665         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
 666         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
 667         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
 668         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
 669         {}
 670 };
 671
 672 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
 673                                               void *function)
 674 {
 675         struct device_node *np;
 676         const struct div_data *data;
 677         const struct of_device_id *match;
 678         void (*setup_function)(struct device_node *, const void *) = function;
 679
 680         for_each_matching_node(np, clk_match) {
 681                 match = of_match_node(clk_match, np);
 682                 data = match->data;
 683                 setup_function(np, data);
 684         }
 685 }
 686
 687 /**
 688  * System clock protection
 689  *
 690  * By enabling these critical clocks, we prevent their accidental gating
 691  * by the framework
 692  */
 693 static void __init sunxi_clock_protect(void)
 694 {
 695         struct clk *clk;
 696
 697         /* memory bus clock - sun5i+ */
 698         clk = clk_get(NULL, "mbus");
 699         if (!IS_ERR(clk)) {
 700                 clk_prepare_enable(clk);
 701                 clk_put(clk);
 702         }
 703
 704         /* DDR clock - sun4i+ */
 705         clk = clk_get(NULL, "pll5_ddr");
 706         if (!IS_ERR(clk)) {
 707                 clk_prepare_enable(clk);
 708                 clk_put(clk);
 709         }
 710 }
 711
 712 static void __init sunxi_init_clocks(void)
 713 {
 714         /* Register factor clocks */
 715         of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
 716
 717         /* Register divider clocks */
 718         of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
 719
 720         /* Register mux clocks */
 721         of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
 722
 723         /* Register gate clocks */
 724         of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
 725
 726         /* Enable core system clocks */
 727         sunxi_clock_protect();
 728 }
 729 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
 730 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
 731 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
 732 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
 733 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);