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clk: sunxi: make use of of_clk_parent_fill helper function
[deliverable/linux.git] / drivers / clk / sunxi / clk-sunxi.c
1 /*
2 * Copyright 2013 Emilio López
3 *
4 * Emilio López <emilio@elopez.com.ar>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
22 #include <linux/spinlock.h>
23 #include <linux/log2.h>
24
25 #include "clk-factors.h"
26
27 static DEFINE_SPINLOCK(clk_lock);
28
29 /**
30 * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
31 */
32
33 #define SUN6I_AHB1_MAX_PARENTS 4
34 #define SUN6I_AHB1_MUX_PARENT_PLL6 3
35 #define SUN6I_AHB1_MUX_SHIFT 12
36 /* un-shifted mask is what mux_clk expects */
37 #define SUN6I_AHB1_MUX_MASK 0x3
38 #define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
39 SUN6I_AHB1_MUX_MASK)
40
41 #define SUN6I_AHB1_DIV_SHIFT 4
42 #define SUN6I_AHB1_DIV_MASK (0x3 << SUN6I_AHB1_DIV_SHIFT)
43 #define SUN6I_AHB1_DIV_GET(reg) ((reg & SUN6I_AHB1_DIV_MASK) >> \
44 SUN6I_AHB1_DIV_SHIFT)
45 #define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
46 (div << SUN6I_AHB1_DIV_SHIFT))
47 #define SUN6I_AHB1_PLL6_DIV_SHIFT 6
48 #define SUN6I_AHB1_PLL6_DIV_MASK (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
49 #define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
50 SUN6I_AHB1_PLL6_DIV_SHIFT)
51 #define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
52 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
53
54 struct sun6i_ahb1_clk {
55 struct clk_hw hw;
56 void __iomem *reg;
57 };
58
59 #define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
60
61 static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
63 {
64 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
65 unsigned long rate;
66 u32 reg;
67
68 /* Fetch the register value */
69 reg = readl(ahb1->reg);
70
71 /* apply pre-divider first if parent is pll6 */
72 if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
73 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
74
75 /* clk divider */
76 rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
77
78 return rate;
79 }
80
81 static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
82 u8 parent, unsigned long parent_rate)
83 {
84 u8 div, calcp, calcm = 1;
85
86 /*
87 * clock can only divide, so we will never be able to achieve
88 * frequencies higher than the parent frequency
89 */
90 if (parent_rate && rate > parent_rate)
91 rate = parent_rate;
92
93 div = DIV_ROUND_UP(parent_rate, rate);
94
95 /* calculate pre-divider if parent is pll6 */
96 if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
97 if (div < 4)
98 calcp = 0;
99 else if (div / 2 < 4)
100 calcp = 1;
101 else if (div / 4 < 4)
102 calcp = 2;
103 else
104 calcp = 3;
105
106 calcm = DIV_ROUND_UP(div, 1 << calcp);
107 } else {
108 calcp = __roundup_pow_of_two(div);
109 calcp = calcp > 3 ? 3 : calcp;
110 }
111
112 /* we were asked to pass back divider values */
113 if (divp) {
114 *divp = calcp;
115 *pre_divp = calcm - 1;
116 }
117
118 return (parent_rate / calcm) >> calcp;
119 }
120
121 static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw,
122 struct clk_rate_request *req)
123 {
124 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
125 int i, num_parents;
126 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
127
128 /* find the parent that can help provide the fastest rate <= rate */
129 num_parents = __clk_get_num_parents(clk);
130 for (i = 0; i < num_parents; i++) {
131 parent = clk_get_parent_by_index(clk, i);
132 if (!parent)
133 continue;
134 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
135 parent_rate = __clk_round_rate(parent, req->rate);
136 else
137 parent_rate = __clk_get_rate(parent);
138
139 child_rate = sun6i_ahb1_clk_round(req->rate, NULL, NULL, i,
140 parent_rate);
141
142 if (child_rate <= req->rate && child_rate > best_child_rate) {
143 best_parent = parent;
144 best = parent_rate;
145 best_child_rate = child_rate;
146 }
147 }
148
149 if (!best_parent)
150 return -EINVAL;
151
152 req->best_parent_hw = __clk_get_hw(best_parent);
153 req->best_parent_rate = best;
154 req->rate = best_child_rate;
155
156 return 0;
157 }
158
159 static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
160 unsigned long parent_rate)
161 {
162 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
163 unsigned long flags;
164 u8 div, pre_div, parent;
165 u32 reg;
166
167 spin_lock_irqsave(&clk_lock, flags);
168
169 reg = readl(ahb1->reg);
170
171 /* need to know which parent is used to apply pre-divider */
172 parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
173 sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
174
175 reg = SUN6I_AHB1_DIV_SET(reg, div);
176 reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
177 writel(reg, ahb1->reg);
178
179 spin_unlock_irqrestore(&clk_lock, flags);
180
181 return 0;
182 }
183
184 static const struct clk_ops sun6i_ahb1_clk_ops = {
185 .determine_rate = sun6i_ahb1_clk_determine_rate,
186 .recalc_rate = sun6i_ahb1_clk_recalc_rate,
187 .set_rate = sun6i_ahb1_clk_set_rate,
188 };
189
190 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
191 {
192 struct clk *clk;
193 struct sun6i_ahb1_clk *ahb1;
194 struct clk_mux *mux;
195 const char *clk_name = node->name;
196 const char *parents[SUN6I_AHB1_MAX_PARENTS];
197 void __iomem *reg;
198 int i;
199
200 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
201 if (IS_ERR(reg))
202 return;
203
204 /* we have a mux, we will have >1 parents */
205 i = of_clk_parent_fill(node, parents, SUN6I_AHB1_MAX_PARENTS);
206 of_property_read_string(node, "clock-output-names", &clk_name);
207
208 ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
209 if (!ahb1)
210 return;
211
212 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
213 if (!mux) {
214 kfree(ahb1);
215 return;
216 }
217
218 /* set up clock properties */
219 mux->reg = reg;
220 mux->shift = SUN6I_AHB1_MUX_SHIFT;
221 mux->mask = SUN6I_AHB1_MUX_MASK;
222 mux->lock = &clk_lock;
223 ahb1->reg = reg;
224
225 clk = clk_register_composite(NULL, clk_name, parents, i,
226 &mux->hw, &clk_mux_ops,
227 &ahb1->hw, &sun6i_ahb1_clk_ops,
228 NULL, NULL, 0);
229
230 if (!IS_ERR(clk)) {
231 of_clk_add_provider(node, of_clk_src_simple_get, clk);
232 clk_register_clkdev(clk, clk_name, NULL);
233 }
234 }
235 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
236
237 /* Maximum number of parents our clocks have */
238 #define SUNXI_MAX_PARENTS 5
239
240 /**
241 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
242 * PLL1 rate is calculated as follows
243 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
244 * parent_rate is always 24Mhz
245 */
246
247 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
248 u8 *n, u8 *k, u8 *m, u8 *p)
249 {
250 u8 div;
251
252 /* Normalize value to a 6M multiple */
253 div = *freq / 6000000;
254 *freq = 6000000 * div;
255
256 /* we were called to round the frequency, we can now return */
257 if (n == NULL)
258 return;
259
260 /* m is always zero for pll1 */
261 *m = 0;
262
263 /* k is 1 only on these cases */
264 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
265 *k = 1;
266 else
267 *k = 0;
268
269 /* p will be 3 for divs under 10 */
270 if (div < 10)
271 *p = 3;
272
273 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
274 else if (div < 20 || (div < 32 && (div & 1)))
275 *p = 2;
276
277 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
278 * of divs between 40-62 */
279 else if (div < 40 || (div < 64 && (div & 2)))
280 *p = 1;
281
282 /* any other entries have p = 0 */
283 else
284 *p = 0;
285
286 /* calculate a suitable n based on k and p */
287 div <<= *p;
288 div /= (*k + 1);
289 *n = div / 4;
290 }
291
292 /**
293 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
294 * PLL1 rate is calculated as follows
295 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
296 * parent_rate should always be 24MHz
297 */
298 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
299 u8 *n, u8 *k, u8 *m, u8 *p)
300 {
301 /*
302 * We can operate only on MHz, this will make our life easier
303 * later.
304 */
305 u32 freq_mhz = *freq / 1000000;
306 u32 parent_freq_mhz = parent_rate / 1000000;
307
308 /*
309 * Round down the frequency to the closest multiple of either
310 * 6 or 16
311 */
312 u32 round_freq_6 = round_down(freq_mhz, 6);
313 u32 round_freq_16 = round_down(freq_mhz, 16);
314
315 if (round_freq_6 > round_freq_16)
316 freq_mhz = round_freq_6;
317 else
318 freq_mhz = round_freq_16;
319
320 *freq = freq_mhz * 1000000;
321
322 /*
323 * If the factors pointer are null, we were just called to
324 * round down the frequency.
325 * Exit.
326 */
327 if (n == NULL)
328 return;
329
330 /* If the frequency is a multiple of 32 MHz, k is always 3 */
331 if (!(freq_mhz % 32))
332 *k = 3;
333 /* If the frequency is a multiple of 9 MHz, k is always 2 */
334 else if (!(freq_mhz % 9))
335 *k = 2;
336 /* If the frequency is a multiple of 8 MHz, k is always 1 */
337 else if (!(freq_mhz % 8))
338 *k = 1;
339 /* Otherwise, we don't use the k factor */
340 else
341 *k = 0;
342
343 /*
344 * If the frequency is a multiple of 2 but not a multiple of
345 * 3, m is 3. This is the first time we use 6 here, yet we
346 * will use it on several other places.
347 * We use this number because it's the lowest frequency we can
348 * generate (with n = 0, k = 0, m = 3), so every other frequency
349 * somehow relates to this frequency.
350 */
351 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
352 *m = 2;
353 /*
354 * If the frequency is a multiple of 6MHz, but the factor is
355 * odd, m will be 3
356 */
357 else if ((freq_mhz / 6) & 1)
358 *m = 3;
359 /* Otherwise, we end up with m = 1 */
360 else
361 *m = 1;
362
363 /* Calculate n thanks to the above factors we already got */
364 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
365
366 /*
367 * If n end up being outbound, and that we can still decrease
368 * m, do it.
369 */
370 if ((*n + 1) > 31 && (*m + 1) > 1) {
371 *n = (*n + 1) / 2 - 1;
372 *m = (*m + 1) / 2 - 1;
373 }
374 }
375
376 /**
377 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
378 * PLL1 rate is calculated as follows
379 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
380 * parent_rate is always 24Mhz
381 */
382
383 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
384 u8 *n, u8 *k, u8 *m, u8 *p)
385 {
386 u8 div;
387
388 /* Normalize value to a 6M multiple */
389 div = *freq / 6000000;
390 *freq = 6000000 * div;
391
392 /* we were called to round the frequency, we can now return */
393 if (n == NULL)
394 return;
395
396 /* m is always zero for pll1 */
397 *m = 0;
398
399 /* k is 1 only on these cases */
400 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
401 *k = 1;
402 else
403 *k = 0;
404
405 /* p will be 2 for divs under 20 and odd divs under 32 */
406 if (div < 20 || (div < 32 && (div & 1)))
407 *p = 2;
408
409 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
410 * of divs between 40-62 */
411 else if (div < 40 || (div < 64 && (div & 2)))
412 *p = 1;
413
414 /* any other entries have p = 0 */
415 else
416 *p = 0;
417
418 /* calculate a suitable n based on k and p */
419 div <<= *p;
420 div /= (*k + 1);
421 *n = div / 4 - 1;
422 }
423
424 /**
425 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
426 * PLL5 rate is calculated as follows
427 * rate = parent_rate * n * (k + 1)
428 * parent_rate is always 24Mhz
429 */
430
431 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
432 u8 *n, u8 *k, u8 *m, u8 *p)
433 {
434 u8 div;
435
436 /* Normalize value to a parent_rate multiple (24M) */
437 div = *freq / parent_rate;
438 *freq = parent_rate * div;
439
440 /* we were called to round the frequency, we can now return */
441 if (n == NULL)
442 return;
443
444 if (div < 31)
445 *k = 0;
446 else if (div / 2 < 31)
447 *k = 1;
448 else if (div / 3 < 31)
449 *k = 2;
450 else
451 *k = 3;
452
453 *n = DIV_ROUND_UP(div, (*k+1));
454 }
455
456 /**
457 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
458 * PLL6x2 rate is calculated as follows
459 * rate = parent_rate * (n + 1) * (k + 1)
460 * parent_rate is always 24Mhz
461 */
462
463 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
464 u8 *n, u8 *k, u8 *m, u8 *p)
465 {
466 u8 div;
467
468 /* Normalize value to a parent_rate multiple (24M) */
469 div = *freq / parent_rate;
470 *freq = parent_rate * div;
471
472 /* we were called to round the frequency, we can now return */
473 if (n == NULL)
474 return;
475
476 *k = div / 32;
477 if (*k > 3)
478 *k = 3;
479
480 *n = DIV_ROUND_UP(div, (*k+1)) - 1;
481 }
482
483 /**
484 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
485 * AHB rate is calculated as follows
486 * rate = parent_rate >> p
487 */
488
489 static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
490 u8 *n, u8 *k, u8 *m, u8 *p)
491 {
492 u32 div;
493
494 /* divide only */
495 if (parent_rate < *freq)
496 *freq = parent_rate;
497
498 /*
499 * user manual says valid speed is 8k ~ 276M, but tests show it
500 * can work at speeds up to 300M, just after reparenting to pll6
501 */
502 if (*freq < 8000)
503 *freq = 8000;
504 if (*freq > 300000000)
505 *freq = 300000000;
506
507 div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
508
509 /* p = 0 ~ 3 */
510 if (div > 3)
511 div = 3;
512
513 *freq = parent_rate >> div;
514
515 /* we were called to round the frequency, we can now return */
516 if (p == NULL)
517 return;
518
519 *p = div;
520 }
521
522 /**
523 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
524 * APB1 rate is calculated as follows
525 * rate = (parent_rate >> p) / (m + 1);
526 */
527
528 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
529 u8 *n, u8 *k, u8 *m, u8 *p)
530 {
531 u8 calcm, calcp;
532
533 if (parent_rate < *freq)
534 *freq = parent_rate;
535
536 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
537
538 /* Invalid rate! */
539 if (parent_rate > 32)
540 return;
541
542 if (parent_rate <= 4)
543 calcp = 0;
544 else if (parent_rate <= 8)
545 calcp = 1;
546 else if (parent_rate <= 16)
547 calcp = 2;
548 else
549 calcp = 3;
550
551 calcm = (parent_rate >> calcp) - 1;
552
553 *freq = (parent_rate >> calcp) / (calcm + 1);
554
555 /* we were called to round the frequency, we can now return */
556 if (n == NULL)
557 return;
558
559 *m = calcm;
560 *p = calcp;
561 }
562
563
564
565
566 /**
567 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
568 * CLK_OUT rate is calculated as follows
569 * rate = (parent_rate >> p) / (m + 1);
570 */
571
572 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
573 u8 *n, u8 *k, u8 *m, u8 *p)
574 {
575 u8 div, calcm, calcp;
576
577 /* These clocks can only divide, so we will never be able to achieve
578 * frequencies higher than the parent frequency */
579 if (*freq > parent_rate)
580 *freq = parent_rate;
581
582 div = DIV_ROUND_UP(parent_rate, *freq);
583
584 if (div < 32)
585 calcp = 0;
586 else if (div / 2 < 32)
587 calcp = 1;
588 else if (div / 4 < 32)
589 calcp = 2;
590 else
591 calcp = 3;
592
593 calcm = DIV_ROUND_UP(div, 1 << calcp);
594
595 *freq = (parent_rate >> calcp) / calcm;
596
597 /* we were called to round the frequency, we can now return */
598 if (n == NULL)
599 return;
600
601 *m = calcm - 1;
602 *p = calcp;
603 }
604
605 /**
606 * sunxi_factors_clk_setup() - Setup function for factor clocks
607 */
608
609 static struct clk_factors_config sun4i_pll1_config = {
610 .nshift = 8,
611 .nwidth = 5,
612 .kshift = 4,
613 .kwidth = 2,
614 .mshift = 0,
615 .mwidth = 2,
616 .pshift = 16,
617 .pwidth = 2,
618 };
619
620 static struct clk_factors_config sun6i_a31_pll1_config = {
621 .nshift = 8,
622 .nwidth = 5,
623 .kshift = 4,
624 .kwidth = 2,
625 .mshift = 0,
626 .mwidth = 2,
627 .n_start = 1,
628 };
629
630 static struct clk_factors_config sun8i_a23_pll1_config = {
631 .nshift = 8,
632 .nwidth = 5,
633 .kshift = 4,
634 .kwidth = 2,
635 .mshift = 0,
636 .mwidth = 2,
637 .pshift = 16,
638 .pwidth = 2,
639 .n_start = 1,
640 };
641
642 static struct clk_factors_config sun4i_pll5_config = {
643 .nshift = 8,
644 .nwidth = 5,
645 .kshift = 4,
646 .kwidth = 2,
647 };
648
649 static struct clk_factors_config sun6i_a31_pll6_config = {
650 .nshift = 8,
651 .nwidth = 5,
652 .kshift = 4,
653 .kwidth = 2,
654 .n_start = 1,
655 };
656
657 static struct clk_factors_config sun5i_a13_ahb_config = {
658 .pshift = 4,
659 .pwidth = 2,
660 };
661
662 static struct clk_factors_config sun4i_apb1_config = {
663 .mshift = 0,
664 .mwidth = 5,
665 .pshift = 16,
666 .pwidth = 2,
667 };
668
669 /* user manual says "n" but it's really "p" */
670 static struct clk_factors_config sun7i_a20_out_config = {
671 .mshift = 8,
672 .mwidth = 5,
673 .pshift = 20,
674 .pwidth = 2,
675 };
676
677 static const struct factors_data sun4i_pll1_data __initconst = {
678 .enable = 31,
679 .table = &sun4i_pll1_config,
680 .getter = sun4i_get_pll1_factors,
681 };
682
683 static const struct factors_data sun6i_a31_pll1_data __initconst = {
684 .enable = 31,
685 .table = &sun6i_a31_pll1_config,
686 .getter = sun6i_a31_get_pll1_factors,
687 };
688
689 static const struct factors_data sun8i_a23_pll1_data __initconst = {
690 .enable = 31,
691 .table = &sun8i_a23_pll1_config,
692 .getter = sun8i_a23_get_pll1_factors,
693 };
694
695 static const struct factors_data sun7i_a20_pll4_data __initconst = {
696 .enable = 31,
697 .table = &sun4i_pll5_config,
698 .getter = sun4i_get_pll5_factors,
699 };
700
701 static const struct factors_data sun4i_pll5_data __initconst = {
702 .enable = 31,
703 .table = &sun4i_pll5_config,
704 .getter = sun4i_get_pll5_factors,
705 .name = "pll5",
706 };
707
708 static const struct factors_data sun4i_pll6_data __initconst = {
709 .enable = 31,
710 .table = &sun4i_pll5_config,
711 .getter = sun4i_get_pll5_factors,
712 .name = "pll6",
713 };
714
715 static const struct factors_data sun6i_a31_pll6_data __initconst = {
716 .enable = 31,
717 .table = &sun6i_a31_pll6_config,
718 .getter = sun6i_a31_get_pll6_factors,
719 .name = "pll6x2",
720 };
721
722 static const struct factors_data sun5i_a13_ahb_data __initconst = {
723 .mux = 6,
724 .muxmask = BIT(1) | BIT(0),
725 .table = &sun5i_a13_ahb_config,
726 .getter = sun5i_a13_get_ahb_factors,
727 };
728
729 static const struct factors_data sun4i_apb1_data __initconst = {
730 .mux = 24,
731 .muxmask = BIT(1) | BIT(0),
732 .table = &sun4i_apb1_config,
733 .getter = sun4i_get_apb1_factors,
734 };
735
736 static const struct factors_data sun7i_a20_out_data __initconst = {
737 .enable = 31,
738 .mux = 24,
739 .muxmask = BIT(1) | BIT(0),
740 .table = &sun7i_a20_out_config,
741 .getter = sun7i_a20_get_out_factors,
742 };
743
744 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
745 const struct factors_data *data)
746 {
747 void __iomem *reg;
748
749 reg = of_iomap(node, 0);
750 if (!reg) {
751 pr_err("Could not get registers for factors-clk: %s\n",
752 node->name);
753 return NULL;
754 }
755
756 return sunxi_factors_register(node, data, &clk_lock, reg);
757 }
758
759
760
761 /**
762 * sunxi_mux_clk_setup() - Setup function for muxes
763 */
764
765 #define SUNXI_MUX_GATE_WIDTH 2
766
767 struct mux_data {
768 u8 shift;
769 };
770
771 static const struct mux_data sun4i_cpu_mux_data __initconst = {
772 .shift = 16,
773 };
774
775 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
776 .shift = 12,
777 };
778
779 static void __init sunxi_mux_clk_setup(struct device_node *node,
780 struct mux_data *data)
781 {
782 struct clk *clk;
783 const char *clk_name = node->name;
784 const char *parents[SUNXI_MAX_PARENTS];
785 void __iomem *reg;
786 int i;
787
788 reg = of_iomap(node, 0);
789
790 i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
791 of_property_read_string(node, "clock-output-names", &clk_name);
792
793 clk = clk_register_mux(NULL, clk_name, parents, i,
794 CLK_SET_RATE_PARENT, reg,
795 data->shift, SUNXI_MUX_GATE_WIDTH,
796 0, &clk_lock);
797
798 if (clk) {
799 of_clk_add_provider(node, of_clk_src_simple_get, clk);
800 clk_register_clkdev(clk, clk_name, NULL);
801 }
802 }
803
804
805
806 /**
807 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
808 */
809
810 struct div_data {
811 u8 shift;
812 u8 pow;
813 u8 width;
814 const struct clk_div_table *table;
815 };
816
817 static const struct div_data sun4i_axi_data __initconst = {
818 .shift = 0,
819 .pow = 0,
820 .width = 2,
821 };
822
823 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
824 { .val = 0, .div = 1 },
825 { .val = 1, .div = 2 },
826 { .val = 2, .div = 3 },
827 { .val = 3, .div = 4 },
828 { .val = 4, .div = 4 },
829 { .val = 5, .div = 4 },
830 { .val = 6, .div = 4 },
831 { .val = 7, .div = 4 },
832 { } /* sentinel */
833 };
834
835 static const struct div_data sun8i_a23_axi_data __initconst = {
836 .width = 3,
837 .table = sun8i_a23_axi_table,
838 };
839
840 static const struct div_data sun4i_ahb_data __initconst = {
841 .shift = 4,
842 .pow = 1,
843 .width = 2,
844 };
845
846 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
847 { .val = 0, .div = 2 },
848 { .val = 1, .div = 2 },
849 { .val = 2, .div = 4 },
850 { .val = 3, .div = 8 },
851 { } /* sentinel */
852 };
853
854 static const struct div_data sun4i_apb0_data __initconst = {
855 .shift = 8,
856 .pow = 1,
857 .width = 2,
858 .table = sun4i_apb0_table,
859 };
860
861 static void __init sunxi_divider_clk_setup(struct device_node *node,
862 struct div_data *data)
863 {
864 struct clk *clk;
865 const char *clk_name = node->name;
866 const char *clk_parent;
867 void __iomem *reg;
868
869 reg = of_iomap(node, 0);
870
871 clk_parent = of_clk_get_parent_name(node, 0);
872
873 of_property_read_string(node, "clock-output-names", &clk_name);
874
875 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
876 reg, data->shift, data->width,
877 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
878 data->table, &clk_lock);
879 if (clk) {
880 of_clk_add_provider(node, of_clk_src_simple_get, clk);
881 clk_register_clkdev(clk, clk_name, NULL);
882 }
883 }
884
885
886
887 /**
888 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
889 */
890
891 #define SUNXI_GATES_MAX_SIZE 64
892
893 struct gates_data {
894 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
895 };
896
897 static const struct gates_data sun4i_axi_gates_data __initconst = {
898 .mask = {1},
899 };
900
901 static const struct gates_data sun4i_ahb_gates_data __initconst = {
902 .mask = {0x7F77FFF, 0x14FB3F},
903 };
904
905 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
906 .mask = {0x147667e7, 0x185915},
907 };
908
909 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
910 .mask = {0x107067e7, 0x185111},
911 };
912
913 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
914 .mask = {0xEDFE7F62, 0x794F931},
915 };
916
917 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
918 .mask = { 0x12f77fff, 0x16ff3f },
919 };
920
921 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
922 .mask = {0x25386742, 0x2505111},
923 };
924
925 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
926 .mask = {0xF5F12B},
927 };
928
929 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
930 .mask = {0x1E20003},
931 };
932
933 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
934 .mask = {0x9B7},
935 };
936
937 static const struct gates_data sun4i_apb0_gates_data __initconst = {
938 .mask = {0x4EF},
939 };
940
941 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
942 .mask = {0x469},
943 };
944
945 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
946 .mask = {0x61},
947 };
948
949 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
950 .mask = { 0x4ff },
951 };
952
953 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
954 .mask = {0xEB822},
955 };
956
957 static const struct gates_data sun4i_apb1_gates_data __initconst = {
958 .mask = {0xFF00F7},
959 };
960
961 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
962 .mask = {0xf0007},
963 };
964
965 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
966 .mask = {0xa0007},
967 };
968
969 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
970 .mask = {0x3031},
971 };
972
973 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
974 .mask = {0x3021},
975 };
976
977 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
978 .mask = {0x3F000F},
979 };
980
981 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
982 .mask = { 0xff80ff },
983 };
984
985 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
986 .mask = {0x3F001F},
987 };
988
989 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
990 .mask = {0x1F0007},
991 };
992
993 static void __init sunxi_gates_clk_setup(struct device_node *node,
994 struct gates_data *data)
995 {
996 struct clk_onecell_data *clk_data;
997 const char *clk_parent;
998 const char *clk_name;
999 void __iomem *reg;
1000 int qty;
1001 int i = 0;
1002 int j = 0;
1003
1004 reg = of_iomap(node, 0);
1005
1006 clk_parent = of_clk_get_parent_name(node, 0);
1007
1008 /* Worst-case size approximation and memory allocation */
1009 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
1010 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1011 if (!clk_data)
1012 return;
1013 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
1014 if (!clk_data->clks) {
1015 kfree(clk_data);
1016 return;
1017 }
1018
1019 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1020 of_property_read_string_index(node, "clock-output-names",
1021 j, &clk_name);
1022
1023 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1024 clk_parent, 0,
1025 reg + 4 * (i/32), i % 32,
1026 0, &clk_lock);
1027 WARN_ON(IS_ERR(clk_data->clks[i]));
1028 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
1029
1030 j++;
1031 }
1032
1033 /* Adjust to the real max */
1034 clk_data->clk_num = i;
1035
1036 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1037 }
1038
1039
1040
1041 /**
1042 * sunxi_divs_clk_setup() helper data
1043 */
1044
1045 #define SUNXI_DIVS_MAX_QTY 4
1046 #define SUNXI_DIVISOR_WIDTH 2
1047
1048 struct divs_data {
1049 const struct factors_data *factors; /* data for the factor clock */
1050 int ndivs; /* number of outputs */
1051 /*
1052 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
1053 * self or base factor clock refers to the output from the pll
1054 * itself. The remaining refer to fixed or configurable divider
1055 * outputs.
1056 */
1057 struct {
1058 u8 self; /* is it the base factor clock? (only one) */
1059 u8 fixed; /* is it a fixed divisor? if not... */
1060 struct clk_div_table *table; /* is it a table based divisor? */
1061 u8 shift; /* otherwise it's a normal divisor with this shift */
1062 u8 pow; /* is it power-of-two based? */
1063 u8 gate; /* is it independently gateable? */
1064 } div[SUNXI_DIVS_MAX_QTY];
1065 };
1066
1067 static struct clk_div_table pll6_sata_tbl[] = {
1068 { .val = 0, .div = 6, },
1069 { .val = 1, .div = 12, },
1070 { .val = 2, .div = 18, },
1071 { .val = 3, .div = 24, },
1072 { } /* sentinel */
1073 };
1074
1075 static const struct divs_data pll5_divs_data __initconst = {
1076 .factors = &sun4i_pll5_data,
1077 .ndivs = 2,
1078 .div = {
1079 { .shift = 0, .pow = 0, }, /* M, DDR */
1080 { .shift = 16, .pow = 1, }, /* P, other */
1081 /* No output for the base factor clock */
1082 }
1083 };
1084
1085 static const struct divs_data pll6_divs_data __initconst = {
1086 .factors = &sun4i_pll6_data,
1087 .ndivs = 4,
1088 .div = {
1089 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1090 { .fixed = 2 }, /* P, other */
1091 { .self = 1 }, /* base factor clock, 2x */
1092 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1093 }
1094 };
1095
1096 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1097 .factors = &sun6i_a31_pll6_data,
1098 .ndivs = 2,
1099 .div = {
1100 { .fixed = 2 }, /* normal output */
1101 { .self = 1 }, /* base factor clock, 2x */
1102 }
1103 };
1104
1105 /**
1106 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1107 *
1108 * These clocks look something like this
1109 * ________________________
1110 * | ___divisor 1---|----> to consumer
1111 * parent >--| pll___/___divisor 2---|----> to consumer
1112 * | \_______________|____> to consumer
1113 * |________________________|
1114 */
1115
1116 static void __init sunxi_divs_clk_setup(struct device_node *node,
1117 struct divs_data *data)
1118 {
1119 struct clk_onecell_data *clk_data;
1120 const char *parent;
1121 const char *clk_name;
1122 struct clk **clks, *pclk;
1123 struct clk_hw *gate_hw, *rate_hw;
1124 const struct clk_ops *rate_ops;
1125 struct clk_gate *gate = NULL;
1126 struct clk_fixed_factor *fix_factor;
1127 struct clk_divider *divider;
1128 void __iomem *reg;
1129 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
1130 int flags, clkflags;
1131
1132 /* if number of children known, use it */
1133 if (data->ndivs)
1134 ndivs = data->ndivs;
1135
1136 /* Set up factor clock that we will be dividing */
1137 pclk = sunxi_factors_clk_setup(node, data->factors);
1138 parent = __clk_get_name(pclk);
1139
1140 reg = of_iomap(node, 0);
1141
1142 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1143 if (!clk_data)
1144 return;
1145
1146 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1147 if (!clks)
1148 goto free_clkdata;
1149
1150 clk_data->clks = clks;
1151
1152 /* It's not a good idea to have automatic reparenting changing
1153 * our RAM clock! */
1154 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1155
1156 for (i = 0; i < ndivs; i++) {
1157 if (of_property_read_string_index(node, "clock-output-names",
1158 i, &clk_name) != 0)
1159 break;
1160
1161 /* If this is the base factor clock, only update clks */
1162 if (data->div[i].self) {
1163 clk_data->clks[i] = pclk;
1164 continue;
1165 }
1166
1167 gate_hw = NULL;
1168 rate_hw = NULL;
1169 rate_ops = NULL;
1170
1171 /* If this leaf clock can be gated, create a gate */
1172 if (data->div[i].gate) {
1173 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1174 if (!gate)
1175 goto free_clks;
1176
1177 gate->reg = reg;
1178 gate->bit_idx = data->div[i].gate;
1179 gate->lock = &clk_lock;
1180
1181 gate_hw = &gate->hw;
1182 }
1183
1184 /* Leaves can be fixed or configurable divisors */
1185 if (data->div[i].fixed) {
1186 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1187 if (!fix_factor)
1188 goto free_gate;
1189
1190 fix_factor->mult = 1;
1191 fix_factor->div = data->div[i].fixed;
1192
1193 rate_hw = &fix_factor->hw;
1194 rate_ops = &clk_fixed_factor_ops;
1195 } else {
1196 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1197 if (!divider)
1198 goto free_gate;
1199
1200 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1201
1202 divider->reg = reg;
1203 divider->shift = data->div[i].shift;
1204 divider->width = SUNXI_DIVISOR_WIDTH;
1205 divider->flags = flags;
1206 divider->lock = &clk_lock;
1207 divider->table = data->div[i].table;
1208
1209 rate_hw = &divider->hw;
1210 rate_ops = &clk_divider_ops;
1211 }
1212
1213 /* Wrap the (potential) gate and the divisor on a composite
1214 * clock to unify them */
1215 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1216 NULL, NULL,
1217 rate_hw, rate_ops,
1218 gate_hw, &clk_gate_ops,
1219 clkflags);
1220
1221 WARN_ON(IS_ERR(clk_data->clks[i]));
1222 clk_register_clkdev(clks[i], clk_name, NULL);
1223 }
1224
1225 /* Adjust to the real max */
1226 clk_data->clk_num = i;
1227
1228 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1229
1230 return;
1231
1232 free_gate:
1233 kfree(gate);
1234 free_clks:
1235 kfree(clks);
1236 free_clkdata:
1237 kfree(clk_data);
1238 }
1239
1240
1241
1242 /* Matches for factors clocks */
1243 static const struct of_device_id clk_factors_match[] __initconst = {
1244 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1245 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1246 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1247 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1248 {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
1249 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1250 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1251 {}
1252 };
1253
1254 /* Matches for divider clocks */
1255 static const struct of_device_id clk_div_match[] __initconst = {
1256 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1257 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1258 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1259 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1260 {}
1261 };
1262
1263 /* Matches for divided outputs */
1264 static const struct of_device_id clk_divs_match[] __initconst = {
1265 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1266 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1267 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1268 {}
1269 };
1270
1271 /* Matches for mux clocks */
1272 static const struct of_device_id clk_mux_match[] __initconst = {
1273 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1274 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1275 {}
1276 };
1277
1278 /* Matches for gate clocks */
1279 static const struct of_device_id clk_gates_match[] __initconst = {
1280 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1281 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1282 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1283 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1284 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1285 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1286 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1287 {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1288 {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1289 {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1290 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1291 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1292 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1293 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1294 {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1295 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1296 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1297 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1298 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1299 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1300 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1301 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1302 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1303 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1304 {}
1305 };
1306
1307 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1308 void *function)
1309 {
1310 struct device_node *np;
1311 const struct div_data *data;
1312 const struct of_device_id *match;
1313 void (*setup_function)(struct device_node *, const void *) = function;
1314
1315 for_each_matching_node_and_match(np, clk_match, &match) {
1316 data = match->data;
1317 setup_function(np, data);
1318 }
1319 }
1320
1321 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1322 {
1323 unsigned int i;
1324
1325 /* Register divided output clocks */
1326 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1327
1328 /* Register factor clocks */
1329 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1330
1331 /* Register divider clocks */
1332 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1333
1334 /* Register mux clocks */
1335 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1336
1337 /* Register gate clocks */
1338 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1339
1340 /* Protect the clocks that needs to stay on */
1341 for (i = 0; i < nclocks; i++) {
1342 struct clk *clk = clk_get(NULL, clocks[i]);
1343
1344 if (!IS_ERR(clk))
1345 clk_prepare_enable(clk);
1346 }
1347 }
1348
1349 static const char *sun4i_a10_critical_clocks[] __initdata = {
1350 "pll5_ddr",
1351 "ahb_sdram",
1352 };
1353
1354 static void __init sun4i_a10_init_clocks(struct device_node *node)
1355 {
1356 sunxi_init_clocks(sun4i_a10_critical_clocks,
1357 ARRAY_SIZE(sun4i_a10_critical_clocks));
1358 }
1359 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1360
1361 static const char *sun5i_critical_clocks[] __initdata = {
1362 "cpu",
1363 "pll5_ddr",
1364 "ahb_sdram",
1365 };
1366
1367 static void __init sun5i_init_clocks(struct device_node *node)
1368 {
1369 sunxi_init_clocks(sun5i_critical_clocks,
1370 ARRAY_SIZE(sun5i_critical_clocks));
1371 }
1372 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1373 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1374 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1375
1376 static const char *sun6i_critical_clocks[] __initdata = {
1377 "cpu",
1378 };
1379
1380 static void __init sun6i_init_clocks(struct device_node *node)
1381 {
1382 sunxi_init_clocks(sun6i_critical_clocks,
1383 ARRAY_SIZE(sun6i_critical_clocks));
1384 }
1385 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1386 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1387 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1388
1389 static void __init sun9i_init_clocks(struct device_node *node)
1390 {
1391 sunxi_init_clocks(NULL, 0);
1392 }
1393 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
Linux kernel - Deliverables
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