drivers/clk/sunxi/clk-sunxi.c

   1 /*
   2  * Copyright 2013 Emilio López
   3  *
   4  * Emilio López <emilio@elopez.com.ar>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clkdev.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/reset-controller.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/log2.h>
  24
  25 #include "clk-factors.h"
  26
  27 static DEFINE_SPINLOCK(clk_lock);
  28
  29 /**
  30  * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
  31  */
  32
  33 #define SUN6I_AHB1_MAX_PARENTS          4
  34 #define SUN6I_AHB1_MUX_PARENT_PLL6      3
  35 #define SUN6I_AHB1_MUX_SHIFT            12
  36 /* un-shifted mask is what mux_clk expects */
  37 #define SUN6I_AHB1_MUX_MASK             0x3
  38 #define SUN6I_AHB1_MUX_GET_PARENT(reg)  ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
  39                                          SUN6I_AHB1_MUX_MASK)
  40
  41 #define SUN6I_AHB1_DIV_SHIFT            4
  42 #define SUN6I_AHB1_DIV_MASK             (0x3 << SUN6I_AHB1_DIV_SHIFT)
  43 #define SUN6I_AHB1_DIV_GET(reg)         ((reg & SUN6I_AHB1_DIV_MASK) >> \
  44                                                 SUN6I_AHB1_DIV_SHIFT)
  45 #define SUN6I_AHB1_DIV_SET(reg, div)    ((reg & ~SUN6I_AHB1_DIV_MASK) | \
  46                                                 (div << SUN6I_AHB1_DIV_SHIFT))
  47 #define SUN6I_AHB1_PLL6_DIV_SHIFT       6
  48 #define SUN6I_AHB1_PLL6_DIV_MASK        (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
  49 #define SUN6I_AHB1_PLL6_DIV_GET(reg)    ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
  50                                                 SUN6I_AHB1_PLL6_DIV_SHIFT)
  51 #define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
  52                                                 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
  53
  54 struct sun6i_ahb1_clk {
  55         struct clk_hw hw;
  56         void __iomem *reg;
  57 };
  58
  59 #define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
  60
  61 static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
  62                                                 unsigned long parent_rate)
  63 {
  64         struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
  65         unsigned long rate;
  66         u32 reg;
  67
  68         /* Fetch the register value */
  69         reg = readl(ahb1->reg);
  70
  71         /* apply pre-divider first if parent is pll6 */
  72         if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
  73                 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
  74
  75         /* clk divider */
  76         rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
  77
  78         return rate;
  79 }
  80
  81 static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
  82                                  u8 parent, unsigned long parent_rate)
  83 {
  84         u8 div, calcp, calcm = 1;
  85
  86         /*
  87          * clock can only divide, so we will never be able to achieve
  88          * frequencies higher than the parent frequency
  89          */
  90         if (parent_rate && rate > parent_rate)
  91                 rate = parent_rate;
  92
  93         div = DIV_ROUND_UP(parent_rate, rate);
  94
  95         /* calculate pre-divider if parent is pll6 */
  96         if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
  97                 if (div < 4)
  98                         calcp = 0;
  99                 else if (div / 2 < 4)
 100                         calcp = 1;
 101                 else if (div / 4 < 4)
 102                         calcp = 2;
 103                 else
 104                         calcp = 3;
 105
 106                 calcm = DIV_ROUND_UP(div, 1 << calcp);
 107         } else {
 108                 calcp = __roundup_pow_of_two(div);
 109                 calcp = calcp > 3 ? 3 : calcp;
 110         }
 111
 112         /* we were asked to pass back divider values */
 113         if (divp) {
 114                 *divp = calcp;
 115                 *pre_divp = calcm - 1;
 116         }
 117
 118         return (parent_rate / calcm) >> calcp;
 119 }
 120
 121 static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
 122                                           unsigned long min_rate,
 123                                           unsigned long max_rate,
 124                                           unsigned long *best_parent_rate,
 125                                           struct clk_hw **best_parent_clk)
 126 {
 127         struct clk *clk = hw->clk, *parent, *best_parent = NULL;
 128         int i, num_parents;
 129         unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
 130
 131         /* find the parent that can help provide the fastest rate <= rate */
 132         num_parents = __clk_get_num_parents(clk);
 133         for (i = 0; i < num_parents; i++) {
 134                 parent = clk_get_parent_by_index(clk, i);
 135                 if (!parent)
 136                         continue;
 137                 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
 138                         parent_rate = __clk_round_rate(parent, rate);
 139                 else
 140                         parent_rate = __clk_get_rate(parent);
 141
 142                 child_rate = sun6i_ahb1_clk_round(rate, NULL, NULL, i,
 143                                                   parent_rate);
 144
 145                 if (child_rate <= rate && child_rate > best_child_rate) {
 146                         best_parent = parent;
 147                         best = parent_rate;
 148                         best_child_rate = child_rate;
 149                 }
 150         }
 151
 152         if (best_parent)
 153                 *best_parent_clk = __clk_get_hw(best_parent);
 154         *best_parent_rate = best;
 155
 156         return best_child_rate;
 157 }
 158
 159 static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 160                                    unsigned long parent_rate)
 161 {
 162         struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
 163         unsigned long flags;
 164         u8 div, pre_div, parent;
 165         u32 reg;
 166
 167         spin_lock_irqsave(&clk_lock, flags);
 168
 169         reg = readl(ahb1->reg);
 170
 171         /* need to know which parent is used to apply pre-divider */
 172         parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
 173         sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
 174
 175         reg = SUN6I_AHB1_DIV_SET(reg, div);
 176         reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
 177         writel(reg, ahb1->reg);
 178
 179         spin_unlock_irqrestore(&clk_lock, flags);
 180
 181         return 0;
 182 }
 183
 184 static const struct clk_ops sun6i_ahb1_clk_ops = {
 185         .determine_rate = sun6i_ahb1_clk_determine_rate,
 186         .recalc_rate    = sun6i_ahb1_clk_recalc_rate,
 187         .set_rate       = sun6i_ahb1_clk_set_rate,
 188 };
 189
 190 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
 191 {
 192         struct clk *clk;
 193         struct sun6i_ahb1_clk *ahb1;
 194         struct clk_mux *mux;
 195         const char *clk_name = node->name;
 196         const char *parents[SUN6I_AHB1_MAX_PARENTS];
 197         void __iomem *reg;
 198         int i = 0;
 199
 200         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 201         if (IS_ERR(reg))
 202                 return;
 203
 204         /* we have a mux, we will have >1 parents */
 205         while (i < SUN6I_AHB1_MAX_PARENTS &&
 206                (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 207                 i++;
 208
 209         of_property_read_string(node, "clock-output-names", &clk_name);
 210
 211         ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
 212         if (!ahb1)
 213                 return;
 214
 215         mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
 216         if (!mux) {
 217                 kfree(ahb1);
 218                 return;
 219         }
 220
 221         /* set up clock properties */
 222         mux->reg = reg;
 223         mux->shift = SUN6I_AHB1_MUX_SHIFT;
 224         mux->mask = SUN6I_AHB1_MUX_MASK;
 225         mux->lock = &clk_lock;
 226         ahb1->reg = reg;
 227
 228         clk = clk_register_composite(NULL, clk_name, parents, i,
 229                                      &mux->hw, &clk_mux_ops,
 230                                      &ahb1->hw, &sun6i_ahb1_clk_ops,
 231                                      NULL, NULL, 0);
 232
 233         if (!IS_ERR(clk)) {
 234                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 235                 clk_register_clkdev(clk, clk_name, NULL);
 236         }
 237 }
 238 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
 239
 240 /* Maximum number of parents our clocks have */
 241 #define SUNXI_MAX_PARENTS       5
 242
 243 /**
 244  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
 245  * PLL1 rate is calculated as follows
 246  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
 247  * parent_rate is always 24Mhz
 248  */
 249
 250 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
 251                                    u8 *n, u8 *k, u8 *m, u8 *p)
 252 {
 253         u8 div;
 254
 255         /* Normalize value to a 6M multiple */
 256         div = *freq / 6000000;
 257         *freq = 6000000 * div;
 258
 259         /* we were called to round the frequency, we can now return */
 260         if (n == NULL)
 261                 return;
 262
 263         /* m is always zero for pll1 */
 264         *m = 0;
 265
 266         /* k is 1 only on these cases */
 267         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
 268                 *k = 1;
 269         else
 270                 *k = 0;
 271
 272         /* p will be 3 for divs under 10 */
 273         if (div < 10)
 274                 *p = 3;
 275
 276         /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
 277         else if (div < 20 || (div < 32 && (div & 1)))
 278                 *p = 2;
 279
 280         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
 281          * of divs between 40-62 */
 282         else if (div < 40 || (div < 64 && (div & 2)))
 283                 *p = 1;
 284
 285         /* any other entries have p = 0 */
 286         else
 287                 *p = 0;
 288
 289         /* calculate a suitable n based on k and p */
 290         div <<= *p;
 291         div /= (*k + 1);
 292         *n = div / 4;
 293 }
 294
 295 /**
 296  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
 297  * PLL1 rate is calculated as follows
 298  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
 299  * parent_rate should always be 24MHz
 300  */
 301 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
 302                                        u8 *n, u8 *k, u8 *m, u8 *p)
 303 {
 304         /*
 305          * We can operate only on MHz, this will make our life easier
 306          * later.
 307          */
 308         u32 freq_mhz = *freq / 1000000;
 309         u32 parent_freq_mhz = parent_rate / 1000000;
 310
 311         /*
 312          * Round down the frequency to the closest multiple of either
 313          * 6 or 16
 314          */
 315         u32 round_freq_6 = round_down(freq_mhz, 6);
 316         u32 round_freq_16 = round_down(freq_mhz, 16);
 317
 318         if (round_freq_6 > round_freq_16)
 319                 freq_mhz = round_freq_6;
 320         else
 321                 freq_mhz = round_freq_16;
 322
 323         *freq = freq_mhz * 1000000;
 324
 325         /*
 326          * If the factors pointer are null, we were just called to
 327          * round down the frequency.
 328          * Exit.
 329          */
 330         if (n == NULL)
 331                 return;
 332
 333         /* If the frequency is a multiple of 32 MHz, k is always 3 */
 334         if (!(freq_mhz % 32))
 335                 *k = 3;
 336         /* If the frequency is a multiple of 9 MHz, k is always 2 */
 337         else if (!(freq_mhz % 9))
 338                 *k = 2;
 339         /* If the frequency is a multiple of 8 MHz, k is always 1 */
 340         else if (!(freq_mhz % 8))
 341                 *k = 1;
 342         /* Otherwise, we don't use the k factor */
 343         else
 344                 *k = 0;
 345
 346         /*
 347          * If the frequency is a multiple of 2 but not a multiple of
 348          * 3, m is 3. This is the first time we use 6 here, yet we
 349          * will use it on several other places.
 350          * We use this number because it's the lowest frequency we can
 351          * generate (with n = 0, k = 0, m = 3), so every other frequency
 352          * somehow relates to this frequency.
 353          */
 354         if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
 355                 *m = 2;
 356         /*
 357          * If the frequency is a multiple of 6MHz, but the factor is
 358          * odd, m will be 3
 359          */
 360         else if ((freq_mhz / 6) & 1)
 361                 *m = 3;
 362         /* Otherwise, we end up with m = 1 */
 363         else
 364                 *m = 1;
 365
 366         /* Calculate n thanks to the above factors we already got */
 367         *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
 368
 369         /*
 370          * If n end up being outbound, and that we can still decrease
 371          * m, do it.
 372          */
 373         if ((*n + 1) > 31 && (*m + 1) > 1) {
 374                 *n = (*n + 1) / 2 - 1;
 375                 *m = (*m + 1) / 2 - 1;
 376         }
 377 }
 378
 379 /**
 380  * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
 381  * PLL1 rate is calculated as follows
 382  * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
 383  * parent_rate is always 24Mhz
 384  */
 385
 386 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
 387                                    u8 *n, u8 *k, u8 *m, u8 *p)
 388 {
 389         u8 div;
 390
 391         /* Normalize value to a 6M multiple */
 392         div = *freq / 6000000;
 393         *freq = 6000000 * div;
 394
 395         /* we were called to round the frequency, we can now return */
 396         if (n == NULL)
 397                 return;
 398
 399         /* m is always zero for pll1 */
 400         *m = 0;
 401
 402         /* k is 1 only on these cases */
 403         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
 404                 *k = 1;
 405         else
 406                 *k = 0;
 407
 408         /* p will be 2 for divs under 20 and odd divs under 32 */
 409         if (div < 20 || (div < 32 && (div & 1)))
 410                 *p = 2;
 411
 412         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
 413          * of divs between 40-62 */
 414         else if (div < 40 || (div < 64 && (div & 2)))
 415                 *p = 1;
 416
 417         /* any other entries have p = 0 */
 418         else
 419                 *p = 0;
 420
 421         /* calculate a suitable n based on k and p */
 422         div <<= *p;
 423         div /= (*k + 1);
 424         *n = div / 4 - 1;
 425 }
 426
 427 /**
 428  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
 429  * PLL5 rate is calculated as follows
 430  * rate = parent_rate * n * (k + 1)
 431  * parent_rate is always 24Mhz
 432  */
 433
 434 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
 435                                    u8 *n, u8 *k, u8 *m, u8 *p)
 436 {
 437         u8 div;
 438
 439         /* Normalize value to a parent_rate multiple (24M) */
 440         div = *freq / parent_rate;
 441         *freq = parent_rate * div;
 442
 443         /* we were called to round the frequency, we can now return */
 444         if (n == NULL)
 445                 return;
 446
 447         if (div < 31)
 448                 *k = 0;
 449         else if (div / 2 < 31)
 450                 *k = 1;
 451         else if (div / 3 < 31)
 452                 *k = 2;
 453         else
 454                 *k = 3;
 455
 456         *n = DIV_ROUND_UP(div, (*k+1));
 457 }
 458
 459 /**
 460  * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
 461  * PLL6x2 rate is calculated as follows
 462  * rate = parent_rate * (n + 1) * (k + 1)
 463  * parent_rate is always 24Mhz
 464  */
 465
 466 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
 467                                        u8 *n, u8 *k, u8 *m, u8 *p)
 468 {
 469         u8 div;
 470
 471         /* Normalize value to a parent_rate multiple (24M) */
 472         div = *freq / parent_rate;
 473         *freq = parent_rate * div;
 474
 475         /* we were called to round the frequency, we can now return */
 476         if (n == NULL)
 477                 return;
 478
 479         *k = div / 32;
 480         if (*k > 3)
 481                 *k = 3;
 482
 483         *n = DIV_ROUND_UP(div, (*k+1)) - 1;
 484 }
 485
 486 /**
 487  * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
 488  * AHB rate is calculated as follows
 489  * rate = parent_rate >> p
 490  */
 491
 492 static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
 493                                        u8 *n, u8 *k, u8 *m, u8 *p)
 494 {
 495         u32 div;
 496
 497         /* divide only */
 498         if (parent_rate < *freq)
 499                 *freq = parent_rate;
 500
 501         /*
 502          * user manual says valid speed is 8k ~ 276M, but tests show it
 503          * can work at speeds up to 300M, just after reparenting to pll6
 504          */
 505         if (*freq < 8000)
 506                 *freq = 8000;
 507         if (*freq > 300000000)
 508                 *freq = 300000000;
 509
 510         div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
 511
 512         /* p = 0 ~ 3 */
 513         if (div > 3)
 514                 div = 3;
 515
 516         *freq = parent_rate >> div;
 517
 518         /* we were called to round the frequency, we can now return */
 519         if (p == NULL)
 520                 return;
 521
 522         *p = div;
 523 }
 524
 525 /**
 526  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
 527  * APB1 rate is calculated as follows
 528  * rate = (parent_rate >> p) / (m + 1);
 529  */
 530
 531 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
 532                                    u8 *n, u8 *k, u8 *m, u8 *p)
 533 {
 534         u8 calcm, calcp;
 535
 536         if (parent_rate < *freq)
 537                 *freq = parent_rate;
 538
 539         parent_rate = DIV_ROUND_UP(parent_rate, *freq);
 540
 541         /* Invalid rate! */
 542         if (parent_rate > 32)
 543                 return;
 544
 545         if (parent_rate <= 4)
 546                 calcp = 0;
 547         else if (parent_rate <= 8)
 548                 calcp = 1;
 549         else if (parent_rate <= 16)
 550                 calcp = 2;
 551         else
 552                 calcp = 3;
 553
 554         calcm = (parent_rate >> calcp) - 1;
 555
 556         *freq = (parent_rate >> calcp) / (calcm + 1);
 557
 558         /* we were called to round the frequency, we can now return */
 559         if (n == NULL)
 560                 return;
 561
 562         *m = calcm;
 563         *p = calcp;
 564 }
 565
 566
 567
 568
 569 /**
 570  * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
 571  * CLK_OUT rate is calculated as follows
 572  * rate = (parent_rate >> p) / (m + 1);
 573  */
 574
 575 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
 576                                       u8 *n, u8 *k, u8 *m, u8 *p)
 577 {
 578         u8 div, calcm, calcp;
 579
 580         /* These clocks can only divide, so we will never be able to achieve
 581          * frequencies higher than the parent frequency */
 582         if (*freq > parent_rate)
 583                 *freq = parent_rate;
 584
 585         div = DIV_ROUND_UP(parent_rate, *freq);
 586
 587         if (div < 32)
 588                 calcp = 0;
 589         else if (div / 2 < 32)
 590                 calcp = 1;
 591         else if (div / 4 < 32)
 592                 calcp = 2;
 593         else
 594                 calcp = 3;
 595
 596         calcm = DIV_ROUND_UP(div, 1 << calcp);
 597
 598         *freq = (parent_rate >> calcp) / calcm;
 599
 600         /* we were called to round the frequency, we can now return */
 601         if (n == NULL)
 602                 return;
 603
 604         *m = calcm - 1;
 605         *p = calcp;
 606 }
 607
 608 /**
 609  * sunxi_factors_clk_setup() - Setup function for factor clocks
 610  */
 611
 612 static struct clk_factors_config sun4i_pll1_config = {
 613         .nshift = 8,
 614         .nwidth = 5,
 615         .kshift = 4,
 616         .kwidth = 2,
 617         .mshift = 0,
 618         .mwidth = 2,
 619         .pshift = 16,
 620         .pwidth = 2,
 621 };
 622
 623 static struct clk_factors_config sun6i_a31_pll1_config = {
 624         .nshift = 8,
 625         .nwidth = 5,
 626         .kshift = 4,
 627         .kwidth = 2,
 628         .mshift = 0,
 629         .mwidth = 2,
 630         .n_start = 1,
 631 };
 632
 633 static struct clk_factors_config sun8i_a23_pll1_config = {
 634         .nshift = 8,
 635         .nwidth = 5,
 636         .kshift = 4,
 637         .kwidth = 2,
 638         .mshift = 0,
 639         .mwidth = 2,
 640         .pshift = 16,
 641         .pwidth = 2,
 642         .n_start = 1,
 643 };
 644
 645 static struct clk_factors_config sun4i_pll5_config = {
 646         .nshift = 8,
 647         .nwidth = 5,
 648         .kshift = 4,
 649         .kwidth = 2,
 650 };
 651
 652 static struct clk_factors_config sun6i_a31_pll6_config = {
 653         .nshift = 8,
 654         .nwidth = 5,
 655         .kshift = 4,
 656         .kwidth = 2,
 657         .n_start = 1,
 658 };
 659
 660 static struct clk_factors_config sun5i_a13_ahb_config = {
 661         .pshift = 4,
 662         .pwidth = 2,
 663 };
 664
 665 static struct clk_factors_config sun4i_apb1_config = {
 666         .mshift = 0,
 667         .mwidth = 5,
 668         .pshift = 16,
 669         .pwidth = 2,
 670 };
 671
 672 /* user manual says "n" but it's really "p" */
 673 static struct clk_factors_config sun7i_a20_out_config = {
 674         .mshift = 8,
 675         .mwidth = 5,
 676         .pshift = 20,
 677         .pwidth = 2,
 678 };
 679
 680 static const struct factors_data sun4i_pll1_data __initconst = {
 681         .enable = 31,
 682         .table = &sun4i_pll1_config,
 683         .getter = sun4i_get_pll1_factors,
 684 };
 685
 686 static const struct factors_data sun6i_a31_pll1_data __initconst = {
 687         .enable = 31,
 688         .table = &sun6i_a31_pll1_config,
 689         .getter = sun6i_a31_get_pll1_factors,
 690 };
 691
 692 static const struct factors_data sun8i_a23_pll1_data __initconst = {
 693         .enable = 31,
 694         .table = &sun8i_a23_pll1_config,
 695         .getter = sun8i_a23_get_pll1_factors,
 696 };
 697
 698 static const struct factors_data sun7i_a20_pll4_data __initconst = {
 699         .enable = 31,
 700         .table = &sun4i_pll5_config,
 701         .getter = sun4i_get_pll5_factors,
 702 };
 703
 704 static const struct factors_data sun4i_pll5_data __initconst = {
 705         .enable = 31,
 706         .table = &sun4i_pll5_config,
 707         .getter = sun4i_get_pll5_factors,
 708         .name = "pll5",
 709 };
 710
 711 static const struct factors_data sun4i_pll6_data __initconst = {
 712         .enable = 31,
 713         .table = &sun4i_pll5_config,
 714         .getter = sun4i_get_pll5_factors,
 715         .name = "pll6",
 716 };
 717
 718 static const struct factors_data sun6i_a31_pll6_data __initconst = {
 719         .enable = 31,
 720         .table = &sun6i_a31_pll6_config,
 721         .getter = sun6i_a31_get_pll6_factors,
 722         .name = "pll6x2",
 723 };
 724
 725 static const struct factors_data sun5i_a13_ahb_data __initconst = {
 726         .mux = 6,
 727         .muxmask = BIT(1) | BIT(0),
 728         .table = &sun5i_a13_ahb_config,
 729         .getter = sun5i_a13_get_ahb_factors,
 730 };
 731
 732 static const struct factors_data sun4i_apb1_data __initconst = {
 733         .mux = 24,
 734         .muxmask = BIT(1) | BIT(0),
 735         .table = &sun4i_apb1_config,
 736         .getter = sun4i_get_apb1_factors,
 737 };
 738
 739 static const struct factors_data sun7i_a20_out_data __initconst = {
 740         .enable = 31,
 741         .mux = 24,
 742         .muxmask = BIT(1) | BIT(0),
 743         .table = &sun7i_a20_out_config,
 744         .getter = sun7i_a20_get_out_factors,
 745 };
 746
 747 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 748                                                    const struct factors_data *data)
 749 {
 750         void __iomem *reg;
 751
 752         reg = of_iomap(node, 0);
 753         if (!reg) {
 754                 pr_err("Could not get registers for factors-clk: %s\n",
 755                        node->name);
 756                 return NULL;
 757         }
 758
 759         return sunxi_factors_register(node, data, &clk_lock, reg);
 760 }
 761
 762
 763
 764 /**
 765  * sunxi_mux_clk_setup() - Setup function for muxes
 766  */
 767
 768 #define SUNXI_MUX_GATE_WIDTH    2
 769
 770 struct mux_data {
 771         u8 shift;
 772 };
 773
 774 static const struct mux_data sun4i_cpu_mux_data __initconst = {
 775         .shift = 16,
 776 };
 777
 778 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
 779         .shift = 12,
 780 };
 781
 782 static void __init sunxi_mux_clk_setup(struct device_node *node,
 783                                        struct mux_data *data)
 784 {
 785         struct clk *clk;
 786         const char *clk_name = node->name;
 787         const char *parents[SUNXI_MAX_PARENTS];
 788         void __iomem *reg;
 789         int i = 0;
 790
 791         reg = of_iomap(node, 0);
 792
 793         while (i < SUNXI_MAX_PARENTS &&
 794                (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 795                 i++;
 796
 797         of_property_read_string(node, "clock-output-names", &clk_name);
 798
 799         clk = clk_register_mux(NULL, clk_name, parents, i,
 800                                CLK_SET_RATE_PARENT, reg,
 801                                data->shift, SUNXI_MUX_GATE_WIDTH,
 802                                0, &clk_lock);
 803
 804         if (clk) {
 805                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 806                 clk_register_clkdev(clk, clk_name, NULL);
 807         }
 808 }
 809
 810
 811
 812 /**
 813  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
 814  */
 815
 816 struct div_data {
 817         u8      shift;
 818         u8      pow;
 819         u8      width;
 820         const struct clk_div_table *table;
 821 };
 822
 823 static const struct div_data sun4i_axi_data __initconst = {
 824         .shift  = 0,
 825         .pow    = 0,
 826         .width  = 2,
 827 };
 828
 829 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
 830         { .val = 0, .div = 1 },
 831         { .val = 1, .div = 2 },
 832         { .val = 2, .div = 3 },
 833         { .val = 3, .div = 4 },
 834         { .val = 4, .div = 4 },
 835         { .val = 5, .div = 4 },
 836         { .val = 6, .div = 4 },
 837         { .val = 7, .div = 4 },
 838         { } /* sentinel */
 839 };
 840
 841 static const struct div_data sun8i_a23_axi_data __initconst = {
 842         .width  = 3,
 843         .table  = sun8i_a23_axi_table,
 844 };
 845
 846 static const struct div_data sun4i_ahb_data __initconst = {
 847         .shift  = 4,
 848         .pow    = 1,
 849         .width  = 2,
 850 };
 851
 852 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
 853         { .val = 0, .div = 2 },
 854         { .val = 1, .div = 2 },
 855         { .val = 2, .div = 4 },
 856         { .val = 3, .div = 8 },
 857         { } /* sentinel */
 858 };
 859
 860 static const struct div_data sun4i_apb0_data __initconst = {
 861         .shift  = 8,
 862         .pow    = 1,
 863         .width  = 2,
 864         .table  = sun4i_apb0_table,
 865 };
 866
 867 static void __init sunxi_divider_clk_setup(struct device_node *node,
 868                                            struct div_data *data)
 869 {
 870         struct clk *clk;
 871         const char *clk_name = node->name;
 872         const char *clk_parent;
 873         void __iomem *reg;
 874
 875         reg = of_iomap(node, 0);
 876
 877         clk_parent = of_clk_get_parent_name(node, 0);
 878
 879         of_property_read_string(node, "clock-output-names", &clk_name);
 880
 881         clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
 882                                          reg, data->shift, data->width,
 883                                          data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
 884                                          data->table, &clk_lock);
 885         if (clk) {
 886                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 887                 clk_register_clkdev(clk, clk_name, NULL);
 888         }
 889 }
 890
 891
 892
 893 /**
 894  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
 895  */
 896
 897 #define SUNXI_GATES_MAX_SIZE    64
 898
 899 struct gates_data {
 900         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
 901 };
 902
 903 static const struct gates_data sun4i_axi_gates_data __initconst = {
 904         .mask = {1},
 905 };
 906
 907 static const struct gates_data sun4i_ahb_gates_data __initconst = {
 908         .mask = {0x7F77FFF, 0x14FB3F},
 909 };
 910
 911 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
 912         .mask = {0x147667e7, 0x185915},
 913 };
 914
 915 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
 916         .mask = {0x107067e7, 0x185111},
 917 };
 918
 919 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
 920         .mask = {0xEDFE7F62, 0x794F931},
 921 };
 922
 923 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
 924         .mask = { 0x12f77fff, 0x16ff3f },
 925 };
 926
 927 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
 928         .mask = {0x25386742, 0x2505111},
 929 };
 930
 931 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
 932         .mask = {0xF5F12B},
 933 };
 934
 935 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
 936         .mask = {0x1E20003},
 937 };
 938
 939 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
 940         .mask = {0x9B7},
 941 };
 942
 943 static const struct gates_data sun4i_apb0_gates_data __initconst = {
 944         .mask = {0x4EF},
 945 };
 946
 947 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
 948         .mask = {0x469},
 949 };
 950
 951 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
 952         .mask = {0x61},
 953 };
 954
 955 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
 956         .mask = { 0x4ff },
 957 };
 958
 959 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
 960         .mask = {0xEB822},
 961 };
 962
 963 static const struct gates_data sun4i_apb1_gates_data __initconst = {
 964         .mask = {0xFF00F7},
 965 };
 966
 967 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
 968         .mask = {0xf0007},
 969 };
 970
 971 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
 972         .mask = {0xa0007},
 973 };
 974
 975 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
 976         .mask = {0x3031},
 977 };
 978
 979 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
 980         .mask = {0x3021},
 981 };
 982
 983 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
 984         .mask = {0x3F000F},
 985 };
 986
 987 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
 988         .mask = { 0xff80ff },
 989 };
 990
 991 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
 992         .mask = {0x3F001F},
 993 };
 994
 995 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
 996         .mask = {0x1F0007},
 997 };
 998
 999 static void __init sunxi_gates_clk_setup(struct device_node *node,
1000                                          struct gates_data *data)
1001 {
1002         struct clk_onecell_data *clk_data;
1003         const char *clk_parent;
1004         const char *clk_name;
1005         void __iomem *reg;
1006         int qty;
1007         int i = 0;
1008         int j = 0;
1009
1010         reg = of_iomap(node, 0);
1011
1012         clk_parent = of_clk_get_parent_name(node, 0);
1013
1014         /* Worst-case size approximation and memory allocation */
1015         qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
1016         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1017         if (!clk_data)
1018                 return;
1019         clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
1020         if (!clk_data->clks) {
1021                 kfree(clk_data);
1022                 return;
1023         }
1024
1025         for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1026                 of_property_read_string_index(node, "clock-output-names",
1027                                               j, &clk_name);
1028
1029                 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1030                                                       clk_parent, 0,
1031                                                       reg + 4 * (i/32), i % 32,
1032                                                       0, &clk_lock);
1033                 WARN_ON(IS_ERR(clk_data->clks[i]));
1034                 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
1035
1036                 j++;
1037         }
1038
1039         /* Adjust to the real max */
1040         clk_data->clk_num = i;
1041
1042         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1043 }
1044
1045
1046
1047 /**
1048  * sunxi_divs_clk_setup() helper data
1049  */
1050
1051 #define SUNXI_DIVS_MAX_QTY      4
1052 #define SUNXI_DIVISOR_WIDTH     2
1053
1054 struct divs_data {
1055         const struct factors_data *factors; /* data for the factor clock */
1056         int ndivs; /* number of outputs */
1057         /*
1058          * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
1059          * self or base factor clock refers to the output from the pll
1060          * itself. The remaining refer to fixed or configurable divider
1061          * outputs.
1062          */
1063         struct {
1064                 u8 self; /* is it the base factor clock? (only one) */
1065                 u8 fixed; /* is it a fixed divisor? if not... */
1066                 struct clk_div_table *table; /* is it a table based divisor? */
1067                 u8 shift; /* otherwise it's a normal divisor with this shift */
1068                 u8 pow;   /* is it power-of-two based? */
1069                 u8 gate;  /* is it independently gateable? */
1070         } div[SUNXI_DIVS_MAX_QTY];
1071 };
1072
1073 static struct clk_div_table pll6_sata_tbl[] = {
1074         { .val = 0, .div = 6, },
1075         { .val = 1, .div = 12, },
1076         { .val = 2, .div = 18, },
1077         { .val = 3, .div = 24, },
1078         { } /* sentinel */
1079 };
1080
1081 static const struct divs_data pll5_divs_data __initconst = {
1082         .factors = &sun4i_pll5_data,
1083         .ndivs = 2,
1084         .div = {
1085                 { .shift = 0, .pow = 0, }, /* M, DDR */
1086                 { .shift = 16, .pow = 1, }, /* P, other */
1087                 /* No output for the base factor clock */
1088         }
1089 };
1090
1091 static const struct divs_data pll6_divs_data __initconst = {
1092         .factors = &sun4i_pll6_data,
1093         .ndivs = 4,
1094         .div = {
1095                 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1096                 { .fixed = 2 }, /* P, other */
1097                 { .self = 1 }, /* base factor clock, 2x */
1098                 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1099         }
1100 };
1101
1102 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1103         .factors = &sun6i_a31_pll6_data,
1104         .ndivs = 2,
1105         .div = {
1106                 { .fixed = 2 }, /* normal output */
1107                 { .self = 1 }, /* base factor clock, 2x */
1108         }
1109 };
1110
1111 /**
1112  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1113  *
1114  * These clocks look something like this
1115  *            ________________________
1116  *           |         ___divisor 1---|----> to consumer
1117  * parent >--|  pll___/___divisor 2---|----> to consumer
1118  *           |        \_______________|____> to consumer
1119  *           |________________________|
1120  */
1121
1122 static void __init sunxi_divs_clk_setup(struct device_node *node,
1123                                         struct divs_data *data)
1124 {
1125         struct clk_onecell_data *clk_data;
1126         const char *parent;
1127         const char *clk_name;
1128         struct clk **clks, *pclk;
1129         struct clk_hw *gate_hw, *rate_hw;
1130         const struct clk_ops *rate_ops;
1131         struct clk_gate *gate = NULL;
1132         struct clk_fixed_factor *fix_factor;
1133         struct clk_divider *divider;
1134         void __iomem *reg;
1135         int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
1136         int flags, clkflags;
1137
1138         /* if number of children known, use it */
1139         if (data->ndivs)
1140                 ndivs = data->ndivs;
1141
1142         /* Set up factor clock that we will be dividing */
1143         pclk = sunxi_factors_clk_setup(node, data->factors);
1144         parent = __clk_get_name(pclk);
1145
1146         reg = of_iomap(node, 0);
1147
1148         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1149         if (!clk_data)
1150                 return;
1151
1152         clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1153         if (!clks)
1154                 goto free_clkdata;
1155
1156         clk_data->clks = clks;
1157
1158         /* It's not a good idea to have automatic reparenting changing
1159          * our RAM clock! */
1160         clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1161
1162         for (i = 0; i < ndivs; i++) {
1163                 if (of_property_read_string_index(node, "clock-output-names",
1164                                                   i, &clk_name) != 0)
1165                         break;
1166
1167                 /* If this is the base factor clock, only update clks */
1168                 if (data->div[i].self) {
1169                         clk_data->clks[i] = pclk;
1170                         continue;
1171                 }
1172
1173                 gate_hw = NULL;
1174                 rate_hw = NULL;
1175                 rate_ops = NULL;
1176
1177                 /* If this leaf clock can be gated, create a gate */
1178                 if (data->div[i].gate) {
1179                         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1180                         if (!gate)
1181                                 goto free_clks;
1182
1183                         gate->reg = reg;
1184                         gate->bit_idx = data->div[i].gate;
1185                         gate->lock = &clk_lock;
1186
1187                         gate_hw = &gate->hw;
1188                 }
1189
1190                 /* Leaves can be fixed or configurable divisors */
1191                 if (data->div[i].fixed) {
1192                         fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1193                         if (!fix_factor)
1194                                 goto free_gate;
1195
1196                         fix_factor->mult = 1;
1197                         fix_factor->div = data->div[i].fixed;
1198
1199                         rate_hw = &fix_factor->hw;
1200                         rate_ops = &clk_fixed_factor_ops;
1201                 } else {
1202                         divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1203                         if (!divider)
1204                                 goto free_gate;
1205
1206                         flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1207
1208                         divider->reg = reg;
1209                         divider->shift = data->div[i].shift;
1210                         divider->width = SUNXI_DIVISOR_WIDTH;
1211                         divider->flags = flags;
1212                         divider->lock = &clk_lock;
1213                         divider->table = data->div[i].table;
1214
1215                         rate_hw = &divider->hw;
1216                         rate_ops = &clk_divider_ops;
1217                 }
1218
1219                 /* Wrap the (potential) gate and the divisor on a composite
1220                  * clock to unify them */
1221                 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1222                                                  NULL, NULL,
1223                                                  rate_hw, rate_ops,
1224                                                  gate_hw, &clk_gate_ops,
1225                                                  clkflags);
1226
1227                 WARN_ON(IS_ERR(clk_data->clks[i]));
1228                 clk_register_clkdev(clks[i], clk_name, NULL);
1229         }
1230
1231         /* Adjust to the real max */
1232         clk_data->clk_num = i;
1233
1234         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1235
1236         return;
1237
1238 free_gate:
1239         kfree(gate);
1240 free_clks:
1241         kfree(clks);
1242 free_clkdata:
1243         kfree(clk_data);
1244 }
1245
1246
1247
1248 /* Matches for factors clocks */
1249 static const struct of_device_id clk_factors_match[] __initconst = {
1250         {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1251         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1252         {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1253         {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1254         {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
1255         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1256         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1257         {}
1258 };
1259
1260 /* Matches for divider clocks */
1261 static const struct of_device_id clk_div_match[] __initconst = {
1262         {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1263         {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1264         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1265         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1266         {}
1267 };
1268
1269 /* Matches for divided outputs */
1270 static const struct of_device_id clk_divs_match[] __initconst = {
1271         {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1272         {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1273         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1274         {}
1275 };
1276
1277 /* Matches for mux clocks */
1278 static const struct of_device_id clk_mux_match[] __initconst = {
1279         {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1280         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1281         {}
1282 };
1283
1284 /* Matches for gate clocks */
1285 static const struct of_device_id clk_gates_match[] __initconst = {
1286         {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1287         {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1288         {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1289         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1290         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1291         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1292         {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1293         {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1294         {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1295         {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1296         {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1297         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1298         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1299         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1300         {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1301         {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1302         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1303         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1304         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1305         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1306         {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1307         {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1308         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1309         {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1310         {}
1311 };
1312
1313 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1314                                               void *function)
1315 {
1316         struct device_node *np;
1317         const struct div_data *data;
1318         const struct of_device_id *match;
1319         void (*setup_function)(struct device_node *, const void *) = function;
1320
1321         for_each_matching_node_and_match(np, clk_match, &match) {
1322                 data = match->data;
1323                 setup_function(np, data);
1324         }
1325 }
1326
1327 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1328 {
1329         unsigned int i;
1330
1331         /* Register divided output clocks */
1332         of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1333
1334         /* Register factor clocks */
1335         of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1336
1337         /* Register divider clocks */
1338         of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1339
1340         /* Register mux clocks */
1341         of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1342
1343         /* Register gate clocks */
1344         of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1345
1346         /* Protect the clocks that needs to stay on */
1347         for (i = 0; i < nclocks; i++) {
1348                 struct clk *clk = clk_get(NULL, clocks[i]);
1349
1350                 if (!IS_ERR(clk))
1351                         clk_prepare_enable(clk);
1352         }
1353 }
1354
1355 static const char *sun4i_a10_critical_clocks[] __initdata = {
1356         "pll5_ddr",
1357         "ahb_sdram",
1358 };
1359
1360 static void __init sun4i_a10_init_clocks(struct device_node *node)
1361 {
1362         sunxi_init_clocks(sun4i_a10_critical_clocks,
1363                           ARRAY_SIZE(sun4i_a10_critical_clocks));
1364 }
1365 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1366
1367 static const char *sun5i_critical_clocks[] __initdata = {
1368         "cpu",
1369         "pll5_ddr",
1370         "ahb_sdram",
1371 };
1372
1373 static void __init sun5i_init_clocks(struct device_node *node)
1374 {
1375         sunxi_init_clocks(sun5i_critical_clocks,
1376                           ARRAY_SIZE(sun5i_critical_clocks));
1377 }
1378 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1379 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1380 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1381
1382 static const char *sun6i_critical_clocks[] __initdata = {
1383         "cpu",
1384 };
1385
1386 static void __init sun6i_init_clocks(struct device_node *node)
1387 {
1388         sunxi_init_clocks(sun6i_critical_clocks,
1389                           ARRAY_SIZE(sun6i_critical_clocks));
1390 }
1391 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1392 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1393 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1394
1395 static void __init sun9i_init_clocks(struct device_node *node)
1396 {
1397         sunxi_init_clocks(NULL, 0);
1398 }
1399 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);