drivers/clk/tegra/clk-periph-gate.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/slab.h>
  20 #include <linux/io.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/tegra-soc.h>
  24
  25 #include "clk.h"
  26
  27 static DEFINE_SPINLOCK(periph_ref_lock);
  28
  29 /* Macros to assist peripheral gate clock */
  30 #define read_enb(gate) \
  31         readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
  32 #define write_enb_set(val, gate) \
  33         writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
  34 #define write_enb_clr(val, gate) \
  35         writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
  36
  37 #define read_rst(gate) \
  38         readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
  39 #define write_rst_set(val, gate) \
  40         writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
  41 #define write_rst_clr(val, gate) \
  42         writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
  43
  44 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
  45
  46 #define LVL2_CLK_GATE_OVRE 0x554
  47
  48 /* Peripheral gate clock ops */
  49 static int clk_periph_is_enabled(struct clk_hw *hw)
  50 {
  51         struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
  52         int state = 1;
  53
  54         if (!(read_enb(gate) & periph_clk_to_bit(gate)))
  55                 state = 0;
  56
  57         if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
  58                 if (read_rst(gate) & periph_clk_to_bit(gate))
  59                         state = 0;
  60
  61         return state;
  62 }
  63
  64 static int clk_periph_enable(struct clk_hw *hw)
  65 {
  66         struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
  67         unsigned long flags = 0;
  68
  69         spin_lock_irqsave(&periph_ref_lock, flags);
  70
  71         gate->enable_refcnt[gate->clk_num]++;
  72         if (gate->enable_refcnt[gate->clk_num] > 1) {
  73                 spin_unlock_irqrestore(&periph_ref_lock, flags);
  74                 return 0;
  75         }
  76
  77         write_enb_set(periph_clk_to_bit(gate), gate);
  78         udelay(2);
  79
  80         if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
  81             !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
  82                 if (read_rst(gate) & periph_clk_to_bit(gate)) {
  83                         udelay(5); /* reset propogation delay */
  84                         write_rst_clr(periph_clk_to_bit(gate), gate);
  85                 }
  86         }
  87
  88         if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
  89                 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
  90                 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
  91                 udelay(1);
  92                 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
  93         }
  94
  95         spin_unlock_irqrestore(&periph_ref_lock, flags);
  96
  97         return 0;
  98 }
  99
 100 static void clk_periph_disable(struct clk_hw *hw)
 101 {
 102         struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
 103         unsigned long flags = 0;
 104
 105         spin_lock_irqsave(&periph_ref_lock, flags);
 106
 107         gate->enable_refcnt[gate->clk_num]--;
 108         if (gate->enable_refcnt[gate->clk_num] > 0) {
 109                 spin_unlock_irqrestore(&periph_ref_lock, flags);
 110                 return;
 111         }
 112
 113         /*
 114          * If peripheral is in the APB bus then read the APB bus to
 115          * flush the write operation in apb bus. This will avoid the
 116          * peripheral access after disabling clock
 117          */
 118         if (gate->flags & TEGRA_PERIPH_ON_APB)
 119                 tegra_read_chipid();
 120
 121         write_enb_clr(periph_clk_to_bit(gate), gate);
 122
 123         spin_unlock_irqrestore(&periph_ref_lock, flags);
 124 }
 125
 126 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
 127 {
 128         if (gate->flags & TEGRA_PERIPH_NO_RESET)
 129                 return;
 130
 131         if (assert) {
 132                 /*
 133                  * If peripheral is in the APB bus then read the APB bus to
 134                  * flush the write operation in apb bus. This will avoid the
 135                  * peripheral access after disabling clock
 136                  */
 137                 if (gate->flags & TEGRA_PERIPH_ON_APB)
 138                         tegra_read_chipid();
 139
 140                 write_rst_set(periph_clk_to_bit(gate), gate);
 141         } else {
 142                 write_rst_clr(periph_clk_to_bit(gate), gate);
 143         }
 144 }
 145
 146 const struct clk_ops tegra_clk_periph_gate_ops = {
 147         .is_enabled = clk_periph_is_enabled,
 148         .enable = clk_periph_enable,
 149         .disable = clk_periph_disable,
 150 };
 151
 152 struct clk *tegra_clk_register_periph_gate(const char *name,
 153                 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
 154                 unsigned long flags, int clk_num,
 155                 struct tegra_clk_periph_regs *pregs, int *enable_refcnt)
 156 {
 157         struct tegra_clk_periph_gate *gate;
 158         struct clk *clk;
 159         struct clk_init_data init;
 160
 161         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 162         if (!gate) {
 163                 pr_err("%s: could not allocate periph gate clk\n", __func__);
 164                 return ERR_PTR(-ENOMEM);
 165         }
 166
 167         init.name = name;
 168         init.flags = flags;
 169         init.parent_names = parent_name ? &parent_name : NULL;
 170         init.num_parents = parent_name ? 1 : 0;
 171         init.ops = &tegra_clk_periph_gate_ops;
 172
 173         gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
 174         gate->clk_base = clk_base;
 175         gate->clk_num = clk_num;
 176         gate->flags = gate_flags;
 177         gate->enable_refcnt = enable_refcnt;
 178         gate->regs = pregs;
 179
 180         /* Data in .init is copied by clk_register(), so stack variable OK */
 181         gate->hw.init = &init;
 182
 183         clk = clk_register(NULL, &gate->hw);
 184         if (IS_ERR(clk))
 185                 kfree(gate);
 186
 187         return clk;
 188 }