2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License as
4 * published by the Free Software Foundation version 2.
6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
7 * kind, whether express or implied; without even the implied warranty
8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
17 #include <linux/of_address.h>
18 #include <linux/clk/ti.h>
19 #include <asm/div64.h>
21 /* FAPLL Control Register PLL_CTRL */
22 #define FAPLL_MAIN_LOCK BIT(7)
23 #define FAPLL_MAIN_PLLEN BIT(3)
24 #define FAPLL_MAIN_BP BIT(2)
25 #define FAPLL_MAIN_LOC_CTL BIT(0)
27 /* FAPLL powerdown register PWD */
28 #define FAPLL_PWD_OFFSET 4
30 #define MAX_FAPLL_OUTPUTS 7
31 #define FAPLL_MAX_RETRIES 1000
33 #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
34 #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
36 /* The bypass bit is inverted on the ddr_pll.. */
37 #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
40 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
41 * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
43 #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
44 #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
46 /* Synthesizer divider register */
47 #define SYNTH_LDMDIV1 BIT(8)
49 /* Synthesizer frequency register */
50 #define SYNTH_LDFREQ BIT(31)
57 struct clk
*clk_bypass
;
58 struct clk_onecell_data outputs
;
59 bool bypass_bit_inverted
;
64 struct fapll_data
*fd
;
72 static bool ti_fapll_clock_is_bypass(struct fapll_data
*fd
)
74 u32 v
= readl_relaxed(fd
->base
);
76 if (fd
->bypass_bit_inverted
)
77 return !(v
& FAPLL_MAIN_BP
);
79 return !!(v
& FAPLL_MAIN_BP
);
82 static int ti_fapll_enable(struct clk_hw
*hw
)
84 struct fapll_data
*fd
= to_fapll(hw
);
85 u32 v
= readl_relaxed(fd
->base
);
87 v
|= FAPLL_MAIN_PLLEN
;
88 writel_relaxed(v
, fd
->base
);
93 static void ti_fapll_disable(struct clk_hw
*hw
)
95 struct fapll_data
*fd
= to_fapll(hw
);
96 u32 v
= readl_relaxed(fd
->base
);
98 v
&= ~FAPLL_MAIN_PLLEN
;
99 writel_relaxed(v
, fd
->base
);
102 static int ti_fapll_is_enabled(struct clk_hw
*hw
)
104 struct fapll_data
*fd
= to_fapll(hw
);
105 u32 v
= readl_relaxed(fd
->base
);
107 return v
& FAPLL_MAIN_PLLEN
;
110 static unsigned long ti_fapll_recalc_rate(struct clk_hw
*hw
,
111 unsigned long parent_rate
)
113 struct fapll_data
*fd
= to_fapll(hw
);
114 u32 fapll_n
, fapll_p
, v
;
117 if (ti_fapll_clock_is_bypass(fd
))
122 /* PLL pre-divider is P and multiplier is N */
123 v
= readl_relaxed(fd
->base
);
124 fapll_p
= (v
>> 8) & 0xff;
126 do_div(rate
, fapll_p
);
134 static u8
ti_fapll_get_parent(struct clk_hw
*hw
)
136 struct fapll_data
*fd
= to_fapll(hw
);
138 if (ti_fapll_clock_is_bypass(fd
))
144 static struct clk_ops ti_fapll_ops
= {
145 .enable
= ti_fapll_enable
,
146 .disable
= ti_fapll_disable
,
147 .is_enabled
= ti_fapll_is_enabled
,
148 .recalc_rate
= ti_fapll_recalc_rate
,
149 .get_parent
= ti_fapll_get_parent
,
152 static int ti_fapll_synth_enable(struct clk_hw
*hw
)
154 struct fapll_synth
*synth
= to_synth(hw
);
155 u32 v
= readl_relaxed(synth
->fd
->base
+ FAPLL_PWD_OFFSET
);
157 v
&= ~(1 << synth
->index
);
158 writel_relaxed(v
, synth
->fd
->base
+ FAPLL_PWD_OFFSET
);
163 static void ti_fapll_synth_disable(struct clk_hw
*hw
)
165 struct fapll_synth
*synth
= to_synth(hw
);
166 u32 v
= readl_relaxed(synth
->fd
->base
+ FAPLL_PWD_OFFSET
);
168 v
|= 1 << synth
->index
;
169 writel_relaxed(v
, synth
->fd
->base
+ FAPLL_PWD_OFFSET
);
172 static int ti_fapll_synth_is_enabled(struct clk_hw
*hw
)
174 struct fapll_synth
*synth
= to_synth(hw
);
175 u32 v
= readl_relaxed(synth
->fd
->base
+ FAPLL_PWD_OFFSET
);
177 return !(v
& (1 << synth
->index
));
181 * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
183 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw
*hw
,
184 unsigned long parent_rate
)
186 struct fapll_synth
*synth
= to_synth(hw
);
190 /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
195 * PLL in bypass sets the synths in bypass mode too. The PLL rate
196 * can be also be set to 27MHz, so we can't use parent_rate to
197 * check for bypass mode.
199 if (ti_fapll_clock_is_bypass(synth
->fd
))
205 * Synth frequency integer and fractional divider.
206 * Note that the phase output K is 8, so the result needs
207 * to be multiplied by 8.
210 u32 v
, synth_int_div
, synth_frac_div
, synth_div_freq
;
212 v
= readl_relaxed(synth
->freq
);
213 synth_int_div
= (v
>> 24) & 0xf;
214 synth_frac_div
= v
& 0xffffff;
215 synth_div_freq
= (synth_int_div
* 10000000) + synth_frac_div
;
217 do_div(rate
, synth_div_freq
);
221 /* Synth ost-divider M */
222 synth_div_m
= readl_relaxed(synth
->div
) & 0xff;
223 do_div(rate
, synth_div_m
);
228 static struct clk_ops ti_fapll_synt_ops
= {
229 .enable
= ti_fapll_synth_enable
,
230 .disable
= ti_fapll_synth_disable
,
231 .is_enabled
= ti_fapll_synth_is_enabled
,
232 .recalc_rate
= ti_fapll_synth_recalc_rate
,
235 static struct clk
* __init
ti_fapll_synth_setup(struct fapll_data
*fd
,
243 struct clk_init_data
*init
;
244 struct fapll_synth
*synth
;
246 init
= kzalloc(sizeof(*init
), GFP_KERNEL
);
248 return ERR_PTR(-ENOMEM
);
250 init
->ops
= &ti_fapll_synt_ops
;
252 init
->parent_names
= &parent
;
253 init
->num_parents
= 1;
255 synth
= kzalloc(sizeof(*synth
), GFP_KERNEL
);
260 synth
->index
= index
;
264 synth
->hw
.init
= init
;
265 synth
->clk_pll
= pll_clk
;
267 return clk_register(NULL
, &synth
->hw
);
273 return ERR_PTR(-ENOMEM
);
276 static void __init
ti_fapll_setup(struct device_node
*node
)
278 struct fapll_data
*fd
;
279 struct clk_init_data
*init
= NULL
;
280 const char *parent_name
[2];
284 fd
= kzalloc(sizeof(*fd
), GFP_KERNEL
);
288 fd
->outputs
.clks
= kzalloc(sizeof(struct clk
*) *
289 MAX_FAPLL_OUTPUTS
+ 1,
291 if (!fd
->outputs
.clks
)
294 init
= kzalloc(sizeof(*init
), GFP_KERNEL
);
298 init
->ops
= &ti_fapll_ops
;
299 init
->name
= node
->name
;
301 init
->num_parents
= of_clk_get_parent_count(node
);
302 if (init
->num_parents
!= 2) {
303 pr_err("%s must have two parents\n", node
->name
);
307 parent_name
[0] = of_clk_get_parent_name(node
, 0);
308 parent_name
[1] = of_clk_get_parent_name(node
, 1);
309 init
->parent_names
= parent_name
;
311 fd
->clk_ref
= of_clk_get(node
, 0);
312 if (IS_ERR(fd
->clk_ref
)) {
313 pr_err("%s could not get clk_ref\n", node
->name
);
317 fd
->clk_bypass
= of_clk_get(node
, 1);
318 if (IS_ERR(fd
->clk_bypass
)) {
319 pr_err("%s could not get clk_bypass\n", node
->name
);
323 fd
->base
= of_iomap(node
, 0);
325 pr_err("%s could not get IO base\n", node
->name
);
329 if (fapll_is_ddr_pll(fd
->base
))
330 fd
->bypass_bit_inverted
= true;
332 fd
->name
= node
->name
;
335 /* Register the parent PLL */
336 pll_clk
= clk_register(NULL
, &fd
->hw
);
340 fd
->outputs
.clks
[0] = pll_clk
;
341 fd
->outputs
.clk_num
++;
344 * Set up the child synthesizers starting at index 1 as the
345 * PLL output is at index 0. We need to check the clock-indices
346 * for numbering in case there are holes in the synth mapping,
347 * and then probe the synth register to see if it has a FREQ
348 * register available.
350 for (i
= 0; i
< MAX_FAPLL_OUTPUTS
; i
++) {
351 const char *output_name
;
352 void __iomem
*freq
, *div
;
353 struct clk
*synth_clk
;
357 if (of_property_read_string_index(node
, "clock-output-names",
361 if (of_property_read_u32_index(node
, "clock-indices", i
,
365 freq
= fd
->base
+ (output_instance
* 8);
368 /* Check for hardwired audio_pll_clk1 */
369 if (is_audio_pll_clk1(freq
)) {
373 /* Does the synthesizer have a FREQ register? */
374 v
= readl_relaxed(freq
);
378 synth_clk
= ti_fapll_synth_setup(fd
, freq
, div
, output_instance
,
379 output_name
, node
->name
,
381 if (IS_ERR(synth_clk
))
384 fd
->outputs
.clks
[output_instance
] = synth_clk
;
385 fd
->outputs
.clk_num
++;
387 clk_register_clkdev(synth_clk
, output_name
, NULL
);
390 /* Register the child synthesizers as the FAPLL outputs */
391 of_clk_add_provider(node
, of_clk_src_onecell_get
, &fd
->outputs
);
392 /* Add clock alias for the outputs */
402 clk_put(fd
->clk_bypass
);
404 clk_put(fd
->clk_ref
);
405 kfree(fd
->outputs
.clks
);
410 CLK_OF_DECLARE(ti_fapll_clock
, "ti,dm816-fapll-clock", ti_fapll_setup
);