2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
23 #include <linux/slab.h>
24 #include <linux/sched_clock.h>
25 #include <linux/acpi.h>
27 #include <asm/arch_timer.h>
30 #include <clocksource/arm_arch_timer.h>
33 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
35 #define CNTACR(n) (0x40 + ((n) * 4))
36 #define CNTACR_RPCT BIT(0)
37 #define CNTACR_RVCT BIT(1)
38 #define CNTACR_RFRQ BIT(2)
39 #define CNTACR_RVOFF BIT(3)
40 #define CNTACR_RWVT BIT(4)
41 #define CNTACR_RWPT BIT(5)
43 #define CNTVCT_LO 0x08
44 #define CNTVCT_HI 0x0c
46 #define CNTP_TVAL 0x28
48 #define CNTV_TVAL 0x38
51 #define ARCH_CP15_TIMER BIT(0)
52 #define ARCH_MEM_TIMER BIT(1)
53 static unsigned arch_timers_present __initdata
;
55 static void __iomem
*arch_counter_base
;
59 struct clock_event_device evt
;
62 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
64 static u32 arch_timer_rate
;
74 static int arch_timer_ppi
[MAX_TIMER_PPI
];
76 static struct clock_event_device __percpu
*arch_timer_evt
;
78 static enum ppi_nr arch_timer_uses_ppi
= VIRT_PPI
;
79 static bool arch_timer_c3stop
;
80 static bool arch_timer_mem_use_virtual
;
82 static bool evtstrm_enable
= IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM
);
84 static int __init
early_evtstrm_cfg(char *buf
)
86 return strtobool(buf
, &evtstrm_enable
);
88 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg
);
91 * Architected system timer support.
94 static __always_inline
95 void arch_timer_reg_write(int access
, enum arch_timer_reg reg
, u32 val
,
96 struct clock_event_device
*clk
)
98 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
99 struct arch_timer
*timer
= to_arch_timer(clk
);
101 case ARCH_TIMER_REG_CTRL
:
102 writel_relaxed(val
, timer
->base
+ CNTP_CTL
);
104 case ARCH_TIMER_REG_TVAL
:
105 writel_relaxed(val
, timer
->base
+ CNTP_TVAL
);
108 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
109 struct arch_timer
*timer
= to_arch_timer(clk
);
111 case ARCH_TIMER_REG_CTRL
:
112 writel_relaxed(val
, timer
->base
+ CNTV_CTL
);
114 case ARCH_TIMER_REG_TVAL
:
115 writel_relaxed(val
, timer
->base
+ CNTV_TVAL
);
119 arch_timer_reg_write_cp15(access
, reg
, val
);
123 static __always_inline
124 u32
arch_timer_reg_read(int access
, enum arch_timer_reg reg
,
125 struct clock_event_device
*clk
)
129 if (access
== ARCH_TIMER_MEM_PHYS_ACCESS
) {
130 struct arch_timer
*timer
= to_arch_timer(clk
);
132 case ARCH_TIMER_REG_CTRL
:
133 val
= readl_relaxed(timer
->base
+ CNTP_CTL
);
135 case ARCH_TIMER_REG_TVAL
:
136 val
= readl_relaxed(timer
->base
+ CNTP_TVAL
);
139 } else if (access
== ARCH_TIMER_MEM_VIRT_ACCESS
) {
140 struct arch_timer
*timer
= to_arch_timer(clk
);
142 case ARCH_TIMER_REG_CTRL
:
143 val
= readl_relaxed(timer
->base
+ CNTV_CTL
);
145 case ARCH_TIMER_REG_TVAL
:
146 val
= readl_relaxed(timer
->base
+ CNTV_TVAL
);
150 val
= arch_timer_reg_read_cp15(access
, reg
);
156 static __always_inline irqreturn_t
timer_handler(const int access
,
157 struct clock_event_device
*evt
)
161 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, evt
);
162 if (ctrl
& ARCH_TIMER_CTRL_IT_STAT
) {
163 ctrl
|= ARCH_TIMER_CTRL_IT_MASK
;
164 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, evt
);
165 evt
->event_handler(evt
);
172 static irqreturn_t
arch_timer_handler_virt(int irq
, void *dev_id
)
174 struct clock_event_device
*evt
= dev_id
;
176 return timer_handler(ARCH_TIMER_VIRT_ACCESS
, evt
);
179 static irqreturn_t
arch_timer_handler_phys(int irq
, void *dev_id
)
181 struct clock_event_device
*evt
= dev_id
;
183 return timer_handler(ARCH_TIMER_PHYS_ACCESS
, evt
);
186 static irqreturn_t
arch_timer_handler_phys_mem(int irq
, void *dev_id
)
188 struct clock_event_device
*evt
= dev_id
;
190 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
);
193 static irqreturn_t
arch_timer_handler_virt_mem(int irq
, void *dev_id
)
195 struct clock_event_device
*evt
= dev_id
;
197 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
);
200 static __always_inline
int timer_shutdown(const int access
,
201 struct clock_event_device
*clk
)
205 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
206 ctrl
&= ~ARCH_TIMER_CTRL_ENABLE
;
207 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
212 static int arch_timer_shutdown_virt(struct clock_event_device
*clk
)
214 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS
, clk
);
217 static int arch_timer_shutdown_phys(struct clock_event_device
*clk
)
219 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS
, clk
);
222 static int arch_timer_shutdown_virt_mem(struct clock_event_device
*clk
)
224 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS
, clk
);
227 static int arch_timer_shutdown_phys_mem(struct clock_event_device
*clk
)
229 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS
, clk
);
232 static __always_inline
void set_next_event(const int access
, unsigned long evt
,
233 struct clock_event_device
*clk
)
236 ctrl
= arch_timer_reg_read(access
, ARCH_TIMER_REG_CTRL
, clk
);
237 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
238 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
239 arch_timer_reg_write(access
, ARCH_TIMER_REG_TVAL
, evt
, clk
);
240 arch_timer_reg_write(access
, ARCH_TIMER_REG_CTRL
, ctrl
, clk
);
243 static int arch_timer_set_next_event_virt(unsigned long evt
,
244 struct clock_event_device
*clk
)
246 set_next_event(ARCH_TIMER_VIRT_ACCESS
, evt
, clk
);
250 static int arch_timer_set_next_event_phys(unsigned long evt
,
251 struct clock_event_device
*clk
)
253 set_next_event(ARCH_TIMER_PHYS_ACCESS
, evt
, clk
);
257 static int arch_timer_set_next_event_virt_mem(unsigned long evt
,
258 struct clock_event_device
*clk
)
260 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS
, evt
, clk
);
264 static int arch_timer_set_next_event_phys_mem(unsigned long evt
,
265 struct clock_event_device
*clk
)
267 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS
, evt
, clk
);
271 static void __arch_timer_setup(unsigned type
,
272 struct clock_event_device
*clk
)
274 clk
->features
= CLOCK_EVT_FEAT_ONESHOT
;
276 if (type
== ARCH_CP15_TIMER
) {
277 if (arch_timer_c3stop
)
278 clk
->features
|= CLOCK_EVT_FEAT_C3STOP
;
279 clk
->name
= "arch_sys_timer";
281 clk
->cpumask
= cpumask_of(smp_processor_id());
282 clk
->irq
= arch_timer_ppi
[arch_timer_uses_ppi
];
283 switch (arch_timer_uses_ppi
) {
285 clk
->set_state_shutdown
= arch_timer_shutdown_virt
;
286 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt
;
287 clk
->set_next_event
= arch_timer_set_next_event_virt
;
289 case PHYS_SECURE_PPI
:
290 case PHYS_NONSECURE_PPI
:
292 clk
->set_state_shutdown
= arch_timer_shutdown_phys
;
293 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys
;
294 clk
->set_next_event
= arch_timer_set_next_event_phys
;
300 clk
->features
|= CLOCK_EVT_FEAT_DYNIRQ
;
301 clk
->name
= "arch_mem_timer";
303 clk
->cpumask
= cpu_all_mask
;
304 if (arch_timer_mem_use_virtual
) {
305 clk
->set_state_shutdown
= arch_timer_shutdown_virt_mem
;
306 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_virt_mem
;
307 clk
->set_next_event
=
308 arch_timer_set_next_event_virt_mem
;
310 clk
->set_state_shutdown
= arch_timer_shutdown_phys_mem
;
311 clk
->set_state_oneshot_stopped
= arch_timer_shutdown_phys_mem
;
312 clk
->set_next_event
=
313 arch_timer_set_next_event_phys_mem
;
317 clk
->set_state_shutdown(clk
);
319 clockevents_config_and_register(clk
, arch_timer_rate
, 0xf, 0x7fffffff);
322 static void arch_timer_evtstrm_enable(int divider
)
324 u32 cntkctl
= arch_timer_get_cntkctl();
326 cntkctl
&= ~ARCH_TIMER_EVT_TRIGGER_MASK
;
327 /* Set the divider and enable virtual event stream */
328 cntkctl
|= (divider
<< ARCH_TIMER_EVT_TRIGGER_SHIFT
)
329 | ARCH_TIMER_VIRT_EVT_EN
;
330 arch_timer_set_cntkctl(cntkctl
);
331 elf_hwcap
|= HWCAP_EVTSTRM
;
333 compat_elf_hwcap
|= COMPAT_HWCAP_EVTSTRM
;
337 static void arch_timer_configure_evtstream(void)
339 int evt_stream_div
, pos
;
341 /* Find the closest power of two to the divisor */
342 evt_stream_div
= arch_timer_rate
/ ARCH_TIMER_EVT_STREAM_FREQ
;
343 pos
= fls(evt_stream_div
);
344 if (pos
> 1 && !(evt_stream_div
& (1 << (pos
- 2))))
346 /* enable event stream */
347 arch_timer_evtstrm_enable(min(pos
, 15));
350 static void arch_counter_set_user_access(void)
352 u32 cntkctl
= arch_timer_get_cntkctl();
354 /* Disable user access to the timers and the physical counter */
355 /* Also disable virtual event stream */
356 cntkctl
&= ~(ARCH_TIMER_USR_PT_ACCESS_EN
357 | ARCH_TIMER_USR_VT_ACCESS_EN
358 | ARCH_TIMER_VIRT_EVT_EN
359 | ARCH_TIMER_USR_PCT_ACCESS_EN
);
361 /* Enable user access to the virtual counter */
362 cntkctl
|= ARCH_TIMER_USR_VCT_ACCESS_EN
;
364 arch_timer_set_cntkctl(cntkctl
);
367 static bool arch_timer_has_nonsecure_ppi(void)
369 return (arch_timer_uses_ppi
== PHYS_SECURE_PPI
&&
370 arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
373 static int arch_timer_starting_cpu(unsigned int cpu
)
375 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
377 __arch_timer_setup(ARCH_CP15_TIMER
, clk
);
379 enable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], 0);
381 if (arch_timer_has_nonsecure_ppi())
382 enable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
], 0);
384 arch_counter_set_user_access();
386 arch_timer_configure_evtstream();
392 arch_timer_detect_rate(void __iomem
*cntbase
, struct device_node
*np
)
394 /* Who has more than one independent system counter? */
399 * Try to determine the frequency from the device tree or CNTFRQ,
400 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
402 if (!acpi_disabled
||
403 of_property_read_u32(np
, "clock-frequency", &arch_timer_rate
)) {
405 arch_timer_rate
= readl_relaxed(cntbase
+ CNTFRQ
);
407 arch_timer_rate
= arch_timer_get_cntfrq();
410 /* Check the timer frequency. */
411 if (arch_timer_rate
== 0)
412 pr_warn("Architected timer frequency not available\n");
415 static void arch_timer_banner(unsigned type
)
417 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
418 type
& ARCH_CP15_TIMER
? "cp15" : "",
419 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? " and " : "",
420 type
& ARCH_MEM_TIMER
? "mmio" : "",
421 (unsigned long)arch_timer_rate
/ 1000000,
422 (unsigned long)(arch_timer_rate
/ 10000) % 100,
423 type
& ARCH_CP15_TIMER
?
424 (arch_timer_uses_ppi
== VIRT_PPI
) ? "virt" : "phys" :
426 type
== (ARCH_CP15_TIMER
| ARCH_MEM_TIMER
) ? "/" : "",
427 type
& ARCH_MEM_TIMER
?
428 arch_timer_mem_use_virtual
? "virt" : "phys" :
432 u32
arch_timer_get_rate(void)
434 return arch_timer_rate
;
437 static u64
arch_counter_get_cntvct_mem(void)
439 u32 vct_lo
, vct_hi
, tmp_hi
;
442 vct_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
443 vct_lo
= readl_relaxed(arch_counter_base
+ CNTVCT_LO
);
444 tmp_hi
= readl_relaxed(arch_counter_base
+ CNTVCT_HI
);
445 } while (vct_hi
!= tmp_hi
);
447 return ((u64
) vct_hi
<< 32) | vct_lo
;
451 * Default to cp15 based access because arm64 uses this function for
452 * sched_clock() before DT is probed and the cp15 method is guaranteed
453 * to exist on arm64. arm doesn't use this before DT is probed so even
454 * if we don't have the cp15 accessors we won't have a problem.
456 u64 (*arch_timer_read_counter
)(void) = arch_counter_get_cntvct
;
458 static cycle_t
arch_counter_read(struct clocksource
*cs
)
460 return arch_timer_read_counter();
463 static cycle_t
arch_counter_read_cc(const struct cyclecounter
*cc
)
465 return arch_timer_read_counter();
468 static struct clocksource clocksource_counter
= {
469 .name
= "arch_sys_counter",
471 .read
= arch_counter_read
,
472 .mask
= CLOCKSOURCE_MASK(56),
473 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
| CLOCK_SOURCE_SUSPEND_NONSTOP
,
476 static struct cyclecounter cyclecounter
= {
477 .read
= arch_counter_read_cc
,
478 .mask
= CLOCKSOURCE_MASK(56),
481 static struct arch_timer_kvm_info arch_timer_kvm_info
;
483 struct arch_timer_kvm_info
*arch_timer_get_kvm_info(void)
485 return &arch_timer_kvm_info
;
488 static void __init
arch_counter_register(unsigned type
)
492 /* Register the CP15 based counter if we have one */
493 if (type
& ARCH_CP15_TIMER
) {
494 if (IS_ENABLED(CONFIG_ARM64
) || arch_timer_uses_ppi
== VIRT_PPI
)
495 arch_timer_read_counter
= arch_counter_get_cntvct
;
497 arch_timer_read_counter
= arch_counter_get_cntpct
;
499 arch_timer_read_counter
= arch_counter_get_cntvct_mem
;
501 /* If the clocksource name is "arch_sys_counter" the
502 * VDSO will attempt to read the CP15-based counter.
503 * Ensure this does not happen when CP15-based
504 * counter is not available.
506 clocksource_counter
.name
= "arch_mem_counter";
509 start_count
= arch_timer_read_counter();
510 clocksource_register_hz(&clocksource_counter
, arch_timer_rate
);
511 cyclecounter
.mult
= clocksource_counter
.mult
;
512 cyclecounter
.shift
= clocksource_counter
.shift
;
513 timecounter_init(&arch_timer_kvm_info
.timecounter
,
514 &cyclecounter
, start_count
);
516 /* 56 bits minimum, so we assume worst case rollover */
517 sched_clock_register(arch_timer_read_counter
, 56, arch_timer_rate
);
520 static void arch_timer_stop(struct clock_event_device
*clk
)
522 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
523 clk
->irq
, smp_processor_id());
525 disable_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
]);
526 if (arch_timer_has_nonsecure_ppi())
527 disable_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
529 clk
->set_state_shutdown(clk
);
532 static int arch_timer_dying_cpu(unsigned int cpu
)
534 struct clock_event_device
*clk
= this_cpu_ptr(arch_timer_evt
);
536 arch_timer_stop(clk
);
541 static unsigned int saved_cntkctl
;
542 static int arch_timer_cpu_pm_notify(struct notifier_block
*self
,
543 unsigned long action
, void *hcpu
)
545 if (action
== CPU_PM_ENTER
)
546 saved_cntkctl
= arch_timer_get_cntkctl();
547 else if (action
== CPU_PM_ENTER_FAILED
|| action
== CPU_PM_EXIT
)
548 arch_timer_set_cntkctl(saved_cntkctl
);
552 static struct notifier_block arch_timer_cpu_pm_notifier
= {
553 .notifier_call
= arch_timer_cpu_pm_notify
,
556 static int __init
arch_timer_cpu_pm_init(void)
558 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier
);
561 static void __init
arch_timer_cpu_pm_deinit(void)
563 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier
));
567 static int __init
arch_timer_cpu_pm_init(void)
572 static void __init
arch_timer_cpu_pm_deinit(void)
577 static int __init
arch_timer_register(void)
582 arch_timer_evt
= alloc_percpu(struct clock_event_device
);
583 if (!arch_timer_evt
) {
588 ppi
= arch_timer_ppi
[arch_timer_uses_ppi
];
589 switch (arch_timer_uses_ppi
) {
591 err
= request_percpu_irq(ppi
, arch_timer_handler_virt
,
592 "arch_timer", arch_timer_evt
);
594 case PHYS_SECURE_PPI
:
595 case PHYS_NONSECURE_PPI
:
596 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
597 "arch_timer", arch_timer_evt
);
598 if (!err
&& arch_timer_ppi
[PHYS_NONSECURE_PPI
]) {
599 ppi
= arch_timer_ppi
[PHYS_NONSECURE_PPI
];
600 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
601 "arch_timer", arch_timer_evt
);
603 free_percpu_irq(arch_timer_ppi
[PHYS_SECURE_PPI
],
608 err
= request_percpu_irq(ppi
, arch_timer_handler_phys
,
609 "arch_timer", arch_timer_evt
);
616 pr_err("arch_timer: can't register interrupt %d (%d)\n",
621 err
= arch_timer_cpu_pm_init();
623 goto out_unreg_notify
;
626 /* Register and immediately configure the timer on the boot CPU */
627 err
= cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING
,
628 "AP_ARM_ARCH_TIMER_STARTING",
629 arch_timer_starting_cpu
, arch_timer_dying_cpu
);
631 goto out_unreg_cpupm
;
635 arch_timer_cpu_pm_deinit();
638 free_percpu_irq(arch_timer_ppi
[arch_timer_uses_ppi
], arch_timer_evt
);
639 if (arch_timer_has_nonsecure_ppi())
640 free_percpu_irq(arch_timer_ppi
[PHYS_NONSECURE_PPI
],
644 free_percpu(arch_timer_evt
);
649 static int __init
arch_timer_mem_register(void __iomem
*base
, unsigned int irq
)
653 struct arch_timer
*t
;
655 t
= kzalloc(sizeof(*t
), GFP_KERNEL
);
661 __arch_timer_setup(ARCH_MEM_TIMER
, &t
->evt
);
663 if (arch_timer_mem_use_virtual
)
664 func
= arch_timer_handler_virt_mem
;
666 func
= arch_timer_handler_phys_mem
;
668 ret
= request_irq(irq
, func
, IRQF_TIMER
, "arch_mem_timer", &t
->evt
);
670 pr_err("arch_timer: Failed to request mem timer irq\n");
677 static const struct of_device_id arch_timer_of_match
[] __initconst
= {
678 { .compatible
= "arm,armv7-timer", },
679 { .compatible
= "arm,armv8-timer", },
683 static const struct of_device_id arch_timer_mem_of_match
[] __initconst
= {
684 { .compatible
= "arm,armv7-timer-mem", },
689 arch_timer_needs_probing(int type
, const struct of_device_id
*matches
)
691 struct device_node
*dn
;
692 bool needs_probing
= false;
694 dn
= of_find_matching_node(NULL
, matches
);
695 if (dn
&& of_device_is_available(dn
) && !(arch_timers_present
& type
))
696 needs_probing
= true;
699 return needs_probing
;
702 static int __init
arch_timer_common_init(void)
704 unsigned mask
= ARCH_CP15_TIMER
| ARCH_MEM_TIMER
;
706 /* Wait until both nodes are probed if we have two timers */
707 if ((arch_timers_present
& mask
) != mask
) {
708 if (arch_timer_needs_probing(ARCH_MEM_TIMER
, arch_timer_mem_of_match
))
710 if (arch_timer_needs_probing(ARCH_CP15_TIMER
, arch_timer_of_match
))
714 arch_timer_banner(arch_timers_present
);
715 arch_counter_register(arch_timers_present
);
716 return arch_timer_arch_init();
719 static int __init
arch_timer_init(void)
723 * If HYP mode is available, we know that the physical timer
724 * has been configured to be accessible from PL1. Use it, so
725 * that a guest can use the virtual timer instead.
727 * If no interrupt provided for virtual timer, we'll have to
728 * stick to the physical timer. It'd better be accessible...
730 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
731 * accesses to CNTP_*_EL1 registers are silently redirected to
732 * their CNTHP_*_EL2 counterparts, and use a different PPI
735 if (is_hyp_mode_available() || !arch_timer_ppi
[VIRT_PPI
]) {
738 if (is_kernel_in_hyp_mode()) {
739 arch_timer_uses_ppi
= HYP_PPI
;
740 has_ppi
= !!arch_timer_ppi
[HYP_PPI
];
742 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
743 has_ppi
= (!!arch_timer_ppi
[PHYS_SECURE_PPI
] ||
744 !!arch_timer_ppi
[PHYS_NONSECURE_PPI
]);
748 pr_warn("arch_timer: No interrupt available, giving up\n");
753 ret
= arch_timer_register();
757 ret
= arch_timer_common_init();
761 arch_timer_kvm_info
.virtual_irq
= arch_timer_ppi
[VIRT_PPI
];
766 static int __init
arch_timer_of_init(struct device_node
*np
)
770 if (arch_timers_present
& ARCH_CP15_TIMER
) {
771 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
775 arch_timers_present
|= ARCH_CP15_TIMER
;
776 for (i
= PHYS_SECURE_PPI
; i
< MAX_TIMER_PPI
; i
++)
777 arch_timer_ppi
[i
] = irq_of_parse_and_map(np
, i
);
779 arch_timer_detect_rate(NULL
, np
);
781 arch_timer_c3stop
= !of_property_read_bool(np
, "always-on");
784 * If we cannot rely on firmware initializing the timer registers then
785 * we should use the physical timers instead.
787 if (IS_ENABLED(CONFIG_ARM
) &&
788 of_property_read_bool(np
, "arm,cpu-registers-not-fw-configured"))
789 arch_timer_uses_ppi
= PHYS_SECURE_PPI
;
791 return arch_timer_init();
793 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer
, "arm,armv7-timer", arch_timer_of_init
);
794 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer
, "arm,armv8-timer", arch_timer_of_init
);
796 static int __init
arch_timer_mem_init(struct device_node
*np
)
798 struct device_node
*frame
, *best_frame
= NULL
;
799 void __iomem
*cntctlbase
, *base
;
800 unsigned int irq
, ret
= -EINVAL
;
803 arch_timers_present
|= ARCH_MEM_TIMER
;
804 cntctlbase
= of_iomap(np
, 0);
806 pr_err("arch_timer: Can't find CNTCTLBase\n");
810 cnttidr
= readl_relaxed(cntctlbase
+ CNTTIDR
);
813 * Try to find a virtual capable frame. Otherwise fall back to a
814 * physical capable frame.
816 for_each_available_child_of_node(np
, frame
) {
820 if (of_property_read_u32(frame
, "frame-number", &n
)) {
821 pr_err("arch_timer: Missing frame-number\n");
826 /* Try enabling everything, and see what sticks */
827 cntacr
= CNTACR_RFRQ
| CNTACR_RWPT
| CNTACR_RPCT
|
828 CNTACR_RWVT
| CNTACR_RVOFF
| CNTACR_RVCT
;
829 writel_relaxed(cntacr
, cntctlbase
+ CNTACR(n
));
830 cntacr
= readl_relaxed(cntctlbase
+ CNTACR(n
));
832 if ((cnttidr
& CNTTIDR_VIRT(n
)) &&
833 !(~cntacr
& (CNTACR_RWVT
| CNTACR_RVCT
))) {
834 of_node_put(best_frame
);
836 arch_timer_mem_use_virtual
= true;
840 if (~cntacr
& (CNTACR_RWPT
| CNTACR_RPCT
))
843 of_node_put(best_frame
);
844 best_frame
= of_node_get(frame
);
848 base
= arch_counter_base
= of_iomap(best_frame
, 0);
850 pr_err("arch_timer: Can't map frame's registers\n");
854 if (arch_timer_mem_use_virtual
)
855 irq
= irq_of_parse_and_map(best_frame
, 1);
857 irq
= irq_of_parse_and_map(best_frame
, 0);
861 pr_err("arch_timer: Frame missing %s irq",
862 arch_timer_mem_use_virtual
? "virt" : "phys");
866 arch_timer_detect_rate(base
, np
);
867 ret
= arch_timer_mem_register(base
, irq
);
871 return arch_timer_common_init();
874 of_node_put(best_frame
);
877 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem
, "arm,armv7-timer-mem",
878 arch_timer_mem_init
);
881 static int __init
map_generic_timer_interrupt(u32 interrupt
, u32 flags
)
883 int trigger
, polarity
;
888 trigger
= (flags
& ACPI_GTDT_INTERRUPT_MODE
) ? ACPI_EDGE_SENSITIVE
889 : ACPI_LEVEL_SENSITIVE
;
891 polarity
= (flags
& ACPI_GTDT_INTERRUPT_POLARITY
) ? ACPI_ACTIVE_LOW
894 return acpi_register_gsi(NULL
, interrupt
, trigger
, polarity
);
897 /* Initialize per-processor generic timer */
898 static int __init
arch_timer_acpi_init(struct acpi_table_header
*table
)
900 struct acpi_table_gtdt
*gtdt
;
902 if (arch_timers_present
& ARCH_CP15_TIMER
) {
903 pr_warn("arch_timer: already initialized, skipping\n");
907 gtdt
= container_of(table
, struct acpi_table_gtdt
, header
);
909 arch_timers_present
|= ARCH_CP15_TIMER
;
911 arch_timer_ppi
[PHYS_SECURE_PPI
] =
912 map_generic_timer_interrupt(gtdt
->secure_el1_interrupt
,
913 gtdt
->secure_el1_flags
);
915 arch_timer_ppi
[PHYS_NONSECURE_PPI
] =
916 map_generic_timer_interrupt(gtdt
->non_secure_el1_interrupt
,
917 gtdt
->non_secure_el1_flags
);
919 arch_timer_ppi
[VIRT_PPI
] =
920 map_generic_timer_interrupt(gtdt
->virtual_timer_interrupt
,
921 gtdt
->virtual_timer_flags
);
923 arch_timer_ppi
[HYP_PPI
] =
924 map_generic_timer_interrupt(gtdt
->non_secure_el2_interrupt
,
925 gtdt
->non_secure_el2_flags
);
927 /* Get the frequency from CNTFRQ */
928 arch_timer_detect_rate(NULL
, NULL
);
930 /* Always-on capability */
931 arch_timer_c3stop
= !(gtdt
->non_secure_el1_flags
& ACPI_GTDT_ALWAYS_ON
);
936 CLOCKSOURCE_ACPI_DECLARE(arch_timer
, ACPI_SIG_GTDT
, arch_timer_acpi_init
);