drivers/clocksource/arm_arch_timer.c

   1 /*
   2  *  linux/drivers/clocksource/arm_arch_timer.c
   3  *
   4  *  Copyright (C) 2011 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/device.h>
  14 #include <linux/smp.h>
  15 #include <linux/cpu.h>
  16 #include <linux/clockchips.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #include <asm/arch_timer.h>
  24 #include <asm/virt.h>
  25
  26 #include <clocksource/arm_arch_timer.h>
  27
  28 #define CNTTIDR         0x08
  29 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
  30
  31 #define CNTVCT_LO       0x08
  32 #define CNTVCT_HI       0x0c
  33 #define CNTFRQ          0x10
  34 #define CNTP_TVAL       0x28
  35 #define CNTP_CTL        0x2c
  36 #define CNTV_TVAL       0x38
  37 #define CNTV_CTL        0x3c
  38
  39 #define ARCH_CP15_TIMER BIT(0)
  40 #define ARCH_MEM_TIMER  BIT(1)
  41 static unsigned arch_timers_present __initdata;
  42
  43 static void __iomem *arch_counter_base;
  44
  45 struct arch_timer {
  46         void __iomem *base;
  47         struct clock_event_device evt;
  48 };
  49
  50 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
  51
  52 static u32 arch_timer_rate;
  53
  54 enum ppi_nr {
  55         PHYS_SECURE_PPI,
  56         PHYS_NONSECURE_PPI,
  57         VIRT_PPI,
  58         HYP_PPI,
  59         MAX_TIMER_PPI
  60 };
  61
  62 static int arch_timer_ppi[MAX_TIMER_PPI];
  63
  64 static struct clock_event_device __percpu *arch_timer_evt;
  65
  66 static bool arch_timer_use_virtual = true;
  67 static bool arch_timer_mem_use_virtual;
  68
  69 /*
  70  * Architected system timer support.
  71  */
  72
  73 static __always_inline
  74 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
  75                 struct clock_event_device *clk)
  76 {
  77         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
  78                 struct arch_timer *timer = to_arch_timer(clk);
  79                 switch (reg) {
  80                 case ARCH_TIMER_REG_CTRL:
  81                         writel_relaxed(val, timer->base + CNTP_CTL);
  82                         break;
  83                 case ARCH_TIMER_REG_TVAL:
  84                         writel_relaxed(val, timer->base + CNTP_TVAL);
  85                         break;
  86                 }
  87         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
  88                 struct arch_timer *timer = to_arch_timer(clk);
  89                 switch (reg) {
  90                 case ARCH_TIMER_REG_CTRL:
  91                         writel_relaxed(val, timer->base + CNTV_CTL);
  92                         break;
  93                 case ARCH_TIMER_REG_TVAL:
  94                         writel_relaxed(val, timer->base + CNTV_TVAL);
  95                         break;
  96                 }
  97         } else {
  98                 arch_timer_reg_write_cp15(access, reg, val);
  99         }
 100 }
 101
 102 static __always_inline
 103 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
 104                 struct clock_event_device *clk)
 105 {
 106         u32 val;
 107
 108         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 109                 struct arch_timer *timer = to_arch_timer(clk);
 110                 switch (reg) {
 111                 case ARCH_TIMER_REG_CTRL:
 112                         val = readl_relaxed(timer->base + CNTP_CTL);
 113                         break;
 114                 case ARCH_TIMER_REG_TVAL:
 115                         val = readl_relaxed(timer->base + CNTP_TVAL);
 116                         break;
 117                 }
 118         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 119                 struct arch_timer *timer = to_arch_timer(clk);
 120                 switch (reg) {
 121                 case ARCH_TIMER_REG_CTRL:
 122                         val = readl_relaxed(timer->base + CNTV_CTL);
 123                         break;
 124                 case ARCH_TIMER_REG_TVAL:
 125                         val = readl_relaxed(timer->base + CNTV_TVAL);
 126                         break;
 127                 }
 128         } else {
 129                 val = arch_timer_reg_read_cp15(access, reg);
 130         }
 131
 132         return val;
 133 }
 134
 135 static __always_inline irqreturn_t timer_handler(const int access,
 136                                         struct clock_event_device *evt)
 137 {
 138         unsigned long ctrl;
 139         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
 140         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
 141                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
 142                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
 143                 evt->event_handler(evt);
 144                 return IRQ_HANDLED;
 145         }
 146
 147         return IRQ_NONE;
 148 }
 149
 150 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 151 {
 152         struct clock_event_device *evt = dev_id;
 153
 154         return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 155 }
 156
 157 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 158 {
 159         struct clock_event_device *evt = dev_id;
 160
 161         return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
 162 }
 163
 164 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
 165 {
 166         struct clock_event_device *evt = dev_id;
 167
 168         return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
 169 }
 170
 171 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
 172 {
 173         struct clock_event_device *evt = dev_id;
 174
 175         return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
 176 }
 177
 178 static __always_inline void timer_set_mode(const int access, int mode,
 179                                   struct clock_event_device *clk)
 180 {
 181         unsigned long ctrl;
 182         switch (mode) {
 183         case CLOCK_EVT_MODE_UNUSED:
 184         case CLOCK_EVT_MODE_SHUTDOWN:
 185                 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 186                 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
 187                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 188                 break;
 189         default:
 190                 break;
 191         }
 192 }
 193
 194 static void arch_timer_set_mode_virt(enum clock_event_mode mode,
 195                                      struct clock_event_device *clk)
 196 {
 197         timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
 198 }
 199
 200 static void arch_timer_set_mode_phys(enum clock_event_mode mode,
 201                                      struct clock_event_device *clk)
 202 {
 203         timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
 204 }
 205
 206 static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
 207                                          struct clock_event_device *clk)
 208 {
 209         timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
 210 }
 211
 212 static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
 213                                          struct clock_event_device *clk)
 214 {
 215         timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
 216 }
 217
 218 static __always_inline void set_next_event(const int access, unsigned long evt,
 219                                   struct clock_event_device *clk)
 220 {
 221         unsigned long ctrl;
 222         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 223         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 224         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 225         arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
 226         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 227 }
 228
 229 static int arch_timer_set_next_event_virt(unsigned long evt,
 230                                           struct clock_event_device *clk)
 231 {
 232         set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 233         return 0;
 234 }
 235
 236 static int arch_timer_set_next_event_phys(unsigned long evt,
 237                                           struct clock_event_device *clk)
 238 {
 239         set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 240         return 0;
 241 }
 242
 243 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
 244                                               struct clock_event_device *clk)
 245 {
 246         set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
 247         return 0;
 248 }
 249
 250 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 251                                               struct clock_event_device *clk)
 252 {
 253         set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
 254         return 0;
 255 }
 256
 257 static void __cpuinit __arch_timer_setup(unsigned type,
 258                                        struct clock_event_device *clk)
 259 {
 260         clk->features = CLOCK_EVT_FEAT_ONESHOT;
 261
 262         if (type == ARCH_CP15_TIMER) {
 263                 clk->features |= CLOCK_EVT_FEAT_C3STOP;
 264                 clk->name = "arch_sys_timer";
 265                 clk->rating = 450;
 266                 clk->cpumask = cpumask_of(smp_processor_id());
 267                 if (arch_timer_use_virtual) {
 268                         clk->irq = arch_timer_ppi[VIRT_PPI];
 269                         clk->set_mode = arch_timer_set_mode_virt;
 270                         clk->set_next_event = arch_timer_set_next_event_virt;
 271                 } else {
 272                         clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
 273                         clk->set_mode = arch_timer_set_mode_phys;
 274                         clk->set_next_event = arch_timer_set_next_event_phys;
 275                 }
 276         } else {
 277                 clk->name = "arch_mem_timer";
 278                 clk->rating = 400;
 279                 clk->cpumask = cpu_all_mask;
 280                 if (arch_timer_mem_use_virtual) {
 281                         clk->set_mode = arch_timer_set_mode_virt_mem;
 282                         clk->set_next_event =
 283                                 arch_timer_set_next_event_virt_mem;
 284                 } else {
 285                         clk->set_mode = arch_timer_set_mode_phys_mem;
 286                         clk->set_next_event =
 287                                 arch_timer_set_next_event_phys_mem;
 288                 }
 289         }
 290
 291         clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
 292
 293         clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
 294 }
 295
 296 static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 297 {
 298         __arch_timer_setup(ARCH_CP15_TIMER, clk);
 299
 300         if (arch_timer_use_virtual)
 301                 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
 302         else {
 303                 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
 304                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 305                         enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
 306         }
 307
 308         arch_counter_set_user_access();
 309
 310         return 0;
 311 }
 312
 313 static void
 314 arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
 315 {
 316         /* Who has more than one independent system counter? */
 317         if (arch_timer_rate)
 318                 return;
 319
 320         /* Try to determine the frequency from the device tree or CNTFRQ */
 321         if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
 322                 if (cntbase)
 323                         arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
 324                 else
 325                         arch_timer_rate = arch_timer_get_cntfrq();
 326         }
 327
 328         /* Check the timer frequency. */
 329         if (arch_timer_rate == 0)
 330                 pr_warn("Architected timer frequency not available\n");
 331 }
 332
 333 static void arch_timer_banner(unsigned type)
 334 {
 335         pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
 336                      type & ARCH_CP15_TIMER ? "cp15" : "",
 337                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  " and " : "",
 338                      type & ARCH_MEM_TIMER ? "mmio" : "",
 339                      (unsigned long)arch_timer_rate / 1000000,
 340                      (unsigned long)(arch_timer_rate / 10000) % 100,
 341                      type & ARCH_CP15_TIMER ?
 342                         arch_timer_use_virtual ? "virt" : "phys" :
 343                         "",
 344                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  "/" : "",
 345                      type & ARCH_MEM_TIMER ?
 346                         arch_timer_mem_use_virtual ? "virt" : "phys" :
 347                         "");
 348 }
 349
 350 u32 arch_timer_get_rate(void)
 351 {
 352         return arch_timer_rate;
 353 }
 354
 355 static u64 arch_counter_get_cntvct_mem(void)
 356 {
 357         u32 vct_lo, vct_hi, tmp_hi;
 358
 359         do {
 360                 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 361                 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
 362                 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 363         } while (vct_hi != tmp_hi);
 364
 365         return ((u64) vct_hi << 32) | vct_lo;
 366 }
 367
 368 /*
 369  * Default to cp15 based access because arm64 uses this function for
 370  * sched_clock() before DT is probed and the cp15 method is guaranteed
 371  * to exist on arm64. arm doesn't use this before DT is probed so even
 372  * if we don't have the cp15 accessors we won't have a problem.
 373  */
 374 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
 375
 376 static cycle_t arch_counter_read(struct clocksource *cs)
 377 {
 378         return arch_timer_read_counter();
 379 }
 380
 381 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
 382 {
 383         return arch_timer_read_counter();
 384 }
 385
 386 static struct clocksource clocksource_counter = {
 387         .name   = "arch_sys_counter",
 388         .rating = 400,
 389         .read   = arch_counter_read,
 390         .mask   = CLOCKSOURCE_MASK(56),
 391         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 392 };
 393
 394 static struct cyclecounter cyclecounter = {
 395         .read   = arch_counter_read_cc,
 396         .mask   = CLOCKSOURCE_MASK(56),
 397 };
 398
 399 static struct timecounter timecounter;
 400
 401 struct timecounter *arch_timer_get_timecounter(void)
 402 {
 403         return &timecounter;
 404 }
 405
 406 static void __init arch_counter_register(unsigned type)
 407 {
 408         u64 start_count;
 409
 410         /* Register the CP15 based counter if we have one */
 411         if (type & ARCH_CP15_TIMER)
 412                 arch_timer_read_counter = arch_counter_get_cntvct;
 413         else
 414                 arch_timer_read_counter = arch_counter_get_cntvct_mem;
 415
 416         start_count = arch_timer_read_counter();
 417         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 418         cyclecounter.mult = clocksource_counter.mult;
 419         cyclecounter.shift = clocksource_counter.shift;
 420         timecounter_init(&timecounter, &cyclecounter, start_count);
 421 }
 422
 423 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 424 {
 425         pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
 426                  clk->irq, smp_processor_id());
 427
 428         if (arch_timer_use_virtual)
 429                 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
 430         else {
 431                 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
 432                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 433                         disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
 434         }
 435
 436         clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 437 }
 438
 439 static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
 440                                            unsigned long action, void *hcpu)
 441 {
 442         /*
 443          * Grab cpu pointer in each case to avoid spurious
 444          * preemptible warnings
 445          */
 446         switch (action & ~CPU_TASKS_FROZEN) {
 447         case CPU_STARTING:
 448                 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
 449                 break;
 450         case CPU_DYING:
 451                 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
 452                 break;
 453         }
 454
 455         return NOTIFY_OK;
 456 }
 457
 458 static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
 459         .notifier_call = arch_timer_cpu_notify,
 460 };
 461
 462 static int __init arch_timer_register(void)
 463 {
 464         int err;
 465         int ppi;
 466
 467         arch_timer_evt = alloc_percpu(struct clock_event_device);
 468         if (!arch_timer_evt) {
 469                 err = -ENOMEM;
 470                 goto out;
 471         }
 472
 473         if (arch_timer_use_virtual) {
 474                 ppi = arch_timer_ppi[VIRT_PPI];
 475                 err = request_percpu_irq(ppi, arch_timer_handler_virt,
 476                                          "arch_timer", arch_timer_evt);
 477         } else {
 478                 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
 479                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
 480                                          "arch_timer", arch_timer_evt);
 481                 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
 482                         ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
 483                         err = request_percpu_irq(ppi, arch_timer_handler_phys,
 484                                                  "arch_timer", arch_timer_evt);
 485                         if (err)
 486                                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
 487                                                 arch_timer_evt);
 488                 }
 489         }
 490
 491         if (err) {
 492                 pr_err("arch_timer: can't register interrupt %d (%d)\n",
 493                        ppi, err);
 494                 goto out_free;
 495         }
 496
 497         err = register_cpu_notifier(&arch_timer_cpu_nb);
 498         if (err)
 499                 goto out_free_irq;
 500
 501         /* Immediately configure the timer on the boot CPU */
 502         arch_timer_setup(this_cpu_ptr(arch_timer_evt));
 503
 504         return 0;
 505
 506 out_free_irq:
 507         if (arch_timer_use_virtual)
 508                 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
 509         else {
 510                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
 511                                 arch_timer_evt);
 512                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 513                         free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
 514                                         arch_timer_evt);
 515         }
 516
 517 out_free:
 518         free_percpu(arch_timer_evt);
 519 out:
 520         return err;
 521 }
 522
 523 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
 524 {
 525         int ret;
 526         irq_handler_t func;
 527         struct arch_timer *t;
 528
 529         t = kzalloc(sizeof(*t), GFP_KERNEL);
 530         if (!t)
 531                 return -ENOMEM;
 532
 533         t->base = base;
 534         t->evt.irq = irq;
 535         __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
 536
 537         if (arch_timer_mem_use_virtual)
 538                 func = arch_timer_handler_virt_mem;
 539         else
 540                 func = arch_timer_handler_phys_mem;
 541
 542         ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
 543         if (ret) {
 544                 pr_err("arch_timer: Failed to request mem timer irq\n");
 545                 kfree(t);
 546         }
 547
 548         return ret;
 549 }
 550
 551 static const struct of_device_id arch_timer_of_match[] __initconst = {
 552         { .compatible   = "arm,armv7-timer",    },
 553         { .compatible   = "arm,armv8-timer",    },
 554         {},
 555 };
 556
 557 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
 558         { .compatible   = "arm,armv7-timer-mem", },
 559         {},
 560 };
 561
 562 static void __init arch_timer_common_init(void)
 563 {
 564         unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
 565
 566         /* Wait until both nodes are probed if we have two timers */
 567         if ((arch_timers_present & mask) != mask) {
 568                 if (of_find_matching_node(NULL, arch_timer_mem_of_match) &&
 569                                 !(arch_timers_present & ARCH_MEM_TIMER))
 570                         return;
 571                 if (of_find_matching_node(NULL, arch_timer_of_match) &&
 572                                 !(arch_timers_present & ARCH_CP15_TIMER))
 573                         return;
 574         }
 575
 576         arch_timer_banner(arch_timers_present);
 577         arch_counter_register(arch_timers_present);
 578         arch_timer_arch_init();
 579 }
 580
 581 static void __init arch_timer_init(struct device_node *np)
 582 {
 583         int i;
 584
 585         if (arch_timers_present & ARCH_CP15_TIMER) {
 586                 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
 587                 return;
 588         }
 589
 590         arch_timers_present |= ARCH_CP15_TIMER;
 591         for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
 592                 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
 593         arch_timer_detect_rate(NULL, np);
 594
 595         /*
 596          * If HYP mode is available, we know that the physical timer
 597          * has been configured to be accessible from PL1. Use it, so
 598          * that a guest can use the virtual timer instead.
 599          *
 600          * If no interrupt provided for virtual timer, we'll have to
 601          * stick to the physical timer. It'd better be accessible...
 602          */
 603         if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
 604                 arch_timer_use_virtual = false;
 605
 606                 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
 607                     !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
 608                         pr_warn("arch_timer: No interrupt available, giving up\n");
 609                         return;
 610                 }
 611         }
 612
 613         arch_timer_register();
 614         arch_timer_common_init();
 615 }
 616 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
 617 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
 618
 619 static void __init arch_timer_mem_init(struct device_node *np)
 620 {
 621         struct device_node *frame, *best_frame = NULL;
 622         void __iomem *cntctlbase, *base;
 623         unsigned int irq;
 624         u32 cnttidr;
 625
 626         arch_timers_present |= ARCH_MEM_TIMER;
 627         cntctlbase = of_iomap(np, 0);
 628         if (!cntctlbase) {
 629                 pr_err("arch_timer: Can't find CNTCTLBase\n");
 630                 return;
 631         }
 632
 633         cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
 634         iounmap(cntctlbase);
 635
 636         /*
 637          * Try to find a virtual capable frame. Otherwise fall back to a
 638          * physical capable frame.
 639          */
 640         for_each_available_child_of_node(np, frame) {
 641                 int n;
 642
 643                 if (of_property_read_u32(frame, "frame-number", &n)) {
 644                         pr_err("arch_timer: Missing frame-number\n");
 645                         of_node_put(best_frame);
 646                         of_node_put(frame);
 647                         return;
 648                 }
 649
 650                 if (cnttidr & CNTTIDR_VIRT(n)) {
 651                         of_node_put(best_frame);
 652                         best_frame = frame;
 653                         arch_timer_mem_use_virtual = true;
 654                         break;
 655                 }
 656                 of_node_put(best_frame);
 657                 best_frame = of_node_get(frame);
 658         }
 659
 660         base = arch_counter_base = of_iomap(best_frame, 0);
 661         if (!base) {
 662                 pr_err("arch_timer: Can't map frame's registers\n");
 663                 of_node_put(best_frame);
 664                 return;
 665         }
 666
 667         if (arch_timer_mem_use_virtual)
 668                 irq = irq_of_parse_and_map(best_frame, 1);
 669         else
 670                 irq = irq_of_parse_and_map(best_frame, 0);
 671         of_node_put(best_frame);
 672         if (!irq) {
 673                 pr_err("arch_timer: Frame missing %s irq",
 674                                 arch_timer_mem_use_virtual ? "virt" : "phys");
 675                 return;
 676         }
 677
 678         arch_timer_detect_rate(base, np);
 679         arch_timer_mem_register(base, irq);
 680         arch_timer_common_init();
 681 }
 682 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
 683                        arch_timer_mem_init);