1 /* linux/arch/arm/mach-exynos4/mct.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 MCT(Multi-Core Timer) support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpu.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/percpu.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/clocksource.h>
28 #define EXYNOS4_MCTREG(x) (x)
29 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
30 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
31 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
32 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
33 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
34 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
35 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
36 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
37 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
38 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
39 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
40 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
41 #define EXYNOS4_MCT_L_MASK (0xffffff00)
43 #define MCT_L_TCNTB_OFFSET (0x00)
44 #define MCT_L_ICNTB_OFFSET (0x08)
45 #define MCT_L_TCON_OFFSET (0x20)
46 #define MCT_L_INT_CSTAT_OFFSET (0x30)
47 #define MCT_L_INT_ENB_OFFSET (0x34)
48 #define MCT_L_WSTAT_OFFSET (0x40)
49 #define MCT_G_TCON_START (1 << 8)
50 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
51 #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
52 #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
53 #define MCT_L_TCON_INT_START (1 << 1)
54 #define MCT_L_TCON_TIMER_START (1 << 0)
56 #define TICK_BASE_CNT 1
79 static void __iomem
*reg_base
;
80 static unsigned long clk_rate
;
81 static unsigned int mct_int_type
;
82 static int mct_irqs
[MCT_NR_IRQS
];
84 struct mct_clock_event_device
{
85 struct clock_event_device evt
;
90 static void exynos4_mct_write(unsigned int value
, unsigned long offset
)
92 unsigned long stat_addr
;
96 __raw_writel(value
, reg_base
+ offset
);
98 if (likely(offset
>= EXYNOS4_MCT_L_BASE(0))) {
99 stat_addr
= (offset
& ~EXYNOS4_MCT_L_MASK
) + MCT_L_WSTAT_OFFSET
;
100 switch (offset
& EXYNOS4_MCT_L_MASK
) {
101 case MCT_L_TCON_OFFSET
:
102 mask
= 1 << 3; /* L_TCON write status */
104 case MCT_L_ICNTB_OFFSET
:
105 mask
= 1 << 1; /* L_ICNTB write status */
107 case MCT_L_TCNTB_OFFSET
:
108 mask
= 1 << 0; /* L_TCNTB write status */
115 case EXYNOS4_MCT_G_TCON
:
116 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
117 mask
= 1 << 16; /* G_TCON write status */
119 case EXYNOS4_MCT_G_COMP0_L
:
120 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
121 mask
= 1 << 0; /* G_COMP0_L write status */
123 case EXYNOS4_MCT_G_COMP0_U
:
124 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
125 mask
= 1 << 1; /* G_COMP0_U write status */
127 case EXYNOS4_MCT_G_COMP0_ADD_INCR
:
128 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
129 mask
= 1 << 2; /* G_COMP0_ADD_INCR w status */
131 case EXYNOS4_MCT_G_CNT_L
:
132 stat_addr
= EXYNOS4_MCT_G_CNT_WSTAT
;
133 mask
= 1 << 0; /* G_CNT_L write status */
135 case EXYNOS4_MCT_G_CNT_U
:
136 stat_addr
= EXYNOS4_MCT_G_CNT_WSTAT
;
137 mask
= 1 << 1; /* G_CNT_U write status */
144 /* Wait maximum 1 ms until written values are applied */
145 for (i
= 0; i
< loops_per_jiffy
/ 1000 * HZ
; i
++)
146 if (__raw_readl(reg_base
+ stat_addr
) & mask
) {
147 __raw_writel(mask
, reg_base
+ stat_addr
);
151 panic("MCT hangs after writing %d (offset:0x%lx)\n", value
, offset
);
154 /* Clocksource handling */
155 static void exynos4_mct_frc_start(u32 hi
, u32 lo
)
159 exynos4_mct_write(lo
, EXYNOS4_MCT_G_CNT_L
);
160 exynos4_mct_write(hi
, EXYNOS4_MCT_G_CNT_U
);
162 reg
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_TCON
);
163 reg
|= MCT_G_TCON_START
;
164 exynos4_mct_write(reg
, EXYNOS4_MCT_G_TCON
);
167 static cycle_t
exynos4_frc_read(struct clocksource
*cs
)
170 u32 hi2
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_CNT_U
);
174 lo
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_CNT_L
);
175 hi2
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_CNT_U
);
178 return ((cycle_t
)hi
<< 32) | lo
;
181 static void exynos4_frc_resume(struct clocksource
*cs
)
183 exynos4_mct_frc_start(0, 0);
186 struct clocksource mct_frc
= {
189 .read
= exynos4_frc_read
,
190 .mask
= CLOCKSOURCE_MASK(64),
191 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
192 .resume
= exynos4_frc_resume
,
195 static void __init
exynos4_clocksource_init(void)
197 exynos4_mct_frc_start(0, 0);
199 if (clocksource_register_hz(&mct_frc
, clk_rate
))
200 panic("%s: can't register clocksource\n", mct_frc
.name
);
203 static void exynos4_mct_comp0_stop(void)
207 tcon
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_TCON
);
208 tcon
&= ~(MCT_G_TCON_COMP0_ENABLE
| MCT_G_TCON_COMP0_AUTO_INC
);
210 exynos4_mct_write(tcon
, EXYNOS4_MCT_G_TCON
);
211 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB
);
214 static void exynos4_mct_comp0_start(enum clock_event_mode mode
,
215 unsigned long cycles
)
220 tcon
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_TCON
);
222 if (mode
== CLOCK_EVT_MODE_PERIODIC
) {
223 tcon
|= MCT_G_TCON_COMP0_AUTO_INC
;
224 exynos4_mct_write(cycles
, EXYNOS4_MCT_G_COMP0_ADD_INCR
);
227 comp_cycle
= exynos4_frc_read(&mct_frc
) + cycles
;
228 exynos4_mct_write((u32
)comp_cycle
, EXYNOS4_MCT_G_COMP0_L
);
229 exynos4_mct_write((u32
)(comp_cycle
>> 32), EXYNOS4_MCT_G_COMP0_U
);
231 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB
);
233 tcon
|= MCT_G_TCON_COMP0_ENABLE
;
234 exynos4_mct_write(tcon
, EXYNOS4_MCT_G_TCON
);
237 static int exynos4_comp_set_next_event(unsigned long cycles
,
238 struct clock_event_device
*evt
)
240 exynos4_mct_comp0_start(evt
->mode
, cycles
);
245 static void exynos4_comp_set_mode(enum clock_event_mode mode
,
246 struct clock_event_device
*evt
)
248 unsigned long cycles_per_jiffy
;
249 exynos4_mct_comp0_stop();
252 case CLOCK_EVT_MODE_PERIODIC
:
254 (((unsigned long long) NSEC_PER_SEC
/ HZ
* evt
->mult
) >> evt
->shift
);
255 exynos4_mct_comp0_start(mode
, cycles_per_jiffy
);
258 case CLOCK_EVT_MODE_ONESHOT
:
259 case CLOCK_EVT_MODE_UNUSED
:
260 case CLOCK_EVT_MODE_SHUTDOWN
:
261 case CLOCK_EVT_MODE_RESUME
:
266 static struct clock_event_device mct_comp_device
= {
268 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
270 .set_next_event
= exynos4_comp_set_next_event
,
271 .set_mode
= exynos4_comp_set_mode
,
274 static irqreturn_t
exynos4_mct_comp_isr(int irq
, void *dev_id
)
276 struct clock_event_device
*evt
= dev_id
;
278 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT
);
280 evt
->event_handler(evt
);
285 static struct irqaction mct_comp_event_irq
= {
286 .name
= "mct_comp_irq",
287 .flags
= IRQF_TIMER
| IRQF_IRQPOLL
,
288 .handler
= exynos4_mct_comp_isr
,
289 .dev_id
= &mct_comp_device
,
292 static void exynos4_clockevent_init(void)
294 mct_comp_device
.cpumask
= cpumask_of(0);
295 clockevents_config_and_register(&mct_comp_device
, clk_rate
,
297 setup_irq(mct_irqs
[MCT_G0_IRQ
], &mct_comp_event_irq
);
300 static DEFINE_PER_CPU(struct mct_clock_event_device
, percpu_mct_tick
);
302 /* Clock event handling */
303 static void exynos4_mct_tick_stop(struct mct_clock_event_device
*mevt
)
306 unsigned long mask
= MCT_L_TCON_INT_START
| MCT_L_TCON_TIMER_START
;
307 unsigned long offset
= mevt
->base
+ MCT_L_TCON_OFFSET
;
309 tmp
= __raw_readl(reg_base
+ offset
);
312 exynos4_mct_write(tmp
, offset
);
316 static void exynos4_mct_tick_start(unsigned long cycles
,
317 struct mct_clock_event_device
*mevt
)
321 exynos4_mct_tick_stop(mevt
);
323 tmp
= (1 << 31) | cycles
; /* MCT_L_UPDATE_ICNTB */
325 /* update interrupt count buffer */
326 exynos4_mct_write(tmp
, mevt
->base
+ MCT_L_ICNTB_OFFSET
);
328 /* enable MCT tick interrupt */
329 exynos4_mct_write(0x1, mevt
->base
+ MCT_L_INT_ENB_OFFSET
);
331 tmp
= __raw_readl(reg_base
+ mevt
->base
+ MCT_L_TCON_OFFSET
);
332 tmp
|= MCT_L_TCON_INT_START
| MCT_L_TCON_TIMER_START
|
333 MCT_L_TCON_INTERVAL_MODE
;
334 exynos4_mct_write(tmp
, mevt
->base
+ MCT_L_TCON_OFFSET
);
337 static int exynos4_tick_set_next_event(unsigned long cycles
,
338 struct clock_event_device
*evt
)
340 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
342 exynos4_mct_tick_start(cycles
, mevt
);
347 static inline void exynos4_tick_set_mode(enum clock_event_mode mode
,
348 struct clock_event_device
*evt
)
350 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
351 unsigned long cycles_per_jiffy
;
353 exynos4_mct_tick_stop(mevt
);
356 case CLOCK_EVT_MODE_PERIODIC
:
358 (((unsigned long long) NSEC_PER_SEC
/ HZ
* evt
->mult
) >> evt
->shift
);
359 exynos4_mct_tick_start(cycles_per_jiffy
, mevt
);
362 case CLOCK_EVT_MODE_ONESHOT
:
363 case CLOCK_EVT_MODE_UNUSED
:
364 case CLOCK_EVT_MODE_SHUTDOWN
:
365 case CLOCK_EVT_MODE_RESUME
:
370 static int exynos4_mct_tick_clear(struct mct_clock_event_device
*mevt
)
372 struct clock_event_device
*evt
= &mevt
->evt
;
375 * This is for supporting oneshot mode.
376 * Mct would generate interrupt periodically
377 * without explicit stopping.
379 if (evt
->mode
!= CLOCK_EVT_MODE_PERIODIC
)
380 exynos4_mct_tick_stop(mevt
);
382 /* Clear the MCT tick interrupt */
383 if (__raw_readl(reg_base
+ mevt
->base
+ MCT_L_INT_CSTAT_OFFSET
) & 1) {
384 exynos4_mct_write(0x1, mevt
->base
+ MCT_L_INT_CSTAT_OFFSET
);
391 static irqreturn_t
exynos4_mct_tick_isr(int irq
, void *dev_id
)
393 struct mct_clock_event_device
*mevt
= dev_id
;
394 struct clock_event_device
*evt
= &mevt
->evt
;
396 exynos4_mct_tick_clear(mevt
);
398 evt
->event_handler(evt
);
403 static int exynos4_local_timer_setup(struct clock_event_device
*evt
)
405 struct mct_clock_event_device
*mevt
;
406 unsigned int cpu
= smp_processor_id();
408 mevt
= container_of(evt
, struct mct_clock_event_device
, evt
);
410 mevt
->base
= EXYNOS4_MCT_L_BASE(cpu
);
411 snprintf(mevt
->name
, sizeof(mevt
->name
), "mct_tick%d", cpu
);
413 evt
->name
= mevt
->name
;
414 evt
->cpumask
= cpumask_of(cpu
);
415 evt
->set_next_event
= exynos4_tick_set_next_event
;
416 evt
->set_mode
= exynos4_tick_set_mode
;
417 evt
->features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
;
420 exynos4_mct_write(TICK_BASE_CNT
, mevt
->base
+ MCT_L_TCNTB_OFFSET
);
422 if (mct_int_type
== MCT_INT_SPI
) {
423 evt
->irq
= mct_irqs
[MCT_L0_IRQ
+ cpu
];
424 if (request_irq(evt
->irq
, exynos4_mct_tick_isr
,
425 IRQF_TIMER
| IRQF_NOBALANCING
,
427 pr_err("exynos-mct: cannot register IRQ %d\n",
431 irq_force_affinity(mct_irqs
[MCT_L0_IRQ
+ cpu
], cpumask_of(cpu
));
433 enable_percpu_irq(mct_irqs
[MCT_L0_IRQ
], 0);
435 clockevents_config_and_register(evt
, clk_rate
/ (TICK_BASE_CNT
+ 1),
441 static void exynos4_local_timer_stop(struct clock_event_device
*evt
)
443 evt
->set_mode(CLOCK_EVT_MODE_UNUSED
, evt
);
444 if (mct_int_type
== MCT_INT_SPI
)
445 free_irq(evt
->irq
, this_cpu_ptr(&percpu_mct_tick
));
447 disable_percpu_irq(mct_irqs
[MCT_L0_IRQ
]);
450 static int exynos4_mct_cpu_notify(struct notifier_block
*self
,
451 unsigned long action
, void *hcpu
)
453 struct mct_clock_event_device
*mevt
;
456 * Grab cpu pointer in each case to avoid spurious
457 * preemptible warnings
459 switch (action
& ~CPU_TASKS_FROZEN
) {
461 mevt
= this_cpu_ptr(&percpu_mct_tick
);
462 exynos4_local_timer_setup(&mevt
->evt
);
465 mevt
= this_cpu_ptr(&percpu_mct_tick
);
466 exynos4_local_timer_stop(&mevt
->evt
);
473 static struct notifier_block exynos4_mct_cpu_nb
= {
474 .notifier_call
= exynos4_mct_cpu_notify
,
477 static void __init
exynos4_timer_resources(struct device_node
*np
, void __iomem
*base
)
480 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
481 struct clk
*mct_clk
, *tick_clk
;
483 tick_clk
= np
? of_clk_get_by_name(np
, "fin_pll") :
484 clk_get(NULL
, "fin_pll");
485 if (IS_ERR(tick_clk
))
486 panic("%s: unable to determine tick clock rate\n", __func__
);
487 clk_rate
= clk_get_rate(tick_clk
);
489 mct_clk
= np
? of_clk_get_by_name(np
, "mct") : clk_get(NULL
, "mct");
491 panic("%s: unable to retrieve mct clock instance\n", __func__
);
492 clk_prepare_enable(mct_clk
);
496 panic("%s: unable to ioremap mct address space\n", __func__
);
498 if (mct_int_type
== MCT_INT_PPI
) {
500 err
= request_percpu_irq(mct_irqs
[MCT_L0_IRQ
],
501 exynos4_mct_tick_isr
, "MCT",
503 WARN(err
, "MCT: can't request IRQ %d (%d)\n",
504 mct_irqs
[MCT_L0_IRQ
], err
);
506 irq_set_affinity(mct_irqs
[MCT_L0_IRQ
], cpumask_of(0));
509 err
= register_cpu_notifier(&exynos4_mct_cpu_nb
);
513 /* Immediately configure the timer on the boot CPU */
514 exynos4_local_timer_setup(&mevt
->evt
);
518 free_percpu_irq(mct_irqs
[MCT_L0_IRQ
], &percpu_mct_tick
);
521 void __init
mct_init(void __iomem
*base
, int irq_g0
, int irq_l0
, int irq_l1
)
523 mct_irqs
[MCT_G0_IRQ
] = irq_g0
;
524 mct_irqs
[MCT_L0_IRQ
] = irq_l0
;
525 mct_irqs
[MCT_L1_IRQ
] = irq_l1
;
526 mct_int_type
= MCT_INT_SPI
;
528 exynos4_timer_resources(NULL
, base
);
529 exynos4_clocksource_init();
530 exynos4_clockevent_init();
533 static void __init
mct_init_dt(struct device_node
*np
, unsigned int int_type
)
537 mct_int_type
= int_type
;
539 /* This driver uses only one global timer interrupt */
540 mct_irqs
[MCT_G0_IRQ
] = irq_of_parse_and_map(np
, MCT_G0_IRQ
);
543 * Find out the number of local irqs specified. The local
544 * timer irqs are specified after the four global timer
545 * irqs are specified.
548 nr_irqs
= of_irq_count(np
);
552 for (i
= MCT_L0_IRQ
; i
< nr_irqs
; i
++)
553 mct_irqs
[i
] = irq_of_parse_and_map(np
, i
);
555 exynos4_timer_resources(np
, of_iomap(np
, 0));
556 exynos4_clocksource_init();
557 exynos4_clockevent_init();
561 static void __init
mct_init_spi(struct device_node
*np
)
563 return mct_init_dt(np
, MCT_INT_SPI
);
566 static void __init
mct_init_ppi(struct device_node
*np
)
568 return mct_init_dt(np
, MCT_INT_PPI
);
570 CLOCKSOURCE_OF_DECLARE(exynos4210
, "samsung,exynos4210-mct", mct_init_spi
);
571 CLOCKSOURCE_OF_DECLARE(exynos4412
, "samsung,exynos4412-mct", mct_init_ppi
);