drivers/clocksource/h8300_timer16.c

   1 /*
   2  *  H8/300 16bit Timer driver
   3  *
   4  *  Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
   5  */
   6
   7 #include <linux/interrupt.h>
   8 #include <linux/init.h>
   9 #include <linux/clocksource.h>
  10 #include <linux/clk.h>
  11 #include <linux/io.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15
  16 #define TSTR    0
  17 #define TISRC   6
  18
  19 #define TCR     0
  20 #define TCNT    2
  21
  22 struct timer16_priv {
  23         struct clocksource cs;
  24         unsigned long total_cycles;
  25         void __iomem *mapbase;
  26         void __iomem *mapcommon;
  27         unsigned short cs_enabled;
  28         unsigned char enb;
  29         unsigned char ovf;
  30         unsigned char ovie;
  31         struct clk *clk;
  32 };
  33
  34 static unsigned long timer16_get_counter(struct timer16_priv *p)
  35 {
  36         unsigned long v1, v2, v3;
  37         int o1, o2;
  38
  39         o1 = readb(p->mapcommon + TISRC) & p->ovf;
  40
  41         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
  42         do {
  43                 o2 = o1;
  44                 v1 = readw(p->mapbase + TCNT);
  45                 v2 = readw(p->mapbase + TCNT);
  46                 v3 = readw(p->mapbase + TCNT);
  47                 o1 = readb(p->mapcommon + TISRC) & p->ovf;
  48         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
  49                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
  50
  51         v2 |= 0x10000;
  52         return v2;
  53 }
  54
  55
  56 static irqreturn_t timer16_interrupt(int irq, void *dev_id)
  57 {
  58         struct timer16_priv *p = (struct timer16_priv *)dev_id;
  59
  60         writeb(readb(p->mapcommon + TISRC) & ~p->ovf,
  61                   p->mapcommon + TISRC);
  62         p->total_cycles += 0x10000;
  63
  64         return IRQ_HANDLED;
  65 }
  66
  67 static inline struct timer16_priv *cs_to_priv(struct clocksource *cs)
  68 {
  69         return container_of(cs, struct timer16_priv, cs);
  70 }
  71
  72 static cycle_t timer16_clocksource_read(struct clocksource *cs)
  73 {
  74         struct timer16_priv *p = cs_to_priv(cs);
  75         unsigned long raw, value;
  76
  77         value = p->total_cycles;
  78         raw = timer16_get_counter(p);
  79
  80         return value + raw;
  81 }
  82
  83 static int timer16_enable(struct clocksource *cs)
  84 {
  85         struct timer16_priv *p = cs_to_priv(cs);
  86
  87         WARN_ON(p->cs_enabled);
  88
  89         p->total_cycles = 0;
  90         writew(0x0000, p->mapbase + TCNT);
  91         writeb(0x83, p->mapbase + TCR);
  92         writeb(readb(p->mapcommon + TSTR) | p->enb,
  93                   p->mapcommon + TSTR);
  94         writeb(readb(p->mapcommon + TISRC) | p->ovie,
  95                   p->mapcommon + TSTR);
  96
  97         p->cs_enabled = true;
  98         return 0;
  99 }
 100
 101 static void timer16_disable(struct clocksource *cs)
 102 {
 103         struct timer16_priv *p = cs_to_priv(cs);
 104
 105         WARN_ON(!p->cs_enabled);
 106
 107         writeb(readb(p->mapcommon + TSTR) & ~p->enb,
 108                   p->mapcommon + TSTR);
 109
 110         p->cs_enabled = false;
 111 }
 112
 113 static struct timer16_priv timer16_priv = {
 114         .cs = {
 115                 .name = "h8300_16timer",
 116                 .rating = 200,
 117                 .read = timer16_clocksource_read,
 118                 .enable = timer16_enable,
 119                 .disable = timer16_disable,
 120                 .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
 121                 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 122         },
 123 };
 124
 125 #define REG_CH   0
 126 #define REG_COMM 1
 127
 128 static void __init h8300_16timer_init(struct device_node *node)
 129 {
 130         void __iomem *base[2];
 131         int ret, irq;
 132         unsigned int ch;
 133         struct clk *clk;
 134
 135         clk = of_clk_get(node, 0);
 136         if (IS_ERR(clk)) {
 137                 pr_err("failed to get clock for clocksource\n");
 138                 return;
 139         }
 140
 141         base[REG_CH] = of_iomap(node, 0);
 142         if (!base[REG_CH]) {
 143                 pr_err("failed to map registers for clocksource\n");
 144                 goto free_clk;
 145         }
 146
 147         base[REG_COMM] = of_iomap(node, 1);
 148         if (!base[REG_COMM]) {
 149                 pr_err("failed to map registers for clocksource\n");
 150                 goto unmap_ch;
 151         }
 152
 153         irq = irq_of_parse_and_map(node, 0);
 154         if (!irq) {
 155                 pr_err("failed to get irq for clockevent\n");
 156                 goto unmap_comm;
 157         }
 158
 159         of_property_read_u32(node, "renesas,channel", &ch);
 160
 161         timer16_priv.mapbase = base[REG_CH];
 162         timer16_priv.mapcommon = base[REG_COMM];
 163         timer16_priv.enb = 1 << ch;
 164         timer16_priv.ovf = 1 << ch;
 165         timer16_priv.ovie = 1 << (4 + ch);
 166
 167         ret = request_irq(irq, timer16_interrupt,
 168                           IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
 169         if (ret < 0) {
 170                 pr_err("failed to request irq %d of clocksource\n", irq);
 171                 goto unmap_comm;
 172         }
 173
 174         clocksource_register_hz(&timer16_priv.cs,
 175                                 clk_get_rate(timer16_priv.clk) / 8);
 176         return;
 177
 178 unmap_comm:
 179         iounmap(base[REG_COMM]);
 180 unmap_ch:
 181         iounmap(base[REG_CH]);
 182 free_clk:
 183         clk_put(clk);
 184 }
 185
 186 CLOCKSOURCE_OF_DECLARE(h8300_16bit, "renesas,16bit-timer", h8300_16timer_init);