drivers/clocksource/moxart_timer.c

   1 /*
   2  * MOXA ART SoCs timer handling.
   3  *
   4  * Copyright (C) 2013 Jonas Jensen
   5  *
   6  * Jonas Jensen <jonas.jensen@gmail.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqreturn.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/io.h>
  22 #include <linux/clocksource.h>
  23
  24 #define TIMER1_BASE             0x00
  25 #define TIMER2_BASE             0x10
  26 #define TIMER3_BASE             0x20
  27
  28 #define REG_COUNT               0x0 /* writable */
  29 #define REG_LOAD                0x4
  30 #define REG_MATCH1              0x8
  31 #define REG_MATCH2              0xC
  32
  33 #define TIMER_CR                0x30
  34 #define TIMER_INTR_STATE        0x34
  35 #define TIMER_INTR_MASK         0x38
  36
  37 /*
  38  * TIMER_CR flags:
  39  *
  40  * TIMEREG_CR_*_CLOCK   0: PCLK, 1: EXT1CLK
  41  * TIMEREG_CR_*_INT     overflow interrupt enable bit
  42  */
  43 #define TIMEREG_CR_1_ENABLE     BIT(0)
  44 #define TIMEREG_CR_1_CLOCK      BIT(1)
  45 #define TIMEREG_CR_1_INT        BIT(2)
  46 #define TIMEREG_CR_2_ENABLE     BIT(3)
  47 #define TIMEREG_CR_2_CLOCK      BIT(4)
  48 #define TIMEREG_CR_2_INT        BIT(5)
  49 #define TIMEREG_CR_3_ENABLE     BIT(6)
  50 #define TIMEREG_CR_3_CLOCK      BIT(7)
  51 #define TIMEREG_CR_3_INT        BIT(8)
  52 #define TIMEREG_CR_COUNT_UP     BIT(9)
  53
  54 #define TIMER1_ENABLE           (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE)
  55 #define TIMER1_DISABLE          (TIMEREG_CR_2_ENABLE)
  56
  57 static void __iomem *base;
  58 static unsigned int clock_count_per_tick;
  59
  60 static void moxart_clkevt_mode(enum clock_event_mode mode,
  61                                struct clock_event_device *clk)
  62 {
  63         switch (mode) {
  64         case CLOCK_EVT_MODE_RESUME:
  65         case CLOCK_EVT_MODE_ONESHOT:
  66                 writel(TIMER1_DISABLE, base + TIMER_CR);
  67                 writel(~0, base + TIMER1_BASE + REG_LOAD);
  68                 break;
  69         case CLOCK_EVT_MODE_PERIODIC:
  70                 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
  71                 writel(TIMER1_ENABLE, base + TIMER_CR);
  72                 break;
  73         case CLOCK_EVT_MODE_UNUSED:
  74         case CLOCK_EVT_MODE_SHUTDOWN:
  75         default:
  76                 writel(TIMER1_DISABLE, base + TIMER_CR);
  77                 break;
  78         }
  79 }
  80
  81 static int moxart_clkevt_next_event(unsigned long cycles,
  82                                     struct clock_event_device *unused)
  83 {
  84         u32 u;
  85
  86         writel(TIMER1_DISABLE, base + TIMER_CR);
  87
  88         u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
  89         writel(u, base + TIMER1_BASE + REG_MATCH1);
  90
  91         writel(TIMER1_ENABLE, base + TIMER_CR);
  92
  93         return 0;
  94 }
  95
  96 static struct clock_event_device moxart_clockevent = {
  97         .name           = "moxart_timer",
  98         .rating         = 200,
  99         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 100         .set_mode       = moxart_clkevt_mode,
 101         .set_next_event = moxart_clkevt_next_event,
 102 };
 103
 104 static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
 105 {
 106         struct clock_event_device *evt = dev_id;
 107         evt->event_handler(evt);
 108         return IRQ_HANDLED;
 109 }
 110
 111 static struct irqaction moxart_timer_irq = {
 112         .name           = "moxart-timer",
 113         .flags          = IRQF_TIMER,
 114         .handler        = moxart_timer_interrupt,
 115         .dev_id         = &moxart_clockevent,
 116 };
 117
 118 static void __init moxart_timer_init(struct device_node *node)
 119 {
 120         int ret, irq;
 121         unsigned long pclk;
 122         struct clk *clk;
 123
 124         base = of_iomap(node, 0);
 125         if (!base)
 126                 panic("%s: of_iomap failed\n", node->full_name);
 127
 128         irq = irq_of_parse_and_map(node, 0);
 129         if (irq <= 0)
 130                 panic("%s: irq_of_parse_and_map failed\n", node->full_name);
 131
 132         ret = setup_irq(irq, &moxart_timer_irq);
 133         if (ret)
 134                 panic("%s: setup_irq failed\n", node->full_name);
 135
 136         clk = of_clk_get(node, 0);
 137         if (IS_ERR(clk))
 138                 panic("%s: of_clk_get failed\n", node->full_name);
 139
 140         pclk = clk_get_rate(clk);
 141
 142         if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT,
 143                                   "moxart_timer", pclk, 200, 32,
 144                                   clocksource_mmio_readl_down))
 145                 panic("%s: clocksource_mmio_init failed\n", node->full_name);
 146
 147         clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
 148
 149         writel(~0, base + TIMER2_BASE + REG_LOAD);
 150         writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR);
 151
 152         moxart_clockevent.cpumask = cpumask_of(0);
 153         moxart_clockevent.irq = irq;
 154
 155         /*
 156          * documentation is not publicly available:
 157          * min_delta / max_delta obtained by trial-and-error,
 158          * max_delta 0xfffffffe should be ok because count
 159          * register size is u32
 160          */
 161         clockevents_config_and_register(&moxart_clockevent, pclk,
 162                                         0x4, 0xfffffffe);
 163 }
 164 CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);