2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
26 #include <linux/clk.h>
27 #include <linux/irq.h>
28 #include <linux/err.h>
29 #include <linux/delay.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/pm_domain.h>
36 #include <linux/pm_runtime.h>
40 struct sh_cmt_channel
{
41 struct sh_cmt_device
*cmt
;
47 unsigned long match_value
;
48 unsigned long next_match_value
;
49 unsigned long max_match_value
;
52 struct clock_event_device ced
;
53 struct clocksource cs
;
54 unsigned long total_cycles
;
58 struct sh_cmt_device
{
59 struct platform_device
*pdev
;
61 void __iomem
*mapbase_ch
;
62 void __iomem
*mapbase
;
65 struct sh_cmt_channel
*channels
;
66 unsigned int num_channels
;
68 unsigned long width
; /* 16 or 32 bit version of hardware block */
69 unsigned long overflow_bit
;
70 unsigned long clear_bits
;
72 /* callbacks for CMSTR and CMCSR access */
73 unsigned long (*read_control
)(void __iomem
*base
, unsigned long offs
);
74 void (*write_control
)(void __iomem
*base
, unsigned long offs
,
77 /* callbacks for CMCNT and CMCOR access */
78 unsigned long (*read_count
)(void __iomem
*base
, unsigned long offs
);
79 void (*write_count
)(void __iomem
*base
, unsigned long offs
,
83 /* Examples of supported CMT timer register layouts and I/O access widths:
85 * "16-bit counter and 16-bit control" as found on sh7263:
86 * CMSTR 0xfffec000 16-bit
87 * CMCSR 0xfffec002 16-bit
88 * CMCNT 0xfffec004 16-bit
89 * CMCOR 0xfffec006 16-bit
91 * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
92 * CMSTR 0xffca0000 16-bit
93 * CMCSR 0xffca0060 16-bit
94 * CMCNT 0xffca0064 32-bit
95 * CMCOR 0xffca0068 32-bit
97 * "32-bit counter and 32-bit control" as found on r8a73a4 and r8a7790:
98 * CMSTR 0xffca0500 32-bit
99 * CMCSR 0xffca0510 32-bit
100 * CMCNT 0xffca0514 32-bit
101 * CMCOR 0xffca0518 32-bit
104 static unsigned long sh_cmt_read16(void __iomem
*base
, unsigned long offs
)
106 return ioread16(base
+ (offs
<< 1));
109 static unsigned long sh_cmt_read32(void __iomem
*base
, unsigned long offs
)
111 return ioread32(base
+ (offs
<< 2));
114 static void sh_cmt_write16(void __iomem
*base
, unsigned long offs
,
117 iowrite16(value
, base
+ (offs
<< 1));
120 static void sh_cmt_write32(void __iomem
*base
, unsigned long offs
,
123 iowrite32(value
, base
+ (offs
<< 2));
126 #define CMCSR 0 /* channel register */
127 #define CMCNT 1 /* channel register */
128 #define CMCOR 2 /* channel register */
130 static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel
*ch
)
132 return ch
->cmt
->read_control(ch
->cmt
->mapbase
, 0);
135 static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel
*ch
)
137 return ch
->cmt
->read_control(ch
->base
, CMCSR
);
140 static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel
*ch
)
142 return ch
->cmt
->read_count(ch
->base
, CMCNT
);
145 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel
*ch
,
148 ch
->cmt
->write_control(ch
->cmt
->mapbase
, 0, value
);
151 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel
*ch
,
154 ch
->cmt
->write_control(ch
->base
, CMCSR
, value
);
157 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel
*ch
,
160 ch
->cmt
->write_count(ch
->base
, CMCNT
, value
);
163 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel
*ch
,
166 ch
->cmt
->write_count(ch
->base
, CMCOR
, value
);
169 static unsigned long sh_cmt_get_counter(struct sh_cmt_channel
*ch
,
172 unsigned long v1
, v2
, v3
;
175 o1
= sh_cmt_read_cmcsr(ch
) & ch
->cmt
->overflow_bit
;
177 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
180 v1
= sh_cmt_read_cmcnt(ch
);
181 v2
= sh_cmt_read_cmcnt(ch
);
182 v3
= sh_cmt_read_cmcnt(ch
);
183 o1
= sh_cmt_read_cmcsr(ch
) & ch
->cmt
->overflow_bit
;
184 } while (unlikely((o1
!= o2
) || (v1
> v2
&& v1
< v3
)
185 || (v2
> v3
&& v2
< v1
) || (v3
> v1
&& v3
< v2
)));
191 static DEFINE_RAW_SPINLOCK(sh_cmt_lock
);
193 static void sh_cmt_start_stop_ch(struct sh_cmt_channel
*ch
, int start
)
195 struct sh_timer_config
*cfg
= ch
->cmt
->pdev
->dev
.platform_data
;
196 unsigned long flags
, value
;
198 /* start stop register shared by multiple timer channels */
199 raw_spin_lock_irqsave(&sh_cmt_lock
, flags
);
200 value
= sh_cmt_read_cmstr(ch
);
203 value
|= 1 << cfg
->timer_bit
;
205 value
&= ~(1 << cfg
->timer_bit
);
207 sh_cmt_write_cmstr(ch
, value
);
208 raw_spin_unlock_irqrestore(&sh_cmt_lock
, flags
);
211 static int sh_cmt_enable(struct sh_cmt_channel
*ch
, unsigned long *rate
)
215 pm_runtime_get_sync(&ch
->cmt
->pdev
->dev
);
216 dev_pm_syscore_device(&ch
->cmt
->pdev
->dev
, true);
219 ret
= clk_enable(ch
->cmt
->clk
);
221 dev_err(&ch
->cmt
->pdev
->dev
, "ch%u: cannot enable clock\n",
226 /* make sure channel is disabled */
227 sh_cmt_start_stop_ch(ch
, 0);
229 /* configure channel, periodic mode and maximum timeout */
230 if (ch
->cmt
->width
== 16) {
231 *rate
= clk_get_rate(ch
->cmt
->clk
) / 512;
232 sh_cmt_write_cmcsr(ch
, 0x43);
234 *rate
= clk_get_rate(ch
->cmt
->clk
) / 8;
235 sh_cmt_write_cmcsr(ch
, 0x01a4);
238 sh_cmt_write_cmcor(ch
, 0xffffffff);
239 sh_cmt_write_cmcnt(ch
, 0);
242 * According to the sh73a0 user's manual, as CMCNT can be operated
243 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
244 * modifying CMCNT register; two RCLK cycles are necessary before
245 * this register is either read or any modification of the value
246 * it holds is reflected in the LSI's actual operation.
248 * While at it, we're supposed to clear out the CMCNT as of this
249 * moment, so make sure it's processed properly here. This will
250 * take RCLKx2 at maximum.
252 for (k
= 0; k
< 100; k
++) {
253 if (!sh_cmt_read_cmcnt(ch
))
258 if (sh_cmt_read_cmcnt(ch
)) {
259 dev_err(&ch
->cmt
->pdev
->dev
, "ch%u: cannot clear CMCNT\n",
266 sh_cmt_start_stop_ch(ch
, 1);
270 clk_disable(ch
->cmt
->clk
);
276 static void sh_cmt_disable(struct sh_cmt_channel
*ch
)
278 /* disable channel */
279 sh_cmt_start_stop_ch(ch
, 0);
281 /* disable interrupts in CMT block */
282 sh_cmt_write_cmcsr(ch
, 0);
285 clk_disable(ch
->cmt
->clk
);
287 dev_pm_syscore_device(&ch
->cmt
->pdev
->dev
, false);
288 pm_runtime_put(&ch
->cmt
->pdev
->dev
);
292 #define FLAG_CLOCKEVENT (1 << 0)
293 #define FLAG_CLOCKSOURCE (1 << 1)
294 #define FLAG_REPROGRAM (1 << 2)
295 #define FLAG_SKIPEVENT (1 << 3)
296 #define FLAG_IRQCONTEXT (1 << 4)
298 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel
*ch
,
301 unsigned long new_match
;
302 unsigned long value
= ch
->next_match_value
;
303 unsigned long delay
= 0;
304 unsigned long now
= 0;
307 now
= sh_cmt_get_counter(ch
, &has_wrapped
);
308 ch
->flags
|= FLAG_REPROGRAM
; /* force reprogram */
311 /* we're competing with the interrupt handler.
312 * -> let the interrupt handler reprogram the timer.
313 * -> interrupt number two handles the event.
315 ch
->flags
|= FLAG_SKIPEVENT
;
323 /* reprogram the timer hardware,
324 * but don't save the new match value yet.
326 new_match
= now
+ value
+ delay
;
327 if (new_match
> ch
->max_match_value
)
328 new_match
= ch
->max_match_value
;
330 sh_cmt_write_cmcor(ch
, new_match
);
332 now
= sh_cmt_get_counter(ch
, &has_wrapped
);
333 if (has_wrapped
&& (new_match
> ch
->match_value
)) {
334 /* we are changing to a greater match value,
335 * so this wrap must be caused by the counter
336 * matching the old value.
337 * -> first interrupt reprograms the timer.
338 * -> interrupt number two handles the event.
340 ch
->flags
|= FLAG_SKIPEVENT
;
345 /* we are changing to a smaller match value,
346 * so the wrap must be caused by the counter
347 * matching the new value.
348 * -> save programmed match value.
349 * -> let isr handle the event.
351 ch
->match_value
= new_match
;
355 /* be safe: verify hardware settings */
356 if (now
< new_match
) {
357 /* timer value is below match value, all good.
358 * this makes sure we won't miss any match events.
359 * -> save programmed match value.
360 * -> let isr handle the event.
362 ch
->match_value
= new_match
;
366 /* the counter has reached a value greater
367 * than our new match value. and since the
368 * has_wrapped flag isn't set we must have
369 * programmed a too close event.
370 * -> increase delay and retry.
378 dev_warn(&ch
->cmt
->pdev
->dev
, "ch%u: too long delay\n",
384 static void __sh_cmt_set_next(struct sh_cmt_channel
*ch
, unsigned long delta
)
386 if (delta
> ch
->max_match_value
)
387 dev_warn(&ch
->cmt
->pdev
->dev
, "ch%u: delta out of range\n",
390 ch
->next_match_value
= delta
;
391 sh_cmt_clock_event_program_verify(ch
, 0);
394 static void sh_cmt_set_next(struct sh_cmt_channel
*ch
, unsigned long delta
)
398 raw_spin_lock_irqsave(&ch
->lock
, flags
);
399 __sh_cmt_set_next(ch
, delta
);
400 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
403 static irqreturn_t
sh_cmt_interrupt(int irq
, void *dev_id
)
405 struct sh_cmt_channel
*ch
= dev_id
;
408 sh_cmt_write_cmcsr(ch
, sh_cmt_read_cmcsr(ch
) & ch
->cmt
->clear_bits
);
410 /* update clock source counter to begin with if enabled
411 * the wrap flag should be cleared by the timer specific
412 * isr before we end up here.
414 if (ch
->flags
& FLAG_CLOCKSOURCE
)
415 ch
->total_cycles
+= ch
->match_value
+ 1;
417 if (!(ch
->flags
& FLAG_REPROGRAM
))
418 ch
->next_match_value
= ch
->max_match_value
;
420 ch
->flags
|= FLAG_IRQCONTEXT
;
422 if (ch
->flags
& FLAG_CLOCKEVENT
) {
423 if (!(ch
->flags
& FLAG_SKIPEVENT
)) {
424 if (ch
->ced
.mode
== CLOCK_EVT_MODE_ONESHOT
) {
425 ch
->next_match_value
= ch
->max_match_value
;
426 ch
->flags
|= FLAG_REPROGRAM
;
429 ch
->ced
.event_handler(&ch
->ced
);
433 ch
->flags
&= ~FLAG_SKIPEVENT
;
435 if (ch
->flags
& FLAG_REPROGRAM
) {
436 ch
->flags
&= ~FLAG_REPROGRAM
;
437 sh_cmt_clock_event_program_verify(ch
, 1);
439 if (ch
->flags
& FLAG_CLOCKEVENT
)
440 if ((ch
->ced
.mode
== CLOCK_EVT_MODE_SHUTDOWN
)
441 || (ch
->match_value
== ch
->next_match_value
))
442 ch
->flags
&= ~FLAG_REPROGRAM
;
445 ch
->flags
&= ~FLAG_IRQCONTEXT
;
450 static int sh_cmt_start(struct sh_cmt_channel
*ch
, unsigned long flag
)
455 raw_spin_lock_irqsave(&ch
->lock
, flags
);
457 if (!(ch
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
458 ret
= sh_cmt_enable(ch
, &ch
->rate
);
464 /* setup timeout if no clockevent */
465 if ((flag
== FLAG_CLOCKSOURCE
) && (!(ch
->flags
& FLAG_CLOCKEVENT
)))
466 __sh_cmt_set_next(ch
, ch
->max_match_value
);
468 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
473 static void sh_cmt_stop(struct sh_cmt_channel
*ch
, unsigned long flag
)
478 raw_spin_lock_irqsave(&ch
->lock
, flags
);
480 f
= ch
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
);
483 if (f
&& !(ch
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
486 /* adjust the timeout to maximum if only clocksource left */
487 if ((flag
== FLAG_CLOCKEVENT
) && (ch
->flags
& FLAG_CLOCKSOURCE
))
488 __sh_cmt_set_next(ch
, ch
->max_match_value
);
490 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
493 static struct sh_cmt_channel
*cs_to_sh_cmt(struct clocksource
*cs
)
495 return container_of(cs
, struct sh_cmt_channel
, cs
);
498 static cycle_t
sh_cmt_clocksource_read(struct clocksource
*cs
)
500 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
501 unsigned long flags
, raw
;
505 raw_spin_lock_irqsave(&ch
->lock
, flags
);
506 value
= ch
->total_cycles
;
507 raw
= sh_cmt_get_counter(ch
, &has_wrapped
);
509 if (unlikely(has_wrapped
))
510 raw
+= ch
->match_value
+ 1;
511 raw_spin_unlock_irqrestore(&ch
->lock
, flags
);
516 static int sh_cmt_clocksource_enable(struct clocksource
*cs
)
519 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
521 WARN_ON(ch
->cs_enabled
);
523 ch
->total_cycles
= 0;
525 ret
= sh_cmt_start(ch
, FLAG_CLOCKSOURCE
);
527 __clocksource_updatefreq_hz(cs
, ch
->rate
);
528 ch
->cs_enabled
= true;
533 static void sh_cmt_clocksource_disable(struct clocksource
*cs
)
535 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
537 WARN_ON(!ch
->cs_enabled
);
539 sh_cmt_stop(ch
, FLAG_CLOCKSOURCE
);
540 ch
->cs_enabled
= false;
543 static void sh_cmt_clocksource_suspend(struct clocksource
*cs
)
545 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
547 sh_cmt_stop(ch
, FLAG_CLOCKSOURCE
);
548 pm_genpd_syscore_poweroff(&ch
->cmt
->pdev
->dev
);
551 static void sh_cmt_clocksource_resume(struct clocksource
*cs
)
553 struct sh_cmt_channel
*ch
= cs_to_sh_cmt(cs
);
555 pm_genpd_syscore_poweron(&ch
->cmt
->pdev
->dev
);
556 sh_cmt_start(ch
, FLAG_CLOCKSOURCE
);
559 static int sh_cmt_register_clocksource(struct sh_cmt_channel
*ch
,
560 const char *name
, unsigned long rating
)
562 struct clocksource
*cs
= &ch
->cs
;
566 cs
->read
= sh_cmt_clocksource_read
;
567 cs
->enable
= sh_cmt_clocksource_enable
;
568 cs
->disable
= sh_cmt_clocksource_disable
;
569 cs
->suspend
= sh_cmt_clocksource_suspend
;
570 cs
->resume
= sh_cmt_clocksource_resume
;
571 cs
->mask
= CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
572 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
574 dev_info(&ch
->cmt
->pdev
->dev
, "ch%u: used as clock source\n",
577 /* Register with dummy 1 Hz value, gets updated in ->enable() */
578 clocksource_register_hz(cs
, 1);
582 static struct sh_cmt_channel
*ced_to_sh_cmt(struct clock_event_device
*ced
)
584 return container_of(ced
, struct sh_cmt_channel
, ced
);
587 static void sh_cmt_clock_event_start(struct sh_cmt_channel
*ch
, int periodic
)
589 struct clock_event_device
*ced
= &ch
->ced
;
591 sh_cmt_start(ch
, FLAG_CLOCKEVENT
);
593 /* TODO: calculate good shift from rate and counter bit width */
596 ced
->mult
= div_sc(ch
->rate
, NSEC_PER_SEC
, ced
->shift
);
597 ced
->max_delta_ns
= clockevent_delta2ns(ch
->max_match_value
, ced
);
598 ced
->min_delta_ns
= clockevent_delta2ns(0x1f, ced
);
601 sh_cmt_set_next(ch
, ((ch
->rate
+ HZ
/2) / HZ
) - 1);
603 sh_cmt_set_next(ch
, ch
->max_match_value
);
606 static void sh_cmt_clock_event_mode(enum clock_event_mode mode
,
607 struct clock_event_device
*ced
)
609 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
611 /* deal with old setting first */
613 case CLOCK_EVT_MODE_PERIODIC
:
614 case CLOCK_EVT_MODE_ONESHOT
:
615 sh_cmt_stop(ch
, FLAG_CLOCKEVENT
);
622 case CLOCK_EVT_MODE_PERIODIC
:
623 dev_info(&ch
->cmt
->pdev
->dev
,
624 "ch%u: used for periodic clock events\n", ch
->index
);
625 sh_cmt_clock_event_start(ch
, 1);
627 case CLOCK_EVT_MODE_ONESHOT
:
628 dev_info(&ch
->cmt
->pdev
->dev
,
629 "ch%u: used for oneshot clock events\n", ch
->index
);
630 sh_cmt_clock_event_start(ch
, 0);
632 case CLOCK_EVT_MODE_SHUTDOWN
:
633 case CLOCK_EVT_MODE_UNUSED
:
634 sh_cmt_stop(ch
, FLAG_CLOCKEVENT
);
641 static int sh_cmt_clock_event_next(unsigned long delta
,
642 struct clock_event_device
*ced
)
644 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
646 BUG_ON(ced
->mode
!= CLOCK_EVT_MODE_ONESHOT
);
647 if (likely(ch
->flags
& FLAG_IRQCONTEXT
))
648 ch
->next_match_value
= delta
- 1;
650 sh_cmt_set_next(ch
, delta
- 1);
655 static void sh_cmt_clock_event_suspend(struct clock_event_device
*ced
)
657 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
659 pm_genpd_syscore_poweroff(&ch
->cmt
->pdev
->dev
);
660 clk_unprepare(ch
->cmt
->clk
);
663 static void sh_cmt_clock_event_resume(struct clock_event_device
*ced
)
665 struct sh_cmt_channel
*ch
= ced_to_sh_cmt(ced
);
667 clk_prepare(ch
->cmt
->clk
);
668 pm_genpd_syscore_poweron(&ch
->cmt
->pdev
->dev
);
671 static void sh_cmt_register_clockevent(struct sh_cmt_channel
*ch
,
672 const char *name
, unsigned long rating
)
674 struct clock_event_device
*ced
= &ch
->ced
;
677 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
678 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
679 ced
->rating
= rating
;
680 ced
->cpumask
= cpumask_of(0);
681 ced
->set_next_event
= sh_cmt_clock_event_next
;
682 ced
->set_mode
= sh_cmt_clock_event_mode
;
683 ced
->suspend
= sh_cmt_clock_event_suspend
;
684 ced
->resume
= sh_cmt_clock_event_resume
;
686 dev_info(&ch
->cmt
->pdev
->dev
, "ch%u: used for clock events\n",
688 clockevents_register_device(ced
);
691 static int sh_cmt_register(struct sh_cmt_channel
*ch
, const char *name
,
692 unsigned long clockevent_rating
,
693 unsigned long clocksource_rating
)
695 if (clockevent_rating
)
696 sh_cmt_register_clockevent(ch
, name
, clockevent_rating
);
698 if (clocksource_rating
)
699 sh_cmt_register_clocksource(ch
, name
, clocksource_rating
);
704 static int sh_cmt_setup_channel(struct sh_cmt_channel
*ch
, unsigned int index
,
705 struct sh_cmt_device
*cmt
)
707 struct sh_timer_config
*cfg
= cmt
->pdev
->dev
.platform_data
;
712 ch
->base
= cmt
->mapbase_ch
;
715 irq
= platform_get_irq(cmt
->pdev
, 0);
717 dev_err(&cmt
->pdev
->dev
, "ch%u: failed to get irq\n",
722 if (cmt
->width
== (sizeof(ch
->max_match_value
) * 8))
723 ch
->max_match_value
= ~0;
725 ch
->max_match_value
= (1 << cmt
->width
) - 1;
727 ch
->match_value
= ch
->max_match_value
;
728 raw_spin_lock_init(&ch
->lock
);
730 ret
= sh_cmt_register(ch
, dev_name(&cmt
->pdev
->dev
),
731 cfg
->clockevent_rating
,
732 cfg
->clocksource_rating
);
734 dev_err(&cmt
->pdev
->dev
, "ch%u: registration failed\n",
738 ch
->cs_enabled
= false;
740 ret
= request_irq(irq
, sh_cmt_interrupt
,
741 IRQF_TIMER
| IRQF_IRQPOLL
| IRQF_NOBALANCING
,
742 dev_name(&cmt
->pdev
->dev
), ch
);
744 dev_err(&cmt
->pdev
->dev
, "ch%u: failed to request irq %d\n",
752 static int sh_cmt_setup(struct sh_cmt_device
*cmt
, struct platform_device
*pdev
)
754 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
755 struct resource
*res
, *res2
;
762 dev_err(&cmt
->pdev
->dev
, "missing platform data\n");
766 res
= platform_get_resource(cmt
->pdev
, IORESOURCE_MEM
, 0);
768 dev_err(&cmt
->pdev
->dev
, "failed to get I/O memory\n");
772 /* optional resource for the shared timer start/stop register */
773 res2
= platform_get_resource(cmt
->pdev
, IORESOURCE_MEM
, 1);
775 /* map memory, let mapbase_ch point to our channel */
776 cmt
->mapbase_ch
= ioremap_nocache(res
->start
, resource_size(res
));
777 if (cmt
->mapbase_ch
== NULL
) {
778 dev_err(&cmt
->pdev
->dev
, "failed to remap I/O memory\n");
782 /* map second resource for CMSTR */
783 cmt
->mapbase
= ioremap_nocache(res2
? res2
->start
:
784 res
->start
- cfg
->channel_offset
,
785 res2
? resource_size(res2
) : 2);
786 if (cmt
->mapbase
== NULL
) {
787 dev_err(&cmt
->pdev
->dev
, "failed to remap I/O second memory\n");
791 /* get hold of clock */
792 cmt
->clk
= clk_get(&cmt
->pdev
->dev
, "cmt_fck");
793 if (IS_ERR(cmt
->clk
)) {
794 dev_err(&cmt
->pdev
->dev
, "cannot get clock\n");
795 ret
= PTR_ERR(cmt
->clk
);
799 ret
= clk_prepare(cmt
->clk
);
803 if (res2
&& (resource_size(res2
) == 4)) {
804 /* assume both CMSTR and CMCSR to be 32-bit */
805 cmt
->read_control
= sh_cmt_read32
;
806 cmt
->write_control
= sh_cmt_write32
;
808 cmt
->read_control
= sh_cmt_read16
;
809 cmt
->write_control
= sh_cmt_write16
;
812 if (resource_size(res
) == 6) {
814 cmt
->read_count
= sh_cmt_read16
;
815 cmt
->write_count
= sh_cmt_write16
;
816 cmt
->overflow_bit
= 0x80;
817 cmt
->clear_bits
= ~0x80;
820 cmt
->read_count
= sh_cmt_read32
;
821 cmt
->write_count
= sh_cmt_write32
;
822 cmt
->overflow_bit
= 0x8000;
823 cmt
->clear_bits
= ~0xc000;
826 cmt
->channels
= kzalloc(sizeof(*cmt
->channels
), GFP_KERNEL
);
827 if (cmt
->channels
== NULL
) {
832 cmt
->num_channels
= 1;
834 ret
= sh_cmt_setup_channel(&cmt
->channels
[0], cfg
->timer_bit
, cmt
);
838 platform_set_drvdata(pdev
, cmt
);
842 kfree(cmt
->channels
);
843 clk_unprepare(cmt
->clk
);
847 iounmap(cmt
->mapbase
);
849 iounmap(cmt
->mapbase_ch
);
854 static int sh_cmt_probe(struct platform_device
*pdev
)
856 struct sh_cmt_device
*cmt
= platform_get_drvdata(pdev
);
857 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
860 if (!is_early_platform_device(pdev
)) {
861 pm_runtime_set_active(&pdev
->dev
);
862 pm_runtime_enable(&pdev
->dev
);
866 dev_info(&pdev
->dev
, "kept as earlytimer\n");
870 cmt
= kzalloc(sizeof(*cmt
), GFP_KERNEL
);
872 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
876 ret
= sh_cmt_setup(cmt
, pdev
);
879 pm_runtime_idle(&pdev
->dev
);
882 if (is_early_platform_device(pdev
))
886 if (cfg
->clockevent_rating
|| cfg
->clocksource_rating
)
887 pm_runtime_irq_safe(&pdev
->dev
);
889 pm_runtime_idle(&pdev
->dev
);
894 static int sh_cmt_remove(struct platform_device
*pdev
)
896 return -EBUSY
; /* cannot unregister clockevent and clocksource */
899 static struct platform_driver sh_cmt_device_driver
= {
900 .probe
= sh_cmt_probe
,
901 .remove
= sh_cmt_remove
,
907 static int __init
sh_cmt_init(void)
909 return platform_driver_register(&sh_cmt_device_driver
);
912 static void __exit
sh_cmt_exit(void)
914 platform_driver_unregister(&sh_cmt_device_driver
);
917 early_platform_init("earlytimer", &sh_cmt_device_driver
);
918 subsys_initcall(sh_cmt_init
);
919 module_exit(sh_cmt_exit
);
921 MODULE_AUTHOR("Magnus Damm");
922 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
923 MODULE_LICENSE("GPL v2");