drivers/clocksource/sh_mtu2.c

   1 /*
   2  * SuperH Timer Support - MTU2
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clockchips.h>
  31 #include <linux/sh_timer.h>
  32 #include <linux/slab.h>
  33 #include <linux/module.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/pm_runtime.h>
  36
  37 struct sh_mtu2_priv;
  38
  39 struct sh_mtu2_channel {
  40         struct sh_mtu2_priv *mtu;
  41         int irq;
  42         struct clock_event_device ced;
  43 };
  44
  45 struct sh_mtu2_priv {
  46         struct platform_device *pdev;
  47
  48         void __iomem *mapbase;
  49         struct clk *clk;
  50
  51         struct sh_mtu2_channel channel;
  52 };
  53
  54 static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
  55
  56 #define TSTR -1 /* shared register */
  57 #define TCR  0 /* channel register */
  58 #define TMDR 1 /* channel register */
  59 #define TIOR 2 /* channel register */
  60 #define TIER 3 /* channel register */
  61 #define TSR  4 /* channel register */
  62 #define TCNT 5 /* channel register */
  63 #define TGR  6 /* channel register */
  64
  65 static unsigned long mtu2_reg_offs[] = {
  66         [TCR] = 0,
  67         [TMDR] = 1,
  68         [TIOR] = 2,
  69         [TIER] = 4,
  70         [TSR] = 5,
  71         [TCNT] = 6,
  72         [TGR] = 8,
  73 };
  74
  75 static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
  76 {
  77         struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data;
  78         void __iomem *base = ch->mtu->mapbase;
  79         unsigned long offs;
  80
  81         if (reg_nr == TSTR)
  82                 return ioread8(base + cfg->channel_offset);
  83
  84         offs = mtu2_reg_offs[reg_nr];
  85
  86         if ((reg_nr == TCNT) || (reg_nr == TGR))
  87                 return ioread16(base + offs);
  88         else
  89                 return ioread8(base + offs);
  90 }
  91
  92 static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
  93                                 unsigned long value)
  94 {
  95         struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data;
  96         void __iomem *base = ch->mtu->mapbase;
  97         unsigned long offs;
  98
  99         if (reg_nr == TSTR) {
 100                 iowrite8(value, base + cfg->channel_offset);
 101                 return;
 102         }
 103
 104         offs = mtu2_reg_offs[reg_nr];
 105
 106         if ((reg_nr == TCNT) || (reg_nr == TGR))
 107                 iowrite16(value, base + offs);
 108         else
 109                 iowrite8(value, base + offs);
 110 }
 111
 112 static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
 113 {
 114         struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data;
 115         unsigned long flags, value;
 116
 117         /* start stop register shared by multiple timer channels */
 118         raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
 119         value = sh_mtu2_read(ch, TSTR);
 120
 121         if (start)
 122                 value |= 1 << cfg->timer_bit;
 123         else
 124                 value &= ~(1 << cfg->timer_bit);
 125
 126         sh_mtu2_write(ch, TSTR, value);
 127         raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
 128 }
 129
 130 static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
 131 {
 132         unsigned long periodic;
 133         unsigned long rate;
 134         int ret;
 135
 136         pm_runtime_get_sync(&ch->mtu->pdev->dev);
 137         dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
 138
 139         /* enable clock */
 140         ret = clk_enable(ch->mtu->clk);
 141         if (ret) {
 142                 dev_err(&ch->mtu->pdev->dev, "cannot enable clock\n");
 143                 return ret;
 144         }
 145
 146         /* make sure channel is disabled */
 147         sh_mtu2_start_stop_ch(ch, 0);
 148
 149         rate = clk_get_rate(ch->mtu->clk) / 64;
 150         periodic = (rate + HZ/2) / HZ;
 151
 152         /* "Periodic Counter Operation" */
 153         sh_mtu2_write(ch, TCR, 0x23); /* TGRA clear, divide clock by 64 */
 154         sh_mtu2_write(ch, TIOR, 0);
 155         sh_mtu2_write(ch, TGR, periodic);
 156         sh_mtu2_write(ch, TCNT, 0);
 157         sh_mtu2_write(ch, TMDR, 0);
 158         sh_mtu2_write(ch, TIER, 0x01);
 159
 160         /* enable channel */
 161         sh_mtu2_start_stop_ch(ch, 1);
 162
 163         return 0;
 164 }
 165
 166 static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
 167 {
 168         /* disable channel */
 169         sh_mtu2_start_stop_ch(ch, 0);
 170
 171         /* stop clock */
 172         clk_disable(ch->mtu->clk);
 173
 174         dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
 175         pm_runtime_put(&ch->mtu->pdev->dev);
 176 }
 177
 178 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
 179 {
 180         struct sh_mtu2_channel *ch = dev_id;
 181
 182         /* acknowledge interrupt */
 183         sh_mtu2_read(ch, TSR);
 184         sh_mtu2_write(ch, TSR, 0xfe);
 185
 186         /* notify clockevent layer */
 187         ch->ced.event_handler(&ch->ced);
 188         return IRQ_HANDLED;
 189 }
 190
 191 static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
 192 {
 193         return container_of(ced, struct sh_mtu2_channel, ced);
 194 }
 195
 196 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
 197                                     struct clock_event_device *ced)
 198 {
 199         struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
 200         int disabled = 0;
 201
 202         /* deal with old setting first */
 203         switch (ced->mode) {
 204         case CLOCK_EVT_MODE_PERIODIC:
 205                 sh_mtu2_disable(ch);
 206                 disabled = 1;
 207                 break;
 208         default:
 209                 break;
 210         }
 211
 212         switch (mode) {
 213         case CLOCK_EVT_MODE_PERIODIC:
 214                 dev_info(&ch->mtu->pdev->dev,
 215                          "used for periodic clock events\n");
 216                 sh_mtu2_enable(ch);
 217                 break;
 218         case CLOCK_EVT_MODE_UNUSED:
 219                 if (!disabled)
 220                         sh_mtu2_disable(ch);
 221                 break;
 222         case CLOCK_EVT_MODE_SHUTDOWN:
 223         default:
 224                 break;
 225         }
 226 }
 227
 228 static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
 229 {
 230         pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
 231 }
 232
 233 static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
 234 {
 235         pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
 236 }
 237
 238 static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
 239                                        char *name, unsigned long rating)
 240 {
 241         struct clock_event_device *ced = &ch->ced;
 242         int ret;
 243
 244         memset(ced, 0, sizeof(*ced));
 245
 246         ced->name = name;
 247         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 248         ced->rating = rating;
 249         ced->cpumask = cpumask_of(0);
 250         ced->set_mode = sh_mtu2_clock_event_mode;
 251         ced->suspend = sh_mtu2_clock_event_suspend;
 252         ced->resume = sh_mtu2_clock_event_resume;
 253
 254         dev_info(&ch->mtu->pdev->dev, "used for clock events\n");
 255         clockevents_register_device(ced);
 256
 257         ret = request_irq(ch->irq, sh_mtu2_interrupt,
 258                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 259                           dev_name(&ch->mtu->pdev->dev), ch);
 260         if (ret) {
 261                 dev_err(&ch->mtu->pdev->dev, "failed to request irq %d\n",
 262                         ch->irq);
 263                 return;
 264         }
 265 }
 266
 267 static int sh_mtu2_register(struct sh_mtu2_channel *ch, char *name,
 268                             unsigned long clockevent_rating)
 269 {
 270         if (clockevent_rating)
 271                 sh_mtu2_register_clockevent(ch, name, clockevent_rating);
 272
 273         return 0;
 274 }
 275
 276 static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
 277 {
 278         struct sh_timer_config *cfg = pdev->dev.platform_data;
 279         struct resource *res;
 280         int ret;
 281         ret = -ENXIO;
 282
 283         memset(p, 0, sizeof(*p));
 284         p->pdev = pdev;
 285
 286         if (!cfg) {
 287                 dev_err(&p->pdev->dev, "missing platform data\n");
 288                 goto err0;
 289         }
 290
 291         platform_set_drvdata(pdev, p);
 292
 293         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
 294         if (!res) {
 295                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
 296                 goto err0;
 297         }
 298
 299         p->channel.irq = platform_get_irq(p->pdev, 0);
 300         if (p->channel.irq < 0) {
 301                 dev_err(&p->pdev->dev, "failed to get irq\n");
 302                 goto err0;
 303         }
 304
 305         /* map memory, let mapbase point to our channel */
 306         p->mapbase = ioremap_nocache(res->start, resource_size(res));
 307         if (p->mapbase == NULL) {
 308                 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
 309                 goto err0;
 310         }
 311
 312         /* get hold of clock */
 313         p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
 314         if (IS_ERR(p->clk)) {
 315                 dev_err(&p->pdev->dev, "cannot get clock\n");
 316                 ret = PTR_ERR(p->clk);
 317                 goto err1;
 318         }
 319
 320         ret = clk_prepare(p->clk);
 321         if (ret < 0)
 322                 goto err2;
 323
 324         p->channel.mtu = p;
 325
 326         ret = sh_mtu2_register(&p->channel, (char *)dev_name(&p->pdev->dev),
 327                                cfg->clockevent_rating);
 328         if (ret < 0)
 329                 goto err3;
 330
 331         return 0;
 332  err3:
 333         clk_unprepare(p->clk);
 334  err2:
 335         clk_put(p->clk);
 336  err1:
 337         iounmap(p->mapbase);
 338  err0:
 339         return ret;
 340 }
 341
 342 static int sh_mtu2_probe(struct platform_device *pdev)
 343 {
 344         struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
 345         struct sh_timer_config *cfg = pdev->dev.platform_data;
 346         int ret;
 347
 348         if (!is_early_platform_device(pdev)) {
 349                 pm_runtime_set_active(&pdev->dev);
 350                 pm_runtime_enable(&pdev->dev);
 351         }
 352
 353         if (p) {
 354                 dev_info(&pdev->dev, "kept as earlytimer\n");
 355                 goto out;
 356         }
 357
 358         p = kmalloc(sizeof(*p), GFP_KERNEL);
 359         if (p == NULL) {
 360                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 361                 return -ENOMEM;
 362         }
 363
 364         ret = sh_mtu2_setup(p, pdev);
 365         if (ret) {
 366                 kfree(p);
 367                 pm_runtime_idle(&pdev->dev);
 368                 return ret;
 369         }
 370         if (is_early_platform_device(pdev))
 371                 return 0;
 372
 373  out:
 374         if (cfg->clockevent_rating)
 375                 pm_runtime_irq_safe(&pdev->dev);
 376         else
 377                 pm_runtime_idle(&pdev->dev);
 378
 379         return 0;
 380 }
 381
 382 static int sh_mtu2_remove(struct platform_device *pdev)
 383 {
 384         return -EBUSY; /* cannot unregister clockevent */
 385 }
 386
 387 static struct platform_driver sh_mtu2_device_driver = {
 388         .probe          = sh_mtu2_probe,
 389         .remove         = sh_mtu2_remove,
 390         .driver         = {
 391                 .name   = "sh_mtu2",
 392         }
 393 };
 394
 395 static int __init sh_mtu2_init(void)
 396 {
 397         return platform_driver_register(&sh_mtu2_device_driver);
 398 }
 399
 400 static void __exit sh_mtu2_exit(void)
 401 {
 402         platform_driver_unregister(&sh_mtu2_device_driver);
 403 }
 404
 405 early_platform_init("earlytimer", &sh_mtu2_device_driver);
 406 subsys_initcall(sh_mtu2_init);
 407 module_exit(sh_mtu2_exit);
 408
 409 MODULE_AUTHOR("Magnus Damm");
 410 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
 411 MODULE_LICENSE("GPL v2");