2 * SuperH Timer Support - TMU
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/pm_domain.h>
38 void __iomem
*mapbase
;
40 struct irqaction irqaction
;
41 struct platform_device
*pdev
;
43 unsigned long periodic
;
44 struct clock_event_device ced
;
45 struct clocksource cs
;
48 static DEFINE_RAW_SPINLOCK(sh_tmu_lock
);
50 #define TSTR -1 /* shared register */
51 #define TCOR 0 /* channel register */
52 #define TCNT 1 /* channel register */
53 #define TCR 2 /* channel register */
55 static inline unsigned long sh_tmu_read(struct sh_tmu_priv
*p
, int reg_nr
)
57 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
58 void __iomem
*base
= p
->mapbase
;
62 return ioread8(base
- cfg
->channel_offset
);
67 return ioread16(base
+ offs
);
69 return ioread32(base
+ offs
);
72 static inline void sh_tmu_write(struct sh_tmu_priv
*p
, int reg_nr
,
75 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
76 void __iomem
*base
= p
->mapbase
;
80 iowrite8(value
, base
- cfg
->channel_offset
);
87 iowrite16(value
, base
+ offs
);
89 iowrite32(value
, base
+ offs
);
92 static void sh_tmu_start_stop_ch(struct sh_tmu_priv
*p
, int start
)
94 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
95 unsigned long flags
, value
;
97 /* start stop register shared by multiple timer channels */
98 raw_spin_lock_irqsave(&sh_tmu_lock
, flags
);
99 value
= sh_tmu_read(p
, TSTR
);
102 value
|= 1 << cfg
->timer_bit
;
104 value
&= ~(1 << cfg
->timer_bit
);
106 sh_tmu_write(p
, TSTR
, value
);
107 raw_spin_unlock_irqrestore(&sh_tmu_lock
, flags
);
110 static int sh_tmu_enable(struct sh_tmu_priv
*p
)
115 ret
= clk_enable(p
->clk
);
117 dev_err(&p
->pdev
->dev
, "cannot enable clock\n");
121 /* make sure channel is disabled */
122 sh_tmu_start_stop_ch(p
, 0);
124 /* maximum timeout */
125 sh_tmu_write(p
, TCOR
, 0xffffffff);
126 sh_tmu_write(p
, TCNT
, 0xffffffff);
128 /* configure channel to parent clock / 4, irq off */
129 p
->rate
= clk_get_rate(p
->clk
) / 4;
130 sh_tmu_write(p
, TCR
, 0x0000);
133 sh_tmu_start_stop_ch(p
, 1);
138 static void sh_tmu_disable(struct sh_tmu_priv
*p
)
140 /* disable channel */
141 sh_tmu_start_stop_ch(p
, 0);
143 /* disable interrupts in TMU block */
144 sh_tmu_write(p
, TCR
, 0x0000);
150 static void sh_tmu_set_next(struct sh_tmu_priv
*p
, unsigned long delta
,
154 sh_tmu_start_stop_ch(p
, 0);
156 /* acknowledge interrupt */
159 /* enable interrupt */
160 sh_tmu_write(p
, TCR
, 0x0020);
162 /* reload delta value in case of periodic timer */
164 sh_tmu_write(p
, TCOR
, delta
);
166 sh_tmu_write(p
, TCOR
, 0xffffffff);
168 sh_tmu_write(p
, TCNT
, delta
);
171 sh_tmu_start_stop_ch(p
, 1);
174 static irqreturn_t
sh_tmu_interrupt(int irq
, void *dev_id
)
176 struct sh_tmu_priv
*p
= dev_id
;
178 /* disable or acknowledge interrupt */
179 if (p
->ced
.mode
== CLOCK_EVT_MODE_ONESHOT
)
180 sh_tmu_write(p
, TCR
, 0x0000);
182 sh_tmu_write(p
, TCR
, 0x0020);
184 /* notify clockevent layer */
185 p
->ced
.event_handler(&p
->ced
);
189 static struct sh_tmu_priv
*cs_to_sh_tmu(struct clocksource
*cs
)
191 return container_of(cs
, struct sh_tmu_priv
, cs
);
194 static cycle_t
sh_tmu_clocksource_read(struct clocksource
*cs
)
196 struct sh_tmu_priv
*p
= cs_to_sh_tmu(cs
);
198 return sh_tmu_read(p
, TCNT
) ^ 0xffffffff;
201 static int sh_tmu_clocksource_enable(struct clocksource
*cs
)
203 struct sh_tmu_priv
*p
= cs_to_sh_tmu(cs
);
206 ret
= sh_tmu_enable(p
);
208 __clocksource_updatefreq_hz(cs
, p
->rate
);
212 static void sh_tmu_clocksource_disable(struct clocksource
*cs
)
214 sh_tmu_disable(cs_to_sh_tmu(cs
));
217 static int sh_tmu_register_clocksource(struct sh_tmu_priv
*p
,
218 char *name
, unsigned long rating
)
220 struct clocksource
*cs
= &p
->cs
;
224 cs
->read
= sh_tmu_clocksource_read
;
225 cs
->enable
= sh_tmu_clocksource_enable
;
226 cs
->disable
= sh_tmu_clocksource_disable
;
227 cs
->mask
= CLOCKSOURCE_MASK(32);
228 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
230 dev_info(&p
->pdev
->dev
, "used as clock source\n");
232 /* Register with dummy 1 Hz value, gets updated in ->enable() */
233 clocksource_register_hz(cs
, 1);
237 static struct sh_tmu_priv
*ced_to_sh_tmu(struct clock_event_device
*ced
)
239 return container_of(ced
, struct sh_tmu_priv
, ced
);
242 static void sh_tmu_clock_event_start(struct sh_tmu_priv
*p
, int periodic
)
244 struct clock_event_device
*ced
= &p
->ced
;
248 clockevents_config(ced
, p
->rate
);
251 p
->periodic
= (p
->rate
+ HZ
/2) / HZ
;
252 sh_tmu_set_next(p
, p
->periodic
, 1);
256 static void sh_tmu_clock_event_mode(enum clock_event_mode mode
,
257 struct clock_event_device
*ced
)
259 struct sh_tmu_priv
*p
= ced_to_sh_tmu(ced
);
262 /* deal with old setting first */
264 case CLOCK_EVT_MODE_PERIODIC
:
265 case CLOCK_EVT_MODE_ONESHOT
:
274 case CLOCK_EVT_MODE_PERIODIC
:
275 dev_info(&p
->pdev
->dev
, "used for periodic clock events\n");
276 sh_tmu_clock_event_start(p
, 1);
278 case CLOCK_EVT_MODE_ONESHOT
:
279 dev_info(&p
->pdev
->dev
, "used for oneshot clock events\n");
280 sh_tmu_clock_event_start(p
, 0);
282 case CLOCK_EVT_MODE_UNUSED
:
286 case CLOCK_EVT_MODE_SHUTDOWN
:
292 static int sh_tmu_clock_event_next(unsigned long delta
,
293 struct clock_event_device
*ced
)
295 struct sh_tmu_priv
*p
= ced_to_sh_tmu(ced
);
297 BUG_ON(ced
->mode
!= CLOCK_EVT_MODE_ONESHOT
);
299 /* program new delta value */
300 sh_tmu_set_next(p
, delta
, 0);
304 static void sh_tmu_register_clockevent(struct sh_tmu_priv
*p
,
305 char *name
, unsigned long rating
)
307 struct clock_event_device
*ced
= &p
->ced
;
310 memset(ced
, 0, sizeof(*ced
));
313 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
314 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
315 ced
->rating
= rating
;
316 ced
->cpumask
= cpumask_of(0);
317 ced
->set_next_event
= sh_tmu_clock_event_next
;
318 ced
->set_mode
= sh_tmu_clock_event_mode
;
320 dev_info(&p
->pdev
->dev
, "used for clock events\n");
322 clockevents_config_and_register(ced
, 1, 0x300, 0xffffffff);
324 ret
= setup_irq(p
->irqaction
.irq
, &p
->irqaction
);
326 dev_err(&p
->pdev
->dev
, "failed to request irq %d\n",
332 static int sh_tmu_register(struct sh_tmu_priv
*p
, char *name
,
333 unsigned long clockevent_rating
,
334 unsigned long clocksource_rating
)
336 if (clockevent_rating
)
337 sh_tmu_register_clockevent(p
, name
, clockevent_rating
);
338 else if (clocksource_rating
)
339 sh_tmu_register_clocksource(p
, name
, clocksource_rating
);
344 static int sh_tmu_setup(struct sh_tmu_priv
*p
, struct platform_device
*pdev
)
346 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
347 struct resource
*res
;
351 memset(p
, 0, sizeof(*p
));
355 dev_err(&p
->pdev
->dev
, "missing platform data\n");
359 platform_set_drvdata(pdev
, p
);
361 res
= platform_get_resource(p
->pdev
, IORESOURCE_MEM
, 0);
363 dev_err(&p
->pdev
->dev
, "failed to get I/O memory\n");
367 irq
= platform_get_irq(p
->pdev
, 0);
369 dev_err(&p
->pdev
->dev
, "failed to get irq\n");
373 /* map memory, let mapbase point to our channel */
374 p
->mapbase
= ioremap_nocache(res
->start
, resource_size(res
));
375 if (p
->mapbase
== NULL
) {
376 dev_err(&p
->pdev
->dev
, "failed to remap I/O memory\n");
380 /* setup data for setup_irq() (too early for request_irq()) */
381 p
->irqaction
.name
= dev_name(&p
->pdev
->dev
);
382 p
->irqaction
.handler
= sh_tmu_interrupt
;
383 p
->irqaction
.dev_id
= p
;
384 p
->irqaction
.irq
= irq
;
385 p
->irqaction
.flags
= IRQF_DISABLED
| IRQF_TIMER
| \
386 IRQF_IRQPOLL
| IRQF_NOBALANCING
;
388 /* get hold of clock */
389 p
->clk
= clk_get(&p
->pdev
->dev
, "tmu_fck");
390 if (IS_ERR(p
->clk
)) {
391 dev_err(&p
->pdev
->dev
, "cannot get clock\n");
392 ret
= PTR_ERR(p
->clk
);
396 return sh_tmu_register(p
, (char *)dev_name(&p
->pdev
->dev
),
397 cfg
->clockevent_rating
,
398 cfg
->clocksource_rating
);
405 static int __devinit
sh_tmu_probe(struct platform_device
*pdev
)
407 struct sh_tmu_priv
*p
= platform_get_drvdata(pdev
);
410 if (!is_early_platform_device(pdev
))
411 pm_genpd_dev_always_on(&pdev
->dev
, true);
414 dev_info(&pdev
->dev
, "kept as earlytimer\n");
418 p
= kmalloc(sizeof(*p
), GFP_KERNEL
);
420 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
424 ret
= sh_tmu_setup(p
, pdev
);
427 platform_set_drvdata(pdev
, NULL
);
432 static int __devexit
sh_tmu_remove(struct platform_device
*pdev
)
434 return -EBUSY
; /* cannot unregister clockevent and clocksource */
437 static struct platform_driver sh_tmu_device_driver
= {
438 .probe
= sh_tmu_probe
,
439 .remove
= __devexit_p(sh_tmu_remove
),
445 static int __init
sh_tmu_init(void)
447 return platform_driver_register(&sh_tmu_device_driver
);
450 static void __exit
sh_tmu_exit(void)
452 platform_driver_unregister(&sh_tmu_device_driver
);
455 early_platform_init("earlytimer", &sh_tmu_device_driver
);
456 module_init(sh_tmu_init
);
457 module_exit(sh_tmu_exit
);
459 MODULE_AUTHOR("Magnus Damm");
460 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
461 MODULE_LICENSE("GPL v2");