drivers/clocksource/sunxi_timer.c

   1 /*
   2  * Allwinner A1X SoCs timer handling.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/sunxi_timer.h>
  26 #include <linux/clk-provider.h>
  27
  28 #define TIMER_CTL_REG           0x00
  29 #define TIMER_CTL_ENABLE                (1 << 0)
  30 #define TIMER_IRQ_ST_REG        0x04
  31 #define TIMER0_CTL_REG          0x10
  32 #define TIMER0_CTL_ENABLE               (1 << 0)
  33 #define TIMER0_CTL_AUTORELOAD           (1 << 1)
  34 #define TIMER0_CTL_ONESHOT              (1 << 7)
  35 #define TIMER0_INTVAL_REG       0x14
  36 #define TIMER0_CNTVAL_REG       0x18
  37
  38 #define TIMER_SCAL              16
  39
  40 static void __iomem *timer_base;
  41
  42 static void sunxi_clkevt_mode(enum clock_event_mode mode,
  43                               struct clock_event_device *clk)
  44 {
  45         u32 u = readl(timer_base + TIMER0_CTL_REG);
  46
  47         switch (mode) {
  48         case CLOCK_EVT_MODE_PERIODIC:
  49                 u &= ~(TIMER0_CTL_ONESHOT);
  50                 writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
  51                 break;
  52
  53         case CLOCK_EVT_MODE_ONESHOT:
  54                 writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
  55                 break;
  56         case CLOCK_EVT_MODE_UNUSED:
  57         case CLOCK_EVT_MODE_SHUTDOWN:
  58         default:
  59                 writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
  60                 break;
  61         }
  62 }
  63
  64 static int sunxi_clkevt_next_event(unsigned long evt,
  65                                    struct clock_event_device *unused)
  66 {
  67         u32 u = readl(timer_base + TIMER0_CTL_REG);
  68         writel(evt, timer_base + TIMER0_CNTVAL_REG);
  69         writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
  70                timer_base + TIMER0_CTL_REG);
  71
  72         return 0;
  73 }
  74
  75 static struct clock_event_device sunxi_clockevent = {
  76         .name = "sunxi_tick",
  77         .rating = 300,
  78         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  79         .set_mode = sunxi_clkevt_mode,
  80         .set_next_event = sunxi_clkevt_next_event,
  81 };
  82
  83
  84 static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
  85 {
  86         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
  87
  88         writel(0x1, timer_base + TIMER_IRQ_ST_REG);
  89         evt->event_handler(evt);
  90
  91         return IRQ_HANDLED;
  92 }
  93
  94 static struct irqaction sunxi_timer_irq = {
  95         .name = "sunxi_timer0",
  96         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  97         .handler = sunxi_timer_interrupt,
  98         .dev_id = &sunxi_clockevent,
  99 };
 100
 101 static struct of_device_id sunxi_timer_dt_ids[] = {
 102         { .compatible = "allwinner,sunxi-timer" },
 103         { }
 104 };
 105
 106 void __init sunxi_timer_init(void)
 107 {
 108         struct device_node *node;
 109         unsigned long rate = 0;
 110         struct clk *clk;
 111         int ret, irq;
 112         u32 val;
 113
 114         node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
 115         if (!node)
 116                 panic("No sunxi timer node");
 117
 118         timer_base = of_iomap(node, 0);
 119         if (!timer_base)
 120                 panic("Can't map registers");
 121
 122         irq = irq_of_parse_and_map(node, 0);
 123         if (irq <= 0)
 124                 panic("Can't parse IRQ");
 125
 126         of_clk_init(NULL);
 127
 128         clk = of_clk_get(node, 0);
 129         if (IS_ERR(clk))
 130                 panic("Can't get timer clock");
 131
 132         rate = clk_get_rate(clk);
 133
 134         writel(rate / (TIMER_SCAL * HZ),
 135                timer_base + TIMER0_INTVAL_REG);
 136
 137         /* set clock source to HOSC, 16 pre-division */
 138         val = readl(timer_base + TIMER0_CTL_REG);
 139         val &= ~(0x07 << 4);
 140         val &= ~(0x03 << 2);
 141         val |= (4 << 4) | (1 << 2);
 142         writel(val, timer_base + TIMER0_CTL_REG);
 143
 144         /* set mode to auto reload */
 145         val = readl(timer_base + TIMER0_CTL_REG);
 146         writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
 147
 148         ret = setup_irq(irq, &sunxi_timer_irq);
 149         if (ret)
 150                 pr_warn("failed to setup irq %d\n", irq);
 151
 152         /* Enable timer0 interrupt */
 153         val = readl(timer_base + TIMER_CTL_REG);
 154         writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
 155
 156         sunxi_clockevent.cpumask = cpumask_of(0);
 157
 158         clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
 159                                         0x1, 0xff);
 160 }