drivers/clocksource/tcb_clksrc.c

   1 #include <linux/init.h>
   2 #include <linux/clocksource.h>
   3 #include <linux/clockchips.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/irq.h>
   6
   7 #include <linux/clk.h>
   8 #include <linux/err.h>
   9 #include <linux/ioport.h>
  10 #include <linux/io.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/atmel_tc.h>
  13
  14
  15 /*
  16  * We're configured to use a specific TC block, one that's not hooked
  17  * up to external hardware, to provide a time solution:
  18  *
  19  *   - Two channels combine to create a free-running 32 bit counter
  20  *     with a base rate of 5+ MHz, packaged as a clocksource (with
  21  *     resolution better than 200 nsec).
  22  *   - Some chips support 32 bit counter. A single channel is used for
  23  *     this 32 bit free-running counter. the second channel is not used.
  24  *
  25  *   - The third channel may be used to provide a 16-bit clockevent
  26  *     source, used in either periodic or oneshot mode.  This runs
  27  *     at 32 KiHZ, and can handle delays of up to two seconds.
  28  *
  29  * A boot clocksource and clockevent source are also currently needed,
  30  * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
  31  * this code can be used when init_timers() is called, well before most
  32  * devices are set up.  (Some low end AT91 parts, which can run uClinux,
  33  * have only the timers in one TC block... they currently don't support
  34  * the tclib code, because of that initialization issue.)
  35  *
  36  * REVISIT behavior during system suspend states... we should disable
  37  * all clocks and save the power.  Easily done for clockevent devices,
  38  * but clocksources won't necessarily get the needed notifications.
  39  * For deeper system sleep states, this will be mandatory...
  40  */
  41
  42 static void __iomem *tcaddr;
  43
  44 static cycle_t tc_get_cycles(struct clocksource *cs)
  45 {
  46         unsigned long   flags;
  47         u32             lower, upper;
  48
  49         raw_local_irq_save(flags);
  50         do {
  51                 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
  52                 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  53         } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
  54
  55         raw_local_irq_restore(flags);
  56         return (upper << 16) | lower;
  57 }
  58
  59 static cycle_t tc_get_cycles32(struct clocksource *cs)
  60 {
  61         return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  62 }
  63
  64 static struct clocksource clksrc = {
  65         .name           = "tcb_clksrc",
  66         .rating         = 200,
  67         .read           = tc_get_cycles,
  68         .mask           = CLOCKSOURCE_MASK(32),
  69         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  70 };
  71
  72 #ifdef CONFIG_GENERIC_CLOCKEVENTS
  73
  74 struct tc_clkevt_device {
  75         struct clock_event_device       clkevt;
  76         struct clk                      *clk;
  77         void __iomem                    *regs;
  78 };
  79
  80 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
  81 {
  82         return container_of(clkevt, struct tc_clkevt_device, clkevt);
  83 }
  84
  85 /* For now, we always use the 32K clock ... this optimizes for NO_HZ,
  86  * because using one of the divided clocks would usually mean the
  87  * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
  88  *
  89  * A divided clock could be good for high resolution timers, since
  90  * 30.5 usec resolution can seem "low".
  91  */
  92 static u32 timer_clock;
  93
  94 static int tc_shutdown(struct clock_event_device *d)
  95 {
  96         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
  97         void __iomem            *regs = tcd->regs;
  98
  99         __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
 100         __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 101         clk_disable(tcd->clk);
 102
 103         return 0;
 104 }
 105
 106 static int tc_set_oneshot(struct clock_event_device *d)
 107 {
 108         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 109         void __iomem            *regs = tcd->regs;
 110
 111         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 112                 tc_shutdown(d);
 113
 114         clk_enable(tcd->clk);
 115
 116         /* slow clock, count up to RC, then irq and stop */
 117         __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
 118                      ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
 119         __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 120
 121         /* set_next_event() configures and starts the timer */
 122         return 0;
 123 }
 124
 125 static int tc_set_periodic(struct clock_event_device *d)
 126 {
 127         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 128         void __iomem            *regs = tcd->regs;
 129
 130         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 131                 tc_shutdown(d);
 132
 133         /* By not making the gentime core emulate periodic mode on top
 134          * of oneshot, we get lower overhead and improved accuracy.
 135          */
 136         clk_enable(tcd->clk);
 137
 138         /* slow clock, count up to RC, then irq and restart */
 139         __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 140                      regs + ATMEL_TC_REG(2, CMR));
 141         __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 142
 143         /* Enable clock and interrupts on RC compare */
 144         __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 145
 146         /* go go gadget! */
 147         __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
 148                      ATMEL_TC_REG(2, CCR));
 149         return 0;
 150 }
 151
 152 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 153 {
 154         __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 155
 156         /* go go gadget! */
 157         __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 158                         tcaddr + ATMEL_TC_REG(2, CCR));
 159         return 0;
 160 }
 161
 162 static struct tc_clkevt_device clkevt = {
 163         .clkevt = {
 164                 .name                   = "tc_clkevt",
 165                 .features               = CLOCK_EVT_FEAT_PERIODIC |
 166                                           CLOCK_EVT_FEAT_ONESHOT,
 167                 /* Should be lower than at91rm9200's system timer */
 168                 .rating                 = 125,
 169                 .set_next_event         = tc_next_event,
 170                 .set_state_shutdown     = tc_shutdown,
 171                 .set_state_periodic     = tc_set_periodic,
 172                 .set_state_oneshot      = tc_set_oneshot,
 173         },
 174 };
 175
 176 static irqreturn_t ch2_irq(int irq, void *handle)
 177 {
 178         struct tc_clkevt_device *dev = handle;
 179         unsigned int            sr;
 180
 181         sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
 182         if (sr & ATMEL_TC_CPCS) {
 183                 dev->clkevt.event_handler(&dev->clkevt);
 184                 return IRQ_HANDLED;
 185         }
 186
 187         return IRQ_NONE;
 188 }
 189
 190 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 191 {
 192         int ret;
 193         struct clk *t2_clk = tc->clk[2];
 194         int irq = tc->irq[2];
 195
 196         ret = clk_prepare_enable(tc->slow_clk);
 197         if (ret)
 198                 return ret;
 199
 200         /* try to enable t2 clk to avoid future errors in mode change */
 201         ret = clk_prepare_enable(t2_clk);
 202         if (ret) {
 203                 clk_disable_unprepare(tc->slow_clk);
 204                 return ret;
 205         }
 206
 207         clk_disable(t2_clk);
 208
 209         clkevt.regs = tc->regs;
 210         clkevt.clk = t2_clk;
 211
 212         timer_clock = clk32k_divisor_idx;
 213
 214         clkevt.clkevt.cpumask = cpumask_of(0);
 215
 216         ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
 217         if (ret) {
 218                 clk_unprepare(t2_clk);
 219                 clk_disable_unprepare(tc->slow_clk);
 220                 return ret;
 221         }
 222
 223         clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
 224
 225         return ret;
 226 }
 227
 228 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
 229
 230 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 231 {
 232         /* NOTHING */
 233         return 0;
 234 }
 235
 236 #endif
 237
 238 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 239 {
 240         /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
 241         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 242                         | ATMEL_TC_WAVE
 243                         | ATMEL_TC_WAVESEL_UP           /* free-run */
 244                         | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
 245                         | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
 246                         tcaddr + ATMEL_TC_REG(0, CMR));
 247         __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
 248         __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
 249         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 250         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 251
 252         /* channel 1:  waveform mode, input TIOA0 */
 253         __raw_writel(ATMEL_TC_XC1                       /* input: TIOA0 */
 254                         | ATMEL_TC_WAVE
 255                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 256                         tcaddr + ATMEL_TC_REG(1, CMR));
 257         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));      /* no irqs */
 258         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 259
 260         /* chain channel 0 to channel 1*/
 261         __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 262         /* then reset all the timers */
 263         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 264 }
 265
 266 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 267 {
 268         /* channel 0:  waveform mode, input mclk/8 */
 269         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 270                         | ATMEL_TC_WAVE
 271                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 272                         tcaddr + ATMEL_TC_REG(0, CMR));
 273         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 274         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 275
 276         /* then reset all the timers */
 277         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 278 }
 279
 280 static int __init tcb_clksrc_init(void)
 281 {
 282         static char bootinfo[] __initdata
 283                 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
 284
 285         struct platform_device *pdev;
 286         struct atmel_tc *tc;
 287         struct clk *t0_clk;
 288         u32 rate, divided_rate = 0;
 289         int best_divisor_idx = -1;
 290         int clk32k_divisor_idx = -1;
 291         int i;
 292         int ret;
 293
 294         tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
 295         if (!tc) {
 296                 pr_debug("can't alloc TC for clocksource\n");
 297                 return -ENODEV;
 298         }
 299         tcaddr = tc->regs;
 300         pdev = tc->pdev;
 301
 302         t0_clk = tc->clk[0];
 303         ret = clk_prepare_enable(t0_clk);
 304         if (ret) {
 305                 pr_debug("can't enable T0 clk\n");
 306                 goto err_free_tc;
 307         }
 308
 309         /* How fast will we be counting?  Pick something over 5 MHz.  */
 310         rate = (u32) clk_get_rate(t0_clk);
 311         for (i = 0; i < 5; i++) {
 312                 unsigned divisor = atmel_tc_divisors[i];
 313                 unsigned tmp;
 314
 315                 /* remember 32 KiHz clock for later */
 316                 if (!divisor) {
 317                         clk32k_divisor_idx = i;
 318                         continue;
 319                 }
 320
 321                 tmp = rate / divisor;
 322                 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 323                 if (best_divisor_idx > 0) {
 324                         if (tmp < 5 * 1000 * 1000)
 325                                 continue;
 326                 }
 327                 divided_rate = tmp;
 328                 best_divisor_idx = i;
 329         }
 330
 331
 332         printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
 333                         divided_rate / 1000000,
 334                         ((divided_rate + 500000) % 1000000) / 1000);
 335
 336         if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
 337                 /* use apropriate function to read 32 bit counter */
 338                 clksrc.read = tc_get_cycles32;
 339                 /* setup ony channel 0 */
 340                 tcb_setup_single_chan(tc, best_divisor_idx);
 341         } else {
 342                 /* tclib will give us three clocks no matter what the
 343                  * underlying platform supports.
 344                  */
 345                 ret = clk_prepare_enable(tc->clk[1]);
 346                 if (ret) {
 347                         pr_debug("can't enable T1 clk\n");
 348                         goto err_disable_t0;
 349                 }
 350                 /* setup both channel 0 & 1 */
 351                 tcb_setup_dual_chan(tc, best_divisor_idx);
 352         }
 353
 354         /* and away we go! */
 355         ret = clocksource_register_hz(&clksrc, divided_rate);
 356         if (ret)
 357                 goto err_disable_t1;
 358
 359         /* channel 2:  periodic and oneshot timer support */
 360         ret = setup_clkevents(tc, clk32k_divisor_idx);
 361         if (ret)
 362                 goto err_unregister_clksrc;
 363
 364         return 0;
 365
 366 err_unregister_clksrc:
 367         clocksource_unregister(&clksrc);
 368
 369 err_disable_t1:
 370         if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
 371                 clk_disable_unprepare(tc->clk[1]);
 372
 373 err_disable_t0:
 374         clk_disable_unprepare(t0_clk);
 375
 376 err_free_tc:
 377         atmel_tc_free(tc);
 378         return ret;
 379 }
 380 arch_initcall(tcb_clksrc_init);