drivers/cpufreq/exynos4210-cpufreq.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4210 - CPU frequency scaling support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/cpufreq.h>
  19
  20 #include "exynos-cpufreq.h"
  21
  22 static struct clk *cpu_clk;
  23 static struct clk *moutcore;
  24 static struct clk *mout_mpll;
  25 static struct clk *mout_apll;
  26
  27 static unsigned int exynos4210_volt_table[] = {
  28         1250000, 1150000, 1050000, 975000, 950000,
  29 };
  30
  31 static struct cpufreq_frequency_table exynos4210_freq_table[] = {
  32         {0, L0, 1200 * 1000},
  33         {0, L1, 1000 * 1000},
  34         {0, L2,  800 * 1000},
  35         {0, L3,  500 * 1000},
  36         {0, L4,  200 * 1000},
  37         {0, 0, CPUFREQ_TABLE_END},
  38 };
  39
  40 static struct apll_freq apll_freq_4210[] = {
  41         /*
  42          * values:
  43          * freq
  44          * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
  45          * clock divider for COPY, HPM, RESERVED
  46          * PLL M, P, S
  47          */
  48         APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
  49         APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
  50         APLL_FREQ(800,  0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
  51         APLL_FREQ(500,  0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
  52         APLL_FREQ(200,  0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
  53 };
  54
  55 static void exynos4210_set_clkdiv(unsigned int div_index)
  56 {
  57         unsigned int tmp;
  58
  59         /* Change Divider - CPU0 */
  60
  61         tmp = apll_freq_4210[div_index].clk_div_cpu0;
  62
  63         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
  64
  65         do {
  66                 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
  67         } while (tmp & 0x1111111);
  68
  69         /* Change Divider - CPU1 */
  70
  71         tmp = apll_freq_4210[div_index].clk_div_cpu1;
  72
  73         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
  74
  75         do {
  76                 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
  77         } while (tmp & 0x11);
  78 }
  79
  80 static void exynos4210_set_apll(unsigned int index)
  81 {
  82         unsigned int tmp, freq = apll_freq_4210[index].freq;
  83
  84         /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
  85         clk_set_parent(moutcore, mout_mpll);
  86
  87         do {
  88                 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
  89                         >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
  90                 tmp &= 0x7;
  91         } while (tmp != 0x2);
  92
  93         clk_set_rate(mout_apll, freq * 1000);
  94
  95         /* MUX_CORE_SEL = APLL */
  96         clk_set_parent(moutcore, mout_apll);
  97
  98         do {
  99                 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
 100                 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 101         } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 102 }
 103
 104 static void exynos4210_set_frequency(unsigned int old_index,
 105                                      unsigned int new_index)
 106 {
 107         if (old_index > new_index) {
 108                 exynos4210_set_clkdiv(new_index);
 109                 exynos4210_set_apll(new_index);
 110         } else if (old_index < new_index) {
 111                 exynos4210_set_apll(new_index);
 112                 exynos4210_set_clkdiv(new_index);
 113         }
 114 }
 115
 116 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 117 {
 118         unsigned long rate;
 119
 120         cpu_clk = clk_get(NULL, "armclk");
 121         if (IS_ERR(cpu_clk))
 122                 return PTR_ERR(cpu_clk);
 123
 124         moutcore = clk_get(NULL, "moutcore");
 125         if (IS_ERR(moutcore))
 126                 goto err_moutcore;
 127
 128         mout_mpll = clk_get(NULL, "mout_mpll");
 129         if (IS_ERR(mout_mpll))
 130                 goto err_mout_mpll;
 131
 132         rate = clk_get_rate(mout_mpll) / 1000;
 133
 134         mout_apll = clk_get(NULL, "mout_apll");
 135         if (IS_ERR(mout_apll))
 136                 goto err_mout_apll;
 137
 138         info->mpll_freq_khz = rate;
 139         /* 800Mhz */
 140         info->pll_safe_idx = L2;
 141         info->cpu_clk = cpu_clk;
 142         info->volt_table = exynos4210_volt_table;
 143         info->freq_table = exynos4210_freq_table;
 144         info->set_freq = exynos4210_set_frequency;
 145
 146         return 0;
 147
 148 err_mout_apll:
 149         clk_put(mout_mpll);
 150 err_mout_mpll:
 151         clk_put(moutcore);
 152 err_moutcore:
 153         clk_put(cpu_clk);
 154
 155         pr_debug("%s: failed initialization\n", __func__);
 156         return -EINVAL;
 157 }