drivers/cpufreq/imx6q-cpufreq.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpufreq.h>
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/pm_opp.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19
  20 #define PU_SOC_VOLTAGE_NORMAL   1250000
  21 #define PU_SOC_VOLTAGE_HIGH     1275000
  22 #define FREQ_1P2_GHZ            1200000000
  23
  24 static struct regulator *arm_reg;
  25 static struct regulator *pu_reg;
  26 static struct regulator *soc_reg;
  27
  28 static struct clk *arm_clk;
  29 static struct clk *pll1_sys_clk;
  30 static struct clk *pll1_sw_clk;
  31 static struct clk *step_clk;
  32 static struct clk *pll2_pfd2_396m_clk;
  33
  34 static struct device *cpu_dev;
  35 static struct cpufreq_frequency_table *freq_table;
  36 static unsigned int transition_latency;
  37
  38 static u32 *imx6_soc_volt;
  39 static u32 soc_opp_count;
  40
  41 static unsigned int imx6q_get_speed(unsigned int cpu)
  42 {
  43         return clk_get_rate(arm_clk) / 1000;
  44 }
  45
  46 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
  47 {
  48         struct dev_pm_opp *opp;
  49         unsigned long freq_hz, volt, volt_old;
  50         unsigned int old_freq, new_freq;
  51         int ret;
  52
  53         new_freq = freq_table[index].frequency;
  54         freq_hz = new_freq * 1000;
  55         old_freq = clk_get_rate(arm_clk) / 1000;
  56
  57         rcu_read_lock();
  58         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  59         if (IS_ERR(opp)) {
  60                 rcu_read_unlock();
  61                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  62                 return PTR_ERR(opp);
  63         }
  64
  65         volt = dev_pm_opp_get_voltage(opp);
  66         rcu_read_unlock();
  67         volt_old = regulator_get_voltage(arm_reg);
  68
  69         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  70                 old_freq / 1000, volt_old / 1000,
  71                 new_freq / 1000, volt / 1000);
  72
  73         /* scaling up?  scale voltage before frequency */
  74         if (new_freq > old_freq) {
  75                 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  76                 if (ret) {
  77                         dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
  78                         return ret;
  79                 }
  80                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
  81                 if (ret) {
  82                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
  83                         return ret;
  84                 }
  85                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  86                 if (ret) {
  87                         dev_err(cpu_dev,
  88                                 "failed to scale vddarm up: %d\n", ret);
  89                         return ret;
  90                 }
  91         }
  92
  93         /*
  94          * The setpoints are selected per PLL/PDF frequencies, so we need to
  95          * reprogram PLL for frequency scaling.  The procedure of reprogramming
  96          * PLL1 is as below.
  97          *
  98          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
  99          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 100          *  - Disable pll2_pfd2_396m_clk
 101          */
 102         clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 103         clk_set_parent(pll1_sw_clk, step_clk);
 104         if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
 105                 clk_set_rate(pll1_sys_clk, new_freq * 1000);
 106                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 107         }
 108
 109         /* Ensure the arm clock divider is what we expect */
 110         ret = clk_set_rate(arm_clk, new_freq * 1000);
 111         if (ret) {
 112                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 113                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
 114                 return ret;
 115         }
 116
 117         /* scaling down?  scale voltage after frequency */
 118         if (new_freq < old_freq) {
 119                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 120                 if (ret) {
 121                         dev_warn(cpu_dev,
 122                                  "failed to scale vddarm down: %d\n", ret);
 123                         ret = 0;
 124                 }
 125                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 126                 if (ret) {
 127                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
 128                         ret = 0;
 129                 }
 130                 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 131                 if (ret) {
 132                         dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
 133                         ret = 0;
 134                 }
 135         }
 136
 137         return 0;
 138 }
 139
 140 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 141 {
 142         return cpufreq_generic_init(policy, freq_table, transition_latency);
 143 }
 144
 145 static struct cpufreq_driver imx6q_cpufreq_driver = {
 146         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 147         .verify = cpufreq_generic_frequency_table_verify,
 148         .target_index = imx6q_set_target,
 149         .get = imx6q_get_speed,
 150         .init = imx6q_cpufreq_init,
 151         .exit = cpufreq_generic_exit,
 152         .name = "imx6q-cpufreq",
 153         .attr = cpufreq_generic_attr,
 154 };
 155
 156 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 157 {
 158         struct device_node *np;
 159         struct dev_pm_opp *opp;
 160         unsigned long min_volt, max_volt;
 161         int num, ret;
 162         const struct property *prop;
 163         const __be32 *val;
 164         u32 nr, i, j;
 165
 166         cpu_dev = get_cpu_device(0);
 167         if (!cpu_dev) {
 168                 pr_err("failed to get cpu0 device\n");
 169                 return -ENODEV;
 170         }
 171
 172         np = of_node_get(cpu_dev->of_node);
 173         if (!np) {
 174                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 175                 return -ENOENT;
 176         }
 177
 178         arm_clk = devm_clk_get(cpu_dev, "arm");
 179         pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
 180         pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
 181         step_clk = devm_clk_get(cpu_dev, "step");
 182         pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
 183         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
 184             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
 185                 dev_err(cpu_dev, "failed to get clocks\n");
 186                 ret = -ENOENT;
 187                 goto put_node;
 188         }
 189
 190         arm_reg = devm_regulator_get(cpu_dev, "arm");
 191         pu_reg = devm_regulator_get(cpu_dev, "pu");
 192         soc_reg = devm_regulator_get(cpu_dev, "soc");
 193         if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
 194                 dev_err(cpu_dev, "failed to get regulators\n");
 195                 ret = -ENOENT;
 196                 goto put_node;
 197         }
 198
 199         /*
 200          * We expect an OPP table supplied by platform.
 201          * Just, incase the platform did not supply the OPP
 202          * table, it will try to get it.
 203          */
 204         num = dev_pm_opp_get_opp_count(cpu_dev);
 205         if (num < 0) {
 206                 ret = of_init_opp_table(cpu_dev);
 207                 if (ret < 0) {
 208                         dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
 209                         goto put_node;
 210                 }
 211
 212                 num = dev_pm_opp_get_opp_count(cpu_dev);
 213                 if (num < 0) {
 214                         ret = num;
 215                         dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 216                         goto put_node;
 217                 }
 218         }
 219
 220         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
 221         if (ret) {
 222                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 223                 goto put_node;
 224         }
 225
 226         /* Make imx6_soc_volt array's size same as arm opp number */
 227         imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
 228         if (imx6_soc_volt == NULL) {
 229                 ret = -ENOMEM;
 230                 goto free_freq_table;
 231         }
 232
 233         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
 234         if (!prop || !prop->value)
 235                 goto soc_opp_out;
 236
 237         /*
 238          * Each OPP is a set of tuples consisting of frequency and
 239          * voltage like <freq-kHz vol-uV>.
 240          */
 241         nr = prop->length / sizeof(u32);
 242         if (nr % 2 || (nr / 2) < num)
 243                 goto soc_opp_out;
 244
 245         for (j = 0; j < num; j++) {
 246                 val = prop->value;
 247                 for (i = 0; i < nr / 2; i++) {
 248                         unsigned long freq = be32_to_cpup(val++);
 249                         unsigned long volt = be32_to_cpup(val++);
 250                         if (freq_table[j].frequency == freq) {
 251                                 imx6_soc_volt[soc_opp_count++] = volt;
 252                                 break;
 253                         }
 254                 }
 255         }
 256
 257 soc_opp_out:
 258         /* use fixed soc opp volt if no valid soc opp info found in dtb */
 259         if (soc_opp_count != num) {
 260                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
 261                 for (j = 0; j < num; j++)
 262                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
 263                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
 264                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
 265         }
 266
 267         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 268                 transition_latency = CPUFREQ_ETERNAL;
 269
 270         /*
 271          * Calculate the ramp time for max voltage change in the
 272          * VDDSOC and VDDPU regulators.
 273          */
 274         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 275         if (ret > 0)
 276                 transition_latency += ret * 1000;
 277         ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
 278         if (ret > 0)
 279                 transition_latency += ret * 1000;
 280
 281         /*
 282          * OPP is maintained in order of increasing frequency, and
 283          * freq_table initialised from OPP is therefore sorted in the
 284          * same order.
 285          */
 286         rcu_read_lock();
 287         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 288                                   freq_table[0].frequency * 1000, true);
 289         min_volt = dev_pm_opp_get_voltage(opp);
 290         opp = dev_pm_opp_find_freq_exact(cpu_dev,
 291                                   freq_table[--num].frequency * 1000, true);
 292         max_volt = dev_pm_opp_get_voltage(opp);
 293         rcu_read_unlock();
 294         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 295         if (ret > 0)
 296                 transition_latency += ret * 1000;
 297
 298         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 299         if (ret) {
 300                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 301                 goto free_freq_table;
 302         }
 303
 304         of_node_put(np);
 305         return 0;
 306
 307 free_freq_table:
 308         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 309 put_node:
 310         of_node_put(np);
 311         return ret;
 312 }
 313
 314 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 315 {
 316         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 317         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
 318
 319         return 0;
 320 }
 321
 322 static struct platform_driver imx6q_cpufreq_platdrv = {
 323         .driver = {
 324                 .name   = "imx6q-cpufreq",
 325                 .owner  = THIS_MODULE,
 326         },
 327         .probe          = imx6q_cpufreq_probe,
 328         .remove         = imx6q_cpufreq_remove,
 329 };
 330 module_platform_driver(imx6q_cpufreq_platdrv);
 331
 332 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 333 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 334 MODULE_LICENSE("GPL");