2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
16 #include <linux/pm_opp.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
20 #define PU_SOC_VOLTAGE_NORMAL 1250000
21 #define PU_SOC_VOLTAGE_HIGH 1275000
22 #define FREQ_1P2_GHZ 1200000000
24 static struct regulator
*arm_reg
;
25 static struct regulator
*pu_reg
;
26 static struct regulator
*soc_reg
;
28 static struct clk
*arm_clk
;
29 static struct clk
*pll1_sys_clk
;
30 static struct clk
*pll1_sw_clk
;
31 static struct clk
*step_clk
;
32 static struct clk
*pll2_pfd2_396m_clk
;
34 static struct device
*cpu_dev
;
35 static struct cpufreq_frequency_table
*freq_table
;
36 static unsigned int transition_latency
;
38 static unsigned int imx6q_get_speed(unsigned int cpu
)
40 return clk_get_rate(arm_clk
) / 1000;
43 static int imx6q_set_target(struct cpufreq_policy
*policy
, unsigned int index
)
45 struct dev_pm_opp
*opp
;
46 unsigned long freq_hz
, volt
, volt_old
;
47 unsigned int old_freq
, new_freq
;
50 new_freq
= freq_table
[index
].frequency
;
51 freq_hz
= new_freq
* 1000;
52 old_freq
= clk_get_rate(arm_clk
) / 1000;
55 opp
= dev_pm_opp_find_freq_ceil(cpu_dev
, &freq_hz
);
58 dev_err(cpu_dev
, "failed to find OPP for %ld\n", freq_hz
);
62 volt
= dev_pm_opp_get_voltage(opp
);
64 volt_old
= regulator_get_voltage(arm_reg
);
66 dev_dbg(cpu_dev
, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
67 old_freq
/ 1000, volt_old
/ 1000,
68 new_freq
/ 1000, volt
/ 1000);
70 /* scaling up? scale voltage before frequency */
71 if (new_freq
> old_freq
) {
72 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
75 "failed to scale vddarm up: %d\n", ret
);
80 * Need to increase vddpu and vddsoc for safety
81 * if we are about to run at 1.2 GHz.
83 if (new_freq
== FREQ_1P2_GHZ
/ 1000) {
84 regulator_set_voltage_tol(pu_reg
,
85 PU_SOC_VOLTAGE_HIGH
, 0);
86 regulator_set_voltage_tol(soc_reg
,
87 PU_SOC_VOLTAGE_HIGH
, 0);
92 * The setpoints are selected per PLL/PDF frequencies, so we need to
93 * reprogram PLL for frequency scaling. The procedure of reprogramming
96 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
97 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
98 * - Disable pll2_pfd2_396m_clk
100 clk_set_parent(step_clk
, pll2_pfd2_396m_clk
);
101 clk_set_parent(pll1_sw_clk
, step_clk
);
102 if (freq_hz
> clk_get_rate(pll2_pfd2_396m_clk
)) {
103 clk_set_rate(pll1_sys_clk
, new_freq
* 1000);
104 clk_set_parent(pll1_sw_clk
, pll1_sys_clk
);
107 /* Ensure the arm clock divider is what we expect */
108 ret
= clk_set_rate(arm_clk
, new_freq
* 1000);
110 dev_err(cpu_dev
, "failed to set clock rate: %d\n", ret
);
111 regulator_set_voltage_tol(arm_reg
, volt_old
, 0);
115 /* scaling down? scale voltage after frequency */
116 if (new_freq
< old_freq
) {
117 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
120 "failed to scale vddarm down: %d\n", ret
);
124 if (old_freq
== FREQ_1P2_GHZ
/ 1000) {
125 regulator_set_voltage_tol(pu_reg
,
126 PU_SOC_VOLTAGE_NORMAL
, 0);
127 regulator_set_voltage_tol(soc_reg
,
128 PU_SOC_VOLTAGE_NORMAL
, 0);
135 static int imx6q_cpufreq_init(struct cpufreq_policy
*policy
)
137 return cpufreq_generic_init(policy
, freq_table
, transition_latency
);
140 static struct cpufreq_driver imx6q_cpufreq_driver
= {
141 .verify
= cpufreq_generic_frequency_table_verify
,
142 .target_index
= imx6q_set_target
,
143 .get
= imx6q_get_speed
,
144 .init
= imx6q_cpufreq_init
,
145 .exit
= cpufreq_generic_exit
,
146 .name
= "imx6q-cpufreq",
147 .attr
= cpufreq_generic_attr
,
150 static int imx6q_cpufreq_probe(struct platform_device
*pdev
)
152 struct device_node
*np
;
153 struct dev_pm_opp
*opp
;
154 unsigned long min_volt
, max_volt
;
157 cpu_dev
= get_cpu_device(0);
159 pr_err("failed to get cpu0 device\n");
163 np
= of_node_get(cpu_dev
->of_node
);
165 dev_err(cpu_dev
, "failed to find cpu0 node\n");
169 arm_clk
= devm_clk_get(cpu_dev
, "arm");
170 pll1_sys_clk
= devm_clk_get(cpu_dev
, "pll1_sys");
171 pll1_sw_clk
= devm_clk_get(cpu_dev
, "pll1_sw");
172 step_clk
= devm_clk_get(cpu_dev
, "step");
173 pll2_pfd2_396m_clk
= devm_clk_get(cpu_dev
, "pll2_pfd2_396m");
174 if (IS_ERR(arm_clk
) || IS_ERR(pll1_sys_clk
) || IS_ERR(pll1_sw_clk
) ||
175 IS_ERR(step_clk
) || IS_ERR(pll2_pfd2_396m_clk
)) {
176 dev_err(cpu_dev
, "failed to get clocks\n");
181 arm_reg
= devm_regulator_get(cpu_dev
, "arm");
182 pu_reg
= devm_regulator_get(cpu_dev
, "pu");
183 soc_reg
= devm_regulator_get(cpu_dev
, "soc");
184 if (IS_ERR(arm_reg
) || IS_ERR(pu_reg
) || IS_ERR(soc_reg
)) {
185 dev_err(cpu_dev
, "failed to get regulators\n");
190 /* We expect an OPP table supplied by platform */
191 num
= dev_pm_opp_get_opp_count(cpu_dev
);
194 dev_err(cpu_dev
, "no OPP table is found: %d\n", ret
);
198 ret
= dev_pm_opp_init_cpufreq_table(cpu_dev
, &freq_table
);
200 dev_err(cpu_dev
, "failed to init cpufreq table: %d\n", ret
);
204 if (of_property_read_u32(np
, "clock-latency", &transition_latency
))
205 transition_latency
= CPUFREQ_ETERNAL
;
208 * OPP is maintained in order of increasing frequency, and
209 * freq_table initialised from OPP is therefore sorted in the
213 opp
= dev_pm_opp_find_freq_exact(cpu_dev
,
214 freq_table
[0].frequency
* 1000, true);
215 min_volt
= dev_pm_opp_get_voltage(opp
);
216 opp
= dev_pm_opp_find_freq_exact(cpu_dev
,
217 freq_table
[--num
].frequency
* 1000, true);
218 max_volt
= dev_pm_opp_get_voltage(opp
);
220 ret
= regulator_set_voltage_time(arm_reg
, min_volt
, max_volt
);
222 transition_latency
+= ret
* 1000;
224 /* Count vddpu and vddsoc latency in for 1.2 GHz support */
225 if (freq_table
[num
].frequency
== FREQ_1P2_GHZ
/ 1000) {
226 ret
= regulator_set_voltage_time(pu_reg
, PU_SOC_VOLTAGE_NORMAL
,
227 PU_SOC_VOLTAGE_HIGH
);
229 transition_latency
+= ret
* 1000;
230 ret
= regulator_set_voltage_time(soc_reg
, PU_SOC_VOLTAGE_NORMAL
,
231 PU_SOC_VOLTAGE_HIGH
);
233 transition_latency
+= ret
* 1000;
236 ret
= cpufreq_register_driver(&imx6q_cpufreq_driver
);
238 dev_err(cpu_dev
, "failed register driver: %d\n", ret
);
239 goto free_freq_table
;
246 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
252 static int imx6q_cpufreq_remove(struct platform_device
*pdev
)
254 cpufreq_unregister_driver(&imx6q_cpufreq_driver
);
255 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
260 static struct platform_driver imx6q_cpufreq_platdrv
= {
262 .name
= "imx6q-cpufreq",
263 .owner
= THIS_MODULE
,
265 .probe
= imx6q_cpufreq_probe
,
266 .remove
= imx6q_cpufreq_remove
,
268 module_platform_driver(imx6q_cpufreq_platdrv
);
270 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
271 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
272 MODULE_LICENSE("GPL");