2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/err.h>
13 #include <linux/module.h>
15 #include <linux/pm_opp.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
19 #define PU_SOC_VOLTAGE_NORMAL 1250000
20 #define PU_SOC_VOLTAGE_HIGH 1275000
21 #define FREQ_1P2_GHZ 1200000000
23 static struct regulator
*arm_reg
;
24 static struct regulator
*pu_reg
;
25 static struct regulator
*soc_reg
;
27 static struct clk
*arm_clk
;
28 static struct clk
*pll1_sys_clk
;
29 static struct clk
*pll1_sw_clk
;
30 static struct clk
*step_clk
;
31 static struct clk
*pll2_pfd2_396m_clk
;
33 static struct device
*cpu_dev
;
34 static struct cpufreq_frequency_table
*freq_table
;
35 static unsigned int transition_latency
;
37 static u32
*imx6_soc_volt
;
38 static u32 soc_opp_count
;
40 static int imx6q_set_target(struct cpufreq_policy
*policy
, unsigned int index
)
42 struct dev_pm_opp
*opp
;
43 unsigned long freq_hz
, volt
, volt_old
;
44 unsigned int old_freq
, new_freq
;
47 new_freq
= freq_table
[index
].frequency
;
48 freq_hz
= new_freq
* 1000;
49 old_freq
= clk_get_rate(arm_clk
) / 1000;
52 opp
= dev_pm_opp_find_freq_ceil(cpu_dev
, &freq_hz
);
55 dev_err(cpu_dev
, "failed to find OPP for %ld\n", freq_hz
);
59 volt
= dev_pm_opp_get_voltage(opp
);
61 volt_old
= regulator_get_voltage(arm_reg
);
63 dev_dbg(cpu_dev
, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
64 old_freq
/ 1000, volt_old
/ 1000,
65 new_freq
/ 1000, volt
/ 1000);
67 /* scaling up? scale voltage before frequency */
68 if (new_freq
> old_freq
) {
69 ret
= regulator_set_voltage_tol(pu_reg
, imx6_soc_volt
[index
], 0);
71 dev_err(cpu_dev
, "failed to scale vddpu up: %d\n", ret
);
74 ret
= regulator_set_voltage_tol(soc_reg
, imx6_soc_volt
[index
], 0);
76 dev_err(cpu_dev
, "failed to scale vddsoc up: %d\n", ret
);
79 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
82 "failed to scale vddarm up: %d\n", ret
);
88 * The setpoints are selected per PLL/PDF frequencies, so we need to
89 * reprogram PLL for frequency scaling. The procedure of reprogramming
92 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
93 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
94 * - Disable pll2_pfd2_396m_clk
96 clk_set_parent(step_clk
, pll2_pfd2_396m_clk
);
97 clk_set_parent(pll1_sw_clk
, step_clk
);
98 if (freq_hz
> clk_get_rate(pll2_pfd2_396m_clk
)) {
99 clk_set_rate(pll1_sys_clk
, new_freq
* 1000);
100 clk_set_parent(pll1_sw_clk
, pll1_sys_clk
);
103 /* Ensure the arm clock divider is what we expect */
104 ret
= clk_set_rate(arm_clk
, new_freq
* 1000);
106 dev_err(cpu_dev
, "failed to set clock rate: %d\n", ret
);
107 regulator_set_voltage_tol(arm_reg
, volt_old
, 0);
111 /* scaling down? scale voltage after frequency */
112 if (new_freq
< old_freq
) {
113 ret
= regulator_set_voltage_tol(arm_reg
, volt
, 0);
116 "failed to scale vddarm down: %d\n", ret
);
119 ret
= regulator_set_voltage_tol(soc_reg
, imx6_soc_volt
[index
], 0);
121 dev_warn(cpu_dev
, "failed to scale vddsoc down: %d\n", ret
);
124 ret
= regulator_set_voltage_tol(pu_reg
, imx6_soc_volt
[index
], 0);
126 dev_warn(cpu_dev
, "failed to scale vddpu down: %d\n", ret
);
134 static int imx6q_cpufreq_init(struct cpufreq_policy
*policy
)
136 policy
->clk
= arm_clk
;
137 return cpufreq_generic_init(policy
, freq_table
, transition_latency
);
140 static struct cpufreq_driver imx6q_cpufreq_driver
= {
141 .flags
= CPUFREQ_NEED_INITIAL_FREQ_CHECK
,
142 .verify
= cpufreq_generic_frequency_table_verify
,
143 .target_index
= imx6q_set_target
,
144 .get
= cpufreq_generic_get
,
145 .init
= imx6q_cpufreq_init
,
146 .name
= "imx6q-cpufreq",
147 .attr
= cpufreq_generic_attr
,
150 static int imx6q_cpufreq_probe(struct platform_device
*pdev
)
152 struct device_node
*np
;
153 struct dev_pm_opp
*opp
;
154 unsigned long min_volt
, max_volt
;
156 const struct property
*prop
;
160 cpu_dev
= get_cpu_device(0);
162 pr_err("failed to get cpu0 device\n");
166 np
= of_node_get(cpu_dev
->of_node
);
168 dev_err(cpu_dev
, "failed to find cpu0 node\n");
172 arm_clk
= clk_get(cpu_dev
, "arm");
173 pll1_sys_clk
= clk_get(cpu_dev
, "pll1_sys");
174 pll1_sw_clk
= clk_get(cpu_dev
, "pll1_sw");
175 step_clk
= clk_get(cpu_dev
, "step");
176 pll2_pfd2_396m_clk
= clk_get(cpu_dev
, "pll2_pfd2_396m");
177 if (IS_ERR(arm_clk
) || IS_ERR(pll1_sys_clk
) || IS_ERR(pll1_sw_clk
) ||
178 IS_ERR(step_clk
) || IS_ERR(pll2_pfd2_396m_clk
)) {
179 dev_err(cpu_dev
, "failed to get clocks\n");
184 arm_reg
= regulator_get(cpu_dev
, "arm");
185 pu_reg
= regulator_get(cpu_dev
, "pu");
186 soc_reg
= regulator_get(cpu_dev
, "soc");
187 if (IS_ERR(arm_reg
) || IS_ERR(pu_reg
) || IS_ERR(soc_reg
)) {
188 dev_err(cpu_dev
, "failed to get regulators\n");
194 * We expect an OPP table supplied by platform.
195 * Just, incase the platform did not supply the OPP
196 * table, it will try to get it.
198 num
= dev_pm_opp_get_opp_count(cpu_dev
);
200 ret
= of_init_opp_table(cpu_dev
);
202 dev_err(cpu_dev
, "failed to init OPP table: %d\n", ret
);
206 num
= dev_pm_opp_get_opp_count(cpu_dev
);
209 dev_err(cpu_dev
, "no OPP table is found: %d\n", ret
);
214 ret
= dev_pm_opp_init_cpufreq_table(cpu_dev
, &freq_table
);
216 dev_err(cpu_dev
, "failed to init cpufreq table: %d\n", ret
);
220 /* Make imx6_soc_volt array's size same as arm opp number */
221 imx6_soc_volt
= devm_kzalloc(cpu_dev
, sizeof(*imx6_soc_volt
) * num
, GFP_KERNEL
);
222 if (imx6_soc_volt
== NULL
) {
224 goto free_freq_table
;
227 prop
= of_find_property(np
, "fsl,soc-operating-points", NULL
);
228 if (!prop
|| !prop
->value
)
232 * Each OPP is a set of tuples consisting of frequency and
233 * voltage like <freq-kHz vol-uV>.
235 nr
= prop
->length
/ sizeof(u32
);
236 if (nr
% 2 || (nr
/ 2) < num
)
239 for (j
= 0; j
< num
; j
++) {
241 for (i
= 0; i
< nr
/ 2; i
++) {
242 unsigned long freq
= be32_to_cpup(val
++);
243 unsigned long volt
= be32_to_cpup(val
++);
244 if (freq_table
[j
].frequency
== freq
) {
245 imx6_soc_volt
[soc_opp_count
++] = volt
;
252 /* use fixed soc opp volt if no valid soc opp info found in dtb */
253 if (soc_opp_count
!= num
) {
254 dev_warn(cpu_dev
, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
255 for (j
= 0; j
< num
; j
++)
256 imx6_soc_volt
[j
] = PU_SOC_VOLTAGE_NORMAL
;
257 if (freq_table
[num
- 1].frequency
* 1000 == FREQ_1P2_GHZ
)
258 imx6_soc_volt
[num
- 1] = PU_SOC_VOLTAGE_HIGH
;
261 if (of_property_read_u32(np
, "clock-latency", &transition_latency
))
262 transition_latency
= CPUFREQ_ETERNAL
;
265 * Calculate the ramp time for max voltage change in the
266 * VDDSOC and VDDPU regulators.
268 ret
= regulator_set_voltage_time(soc_reg
, imx6_soc_volt
[0], imx6_soc_volt
[num
- 1]);
270 transition_latency
+= ret
* 1000;
271 ret
= regulator_set_voltage_time(pu_reg
, imx6_soc_volt
[0], imx6_soc_volt
[num
- 1]);
273 transition_latency
+= ret
* 1000;
276 * OPP is maintained in order of increasing frequency, and
277 * freq_table initialised from OPP is therefore sorted in the
281 opp
= dev_pm_opp_find_freq_exact(cpu_dev
,
282 freq_table
[0].frequency
* 1000, true);
283 min_volt
= dev_pm_opp_get_voltage(opp
);
284 opp
= dev_pm_opp_find_freq_exact(cpu_dev
,
285 freq_table
[--num
].frequency
* 1000, true);
286 max_volt
= dev_pm_opp_get_voltage(opp
);
288 ret
= regulator_set_voltage_time(arm_reg
, min_volt
, max_volt
);
290 transition_latency
+= ret
* 1000;
292 ret
= cpufreq_register_driver(&imx6q_cpufreq_driver
);
294 dev_err(cpu_dev
, "failed register driver: %d\n", ret
);
295 goto free_freq_table
;
302 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
304 if (!IS_ERR(arm_reg
))
305 regulator_put(arm_reg
);
307 regulator_put(pu_reg
);
308 if (!IS_ERR(soc_reg
))
309 regulator_put(soc_reg
);
311 if (!IS_ERR(arm_clk
))
313 if (!IS_ERR(pll1_sys_clk
))
314 clk_put(pll1_sys_clk
);
315 if (!IS_ERR(pll1_sw_clk
))
316 clk_put(pll1_sw_clk
);
317 if (!IS_ERR(step_clk
))
319 if (!IS_ERR(pll2_pfd2_396m_clk
))
320 clk_put(pll2_pfd2_396m_clk
);
325 static int imx6q_cpufreq_remove(struct platform_device
*pdev
)
327 cpufreq_unregister_driver(&imx6q_cpufreq_driver
);
328 dev_pm_opp_free_cpufreq_table(cpu_dev
, &freq_table
);
329 regulator_put(arm_reg
);
330 regulator_put(pu_reg
);
331 regulator_put(soc_reg
);
333 clk_put(pll1_sys_clk
);
334 clk_put(pll1_sw_clk
);
336 clk_put(pll2_pfd2_396m_clk
);
341 static struct platform_driver imx6q_cpufreq_platdrv
= {
343 .name
= "imx6q-cpufreq",
344 .owner
= THIS_MODULE
,
346 .probe
= imx6q_cpufreq_probe
,
347 .remove
= imx6q_cpufreq_remove
,
349 module_platform_driver(imx6q_cpufreq_platdrv
);
351 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
352 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
353 MODULE_LICENSE("GPL");