drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/module.h>
  16 #include <linux/ktime.h>
  17 #include <linux/hrtimer.h>
  18 #include <linux/tick.h>
  19 #include <linux/slab.h>
  20 #include <linux/sched.h>
  21 #include <linux/list.h>
  22 #include <linux/cpu.h>
  23 #include <linux/cpufreq.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/types.h>
  26 #include <linux/fs.h>
  27 #include <linux/debugfs.h>
  28 #include <linux/acpi.h>
  29 #include <trace/events/power.h>
  30
  31 #include <asm/div64.h>
  32 #include <asm/msr.h>
  33 #include <asm/cpu_device_id.h>
  34
  35 #define BYT_RATIOS              0x66a
  36 #define BYT_VIDS                0x66b
  37 #define BYT_TURBO_RATIOS        0x66c
  38 #define BYT_TURBO_VIDS          0x66d
  39
  40 #define FRAC_BITS 8
  41 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  42 #define fp_toint(X) ((X) >> FRAC_BITS)
  43
  44
  45 static inline int32_t mul_fp(int32_t x, int32_t y)
  46 {
  47         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  48 }
  49
  50 static inline int32_t div_fp(int32_t x, int32_t y)
  51 {
  52         return div_s64((int64_t)x << FRAC_BITS, y);
  53 }
  54
  55 static inline int ceiling_fp(int32_t x)
  56 {
  57         int mask, ret;
  58
  59         ret = fp_toint(x);
  60         mask = (1 << FRAC_BITS) - 1;
  61         if (x & mask)
  62                 ret += 1;
  63         return ret;
  64 }
  65
  66 struct sample {
  67         int32_t core_pct_busy;
  68         u64 aperf;
  69         u64 mperf;
  70         int freq;
  71         ktime_t time;
  72 };
  73
  74 struct pstate_data {
  75         int     current_pstate;
  76         int     min_pstate;
  77         int     max_pstate;
  78         int     scaling;
  79         int     turbo_pstate;
  80 };
  81
  82 struct vid_data {
  83         int min;
  84         int max;
  85         int turbo;
  86         int32_t ratio;
  87 };
  88
  89 struct _pid {
  90         int setpoint;
  91         int32_t integral;
  92         int32_t p_gain;
  93         int32_t i_gain;
  94         int32_t d_gain;
  95         int deadband;
  96         int32_t last_err;
  97 };
  98
  99 struct cpudata {
 100         int cpu;
 101
 102         struct timer_list timer;
 103
 104         struct pstate_data pstate;
 105         struct vid_data vid;
 106         struct _pid pid;
 107
 108         ktime_t last_sample_time;
 109         u64     prev_aperf;
 110         u64     prev_mperf;
 111         struct sample sample;
 112 };
 113
 114 static struct cpudata **all_cpu_data;
 115 struct pstate_adjust_policy {
 116         int sample_rate_ms;
 117         int deadband;
 118         int setpoint;
 119         int p_gain_pct;
 120         int d_gain_pct;
 121         int i_gain_pct;
 122 };
 123
 124 struct pstate_funcs {
 125         int (*get_max)(void);
 126         int (*get_min)(void);
 127         int (*get_turbo)(void);
 128         int (*get_scaling)(void);
 129         void (*set)(struct cpudata*, int pstate);
 130         void (*get_vid)(struct cpudata *);
 131 };
 132
 133 struct cpu_defaults {
 134         struct pstate_adjust_policy pid_policy;
 135         struct pstate_funcs funcs;
 136 };
 137
 138 static struct pstate_adjust_policy pid_params;
 139 static struct pstate_funcs pstate_funcs;
 140 static int hwp_active;
 141
 142 struct perf_limits {
 143         int no_turbo;
 144         int turbo_disabled;
 145         int max_perf_pct;
 146         int min_perf_pct;
 147         int32_t max_perf;
 148         int32_t min_perf;
 149         int max_policy_pct;
 150         int max_sysfs_pct;
 151 };
 152
 153 static struct perf_limits limits = {
 154         .no_turbo = 0,
 155         .turbo_disabled = 0,
 156         .max_perf_pct = 100,
 157         .max_perf = int_tofp(1),
 158         .min_perf_pct = 0,
 159         .min_perf = 0,
 160         .max_policy_pct = 100,
 161         .max_sysfs_pct = 100,
 162 };
 163
 164 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 165                              int deadband, int integral) {
 166         pid->setpoint = setpoint;
 167         pid->deadband  = deadband;
 168         pid->integral  = int_tofp(integral);
 169         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 170 }
 171
 172 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 173 {
 174         pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
 175 }
 176
 177 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 178 {
 179         pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
 180 }
 181
 182 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 183 {
 184         pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
 185 }
 186
 187 static signed int pid_calc(struct _pid *pid, int32_t busy)
 188 {
 189         signed int result;
 190         int32_t pterm, dterm, fp_error;
 191         int32_t integral_limit;
 192
 193         fp_error = int_tofp(pid->setpoint) - busy;
 194
 195         if (abs(fp_error) <= int_tofp(pid->deadband))
 196                 return 0;
 197
 198         pterm = mul_fp(pid->p_gain, fp_error);
 199
 200         pid->integral += fp_error;
 201
 202         /*
 203          * We limit the integral here so that it will never
 204          * get higher than 30.  This prevents it from becoming
 205          * too large an input over long periods of time and allows
 206          * it to get factored out sooner.
 207          *
 208          * The value of 30 was chosen through experimentation.
 209          */
 210         integral_limit = int_tofp(30);
 211         if (pid->integral > integral_limit)
 212                 pid->integral = integral_limit;
 213         if (pid->integral < -integral_limit)
 214                 pid->integral = -integral_limit;
 215
 216         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 217         pid->last_err = fp_error;
 218
 219         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 220         result = result + (1 << (FRAC_BITS-1));
 221         return (signed int)fp_toint(result);
 222 }
 223
 224 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 225 {
 226         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 227         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 228         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 229
 230         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 231 }
 232
 233 static inline void intel_pstate_reset_all_pid(void)
 234 {
 235         unsigned int cpu;
 236
 237         for_each_online_cpu(cpu) {
 238                 if (all_cpu_data[cpu])
 239                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 240         }
 241 }
 242
 243 static inline void update_turbo_state(void)
 244 {
 245         u64 misc_en;
 246         struct cpudata *cpu;
 247
 248         cpu = all_cpu_data[0];
 249         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 250         limits.turbo_disabled =
 251                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 252                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 253 }
 254
 255 #define PCT_TO_HWP(x) (x * 255 / 100)
 256 static void intel_pstate_hwp_set(void)
 257 {
 258         int min, max, cpu;
 259         u64 value, freq;
 260
 261         get_online_cpus();
 262
 263         for_each_online_cpu(cpu) {
 264                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 265                 min = PCT_TO_HWP(limits.min_perf_pct);
 266                 value &= ~HWP_MIN_PERF(~0L);
 267                 value |= HWP_MIN_PERF(min);
 268
 269                 max = PCT_TO_HWP(limits.max_perf_pct);
 270                 if (limits.no_turbo) {
 271                         rdmsrl( MSR_HWP_CAPABILITIES, freq);
 272                         max = HWP_GUARANTEED_PERF(freq);
 273                 }
 274
 275                 value &= ~HWP_MAX_PERF(~0L);
 276                 value |= HWP_MAX_PERF(max);
 277                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 278         }
 279
 280         put_online_cpus();
 281 }
 282
 283 /************************** debugfs begin ************************/
 284 static int pid_param_set(void *data, u64 val)
 285 {
 286         *(u32 *)data = val;
 287         intel_pstate_reset_all_pid();
 288         return 0;
 289 }
 290
 291 static int pid_param_get(void *data, u64 *val)
 292 {
 293         *val = *(u32 *)data;
 294         return 0;
 295 }
 296 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 297
 298 struct pid_param {
 299         char *name;
 300         void *value;
 301 };
 302
 303 static struct pid_param pid_files[] = {
 304         {"sample_rate_ms", &pid_params.sample_rate_ms},
 305         {"d_gain_pct", &pid_params.d_gain_pct},
 306         {"i_gain_pct", &pid_params.i_gain_pct},
 307         {"deadband", &pid_params.deadband},
 308         {"setpoint", &pid_params.setpoint},
 309         {"p_gain_pct", &pid_params.p_gain_pct},
 310         {NULL, NULL}
 311 };
 312
 313 static void __init intel_pstate_debug_expose_params(void)
 314 {
 315         struct dentry *debugfs_parent;
 316         int i = 0;
 317
 318         if (hwp_active)
 319                 return;
 320         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
 321         if (IS_ERR_OR_NULL(debugfs_parent))
 322                 return;
 323         while (pid_files[i].name) {
 324                 debugfs_create_file(pid_files[i].name, 0660,
 325                                     debugfs_parent, pid_files[i].value,
 326                                     &fops_pid_param);
 327                 i++;
 328         }
 329 }
 330
 331 /************************** debugfs end ************************/
 332
 333 /************************** sysfs begin ************************/
 334 #define show_one(file_name, object)                                     \
 335         static ssize_t show_##file_name                                 \
 336         (struct kobject *kobj, struct attribute *attr, char *buf)       \
 337         {                                                               \
 338                 return sprintf(buf, "%u\n", limits.object);             \
 339         }
 340
 341 static ssize_t show_turbo_pct(struct kobject *kobj,
 342                                 struct attribute *attr, char *buf)
 343 {
 344         struct cpudata *cpu;
 345         int total, no_turbo, turbo_pct;
 346         uint32_t turbo_fp;
 347
 348         cpu = all_cpu_data[0];
 349
 350         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 351         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
 352         turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total));
 353         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
 354         return sprintf(buf, "%u\n", turbo_pct);
 355 }
 356
 357 static ssize_t show_num_pstates(struct kobject *kobj,
 358                                 struct attribute *attr, char *buf)
 359 {
 360         struct cpudata *cpu;
 361         int total;
 362
 363         cpu = all_cpu_data[0];
 364         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 365         return sprintf(buf, "%u\n", total);
 366 }
 367
 368 static ssize_t show_no_turbo(struct kobject *kobj,
 369                              struct attribute *attr, char *buf)
 370 {
 371         ssize_t ret;
 372
 373         update_turbo_state();
 374         if (limits.turbo_disabled)
 375                 ret = sprintf(buf, "%u\n", limits.turbo_disabled);
 376         else
 377                 ret = sprintf(buf, "%u\n", limits.no_turbo);
 378
 379         return ret;
 380 }
 381
 382 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
 383                               const char *buf, size_t count)
 384 {
 385         unsigned int input;
 386         int ret;
 387
 388         ret = sscanf(buf, "%u", &input);
 389         if (ret != 1)
 390                 return -EINVAL;
 391
 392         update_turbo_state();
 393         if (limits.turbo_disabled) {
 394                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
 395                 return -EPERM;
 396         }
 397
 398         limits.no_turbo = clamp_t(int, input, 0, 1);
 399
 400         if (hwp_active)
 401                 intel_pstate_hwp_set();
 402
 403         return count;
 404 }
 405
 406 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
 407                                   const char *buf, size_t count)
 408 {
 409         unsigned int input;
 410         int ret;
 411
 412         ret = sscanf(buf, "%u", &input);
 413         if (ret != 1)
 414                 return -EINVAL;
 415
 416         limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
 417         limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
 418         limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
 419
 420         if (hwp_active)
 421                 intel_pstate_hwp_set();
 422         return count;
 423 }
 424
 425 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
 426                                   const char *buf, size_t count)
 427 {
 428         unsigned int input;
 429         int ret;
 430
 431         ret = sscanf(buf, "%u", &input);
 432         if (ret != 1)
 433                 return -EINVAL;
 434         limits.min_perf_pct = clamp_t(int, input, 0 , 100);
 435         limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
 436
 437         if (hwp_active)
 438                 intel_pstate_hwp_set();
 439         return count;
 440 }
 441
 442 show_one(max_perf_pct, max_perf_pct);
 443 show_one(min_perf_pct, min_perf_pct);
 444
 445 define_one_global_rw(no_turbo);
 446 define_one_global_rw(max_perf_pct);
 447 define_one_global_rw(min_perf_pct);
 448 define_one_global_ro(turbo_pct);
 449 define_one_global_ro(num_pstates);
 450
 451 static struct attribute *intel_pstate_attributes[] = {
 452         &no_turbo.attr,
 453         &max_perf_pct.attr,
 454         &min_perf_pct.attr,
 455         &turbo_pct.attr,
 456         &num_pstates.attr,
 457         NULL
 458 };
 459
 460 static struct attribute_group intel_pstate_attr_group = {
 461         .attrs = intel_pstate_attributes,
 462 };
 463
 464 static void __init intel_pstate_sysfs_expose_params(void)
 465 {
 466         struct kobject *intel_pstate_kobject;
 467         int rc;
 468
 469         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
 470                                                 &cpu_subsys.dev_root->kobj);
 471         BUG_ON(!intel_pstate_kobject);
 472         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
 473         BUG_ON(rc);
 474 }
 475 /************************** sysfs end ************************/
 476
 477 static void intel_pstate_hwp_enable(void)
 478 {
 479         hwp_active++;
 480         pr_info("intel_pstate HWP enabled\n");
 481
 482         wrmsrl( MSR_PM_ENABLE, 0x1);
 483 }
 484
 485 static int byt_get_min_pstate(void)
 486 {
 487         u64 value;
 488
 489         rdmsrl(BYT_RATIOS, value);
 490         return (value >> 8) & 0x7F;
 491 }
 492
 493 static int byt_get_max_pstate(void)
 494 {
 495         u64 value;
 496
 497         rdmsrl(BYT_RATIOS, value);
 498         return (value >> 16) & 0x7F;
 499 }
 500
 501 static int byt_get_turbo_pstate(void)
 502 {
 503         u64 value;
 504
 505         rdmsrl(BYT_TURBO_RATIOS, value);
 506         return value & 0x7F;
 507 }
 508
 509 static void byt_set_pstate(struct cpudata *cpudata, int pstate)
 510 {
 511         u64 val;
 512         int32_t vid_fp;
 513         u32 vid;
 514
 515         val = pstate << 8;
 516         if (limits.no_turbo && !limits.turbo_disabled)
 517                 val |= (u64)1 << 32;
 518
 519         vid_fp = cpudata->vid.min + mul_fp(
 520                 int_tofp(pstate - cpudata->pstate.min_pstate),
 521                 cpudata->vid.ratio);
 522
 523         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
 524         vid = ceiling_fp(vid_fp);
 525
 526         if (pstate > cpudata->pstate.max_pstate)
 527                 vid = cpudata->vid.turbo;
 528
 529         val |= vid;
 530
 531         wrmsrl(MSR_IA32_PERF_CTL, val);
 532 }
 533
 534 #define BYT_BCLK_FREQS 5
 535 static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800};
 536
 537 static int byt_get_scaling(void)
 538 {
 539         u64 value;
 540         int i;
 541
 542         rdmsrl(MSR_FSB_FREQ, value);
 543         i = value & 0x3;
 544
 545         BUG_ON(i > BYT_BCLK_FREQS);
 546
 547         return byt_freq_table[i] * 100;
 548 }
 549
 550 static void byt_get_vid(struct cpudata *cpudata)
 551 {
 552         u64 value;
 553
 554         rdmsrl(BYT_VIDS, value);
 555         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
 556         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
 557         cpudata->vid.ratio = div_fp(
 558                 cpudata->vid.max - cpudata->vid.min,
 559                 int_tofp(cpudata->pstate.max_pstate -
 560                         cpudata->pstate.min_pstate));
 561
 562         rdmsrl(BYT_TURBO_VIDS, value);
 563         cpudata->vid.turbo = value & 0x7f;
 564 }
 565
 566 static int core_get_min_pstate(void)
 567 {
 568         u64 value;
 569
 570         rdmsrl(MSR_PLATFORM_INFO, value);
 571         return (value >> 40) & 0xFF;
 572 }
 573
 574 static int core_get_max_pstate(void)
 575 {
 576         u64 value;
 577
 578         rdmsrl(MSR_PLATFORM_INFO, value);
 579         return (value >> 8) & 0xFF;
 580 }
 581
 582 static int core_get_turbo_pstate(void)
 583 {
 584         u64 value;
 585         int nont, ret;
 586
 587         rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
 588         nont = core_get_max_pstate();
 589         ret = (value) & 255;
 590         if (ret <= nont)
 591                 ret = nont;
 592         return ret;
 593 }
 594
 595 static inline int core_get_scaling(void)
 596 {
 597         return 100000;
 598 }
 599
 600 static void core_set_pstate(struct cpudata *cpudata, int pstate)
 601 {
 602         u64 val;
 603
 604         val = pstate << 8;
 605         if (limits.no_turbo && !limits.turbo_disabled)
 606                 val |= (u64)1 << 32;
 607
 608         wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
 609 }
 610
 611 static struct cpu_defaults core_params = {
 612         .pid_policy = {
 613                 .sample_rate_ms = 10,
 614                 .deadband = 0,
 615                 .setpoint = 97,
 616                 .p_gain_pct = 20,
 617                 .d_gain_pct = 0,
 618                 .i_gain_pct = 0,
 619         },
 620         .funcs = {
 621                 .get_max = core_get_max_pstate,
 622                 .get_min = core_get_min_pstate,
 623                 .get_turbo = core_get_turbo_pstate,
 624                 .get_scaling = core_get_scaling,
 625                 .set = core_set_pstate,
 626         },
 627 };
 628
 629 static struct cpu_defaults byt_params = {
 630         .pid_policy = {
 631                 .sample_rate_ms = 10,
 632                 .deadband = 0,
 633                 .setpoint = 97,
 634                 .p_gain_pct = 14,
 635                 .d_gain_pct = 0,
 636                 .i_gain_pct = 4,
 637         },
 638         .funcs = {
 639                 .get_max = byt_get_max_pstate,
 640                 .get_min = byt_get_min_pstate,
 641                 .get_turbo = byt_get_turbo_pstate,
 642                 .set = byt_set_pstate,
 643                 .get_scaling = byt_get_scaling,
 644                 .get_vid = byt_get_vid,
 645         },
 646 };
 647
 648 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
 649 {
 650         int max_perf = cpu->pstate.turbo_pstate;
 651         int max_perf_adj;
 652         int min_perf;
 653
 654         if (limits.no_turbo || limits.turbo_disabled)
 655                 max_perf = cpu->pstate.max_pstate;
 656
 657         /*
 658          * performance can be limited by user through sysfs, by cpufreq
 659          * policy, or by cpu specific default values determined through
 660          * experimentation.
 661          */
 662         max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
 663         *max = clamp_t(int, max_perf_adj,
 664                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
 665
 666         min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
 667         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
 668 }
 669
 670 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
 671 {
 672         int max_perf, min_perf;
 673
 674         update_turbo_state();
 675
 676         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
 677
 678         pstate = clamp_t(int, pstate, min_perf, max_perf);
 679
 680         if (pstate == cpu->pstate.current_pstate)
 681                 return;
 682
 683         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
 684
 685         cpu->pstate.current_pstate = pstate;
 686
 687         pstate_funcs.set(cpu, pstate);
 688 }
 689
 690 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
 691 {
 692         cpu->pstate.min_pstate = pstate_funcs.get_min();
 693         cpu->pstate.max_pstate = pstate_funcs.get_max();
 694         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
 695         cpu->pstate.scaling = pstate_funcs.get_scaling();
 696
 697         if (pstate_funcs.get_vid)
 698                 pstate_funcs.get_vid(cpu);
 699         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
 700 }
 701
 702 static inline void intel_pstate_calc_busy(struct cpudata *cpu)
 703 {
 704         struct sample *sample = &cpu->sample;
 705         int64_t core_pct;
 706
 707         core_pct = int_tofp(sample->aperf) * int_tofp(100);
 708         core_pct = div64_u64(core_pct, int_tofp(sample->mperf));
 709
 710         sample->freq = fp_toint(
 711                 mul_fp(int_tofp(
 712                         cpu->pstate.max_pstate * cpu->pstate.scaling / 100),
 713                         core_pct));
 714
 715         sample->core_pct_busy = (int32_t)core_pct;
 716 }
 717
 718 static inline void intel_pstate_sample(struct cpudata *cpu)
 719 {
 720         u64 aperf, mperf;
 721         unsigned long flags;
 722
 723         local_irq_save(flags);
 724         rdmsrl(MSR_IA32_APERF, aperf);
 725         rdmsrl(MSR_IA32_MPERF, mperf);
 726         local_irq_restore(flags);
 727
 728         cpu->last_sample_time = cpu->sample.time;
 729         cpu->sample.time = ktime_get();
 730         cpu->sample.aperf = aperf;
 731         cpu->sample.mperf = mperf;
 732         cpu->sample.aperf -= cpu->prev_aperf;
 733         cpu->sample.mperf -= cpu->prev_mperf;
 734
 735         intel_pstate_calc_busy(cpu);
 736
 737         cpu->prev_aperf = aperf;
 738         cpu->prev_mperf = mperf;
 739 }
 740
 741 static inline void intel_hwp_set_sample_time(struct cpudata *cpu)
 742 {
 743         int delay;
 744
 745         delay = msecs_to_jiffies(50);
 746         mod_timer_pinned(&cpu->timer, jiffies + delay);
 747 }
 748
 749 static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
 750 {
 751         int delay;
 752
 753         delay = msecs_to_jiffies(pid_params.sample_rate_ms);
 754         mod_timer_pinned(&cpu->timer, jiffies + delay);
 755 }
 756
 757 static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
 758 {
 759         int32_t core_busy, max_pstate, current_pstate, sample_ratio;
 760         u32 duration_us;
 761         u32 sample_time;
 762
 763         /*
 764          * core_busy is the ratio of actual performance to max
 765          * max_pstate is the max non turbo pstate available
 766          * current_pstate was the pstate that was requested during
 767          *      the last sample period.
 768          *
 769          * We normalize core_busy, which was our actual percent
 770          * performance to what we requested during the last sample
 771          * period. The result will be a percentage of busy at a
 772          * specified pstate.
 773          */
 774         core_busy = cpu->sample.core_pct_busy;
 775         max_pstate = int_tofp(cpu->pstate.max_pstate);
 776         current_pstate = int_tofp(cpu->pstate.current_pstate);
 777         core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
 778
 779         /*
 780          * Since we have a deferred timer, it will not fire unless
 781          * we are in C0.  So, determine if the actual elapsed time
 782          * is significantly greater (3x) than our sample interval.  If it
 783          * is, then we were idle for a long enough period of time
 784          * to adjust our busyness.
 785          */
 786         sample_time = pid_params.sample_rate_ms  * USEC_PER_MSEC;
 787         duration_us = (u32) ktime_us_delta(cpu->sample.time,
 788                                            cpu->last_sample_time);
 789         if (duration_us > sample_time * 3) {
 790                 sample_ratio = div_fp(int_tofp(sample_time),
 791                                       int_tofp(duration_us));
 792                 core_busy = mul_fp(core_busy, sample_ratio);
 793         }
 794
 795         return core_busy;
 796 }
 797
 798 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
 799 {
 800         int32_t busy_scaled;
 801         struct _pid *pid;
 802         signed int ctl;
 803
 804         pid = &cpu->pid;
 805         busy_scaled = intel_pstate_get_scaled_busy(cpu);
 806
 807         ctl = pid_calc(pid, busy_scaled);
 808
 809         /* Negative values of ctl increase the pstate and vice versa */
 810         intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl);
 811 }
 812
 813 static void intel_hwp_timer_func(unsigned long __data)
 814 {
 815         struct cpudata *cpu = (struct cpudata *) __data;
 816
 817         intel_pstate_sample(cpu);
 818         intel_hwp_set_sample_time(cpu);
 819 }
 820
 821 static void intel_pstate_timer_func(unsigned long __data)
 822 {
 823         struct cpudata *cpu = (struct cpudata *) __data;
 824         struct sample *sample;
 825
 826         intel_pstate_sample(cpu);
 827
 828         sample = &cpu->sample;
 829
 830         intel_pstate_adjust_busy_pstate(cpu);
 831
 832         trace_pstate_sample(fp_toint(sample->core_pct_busy),
 833                         fp_toint(intel_pstate_get_scaled_busy(cpu)),
 834                         cpu->pstate.current_pstate,
 835                         sample->mperf,
 836                         sample->aperf,
 837                         sample->freq);
 838
 839         intel_pstate_set_sample_time(cpu);
 840 }
 841
 842 #define ICPU(model, policy) \
 843         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
 844                         (unsigned long)&policy }
 845
 846 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
 847         ICPU(0x2a, core_params),
 848         ICPU(0x2d, core_params),
 849         ICPU(0x37, byt_params),
 850         ICPU(0x3a, core_params),
 851         ICPU(0x3c, core_params),
 852         ICPU(0x3d, core_params),
 853         ICPU(0x3e, core_params),
 854         ICPU(0x3f, core_params),
 855         ICPU(0x45, core_params),
 856         ICPU(0x46, core_params),
 857         ICPU(0x47, core_params),
 858         ICPU(0x4c, byt_params),
 859         ICPU(0x4e, core_params),
 860         ICPU(0x4f, core_params),
 861         ICPU(0x56, core_params),
 862         {}
 863 };
 864 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
 865
 866 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
 867         ICPU(0x56, core_params),
 868         {}
 869 };
 870
 871 static int intel_pstate_init_cpu(unsigned int cpunum)
 872 {
 873         struct cpudata *cpu;
 874
 875         if (!all_cpu_data[cpunum])
 876                 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
 877                                                GFP_KERNEL);
 878         if (!all_cpu_data[cpunum])
 879                 return -ENOMEM;
 880
 881         cpu = all_cpu_data[cpunum];
 882
 883         cpu->cpu = cpunum;
 884         intel_pstate_get_cpu_pstates(cpu);
 885
 886         init_timer_deferrable(&cpu->timer);
 887         cpu->timer.data = (unsigned long)cpu;
 888         cpu->timer.expires = jiffies + HZ/100;
 889
 890         if (!hwp_active)
 891                 cpu->timer.function = intel_pstate_timer_func;
 892         else
 893                 cpu->timer.function = intel_hwp_timer_func;
 894
 895         intel_pstate_busy_pid_reset(cpu);
 896         intel_pstate_sample(cpu);
 897
 898         add_timer_on(&cpu->timer, cpunum);
 899
 900         pr_debug("Intel pstate controlling: cpu %d\n", cpunum);
 901
 902         return 0;
 903 }
 904
 905 static unsigned int intel_pstate_get(unsigned int cpu_num)
 906 {
 907         struct sample *sample;
 908         struct cpudata *cpu;
 909
 910         cpu = all_cpu_data[cpu_num];
 911         if (!cpu)
 912                 return 0;
 913         sample = &cpu->sample;
 914         return sample->freq;
 915 }
 916
 917 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
 918 {
 919         if (!policy->cpuinfo.max_freq)
 920                 return -ENODEV;
 921
 922         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
 923                 limits.min_perf_pct = 100;
 924                 limits.min_perf = int_tofp(1);
 925                 limits.max_policy_pct = 100;
 926                 limits.max_perf_pct = 100;
 927                 limits.max_perf = int_tofp(1);
 928                 limits.no_turbo = 0;
 929                 return 0;
 930         }
 931
 932         limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
 933         limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
 934         limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
 935
 936         limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq;
 937         limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
 938         limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
 939         limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
 940
 941         if (hwp_active)
 942                 intel_pstate_hwp_set();
 943
 944         return 0;
 945 }
 946
 947 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
 948 {
 949         cpufreq_verify_within_cpu_limits(policy);
 950
 951         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
 952             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
 953                 return -EINVAL;
 954
 955         return 0;
 956 }
 957
 958 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
 959 {
 960         int cpu_num = policy->cpu;
 961         struct cpudata *cpu = all_cpu_data[cpu_num];
 962
 963         pr_info("intel_pstate CPU %d exiting\n", cpu_num);
 964
 965         del_timer_sync(&all_cpu_data[cpu_num]->timer);
 966         if (hwp_active)
 967                 return;
 968
 969         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
 970 }
 971
 972 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
 973 {
 974         struct cpudata *cpu;
 975         int rc;
 976
 977         rc = intel_pstate_init_cpu(policy->cpu);
 978         if (rc)
 979                 return rc;
 980
 981         cpu = all_cpu_data[policy->cpu];
 982
 983         if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
 984                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
 985         else
 986                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
 987
 988         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
 989         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
 990
 991         /* cpuinfo and default policy values */
 992         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
 993         policy->cpuinfo.max_freq =
 994                 cpu->pstate.turbo_pstate * cpu->pstate.scaling;
 995         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 996         cpumask_set_cpu(policy->cpu, policy->cpus);
 997
 998         return 0;
 999 }
1000
1001 static struct cpufreq_driver intel_pstate_driver = {
1002         .flags          = CPUFREQ_CONST_LOOPS,
1003         .verify         = intel_pstate_verify_policy,
1004         .setpolicy      = intel_pstate_set_policy,
1005         .get            = intel_pstate_get,
1006         .init           = intel_pstate_cpu_init,
1007         .stop_cpu       = intel_pstate_stop_cpu,
1008         .name           = "intel_pstate",
1009 };
1010
1011 static int __initdata no_load;
1012 static int __initdata no_hwp;
1013 static unsigned int force_load;
1014
1015 static int intel_pstate_msrs_not_valid(void)
1016 {
1017         /* Check that all the msr's we are using are valid. */
1018         u64 aperf, mperf, tmp;
1019
1020         rdmsrl(MSR_IA32_APERF, aperf);
1021         rdmsrl(MSR_IA32_MPERF, mperf);
1022
1023         if (!pstate_funcs.get_max() ||
1024             !pstate_funcs.get_min() ||
1025             !pstate_funcs.get_turbo())
1026                 return -ENODEV;
1027
1028         rdmsrl(MSR_IA32_APERF, tmp);
1029         if (!(tmp - aperf))
1030                 return -ENODEV;
1031
1032         rdmsrl(MSR_IA32_MPERF, tmp);
1033         if (!(tmp - mperf))
1034                 return -ENODEV;
1035
1036         return 0;
1037 }
1038
1039 static void copy_pid_params(struct pstate_adjust_policy *policy)
1040 {
1041         pid_params.sample_rate_ms = policy->sample_rate_ms;
1042         pid_params.p_gain_pct = policy->p_gain_pct;
1043         pid_params.i_gain_pct = policy->i_gain_pct;
1044         pid_params.d_gain_pct = policy->d_gain_pct;
1045         pid_params.deadband = policy->deadband;
1046         pid_params.setpoint = policy->setpoint;
1047 }
1048
1049 static void copy_cpu_funcs(struct pstate_funcs *funcs)
1050 {
1051         pstate_funcs.get_max   = funcs->get_max;
1052         pstate_funcs.get_min   = funcs->get_min;
1053         pstate_funcs.get_turbo = funcs->get_turbo;
1054         pstate_funcs.get_scaling = funcs->get_scaling;
1055         pstate_funcs.set       = funcs->set;
1056         pstate_funcs.get_vid   = funcs->get_vid;
1057 }
1058
1059 #if IS_ENABLED(CONFIG_ACPI)
1060 #include <acpi/processor.h>
1061
1062 static bool intel_pstate_no_acpi_pss(void)
1063 {
1064         int i;
1065
1066         for_each_possible_cpu(i) {
1067                 acpi_status status;
1068                 union acpi_object *pss;
1069                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1070                 struct acpi_processor *pr = per_cpu(processors, i);
1071
1072                 if (!pr)
1073                         continue;
1074
1075                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
1076                 if (ACPI_FAILURE(status))
1077                         continue;
1078
1079                 pss = buffer.pointer;
1080                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
1081                         kfree(pss);
1082                         return false;
1083                 }
1084
1085                 kfree(pss);
1086         }
1087
1088         return true;
1089 }
1090
1091 static bool intel_pstate_has_acpi_ppc(void)
1092 {
1093         int i;
1094
1095         for_each_possible_cpu(i) {
1096                 struct acpi_processor *pr = per_cpu(processors, i);
1097
1098                 if (!pr)
1099                         continue;
1100                 if (acpi_has_method(pr->handle, "_PPC"))
1101                         return true;
1102         }
1103         return false;
1104 }
1105
1106 enum {
1107         PSS,
1108         PPC,
1109 };
1110
1111 struct hw_vendor_info {
1112         u16  valid;
1113         char oem_id[ACPI_OEM_ID_SIZE];
1114         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
1115         int  oem_pwr_table;
1116 };
1117
1118 /* Hardware vendor-specific info that has its own power management modes */
1119 static struct hw_vendor_info vendor_info[] = {
1120         {1, "HP    ", "ProLiant", PSS},
1121         {1, "ORACLE", "X4-2    ", PPC},
1122         {1, "ORACLE", "X4-2L   ", PPC},
1123         {1, "ORACLE", "X4-2B   ", PPC},
1124         {1, "ORACLE", "X3-2    ", PPC},
1125         {1, "ORACLE", "X3-2L   ", PPC},
1126         {1, "ORACLE", "X3-2B   ", PPC},
1127         {1, "ORACLE", "X4470M2 ", PPC},
1128         {1, "ORACLE", "X4270M3 ", PPC},
1129         {1, "ORACLE", "X4270M2 ", PPC},
1130         {1, "ORACLE", "X4170M2 ", PPC},
1131         {0, "", ""},
1132 };
1133
1134 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1135 {
1136         struct acpi_table_header hdr;
1137         struct hw_vendor_info *v_info;
1138         const struct x86_cpu_id *id;
1139         u64 misc_pwr;
1140
1141         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
1142         if (id) {
1143                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
1144                 if ( misc_pwr & (1 << 8))
1145                         return true;
1146         }
1147
1148         if (acpi_disabled ||
1149             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
1150                 return false;
1151
1152         for (v_info = vendor_info; v_info->valid; v_info++) {
1153                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
1154                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
1155                                                 ACPI_OEM_TABLE_ID_SIZE))
1156                         switch (v_info->oem_pwr_table) {
1157                         case PSS:
1158                                 return intel_pstate_no_acpi_pss();
1159                         case PPC:
1160                                 return intel_pstate_has_acpi_ppc() &&
1161                                         (!force_load);
1162                         }
1163         }
1164
1165         return false;
1166 }
1167 #else /* CONFIG_ACPI not enabled */
1168 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1169 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1170 #endif /* CONFIG_ACPI */
1171
1172 static int __init intel_pstate_init(void)
1173 {
1174         int cpu, rc = 0;
1175         const struct x86_cpu_id *id;
1176         struct cpu_defaults *cpu_info;
1177         struct cpuinfo_x86 *c = &boot_cpu_data;
1178
1179         if (no_load)
1180                 return -ENODEV;
1181
1182         id = x86_match_cpu(intel_pstate_cpu_ids);
1183         if (!id)
1184                 return -ENODEV;
1185
1186         /*
1187          * The Intel pstate driver will be ignored if the platform
1188          * firmware has its own power management modes.
1189          */
1190         if (intel_pstate_platform_pwr_mgmt_exists())
1191                 return -ENODEV;
1192
1193         cpu_info = (struct cpu_defaults *)id->driver_data;
1194
1195         copy_pid_params(&cpu_info->pid_policy);
1196         copy_cpu_funcs(&cpu_info->funcs);
1197
1198         if (intel_pstate_msrs_not_valid())
1199                 return -ENODEV;
1200
1201         pr_info("Intel P-state driver initializing.\n");
1202
1203         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
1204         if (!all_cpu_data)
1205                 return -ENOMEM;
1206
1207         if (cpu_has(c,X86_FEATURE_HWP) && !no_hwp)
1208                 intel_pstate_hwp_enable();
1209
1210         rc = cpufreq_register_driver(&intel_pstate_driver);
1211         if (rc)
1212                 goto out;
1213
1214         intel_pstate_debug_expose_params();
1215         intel_pstate_sysfs_expose_params();
1216
1217         return rc;
1218 out:
1219         get_online_cpus();
1220         for_each_online_cpu(cpu) {
1221                 if (all_cpu_data[cpu]) {
1222                         del_timer_sync(&all_cpu_data[cpu]->timer);
1223                         kfree(all_cpu_data[cpu]);
1224                 }
1225         }
1226
1227         put_online_cpus();
1228         vfree(all_cpu_data);
1229         return -ENODEV;
1230 }
1231 device_initcall(intel_pstate_init);
1232
1233 static int __init intel_pstate_setup(char *str)
1234 {
1235         if (!str)
1236                 return -EINVAL;
1237
1238         if (!strcmp(str, "disable"))
1239                 no_load = 1;
1240         if (!strcmp(str, "no_hwp"))
1241                 no_hwp = 1;
1242         if (!strcmp(str, "force"))
1243                 force_load = 1;
1244         return 0;
1245 }
1246 early_param("intel_pstate", intel_pstate_setup);
1247
1248 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1249 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1250 MODULE_LICENSE("GPL");